[PATCH v2 0/4] Wait PSR idle before on dsb commit

[PATCH v2 0/4] Wait PSR idle before on dsb commit

[Jouni Högander]

We are currently observing crc failures after we started using dsb for PSR
updates as well. This seems to happen because PSR HW is still sending
couple of updates using old framebuffers on wake-up.

On non-dsb commit we are waiting PSR HW to idle before starting a new
commit. Fix problems with dsb commit by adding similar wait on dsb
commit as well.

v2: add pass crtc_state->dsb_commit as parameter

Jouni Högander (4):
  drm/i915/psr: Pass intel_crtc_state instead of intel_dp in
    wait_for_idle
  drm/i915/psr: Add new define for PSR idle timeout
  drm/i915/psr: New interface adding PSR idle poll into dsb commit
  drm/i915/psr: Add poll for checking PSR is idle before starting update

 drivers/gpu/drm/i915/display/intel_display.c |  2 +
 drivers/gpu/drm/i915/display/intel_psr.c     | 70 +++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_psr.h     |  1 +
 3 files changed, 57 insertions(+), 16 deletions(-)

-- 
2.43.0

[PATCH v2 1/4] drm/i915/psr: Pass intel_crtc_state instead of intel_dp in wait_for_idle

[Jouni Högander]

This is preparation to add own function for polling PSR being ready for
update when doing dsb commit.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 6bd3454bb00e..c2ab00fe2c20 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2982,10 +2982,11 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
 	}
 }
 
-static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
+static int
+_psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state)
 {
-	struct intel_display *display = to_intel_display(intel_dp);
-	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
+	struct intel_display *display = to_intel_display(new_crtc_state);
+	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 
 	/*
 	 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough.
@@ -2997,10 +2998,11 @@ static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
 				       EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50);
 }
 
-static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
+static int
+_psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state)
 {
-	struct intel_display *display = to_intel_display(intel_dp);
-	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
+	struct intel_display *display = to_intel_display(new_crtc_state);
+	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 
 	/*
 	 * From bspec: Panel Self Refresh (BDW+)
@@ -3039,9 +3041,9 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat
 			continue;
 
 		if (intel_dp->psr.sel_update_enabled)
-			ret = _psr2_ready_for_pipe_update_locked(intel_dp);
+			ret = _psr2_ready_for_pipe_update_locked(new_crtc_state);
 		else
-			ret = _psr1_ready_for_pipe_update_locked(intel_dp);
+			ret = _psr1_ready_for_pipe_update_locked(new_crtc_state);
 
 		if (ret)
 			drm_err(display->drm,
-- 
2.43.0

[PATCH v2 2/4] drm/i915/psr: Add new define for PSR idle timeout

[Jouni Högander]

Currently we are using value 50ms as timeout for waiting PSR to idle. Add
own define for this purpose.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c2ab00fe2c20..172bc0c39968 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2982,6 +2982,14 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
 	}
 }
 
+/*
+ * From bspec: Panel Self Refresh (BDW+)
+ * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
+ * exit training time + 1.5 ms of aux channel handshake. 50 ms is
+ * defensive enough to cover everything.
+ */
+#define PSR_IDLE_TIMEOUT_MS 50
+
 static int
 _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state)
 {
@@ -2995,7 +3003,8 @@ _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state
 	 */
 	return intel_de_wait_for_clear(display,
 				       EDP_PSR2_STATUS(display, cpu_transcoder),
-				       EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50);
+				       EDP_PSR2_STATUS_STATE_DEEP_SLEEP,
+				       PSR_IDLE_TIMEOUT_MS);
 }
 
 static int
@@ -3004,15 +3013,10 @@ _psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state
 	struct intel_display *display = to_intel_display(new_crtc_state);
 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 
-	/*
-	 * From bspec: Panel Self Refresh (BDW+)
-	 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
-	 * exit training time + 1.5 ms of aux channel handshake. 50 ms is
-	 * defensive enough to cover everything.
-	 */
 	return intel_de_wait_for_clear(display,
 				       psr_status_reg(display, cpu_transcoder),
-				       EDP_PSR_STATUS_STATE_MASK, 50);
+				       EDP_PSR_STATUS_STATE_MASK,
+				       PSR_IDLE_TIMEOUT_MS);
 }
 
 /**
-- 
2.43.0

[PATCH v2 3/4] drm/i915/psr: New interface adding PSR idle poll into dsb commit

[Jouni Högander]

We are currently observing crc failures after we started using dsb for PSR
updates as well. This seems to happen because PSR HW is still sending
couple of updates using old framebuffers on wake-up.

This patch is preparing to fix that by adding interface which can be used
to add poll ensuring PSR HW is idle into dsb commit.

v2: add pass crtc_state->dsb_commit as parameter

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 40 +++++++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_psr.h |  1 +
 2 files changed, 37 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 172bc0c39968..2254dd5a3ac4 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -42,6 +42,7 @@
 #include "intel_dmc.h"
 #include "intel_dp.h"
 #include "intel_dp_aux.h"
+#include "intel_dsb.h"
 #include "intel_frontbuffer.h"
 #include "intel_hdmi.h"
 #include "intel_psr.h"
@@ -2991,7 +2992,8 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
 #define PSR_IDLE_TIMEOUT_MS 50
 
 static int
-_psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state)
+_psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state,
+				   struct intel_dsb *dsb)
 {
 	struct intel_display *display = to_intel_display(new_crtc_state);
 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
@@ -3001,6 +3003,13 @@ _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state
 	 * As all higher states has bit 4 of PSR2 state set we can just wait for
 	 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared.
 	 */
+	if (dsb) {
+		intel_dsb_poll(dsb, EDP_PSR2_STATUS(display, cpu_transcoder),
+			       EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 0, 200,
+			       PSR_IDLE_TIMEOUT_MS * 1000 / 200);
+		return true;
+	}
+
 	return intel_de_wait_for_clear(display,
 				       EDP_PSR2_STATUS(display, cpu_transcoder),
 				       EDP_PSR2_STATUS_STATE_DEEP_SLEEP,
@@ -3008,11 +3017,19 @@ _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state
 }
 
 static int
-_psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state)
+_psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state,
+				   struct intel_dsb *dsb)
 {
 	struct intel_display *display = to_intel_display(new_crtc_state);
 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 
+	if (dsb) {
+		intel_dsb_poll(dsb, psr_status_reg(display, cpu_transcoder),
+			       EDP_PSR_STATUS_STATE_MASK, 0, 200,
+			       PSR_IDLE_TIMEOUT_MS * 1000 / 200);
+		return true;
+	}
+
 	return intel_de_wait_for_clear(display,
 				       psr_status_reg(display, cpu_transcoder),
 				       EDP_PSR_STATUS_STATE_MASK,
@@ -3045,9 +3062,11 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat
 			continue;
 
 		if (intel_dp->psr.sel_update_enabled)
-			ret = _psr2_ready_for_pipe_update_locked(new_crtc_state);
+			ret = _psr2_ready_for_pipe_update_locked(new_crtc_state,
+								 NULL);
 		else
-			ret = _psr1_ready_for_pipe_update_locked(new_crtc_state);
+			ret = _psr1_ready_for_pipe_update_locked(new_crtc_state,
+								 NULL);
 
 		if (ret)
 			drm_err(display->drm,
@@ -3055,6 +3074,19 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat
 	}
 }
 
+void intel_psr_wait_for_idle_dsb(const struct intel_crtc_state *new_crtc_state)
+{
+	if (!new_crtc_state->has_psr || new_crtc_state->has_panel_replay)
+		return;
+
+	if (new_crtc_state->has_sel_update)
+		_psr2_ready_for_pipe_update_locked(new_crtc_state,
+						   new_crtc_state->dsb_commit);
+	else
+		_psr1_ready_for_pipe_update_locked(new_crtc_state,
+						   new_crtc_state->dsb_commit);
+}
+
 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 9b061a22361f..0cd0542b2450 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -52,6 +52,7 @@ void intel_psr_get_config(struct intel_encoder *encoder,
 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
 void intel_psr_short_pulse(struct intel_dp *intel_dp);
 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state);
+void intel_psr_wait_for_idle_dsb(const struct intel_crtc_state *new_crtc_state);
 bool intel_psr_enabled(struct intel_dp *intel_dp);
 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 				struct intel_crtc *crtc);
-- 
2.43.0

[PATCH v2 4/4] drm/i915/psr: Add poll for checking PSR is idle before starting update

[Jouni Högander]

We are currently observing crc failures after we started using dsb for PSR
updates as well. This seems to happen because PSR HW is still sending
couple of updates using old framebuffers on wake-up.

Fix this by adding poll ensuring PSR is idle before starting update.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c1a3a95c65f0..411c74c73eae 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7271,6 +7271,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 		intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit,
 						     state, crtc);
 
+		intel_psr_wait_for_idle_dsb(new_crtc_state);
+
 		if (new_crtc_state->use_dsb)
 			intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
 
-- 
2.43.0

✓ CI.KUnit: success for Wait PSR idle before on dsb commit (rev2)

[Patchwork]

== Series Details ==

Series: Wait PSR idle before on dsb commit (rev2)
URL   : https://patchwork.freedesktop.org/series/152470/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[05:28:03] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:28:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:28:35] Starting KUnit Kernel (1/1)...
[05:28:35] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:28:35] ================== guc_buf (11 subtests) ===================
[05:28:35] [PASSED] test_smallest
[05:28:35] [PASSED] test_largest
[05:28:35] [PASSED] test_granular
[05:28:35] [PASSED] test_unique
[05:28:35] [PASSED] test_overlap
[05:28:35] [PASSED] test_reusable
[05:28:35] [PASSED] test_too_big
[05:28:35] [PASSED] test_flush
[05:28:35] [PASSED] test_lookup
[05:28:35] [PASSED] test_data
[05:28:35] [PASSED] test_class
[05:28:35] ===================== [PASSED] guc_buf =====================
[05:28:35] =================== guc_dbm (7 subtests) ===================
[05:28:35] [PASSED] test_empty
[05:28:35] [PASSED] test_default
[05:28:35] ======================== test_size  ========================
[05:28:35] [PASSED] 4
[05:28:35] [PASSED] 8
[05:28:35] [PASSED] 32
[05:28:35] [PASSED] 256
[05:28:35] ==================== [PASSED] test_size ====================
[05:28:35] ======================= test_reuse  ========================
[05:28:35] [PASSED] 4
[05:28:35] [PASSED] 8
[05:28:35] [PASSED] 32
[05:28:35] [PASSED] 256
[05:28:35] =================== [PASSED] test_reuse ====================
[05:28:35] =================== test_range_overlap  ====================
[05:28:35] [PASSED] 4
[05:28:35] [PASSED] 8
[05:28:35] [PASSED] 32
[05:28:35] [PASSED] 256
[05:28:35] =============== [PASSED] test_range_overlap ================
[05:28:35] =================== test_range_compact  ====================
[05:28:35] [PASSED] 4
[05:28:35] [PASSED] 8
[05:28:35] [PASSED] 32
[05:28:35] [PASSED] 256
[05:28:35] =============== [PASSED] test_range_compact ================
[05:28:35] ==================== test_range_spare  =====================
[05:28:35] [PASSED] 4
[05:28:35] [PASSED] 8
[05:28:35] [PASSED] 32
[05:28:35] [PASSED] 256
[05:28:35] ================ [PASSED] test_range_spare =================
[05:28:35] ===================== [PASSED] guc_dbm =====================
[05:28:35] =================== guc_idm (6 subtests) ===================
[05:28:35] [PASSED] bad_init
[05:28:35] [PASSED] no_init
[05:28:35] [PASSED] init_fini
[05:28:35] [PASSED] check_used
[05:28:35] [PASSED] check_quota
[05:28:35] [PASSED] check_all
[05:28:35] ===================== [PASSED] guc_idm =====================
[05:28:35] ================== no_relay (3 subtests) ===================
[05:28:35] [PASSED] xe_drops_guc2pf_if_not_ready
[05:28:35] [PASSED] xe_drops_guc2vf_if_not_ready
[05:28:35] [PASSED] xe_rejects_send_if_not_ready
[05:28:35] ==================== [PASSED] no_relay =====================
[05:28:35] ================== pf_relay (14 subtests) ==================
[05:28:35] [PASSED] pf_rejects_guc2pf_too_short
[05:28:35] [PASSED] pf_rejects_guc2pf_too_long
[05:28:35] [PASSED] pf_rejects_guc2pf_no_payload
[05:28:35] [PASSED] pf_fails_no_payload
[05:28:35] [PASSED] pf_fails_bad_origin
[05:28:35] [PASSED] pf_fails_bad_type
[05:28:35] [PASSED] pf_txn_reports_error
[05:28:35] [PASSED] pf_txn_sends_pf2guc
[05:28:35] [PASSED] pf_sends_pf2guc
[05:28:35] [SKIPPED] pf_loopback_nop
[05:28:35] [SKIPPED] pf_loopback_echo
[05:28:35] [SKIPPED] pf_loopback_fail
[05:28:35] [SKIPPED] pf_loopback_busy
[05:28:35] [SKIPPED] pf_loopback_retry
[05:28:35] ==================== [PASSED] pf_relay =====================
[05:28:35] ================== vf_relay (3 subtests) ===================
[05:28:35] [PASSED] vf_rejects_guc2vf_too_short
[05:28:35] [PASSED] vf_rejects_guc2vf_too_long
[05:28:35] [PASSED] vf_rejects_guc2vf_no_payload
[05:28:35] ==================== [PASSED] vf_relay =====================
[05:28:35] ===================== lmtt (1 subtest) =====================
[05:28:35] ======================== test_ops  =========================
[05:28:35] [PASSED] 2-level
[05:28:35] [PASSED] multi-level
[05:28:35] ==================== [PASSED] test_ops =====================
[05:28:35] ====================== [PASSED] lmtt =======================
[05:28:35] ================= pf_service (11 subtests) =================
[05:28:35] [PASSED] pf_negotiate_any
[05:28:35] [PASSED] pf_negotiate_base_match
[05:28:35] [PASSED] pf_negotiate_base_newer
[05:28:35] [PASSED] pf_negotiate_base_next
[05:28:35] [SKIPPED] pf_negotiate_base_older
[05:28:35] [PASSED] pf_negotiate_base_prev
[05:28:35] [PASSED] pf_negotiate_latest_match
[05:28:35] [PASSED] pf_negotiate_latest_newer
[05:28:35] [PASSED] pf_negotiate_latest_next
[05:28:35] [SKIPPED] pf_negotiate_latest_older
[05:28:35] [SKIPPED] pf_negotiate_latest_prev
[05:28:35] =================== [PASSED] pf_service ====================
[05:28:35] =================== xe_mocs (2 subtests) ===================
[05:28:35] ================ xe_live_mocs_kernel_kunit  ================
[05:28:35] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[05:28:35] ================ xe_live_mocs_reset_kunit  =================
[05:28:35] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[05:28:35] ==================== [SKIPPED] xe_mocs =====================
[05:28:35] ================= xe_migrate (2 subtests) ==================
[05:28:35] ================= xe_migrate_sanity_kunit  =================
[05:28:35] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[05:28:35] ================== xe_validate_ccs_kunit  ==================
[05:28:35] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[05:28:35] =================== [SKIPPED] xe_migrate ===================
[05:28:35] ================== xe_dma_buf (1 subtest) ==================
[05:28:35] ==================== xe_dma_buf_kunit  =====================
[05:28:35] ================ [SKIPPED] xe_dma_buf_kunit ================
[05:28:35] =================== [SKIPPED] xe_dma_buf ===================
[05:28:35] ================= xe_bo_shrink (1 subtest) =================
[05:28:35] =================== xe_bo_shrink_kunit  ====================
[05:28:35] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[05:28:35] ================== [SKIPPED] xe_bo_shrink ==================
[05:28:35] ==================== xe_bo (2 subtests) ====================
[05:28:35] ================== xe_ccs_migrate_kunit  ===================
[05:28:35] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[05:28:35] ==================== xe_bo_evict_kunit  ====================
[05:28:35] =============== [SKIPPED] xe_bo_evict_kunit ================
[05:28:35] ===================== [SKIPPED] xe_bo ======================
[05:28:35] ==================== args (11 subtests) ====================
[05:28:35] [PASSED] count_args_test
[05:28:35] [PASSED] call_args_example
[05:28:35] [PASSED] call_args_test
[05:28:35] [PASSED] drop_first_arg_example
[05:28:35] [PASSED] drop_first_arg_test
[05:28:35] [PASSED] first_arg_example
[05:28:35] [PASSED] first_arg_test
[05:28:35] [PASSED] last_arg_example
[05:28:35] [PASSED] last_arg_test
[05:28:35] [PASSED] pick_arg_example
[05:28:35] [PASSED] sep_comma_example
[05:28:35] ====================== [PASSED] args =======================
[05:28:35] =================== xe_pci (3 subtests) ====================
[05:28:35] ==================== check_graphics_ip  ====================
[05:28:35] [PASSED] 12.70 Xe_LPG
[05:28:35] [PASSED] 12.71 Xe_LPG
[05:28:35] [PASSED] 12.74 Xe_LPG+
[05:28:35] [PASSED] 20.01 Xe2_HPG
[05:28:35] [PASSED] 20.02 Xe2_HPG
[05:28:35] [PASSED] 20.04 Xe2_LPG
[05:28:35] [PASSED] 30.00 Xe3_LPG
[05:28:35] [PASSED] 30.01 Xe3_LPG
[05:28:35] [PASSED] 30.03 Xe3_LPG
[05:28:35] ================ [PASSED] check_graphics_ip ================
[05:28:35] ===================== check_media_ip  ======================
[05:28:35] [PASSED] 13.00 Xe_LPM+
[05:28:35] [PASSED] 13.01 Xe2_HPM
[05:28:35] [PASSED] 20.00 Xe2_LPM
[05:28:35] [PASSED] 30.00 Xe3_LPM
[05:28:35] [PASSED] 30.02 Xe3_LPM
[05:28:35] ================= [PASSED] check_media_ip ==================
[05:28:35] ================= check_platform_gt_count  =================
[05:28:35] [PASSED] 0x9A60 (TIGERLAKE)
[05:28:35] [PASSED] 0x9A68 (TIGERLAKE)
[05:28:35] [PASSED] 0x9A70 (TIGERLAKE)
[05:28:35] [PASSED] 0x9A40 (TIGERLAKE)
[05:28:35] [PASSED] 0x9A49 (TIGERLAKE)
[05:28:35] [PASSED] 0x9A59 (TIGERLAKE)
[05:28:35] [PASSED] 0x9A78 (TIGERLAKE)
[05:28:35] [PASSED] 0x9AC0 (TIGERLAKE)
[05:28:35] [PASSED] 0x9AC9 (TIGERLAKE)
[05:28:35] [PASSED] 0x9AD9 (TIGERLAKE)
[05:28:35] [PASSED] 0x9AF8 (TIGERLAKE)
[05:28:35] [PASSED] 0x4C80 (ROCKETLAKE)
[05:28:35] [PASSED] 0x4C8A (ROCKETLAKE)
[05:28:35] [PASSED] 0x4C8B (ROCKETLAKE)
[05:28:35] [PASSED] 0x4C8C (ROCKETLAKE)
[05:28:35] [PASSED] 0x4C90 (ROCKETLAKE)
[05:28:35] [PASSED] 0x4C9A (ROCKETLAKE)
[05:28:35] [PASSED] 0x4680 (ALDERLAKE_S)
[05:28:35] [PASSED] 0x4682 (ALDERLAKE_S)
[05:28:35] [PASSED] 0x4688 (ALDERLAKE_S)
[05:28:35] [PASSED] 0x468A (ALDERLAKE_S)
[05:28:35] [PASSED] 0x468B (ALDERLAKE_S)
[05:28:35] [PASSED] 0x4690 (ALDERLAKE_S)
[05:28:35] [PASSED] 0x4692 (ALDERLAKE_S)
[05:28:35] [PASSED] 0x4693 (ALDERLAKE_S)
[05:28:35] [PASSED] 0x46A0 (ALDERLAKE_P)
[05:28:35] [PASSED] 0x46A1 (ALDERLAKE_P)
[05:28:35] [PASSED] 0x46A2 (ALDERLAKE_P)
[05:28:35] [PASSED] 0x46A3 (ALDERLAKE_P)
[05:28:35] [PASSED] 0x46A6 (ALDERLAKE_P)
[05:28:35] [PASSED] 0x46A8 (ALDERLAKE_P)
[05:28:35] [PASSED] 0x46AA (ALDERLAKE_P)
[05:28:35] [PASSED] 0x462A (ALDERLAKE_P)
[05:28:35] [PASSED] 0x4626 (ALDERLAKE_P)
[05:28:35] [PASSED] 0x4628 (ALDERLAKE_P)
[05:28:35] [PASSED] 0x46B0 (ALDERLAKE_P)
[05:28:35] [PASSED] 0x46B1 (ALDERLAKE_P)
[05:28:35] [PASSED] 0x46B2 (ALDERLAKE_P)
[05:28:35] [PASSED] 0x46B3 (ALDERLAKE_P)
[05:28:35] [PASSED] 0x46C0 (ALDERLAKE_P)
[05:28:35] [PASSED] 0x46C1 (ALDERLAKE_P)
[05:28:35] [PASSED] 0x46C2 (ALDERLAKE_P)
[05:28:35] [PASSED] 0x46C3 (ALDERLAKE_P)
[05:28:35] [PASSED] 0x46D0 (ALDERLAKE_N)
[05:28:35] [PASSED] 0x46D1 (ALDERLAKE_N)
[05:28:35] [PASSED] 0x46D2 (ALDERLAKE_N)
[05:28:35] [PASSED] 0x46D3 (ALDERLAKE_N)
[05:28:35] [PASSED] 0x46D4 (ALDERLAKE_N)
[05:28:35] [PASSED] 0xA721 (ALDERLAKE_P)
[05:28:35] [PASSED] 0xA7A1 (ALDERLAKE_P)
[05:28:35] [PASSED] 0xA7A9 (ALDERLAKE_P)
[05:28:35] [PASSED] 0xA7AC (ALDERLAKE_P)
[05:28:35] [PASSED] 0xA7AD (ALDERLAKE_P)
[05:28:35] [PASSED] 0xA720 (ALDERLAKE_P)
[05:28:35] [PASSED] 0xA7A0 (ALDERLAKE_P)
[05:28:35] [PASSED] 0xA7A8 (ALDERLAKE_P)
[05:28:35] [PASSED] 0xA7AA (ALDERLAKE_P)
[05:28:35] [PASSED] 0xA7AB (ALDERLAKE_P)
[05:28:35] [PASSED] 0xA780 (ALDERLAKE_S)
[05:28:35] [PASSED] 0xA781 (ALDERLAKE_S)
[05:28:35] [PASSED] 0xA782 (ALDERLAKE_S)
[05:28:35] [PASSED] 0xA783 (ALDERLAKE_S)
[05:28:35] [PASSED] 0xA788 (ALDERLAKE_S)
[05:28:35] [PASSED] 0xA789 (ALDERLAKE_S)
[05:28:35] [PASSED] 0xA78A (ALDERLAKE_S)
[05:28:35] [PASSED] 0xA78B (ALDERLAKE_S)
[05:28:35] [PASSED] 0x4905 (DG1)
[05:28:35] [PASSED] 0x4906 (DG1)
[05:28:35] [PASSED] 0x4907 (DG1)
[05:28:35] [PASSED] 0x4908 (DG1)
[05:28:35] [PASSED] 0x4909 (DG1)
[05:28:35] [PASSED] 0x56C0 (DG2)
[05:28:35] [PASSED] 0x56C2 (DG2)
[05:28:35] [PASSED] 0x56C1 (DG2)
[05:28:35] [PASSED] 0x7D51 (METEORLAKE)
[05:28:35] [PASSED] 0x7DD1 (METEORLAKE)
[05:28:35] [PASSED] 0x7D41 (METEORLAKE)
[05:28:35] [PASSED] 0x7D67 (METEORLAKE)
[05:28:35] [PASSED] 0xB640 (METEORLAKE)
[05:28:35] [PASSED] 0x56A0 (DG2)
[05:28:35] [PASSED] 0x56A1 (DG2)
[05:28:35] [PASSED] 0x56A2 (DG2)
[05:28:35] [PASSED] 0x56BE (DG2)
[05:28:35] [PASSED] 0x56BF (DG2)
[05:28:35] [PASSED] 0x5690 (DG2)
[05:28:35] [PASSED] 0x5691 (DG2)
[05:28:35] [PASSED] 0x5692 (DG2)
[05:28:35] [PASSED] 0x56A5 (DG2)
[05:28:35] [PASSED] 0x56A6 (DG2)
[05:28:35] [PASSED] 0x56B0 (DG2)
[05:28:35] [PASSED] 0x56B1 (DG2)
[05:28:35] [PASSED] 0x56BA (DG2)
[05:28:35] [PASSED] 0x56BB (DG2)
[05:28:35] [PASSED] 0x56BC (DG2)
[05:28:35] [PASSED] 0x56BD (DG2)
[05:28:35] [PASSED] 0x5693 (DG2)
[05:28:35] [PASSED] 0x5694 (DG2)
[05:28:35] [PASSED] 0x5695 (DG2)
[05:28:35] [PASSED] 0x56A3 (DG2)
[05:28:35] [PASSED] 0x56A4 (DG2)
[05:28:35] [PASSED] 0x56B2 (DG2)
[05:28:35] [PASSED] 0x56B3 (DG2)
[05:28:35] [PASSED] 0x5696 (DG2)
[05:28:35] [PASSED] 0x5697 (DG2)
[05:28:35] [PASSED] 0xB69 (PVC)
[05:28:35] [PASSED] 0xB6E (PVC)
[05:28:35] [PASSED] 0xBD4 (PVC)
[05:28:35] [PASSED] 0xBD5 (PVC)
[05:28:35] [PASSED] 0xBD6 (PVC)
[05:28:35] [PASSED] 0xBD7 (PVC)
[05:28:35] [PASSED] 0xBD8 (PVC)
[05:28:35] [PASSED] 0xBD9 (PVC)
[05:28:35] [PASSED] 0xBDA (PVC)
[05:28:35] [PASSED] 0xBDB (PVC)
[05:28:35] [PASSED] 0xBE0 (PVC)
[05:28:35] [PASSED] 0xBE1 (PVC)
[05:28:35] [PASSED] 0xBE5 (PVC)
[05:28:35] [PASSED] 0x7D40 (METEORLAKE)
[05:28:35] [PASSED] 0x7D45 (METEORLAKE)
[05:28:35] [PASSED] 0x7D55 (METEORLAKE)
[05:28:35] [PASSED] 0x7D60 (METEORLAKE)
[05:28:35] [PASSED] 0x7DD5 (METEORLAKE)
[05:28:35] [PASSED] 0x6420 (LUNARLAKE)
[05:28:35] [PASSED] 0x64A0 (LUNARLAKE)
[05:28:35] [PASSED] 0x64B0 (LUNARLAKE)
[05:28:35] [PASSED] 0xE202 (BATTLEMAGE)
[05:28:35] [PASSED] 0xE209 (BATTLEMAGE)
[05:28:35] [PASSED] 0xE20B (BATTLEMAGE)
[05:28:35] [PASSED] 0xE20C (BATTLEMAGE)
[05:28:35] [PASSED] 0xE20D (BATTLEMAGE)
[05:28:35] [PASSED] 0xE210 (BATTLEMAGE)
[05:28:35] [PASSED] 0xE211 (BATTLEMAGE)
[05:28:35] [PASSED] 0xE212 (BATTLEMAGE)
[05:28:35] [PASSED] 0xE216 (BATTLEMAGE)
[05:28:35] [PASSED] 0xE220 (BATTLEMAGE)
[05:28:35] [PASSED] 0xE221 (BATTLEMAGE)
[05:28:35] [PASSED] 0xE222 (BATTLEMAGE)
[05:28:35] [PASSED] 0xE223 (BATTLEMAGE)
[05:28:35] [PASSED] 0xB080 (PANTHERLAKE)
[05:28:35] [PASSED] 0xB081 (PANTHERLAKE)
[05:28:35] [PASSED] 0xB082 (PANTHERLAKE)
[05:28:35] [PASSED] 0xB083 (PANTHERLAKE)
[05:28:35] [PASSED] 0xB084 (PANTHERLAKE)
[05:28:35] [PASSED] 0xB085 (PANTHERLAKE)
[05:28:35] [PASSED] 0xB086 (PANTHERLAKE)
[05:28:35] [PASSED] 0xB087 (PANTHERLAKE)
[05:28:35] [PASSED] 0xB08F (PANTHERLAKE)
[05:28:35] [PASSED] 0xB090 (PANTHERLAKE)
[05:28:35] [PASSED] 0xB0A0 (PANTHERLAKE)
[05:28:35] [PASSED] 0xB0B0 (PANTHERLAKE)
[05:28:35] [PASSED] 0xFD80 (PANTHERLAKE)
[05:28:35] [PASSED] 0xFD81 (PANTHERLAKE)
[05:28:35] ============= [PASSED] check_platform_gt_count =============
[05:28:35] ===================== [PASSED] xe_pci ======================
[05:28:35] =================== xe_rtp (2 subtests) ====================
[05:28:35] =============== xe_rtp_process_to_sr_tests  ================
[05:28:35] [PASSED] coalesce-same-reg
[05:28:35] [PASSED] no-match-no-add
[05:28:35] [PASSED] match-or
[05:28:35] [PASSED] match-or-xfail
[05:28:35] [PASSED] no-match-no-add-multiple-rules
[05:28:35] [PASSED] two-regs-two-entries
[05:28:35] [PASSED] clr-one-set-other
[05:28:35] [PASSED] set-field
[05:28:35] [PASSED] conflict-duplicate
[05:28:35] [PASSED] conflict-not-disjoint
[05:28:35] [PASSED] conflict-reg-type
[05:28:35] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[05:28:35] ================== xe_rtp_process_tests  ===================
[05:28:35] [PASSED] active1
[05:28:35] [PASSED] active2
[05:28:35] [PASSED] active-inactive
[05:28:35] [PASSED] inactive-active
[05:28:35] [PASSED] inactive-1st_or_active-inactive
[05:28:35] [PASSED] inactive-2nd_or_active-inactive
[05:28:35] [PASSED] inactive-last_or_active-inactive
[05:28:35] [PASSED] inactive-no_or_active-inactive
[05:28:35] ============== [PASSED] xe_rtp_process_tests ===============
[05:28:35] ===================== [PASSED] xe_rtp ======================
[05:28:35] ==================== xe_wa (1 subtest) =====================
[05:28:35] ======================== xe_wa_gt  =========================
[05:28:35] [PASSED] TIGERLAKE (B0)
[05:28:35] [PASSED] DG1 (A0)
[05:28:35] [PASSED] DG1 (B0)
[05:28:35] [PASSED] ALDERLAKE_S (A0)
[05:28:35] [PASSED] ALDERLAKE_S (B0)
[05:28:35] [PASSED] ALDERLAKE_S (C0)
[05:28:35] [PASSED] ALDERLAKE_S (D0)
[05:28:35] [PASSED] ALDERLAKE_P (A0)
[05:28:35] [PASSED] ALDERLAKE_P (B0)
[05:28:35] [PASSED] ALDERLAKE_P (C0)
[05:28:35] [PASSED] ALDERLAKE_S_RPLS (D0)
[05:28:35] [PASSED] ALDERLAKE_P_RPLU (E0)
[05:28:35] [PASSED] DG2_G10 (C0)
[05:28:35] [PASSED] DG2_G11 (B1)
[05:28:35] [PASSED] DG2_G12 (A1)
[05:28:35] [PASSED] METEORLAKE (g:A0, m:A0)
[05:28:35] [PASSED] METEORLAKE (g:A0, m:A0)
[05:28:35] [PASSED] METEORLAKE (g:A0, m:A0)
[05:28:35] [PASSED] LUNARLAKE (g:A0, m:A0)
[05:28:35] [PASSED] LUNARLAKE (g:B0, m:A0)
stty: 'standard input': Inappropriate ioctl for device
[05:28:35] [PASSED] BATTLEMAGE (g:A0, m:A1)
[05:28:35] ==================== [PASSED] xe_wa_gt =====================
[05:28:35] ====================== [PASSED] xe_wa ======================
[05:28:35] ============================================================
[05:28:35] Testing complete. Ran 297 tests: passed: 281, skipped: 16
[05:28:35] Elapsed time: 31.674s total, 4.202s configuring, 27.105s building, 0.316s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[05:28:35] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:28:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:28:58] Starting KUnit Kernel (1/1)...
[05:28:58] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:28:58] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[05:28:58] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[05:28:58] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[05:28:58] =========== drm_validate_clone_mode (2 subtests) ===========
[05:28:58] ============== drm_test_check_in_clone_mode  ===============
[05:28:58] [PASSED] in_clone_mode
[05:28:58] [PASSED] not_in_clone_mode
[05:28:58] ========== [PASSED] drm_test_check_in_clone_mode ===========
[05:28:58] =============== drm_test_check_valid_clones  ===============
[05:28:58] [PASSED] not_in_clone_mode
[05:28:58] [PASSED] valid_clone
[05:28:58] [PASSED] invalid_clone
[05:28:58] =========== [PASSED] drm_test_check_valid_clones ===========
[05:28:58] ============= [PASSED] drm_validate_clone_mode =============
[05:28:58] ============= drm_validate_modeset (1 subtest) =============
[05:28:58] [PASSED] drm_test_check_connector_changed_modeset
[05:28:58] ============== [PASSED] drm_validate_modeset ===============
[05:28:58] ====== drm_test_bridge_get_current_state (2 subtests) ======
[05:28:58] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[05:28:58] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[05:28:58] ======== [PASSED] drm_test_bridge_get_current_state ========
[05:28:58] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[05:28:58] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[05:28:58] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[05:28:58] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[05:28:58] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[05:28:58] ============== drm_bridge_alloc (2 subtests) ===============
[05:28:58] [PASSED] drm_test_drm_bridge_alloc_basic
[05:28:58] [PASSED] drm_test_drm_bridge_alloc_get_put
[05:28:58] ================ [PASSED] drm_bridge_alloc =================
[05:28:58] ================== drm_buddy (7 subtests) ==================
[05:28:58] [PASSED] drm_test_buddy_alloc_limit
[05:28:58] [PASSED] drm_test_buddy_alloc_optimistic
[05:28:58] [PASSED] drm_test_buddy_alloc_pessimistic
[05:28:58] [PASSED] drm_test_buddy_alloc_pathological
[05:28:58] [PASSED] drm_test_buddy_alloc_contiguous
[05:28:58] [PASSED] drm_test_buddy_alloc_clear
[05:28:58] [PASSED] drm_test_buddy_alloc_range_bias
[05:28:58] ==================== [PASSED] drm_buddy ====================
[05:28:58] ============= drm_cmdline_parser (40 subtests) =============
[05:28:58] [PASSED] drm_test_cmdline_force_d_only
[05:28:58] [PASSED] drm_test_cmdline_force_D_only_dvi
[05:28:58] [PASSED] drm_test_cmdline_force_D_only_hdmi
[05:28:58] [PASSED] drm_test_cmdline_force_D_only_not_digital
[05:28:58] [PASSED] drm_test_cmdline_force_e_only
[05:28:58] [PASSED] drm_test_cmdline_res
[05:28:58] [PASSED] drm_test_cmdline_res_vesa
[05:28:58] [PASSED] drm_test_cmdline_res_vesa_rblank
[05:28:58] [PASSED] drm_test_cmdline_res_rblank
[05:28:58] [PASSED] drm_test_cmdline_res_bpp
[05:28:58] [PASSED] drm_test_cmdline_res_refresh
[05:28:58] [PASSED] drm_test_cmdline_res_bpp_refresh
[05:28:58] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[05:28:58] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[05:28:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[05:28:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[05:28:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[05:28:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[05:28:58] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[05:28:58] [PASSED] drm_test_cmdline_res_margins_force_on
[05:28:58] [PASSED] drm_test_cmdline_res_vesa_margins
[05:28:58] [PASSED] drm_test_cmdline_name
[05:28:58] [PASSED] drm_test_cmdline_name_bpp
[05:28:58] [PASSED] drm_test_cmdline_name_option
[05:28:58] [PASSED] drm_test_cmdline_name_bpp_option
[05:28:58] [PASSED] drm_test_cmdline_rotate_0
[05:28:58] [PASSED] drm_test_cmdline_rotate_90
[05:28:58] [PASSED] drm_test_cmdline_rotate_180
[05:28:58] [PASSED] drm_test_cmdline_rotate_270
[05:28:58] [PASSED] drm_test_cmdline_hmirror
[05:28:58] [PASSED] drm_test_cmdline_vmirror
[05:28:58] [PASSED] drm_test_cmdline_margin_options
[05:28:58] [PASSED] drm_test_cmdline_multiple_options
[05:28:58] [PASSED] drm_test_cmdline_bpp_extra_and_option
[05:28:58] [PASSED] drm_test_cmdline_extra_and_option
[05:28:58] [PASSED] drm_test_cmdline_freestanding_options
[05:28:58] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[05:28:58] [PASSED] drm_test_cmdline_panel_orientation
[05:28:58] ================ drm_test_cmdline_invalid  =================
[05:28:58] [PASSED] margin_only
[05:28:58] [PASSED] interlace_only
[05:28:58] [PASSED] res_missing_x
[05:28:58] [PASSED] res_missing_y
[05:28:58] [PASSED] res_bad_y
[05:28:58] [PASSED] res_missing_y_bpp
[05:28:58] [PASSED] res_bad_bpp
[05:28:58] [PASSED] res_bad_refresh
[05:28:58] [PASSED] res_bpp_refresh_force_on_off
[05:28:58] [PASSED] res_invalid_mode
[05:28:58] [PASSED] res_bpp_wrong_place_mode
[05:28:58] [PASSED] name_bpp_refresh
[05:28:58] [PASSED] name_refresh
[05:28:58] [PASSED] name_refresh_wrong_mode
[05:28:58] [PASSED] name_refresh_invalid_mode
[05:28:58] [PASSED] rotate_multiple
[05:28:58] [PASSED] rotate_invalid_val
[05:28:58] [PASSED] rotate_truncated
[05:28:58] [PASSED] invalid_option
[05:28:58] [PASSED] invalid_tv_option
[05:28:58] [PASSED] truncated_tv_option
[05:28:58] ============ [PASSED] drm_test_cmdline_invalid =============
[05:28:58] =============== drm_test_cmdline_tv_options  ===============
[05:28:58] [PASSED] NTSC
[05:28:58] [PASSED] NTSC_443
[05:28:58] [PASSED] NTSC_J
[05:28:58] [PASSED] PAL
[05:28:58] [PASSED] PAL_M
[05:28:58] [PASSED] PAL_N
[05:28:58] [PASSED] SECAM
[05:28:58] [PASSED] MONO_525
[05:28:58] [PASSED] MONO_625
[05:28:58] =========== [PASSED] drm_test_cmdline_tv_options ===========
[05:28:58] =============== [PASSED] drm_cmdline_parser ================
[05:28:58] ========== drmm_connector_hdmi_init (20 subtests) ==========
[05:28:58] [PASSED] drm_test_connector_hdmi_init_valid
[05:28:58] [PASSED] drm_test_connector_hdmi_init_bpc_8
[05:28:58] [PASSED] drm_test_connector_hdmi_init_bpc_10
[05:28:58] [PASSED] drm_test_connector_hdmi_init_bpc_12
[05:28:58] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[05:28:58] [PASSED] drm_test_connector_hdmi_init_bpc_null
[05:28:58] [PASSED] drm_test_connector_hdmi_init_formats_empty
[05:28:58] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[05:28:58] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[05:28:58] [PASSED] supported_formats=0x9 yuv420_allowed=1
[05:28:58] [PASSED] supported_formats=0x9 yuv420_allowed=0
[05:28:58] [PASSED] supported_formats=0x3 yuv420_allowed=1
[05:28:58] [PASSED] supported_formats=0x3 yuv420_allowed=0
[05:28:58] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[05:28:58] [PASSED] drm_test_connector_hdmi_init_null_ddc
[05:28:58] [PASSED] drm_test_connector_hdmi_init_null_product
[05:28:58] [PASSED] drm_test_connector_hdmi_init_null_vendor
[05:28:58] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[05:28:58] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[05:28:58] [PASSED] drm_test_connector_hdmi_init_product_valid
[05:28:58] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[05:28:58] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[05:28:58] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[05:28:58] ========= drm_test_connector_hdmi_init_type_valid  =========
[05:28:58] [PASSED] HDMI-A
[05:28:58] [PASSED] HDMI-B
[05:28:58] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[05:28:58] ======== drm_test_connector_hdmi_init_type_invalid  ========
[05:28:58] [PASSED] Unknown
[05:28:58] [PASSED] VGA
[05:28:58] [PASSED] DVI-I
[05:28:58] [PASSED] DVI-D
[05:28:58] [PASSED] DVI-A
[05:28:58] [PASSED] Composite
[05:28:58] [PASSED] SVIDEO
[05:28:58] [PASSED] LVDS
[05:28:58] [PASSED] Component
[05:28:58] [PASSED] DIN
[05:28:58] [PASSED] DP
[05:28:58] [PASSED] TV
[05:28:58] [PASSED] eDP
[05:28:58] [PASSED] Virtual
[05:28:58] [PASSED] DSI
[05:28:58] [PASSED] DPI
[05:28:58] [PASSED] Writeback
[05:28:58] [PASSED] SPI
[05:28:58] [PASSED] USB
[05:28:58] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[05:28:58] ============ [PASSED] drmm_connector_hdmi_init =============
[05:28:58] ============= drmm_connector_init (3 subtests) =============
[05:28:58] [PASSED] drm_test_drmm_connector_init
[05:28:58] [PASSED] drm_test_drmm_connector_init_null_ddc
[05:28:58] ========= drm_test_drmm_connector_init_type_valid  =========
[05:28:58] [PASSED] Unknown
[05:28:58] [PASSED] VGA
[05:28:58] [PASSED] DVI-I
[05:28:58] [PASSED] DVI-D
[05:28:58] [PASSED] DVI-A
[05:28:58] [PASSED] Composite
[05:28:58] [PASSED] SVIDEO
[05:28:58] [PASSED] LVDS
[05:28:58] [PASSED] Component
[05:28:58] [PASSED] DIN
[05:28:58] [PASSED] DP
[05:28:58] [PASSED] HDMI-A
[05:28:58] [PASSED] HDMI-B
[05:28:58] [PASSED] TV
[05:28:58] [PASSED] eDP
[05:28:58] [PASSED] Virtual
[05:28:58] [PASSED] DSI
[05:28:58] [PASSED] DPI
[05:28:58] [PASSED] Writeback
[05:28:58] [PASSED] SPI
[05:28:58] [PASSED] USB
[05:28:58] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[05:28:58] =============== [PASSED] drmm_connector_init ===============
[05:28:58] ========= drm_connector_dynamic_init (6 subtests) ==========
[05:28:58] [PASSED] drm_test_drm_connector_dynamic_init
[05:28:58] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[05:28:58] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[05:28:58] [PASSED] drm_test_drm_connector_dynamic_init_properties
[05:28:58] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[05:28:58] [PASSED] Unknown
[05:28:58] [PASSED] VGA
[05:28:58] [PASSED] DVI-I
[05:28:58] [PASSED] DVI-D
[05:28:58] [PASSED] DVI-A
[05:28:58] [PASSED] Composite
[05:28:58] [PASSED] SVIDEO
[05:28:58] [PASSED] LVDS
[05:28:58] [PASSED] Component
[05:28:58] [PASSED] DIN
[05:28:58] [PASSED] DP
[05:28:58] [PASSED] HDMI-A
[05:28:58] [PASSED] HDMI-B
[05:28:58] [PASSED] TV
[05:28:58] [PASSED] eDP
[05:28:58] [PASSED] Virtual
[05:28:58] [PASSED] DSI
[05:28:58] [PASSED] DPI
[05:28:58] [PASSED] Writeback
[05:28:58] [PASSED] SPI
[05:28:58] [PASSED] USB
[05:28:58] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[05:28:58] ======== drm_test_drm_connector_dynamic_init_name  =========
[05:28:58] [PASSED] Unknown
[05:28:58] [PASSED] VGA
[05:28:58] [PASSED] DVI-I
[05:28:58] [PASSED] DVI-D
[05:28:58] [PASSED] DVI-A
[05:28:58] [PASSED] Composite
[05:28:58] [PASSED] SVIDEO
[05:28:58] [PASSED] LVDS
[05:28:58] [PASSED] Component
[05:28:58] [PASSED] DIN
[05:28:58] [PASSED] DP
[05:28:58] [PASSED] HDMI-A
[05:28:58] [PASSED] HDMI-B
[05:28:58] [PASSED] TV
[05:28:58] [PASSED] eDP
[05:28:58] [PASSED] Virtual
[05:28:58] [PASSED] DSI
[05:28:58] [PASSED] DPI
[05:28:58] [PASSED] Writeback
[05:28:58] [PASSED] SPI
[05:28:58] [PASSED] USB
[05:28:58] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[05:28:58] =========== [PASSED] drm_connector_dynamic_init ============
[05:28:58] ==== drm_connector_dynamic_register_early (4 subtests) =====
[05:28:58] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[05:28:58] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[05:28:58] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[05:28:58] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[05:28:58] ====== [PASSED] drm_connector_dynamic_register_early =======
[05:28:58] ======= drm_connector_dynamic_register (7 subtests) ========
[05:28:58] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[05:28:58] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[05:28:58] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[05:28:58] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[05:28:58] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[05:28:58] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[05:28:58] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[05:28:58] ========= [PASSED] drm_connector_dynamic_register ==========
[05:28:58] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[05:28:58] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[05:28:58] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[05:28:58] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[05:28:58] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[05:28:58] ========== drm_test_get_tv_mode_from_name_valid  ===========
[05:28:58] [PASSED] NTSC
[05:28:58] [PASSED] NTSC-443
[05:28:58] [PASSED] NTSC-J
[05:28:58] [PASSED] PAL
[05:28:58] [PASSED] PAL-M
[05:28:58] [PASSED] PAL-N
[05:28:58] [PASSED] SECAM
[05:28:58] [PASSED] Mono
[05:28:58] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[05:28:58] [PASSED] drm_test_get_tv_mode_from_name_truncated
[05:28:58] ============ [PASSED] drm_get_tv_mode_from_name ============
[05:28:58] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[05:28:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[05:28:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[05:28:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[05:28:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[05:28:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[05:28:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[05:28:58] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[05:28:58] [PASSED] VIC 96
[05:28:58] [PASSED] VIC 97
[05:28:58] [PASSED] VIC 101
[05:28:58] [PASSED] VIC 102
[05:28:58] [PASSED] VIC 106
[05:28:58] [PASSED] VIC 107
[05:28:58] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[05:28:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[05:28:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[05:28:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[05:28:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[05:28:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[05:28:58] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[05:28:58] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[05:28:58] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[05:28:58] [PASSED] Automatic
[05:28:58] [PASSED] Full
[05:28:58] [PASSED] Limited 16:235
[05:28:58] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[05:28:58] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[05:28:58] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[05:28:58] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[05:28:58] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[05:28:58] [PASSED] RGB
[05:28:58] [PASSED] YUV 4:2:0
[05:28:58] [PASSED] YUV 4:2:2
[05:28:58] [PASSED] YUV 4:4:4
[05:28:58] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[05:28:58] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[05:28:58] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[05:28:58] ============= drm_damage_helper (21 subtests) ==============
[05:28:58] [PASSED] drm_test_damage_iter_no_damage
[05:28:58] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[05:28:58] [PASSED] drm_test_damage_iter_no_damage_src_moved
[05:28:58] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[05:28:58] [PASSED] drm_test_damage_iter_no_damage_not_visible
[05:28:58] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[05:28:58] [PASSED] drm_test_damage_iter_no_damage_no_fb
[05:28:58] [PASSED] drm_test_damage_iter_simple_damage
[05:28:58] [PASSED] drm_test_damage_iter_single_damage
[05:28:58] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[05:28:58] [PASSED] drm_test_damage_iter_single_damage_outside_src
[05:28:58] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[05:28:58] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[05:28:58] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[05:28:58] [PASSED] drm_test_damage_iter_single_damage_src_moved
[05:28:58] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[05:28:58] [PASSED] drm_test_damage_iter_damage
[05:28:58] [PASSED] drm_test_damage_iter_damage_one_intersect
[05:28:58] [PASSED] drm_test_damage_iter_damage_one_outside
[05:28:58] [PASSED] drm_test_damage_iter_damage_src_moved
[05:28:58] [PASSED] drm_test_damage_iter_damage_not_visible
[05:28:58] ================ [PASSED] drm_damage_helper ================
[05:28:58] ============== drm_dp_mst_helper (3 subtests) ==============
[05:28:58] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[05:28:58] [PASSED] Clock 154000 BPP 30 DSC disabled
[05:28:58] [PASSED] Clock 234000 BPP 30 DSC disabled
[05:28:58] [PASSED] Clock 297000 BPP 24 DSC disabled
[05:28:58] [PASSED] Clock 332880 BPP 24 DSC enabled
[05:28:58] [PASSED] Clock 324540 BPP 24 DSC enabled
[05:28:58] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[05:28:58] ============== drm_test_dp_mst_calc_pbn_div  ===============
[05:28:58] [PASSED] Link rate 2000000 lane count 4
[05:28:58] [PASSED] Link rate 2000000 lane count 2
[05:28:58] [PASSED] Link rate 2000000 lane count 1
[05:28:58] [PASSED] Link rate 1350000 lane count 4
[05:28:58] [PASSED] Link rate 1350000 lane count 2
[05:28:58] [PASSED] Link rate 1350000 lane count 1
[05:28:58] [PASSED] Link rate 1000000 lane count 4
[05:28:58] [PASSED] Link rate 1000000 lane count 2
[05:28:58] [PASSED] Link rate 1000000 lane count 1
[05:28:58] [PASSED] Link rate 810000 lane count 4
[05:28:58] [PASSED] Link rate 810000 lane count 2
[05:28:58] [PASSED] Link rate 810000 lane count 1
[05:28:58] [PASSED] Link rate 540000 lane count 4
[05:28:58] [PASSED] Link rate 540000 lane count 2
[05:28:58] [PASSED] Link rate 540000 lane count 1
[05:28:58] [PASSED] Link rate 270000 lane count 4
[05:28:58] [PASSED] Link rate 270000 lane count 2
[05:28:58] [PASSED] Link rate 270000 lane count 1
[05:28:58] [PASSED] Link rate 162000 lane count 4
[05:28:58] [PASSED] Link rate 162000 lane count 2
[05:28:58] [PASSED] Link rate 162000 lane count 1
[05:28:58] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[05:28:58] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[05:28:58] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[05:28:58] [PASSED] DP_POWER_UP_PHY with port number
[05:28:58] [PASSED] DP_POWER_DOWN_PHY with port number
[05:28:58] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[05:28:58] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[05:28:58] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[05:28:58] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[05:28:58] [PASSED] DP_QUERY_PAYLOAD with port number
[05:28:58] [PASSED] DP_QUERY_PAYLOAD with VCPI
[05:28:58] [PASSED] DP_REMOTE_DPCD_READ with port number
[05:28:58] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[05:28:58] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[05:28:58] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[05:28:58] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[05:28:58] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[05:28:58] [PASSED] DP_REMOTE_I2C_READ with port number
[05:28:58] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[05:28:58] [PASSED] DP_REMOTE_I2C_READ with transactions array
[05:28:58] [PASSED] DP_REMOTE_I2C_WRITE with port number
[05:28:58] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[05:28:58] [PASSED] DP_REMOTE_I2C_WRITE with data array
[05:28:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[05:28:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[05:28:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[05:28:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[05:28:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[05:28:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[05:28:58] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[05:28:58] ================ [PASSED] drm_dp_mst_helper ================
[05:28:58] ================== drm_exec (7 subtests) ===================
[05:28:58] [PASSED] sanitycheck
[05:28:58] [PASSED] test_lock
[05:28:58] [PASSED] test_lock_unlock
[05:28:58] [PASSED] test_duplicates
[05:28:58] [PASSED] test_prepare
[05:28:58] [PASSED] test_prepare_array
[05:28:58] [PASSED] test_multiple_loops
[05:28:58] ==================== [PASSED] drm_exec =====================
[05:28:58] =========== drm_format_helper_test (17 subtests) ===========
[05:28:58] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[05:28:58] [PASSED] single_pixel_source_buffer
[05:28:58] [PASSED] single_pixel_clip_rectangle
[05:28:58] [PASSED] well_known_colors
[05:28:58] [PASSED] destination_pitch
[05:28:58] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[05:28:58] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[05:28:58] [PASSED] single_pixel_source_buffer
[05:28:58] [PASSED] single_pixel_clip_rectangle
[05:28:58] [PASSED] well_known_colors
[05:28:58] [PASSED] destination_pitch
[05:28:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[05:28:58] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[05:28:58] [PASSED] single_pixel_source_buffer
[05:28:58] [PASSED] single_pixel_clip_rectangle
[05:28:58] [PASSED] well_known_colors
[05:28:58] [PASSED] destination_pitch
[05:28:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[05:28:58] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[05:28:58] [PASSED] single_pixel_source_buffer
[05:28:58] [PASSED] single_pixel_clip_rectangle
[05:28:58] [PASSED] well_known_colors
[05:28:58] [PASSED] destination_pitch
[05:28:58] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[05:28:58] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[05:28:58] [PASSED] single_pixel_source_buffer
[05:28:58] [PASSED] single_pixel_clip_rectangle
[05:28:58] [PASSED] well_known_colors
[05:28:58] [PASSED] destination_pitch
[05:28:58] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[05:28:58] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[05:28:58] [PASSED] single_pixel_source_buffer
[05:28:58] [PASSED] single_pixel_clip_rectangle
[05:28:58] [PASSED] well_known_colors
[05:28:58] [PASSED] destination_pitch
[05:28:58] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[05:28:58] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[05:28:58] [PASSED] single_pixel_source_buffer
[05:28:58] [PASSED] single_pixel_clip_rectangle
[05:28:58] [PASSED] well_known_colors
[05:28:58] [PASSED] destination_pitch
[05:28:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[05:28:58] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[05:28:58] [PASSED] single_pixel_source_buffer
[05:28:58] [PASSED] single_pixel_clip_rectangle
[05:28:58] [PASSED] well_known_colors
[05:28:58] [PASSED] destination_pitch
[05:28:58] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[05:28:58] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[05:28:58] [PASSED] single_pixel_source_buffer
[05:28:58] [PASSED] single_pixel_clip_rectangle
[05:28:58] [PASSED] well_known_colors
[05:28:58] [PASSED] destination_pitch
[05:28:58] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[05:28:58] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[05:28:58] [PASSED] single_pixel_source_buffer
[05:28:58] [PASSED] single_pixel_clip_rectangle
[05:28:58] [PASSED] well_known_colors
[05:28:58] [PASSED] destination_pitch
[05:28:58] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[05:28:58] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[05:28:58] [PASSED] single_pixel_source_buffer
[05:28:58] [PASSED] single_pixel_clip_rectangle
[05:28:58] [PASSED] well_known_colors
[05:28:58] [PASSED] destination_pitch
[05:28:58] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[05:28:58] ============== drm_test_fb_xrgb8888_to_mono  ===============
[05:28:58] [PASSED] single_pixel_source_buffer
[05:28:58] [PASSED] single_pixel_clip_rectangle
[05:28:58] [PASSED] well_known_colors
[05:28:58] [PASSED] destination_pitch
[05:28:58] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[05:28:58] ==================== drm_test_fb_swab  =====================
[05:28:58] [PASSED] single_pixel_source_buffer
[05:28:58] [PASSED] single_pixel_clip_rectangle
[05:28:58] [PASSED] well_known_colors
[05:28:58] [PASSED] destination_pitch
[05:28:58] ================ [PASSED] drm_test_fb_swab =================
[05:28:58] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[05:28:58] [PASSED] single_pixel_source_buffer
[05:28:58] [PASSED] single_pixel_clip_rectangle
[05:28:58] [PASSED] well_known_colors
[05:28:58] [PASSED] destination_pitch
[05:28:58] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[05:28:58] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[05:28:58] [PASSED] single_pixel_source_buffer
[05:28:58] [PASSED] single_pixel_clip_rectangle
[05:28:58] [PASSED] well_known_colors
[05:28:58] [PASSED] destination_pitch
[05:28:58] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[05:28:58] ================= drm_test_fb_clip_offset  =================
[05:28:58] [PASSED] pass through
[05:28:58] [PASSED] horizontal offset
[05:28:58] [PASSED] vertical offset
[05:28:58] [PASSED] horizontal and vertical offset
[05:28:58] [PASSED] horizontal offset (custom pitch)
[05:28:58] [PASSED] vertical offset (custom pitch)
[05:28:58] [PASSED] horizontal and vertical offset (custom pitch)
[05:28:58] ============= [PASSED] drm_test_fb_clip_offset =============
[05:28:58] =================== drm_test_fb_memcpy  ====================
[05:28:58] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[05:28:58] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[05:28:58] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[05:28:58] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[05:28:58] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[05:28:58] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[05:28:58] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[05:28:58] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[05:28:58] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[05:28:58] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[05:28:58] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[05:28:58] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[05:28:58] =============== [PASSED] drm_test_fb_memcpy ================
[05:28:58] ============= [PASSED] drm_format_helper_test ==============
[05:28:58] ================= drm_format (18 subtests) =================
[05:28:58] [PASSED] drm_test_format_block_width_invalid
[05:28:58] [PASSED] drm_test_format_block_width_one_plane
[05:28:58] [PASSED] drm_test_format_block_width_two_plane
[05:28:58] [PASSED] drm_test_format_block_width_three_plane
[05:28:58] [PASSED] drm_test_format_block_width_tiled
[05:28:58] [PASSED] drm_test_format_block_height_invalid
[05:28:58] [PASSED] drm_test_format_block_height_one_plane
[05:28:58] [PASSED] drm_test_format_block_height_two_plane
[05:28:58] [PASSED] drm_test_format_block_height_three_plane
[05:28:58] [PASSED] drm_test_format_block_height_tiled
[05:28:58] [PASSED] drm_test_format_min_pitch_invalid
[05:28:58] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[05:28:58] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[05:28:58] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[05:28:58] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[05:28:58] [PASSED] drm_test_format_min_pitch_two_plane
[05:28:58] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[05:28:58] [PASSED] drm_test_format_min_pitch_tiled
[05:28:58] =================== [PASSED] drm_format ====================
[05:28:58] ============== drm_framebuffer (10 subtests) ===============
[05:28:58] ========== drm_test_framebuffer_check_src_coords  ==========
[05:28:58] [PASSED] Success: source fits into fb
[05:28:58] [PASSED] Fail: overflowing fb with x-axis coordinate
[05:28:58] [PASSED] Fail: overflowing fb with y-axis coordinate
[05:28:58] [PASSED] Fail: overflowing fb with source width
[05:28:58] [PASSED] Fail: overflowing fb with source height
[05:28:58] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[05:28:58] [PASSED] drm_test_framebuffer_cleanup
[05:28:58] =============== drm_test_framebuffer_create  ===============
[05:28:58] [PASSED] ABGR8888 normal sizes
[05:28:58] [PASSED] ABGR8888 max sizes
[05:28:58] [PASSED] ABGR8888 pitch greater than min required
[05:28:58] [PASSED] ABGR8888 pitch less than min required
[05:28:58] [PASSED] ABGR8888 Invalid width
[05:28:58] [PASSED] ABGR8888 Invalid buffer handle
[05:28:58] [PASSED] No pixel format
[05:28:58] [PASSED] ABGR8888 Width 0
[05:28:58] [PASSED] ABGR8888 Height 0
[05:28:58] [PASSED] ABGR8888 Out of bound height * pitch combination
[05:28:58] [PASSED] ABGR8888 Large buffer offset
[05:28:58] [PASSED] ABGR8888 Buffer offset for inexistent plane
[05:28:58] [PASSED] ABGR8888 Invalid flag
[05:28:58] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[05:28:58] [PASSED] ABGR8888 Valid buffer modifier
[05:28:58] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[05:28:58] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[05:28:58] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[05:28:58] [PASSED] NV12 Normal sizes
[05:28:58] [PASSED] NV12 Max sizes
[05:28:58] [PASSED] NV12 Invalid pitch
[05:28:58] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[05:28:58] [PASSED] NV12 different  modifier per-plane
[05:28:58] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[05:28:58] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[05:28:58] [PASSED] NV12 Modifier for inexistent plane
[05:28:58] [PASSED] NV12 Handle for inexistent plane
[05:28:58] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[05:28:58] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[05:28:58] [PASSED] YVU420 Normal sizes
[05:28:58] [PASSED] YVU420 Max sizes
[05:28:58] [PASSED] YVU420 Invalid pitch
[05:28:58] [PASSED] YVU420 Different pitches
[05:28:58] [PASSED] YVU420 Different buffer offsets/pitches
[05:28:58] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[05:28:58] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[05:28:58] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[05:28:58] [PASSED] YVU420 Valid modifier
[05:28:58] [PASSED] YVU420 Different modifiers per plane
[05:28:58] [PASSED] YVU420 Modifier for inexistent plane
[05:28:58] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[05:28:58] [PASSED] X0L2 Normal sizes
[05:28:58] [PASSED] X0L2 Max sizes
[05:28:58] [PASSED] X0L2 Invalid pitch
[05:28:58] [PASSED] X0L2 Pitch greater than minimum required
[05:28:58] [PASSED] X0L2 Handle for inexistent plane
[05:28:58] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[05:28:58] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[05:28:58] [PASSED] X0L2 Valid modifier
[05:28:58] [PASSED] X0L2 Modifier for inexistent plane
[05:28:58] =========== [PASSED] drm_test_framebuffer_create ===========
[05:28:58] [PASSED] drm_test_framebuffer_free
[05:28:58] [PASSED] drm_test_framebuffer_init
[05:28:58] [PASSED] drm_test_framebuffer_init_bad_format
[05:28:58] [PASSED] drm_test_framebuffer_init_dev_mismatch
[05:28:58] [PASSED] drm_test_framebuffer_lookup
[05:28:58] [PASSED] drm_test_framebuffer_lookup_inexistent
[05:28:58] [PASSED] drm_test_framebuffer_modifiers_not_supported
[05:28:58] ================= [PASSED] drm_framebuffer =================
[05:28:58] ================ drm_gem_shmem (8 subtests) ================
[05:28:58] [PASSED] drm_gem_shmem_test_obj_create
[05:28:58] [PASSED] drm_gem_shmem_test_obj_create_private
[05:28:58] [PASSED] drm_gem_shmem_test_pin_pages
[05:28:58] [PASSED] drm_gem_shmem_test_vmap
[05:28:58] [PASSED] drm_gem_shmem_test_get_pages_sgt
[05:28:58] [PASSED] drm_gem_shmem_test_get_sg_table
[05:28:58] [PASSED] drm_gem_shmem_test_madvise
[05:28:58] [PASSED] drm_gem_shmem_test_purge
[05:28:58] ================== [PASSED] drm_gem_shmem ==================
[05:28:58] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[05:28:58] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[05:28:58] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[05:28:58] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[05:28:58] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[05:28:58] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[05:28:58] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[05:28:58] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[05:28:58] [PASSED] Automatic
[05:28:58] [PASSED] Full
[05:28:58] [PASSED] Limited 16:235
[05:28:58] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[05:28:58] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[05:28:58] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[05:28:58] [PASSED] drm_test_check_disable_connector
[05:28:58] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[05:28:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[05:28:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[05:28:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[05:28:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[05:28:58] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[05:28:58] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[05:28:58] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[05:28:58] [PASSED] drm_test_check_output_bpc_dvi
[05:28:58] [PASSED] drm_test_check_output_bpc_format_vic_1
[05:28:58] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[05:28:58] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[05:28:58] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[05:28:58] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[05:28:58] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[05:28:58] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[05:28:58] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[05:28:58] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[05:28:58] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[05:28:58] [PASSED] drm_test_check_broadcast_rgb_value
[05:28:58] [PASSED] drm_test_check_bpc_8_value
[05:28:58] [PASSED] drm_test_check_bpc_10_value
[05:28:58] [PASSED] drm_test_check_bpc_12_value
[05:28:58] [PASSED] drm_test_check_format_value
[05:28:58] [PASSED] drm_test_check_tmds_char_value
[05:28:58] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[05:28:58] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[05:28:58] [PASSED] drm_test_check_mode_valid
[05:28:58] [PASSED] drm_test_check_mode_valid_reject
[05:28:58] [PASSED] drm_test_check_mode_valid_reject_rate
[05:28:58] [PASSED] drm_test_check_mode_valid_reject_max_clock
[05:28:58] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[05:28:58] ================= drm_managed (2 subtests) =================
[05:28:58] [PASSED] drm_test_managed_release_action
[05:28:58] [PASSED] drm_test_managed_run_action
[05:28:58] =================== [PASSED] drm_managed ===================
[05:28:58] =================== drm_mm (6 subtests) ====================
[05:28:58] [PASSED] drm_test_mm_init
[05:28:58] [PASSED] drm_test_mm_debug
[05:28:58] [PASSED] drm_test_mm_align32
[05:28:58] [PASSED] drm_test_mm_align64
[05:28:58] [PASSED] drm_test_mm_lowest
[05:28:58] [PASSED] drm_test_mm_highest
[05:28:58] ===================== [PASSED] drm_mm ======================
[05:28:58] ============= drm_modes_analog_tv (5 subtests) =============
[05:28:58] [PASSED] drm_test_modes_analog_tv_mono_576i
[05:28:58] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[05:28:58] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[05:28:58] [PASSED] drm_test_modes_analog_tv_pal_576i
[05:28:58] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[05:28:58] =============== [PASSED] drm_modes_analog_tv ===============
[05:28:58] ============== drm_plane_helper (2 subtests) ===============
[05:28:58] =============== drm_test_check_plane_state  ================
[05:28:58] [PASSED] clipping_simple
[05:28:58] [PASSED] clipping_rotate_reflect
[05:28:58] [PASSED] positioning_simple
[05:28:58] [PASSED] upscaling
[05:28:58] [PASSED] downscaling
[05:28:58] [PASSED] rounding1
[05:28:58] [PASSED] rounding2
[05:28:58] [PASSED] rounding3
[05:28:58] [PASSED] rounding4
[05:28:58] =========== [PASSED] drm_test_check_plane_state ============
[05:28:58] =========== drm_test_check_invalid_plane_state  ============
[05:28:58] [PASSED] positioning_invalid
[05:28:58] [PASSED] upscaling_invalid
[05:28:58] [PASSED] downscaling_invalid
[05:28:58] ======= [PASSED] drm_test_check_invalid_plane_state ========
[05:28:58] ================ [PASSED] drm_plane_helper =================
[05:28:58] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[05:28:58] ====== drm_test_connector_helper_tv_get_modes_check  =======
[05:28:58] [PASSED] None
[05:28:58] [PASSED] PAL
[05:28:58] [PASSED] NTSC
[05:28:58] [PASSED] Both, NTSC Default
[05:28:58] [PASSED] Both, PAL Default
[05:28:58] [PASSED] Both, NTSC Default, with PAL on command-line
[05:28:58] [PASSED] Both, PAL Default, with NTSC on command-line
[05:28:58] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[05:28:58] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[05:28:58] ================== drm_rect (9 subtests) ===================
[05:28:58] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[05:28:58] [PASSED] drm_test_rect_clip_scaled_not_clipped
[05:28:58] [PASSED] drm_test_rect_clip_scaled_clipped
[05:28:58] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[05:28:58] ================= drm_test_rect_intersect  =================
[05:28:58] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[05:28:58] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[05:28:58] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[05:28:58] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[05:28:58] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[05:28:58] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[05:28:58] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[05:28:58] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[05:28:58] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[05:28:58] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[05:28:58] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[05:28:58] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[05:28:58] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[05:28:58] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[05:28:58] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[05:28:58] ============= [PASSED] drm_test_rect_intersect =============
[05:28:58] ================ drm_test_rect_calc_hscale  ================
[05:28:58] [PASSED] normal use
[05:28:58] [PASSED] out of max range
[05:28:58] [PASSED] out of min range
[05:28:58] [PASSED] zero dst
[05:28:58] [PASSED] negative src
[05:28:58] [PASSED] negative dst
[05:28:58] ============ [PASSED] drm_test_rect_calc_hscale ============
[05:28:58] ================ drm_test_rect_calc_vscale  ================
[05:28:58] [PASSED] normal use
[05:28:58] [PASSED] out of max range
[05:28:58] [PASSED] out of min range
[05:28:58] [PASSED] zero dst
[05:28:58] [PASSED] negative src
[05:28:58] [PASSED] negative dst
[05:28:58] ============ [PASSED] drm_test_rect_calc_vscale ============
[05:28:58] ================== drm_test_rect_rotate  ===================
[05:28:58] [PASSED] reflect-x
[05:28:58] [PASSED] reflect-y
[05:28:58] [PASSED] rotate-0
[05:28:58] [PASSED] rotate-90
[05:28:58] [PASSED] rotate-180
[05:28:58] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[05:28:58] ============== [PASSED] drm_test_rect_rotate ===============
[05:28:58] ================ drm_test_rect_rotate_inv  =================
[05:28:58] [PASSED] reflect-x
[05:28:58] [PASSED] reflect-y
[05:28:58] [PASSED] rotate-0
[05:28:58] [PASSED] rotate-90
[05:28:58] [PASSED] rotate-180
[05:28:58] [PASSED] rotate-270
[05:28:58] ============ [PASSED] drm_test_rect_rotate_inv =============
[05:28:58] ==================== [PASSED] drm_rect =====================
[05:28:58] ============ drm_sysfb_modeset_test (1 subtest) ============
[05:28:58] ============ drm_test_sysfb_build_fourcc_list  =============
[05:28:58] [PASSED] no native formats
[05:28:58] [PASSED] XRGB8888 as native format
[05:28:58] [PASSED] remove duplicates
[05:28:58] [PASSED] convert alpha formats
[05:28:58] [PASSED] random formats
[05:28:58] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[05:28:58] ============= [PASSED] drm_sysfb_modeset_test ==============
[05:28:58] ============================================================
[05:28:58] Testing complete. Ran 616 tests: passed: 616
[05:28:58] Elapsed time: 23.351s total, 1.709s configuring, 21.470s building, 0.143s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[05:28:58] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:29:00] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:29:08] Starting KUnit Kernel (1/1)...
[05:29:08] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:29:08] ================= ttm_device (5 subtests) ==================
[05:29:08] [PASSED] ttm_device_init_basic
[05:29:08] [PASSED] ttm_device_init_multiple
[05:29:08] [PASSED] ttm_device_fini_basic
[05:29:08] [PASSED] ttm_device_init_no_vma_man
[05:29:08] ================== ttm_device_init_pools  ==================
[05:29:08] [PASSED] No DMA allocations, no DMA32 required
[05:29:08] [PASSED] DMA allocations, DMA32 required
[05:29:08] [PASSED] No DMA allocations, DMA32 required
[05:29:08] [PASSED] DMA allocations, no DMA32 required
[05:29:08] ============== [PASSED] ttm_device_init_pools ==============
[05:29:08] =================== [PASSED] ttm_device ====================
[05:29:08] ================== ttm_pool (8 subtests) ===================
[05:29:08] ================== ttm_pool_alloc_basic  ===================
[05:29:08] [PASSED] One page
[05:29:08] [PASSED] More than one page
[05:29:08] [PASSED] Above the allocation limit
[05:29:08] [PASSED] One page, with coherent DMA mappings enabled
[05:29:08] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:29:08] ============== [PASSED] ttm_pool_alloc_basic ===============
[05:29:08] ============== ttm_pool_alloc_basic_dma_addr  ==============
[05:29:08] [PASSED] One page
[05:29:08] [PASSED] More than one page
[05:29:08] [PASSED] Above the allocation limit
[05:29:08] [PASSED] One page, with coherent DMA mappings enabled
[05:29:08] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:29:08] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[05:29:08] [PASSED] ttm_pool_alloc_order_caching_match
[05:29:08] [PASSED] ttm_pool_alloc_caching_mismatch
[05:29:08] [PASSED] ttm_pool_alloc_order_mismatch
[05:29:08] [PASSED] ttm_pool_free_dma_alloc
[05:29:08] [PASSED] ttm_pool_free_no_dma_alloc
[05:29:08] [PASSED] ttm_pool_fini_basic
[05:29:08] ==================== [PASSED] ttm_pool =====================
[05:29:08] ================ ttm_resource (8 subtests) =================
[05:29:08] ================= ttm_resource_init_basic  =================
[05:29:08] [PASSED] Init resource in TTM_PL_SYSTEM
[05:29:08] [PASSED] Init resource in TTM_PL_VRAM
[05:29:08] [PASSED] Init resource in a private placement
[05:29:08] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[05:29:08] ============= [PASSED] ttm_resource_init_basic =============
[05:29:08] [PASSED] ttm_resource_init_pinned
[05:29:08] [PASSED] ttm_resource_fini_basic
[05:29:08] [PASSED] ttm_resource_manager_init_basic
[05:29:08] [PASSED] ttm_resource_manager_usage_basic
[05:29:08] [PASSED] ttm_resource_manager_set_used_basic
[05:29:08] [PASSED] ttm_sys_man_alloc_basic
[05:29:08] [PASSED] ttm_sys_man_free_basic
[05:29:08] ================== [PASSED] ttm_resource ===================
[05:29:08] =================== ttm_tt (15 subtests) ===================
[05:29:08] ==================== ttm_tt_init_basic  ====================
[05:29:08] [PASSED] Page-aligned size
[05:29:08] [PASSED] Extra pages requested
[05:29:08] ================ [PASSED] ttm_tt_init_basic ================
[05:29:08] [PASSED] ttm_tt_init_misaligned
[05:29:08] [PASSED] ttm_tt_fini_basic
[05:29:08] [PASSED] ttm_tt_fini_sg
[05:29:08] [PASSED] ttm_tt_fini_shmem
[05:29:08] [PASSED] ttm_tt_create_basic
[05:29:08] [PASSED] ttm_tt_create_invalid_bo_type
[05:29:08] [PASSED] ttm_tt_create_ttm_exists
[05:29:08] [PASSED] ttm_tt_create_failed
[05:29:08] [PASSED] ttm_tt_destroy_basic
[05:29:08] [PASSED] ttm_tt_populate_null_ttm
[05:29:08] [PASSED] ttm_tt_populate_populated_ttm
[05:29:08] [PASSED] ttm_tt_unpopulate_basic
[05:29:08] [PASSED] ttm_tt_unpopulate_empty_ttm
[05:29:08] [PASSED] ttm_tt_swapin_basic
[05:29:08] ===================== [PASSED] ttm_tt ======================
[05:29:08] =================== ttm_bo (14 subtests) ===================
[05:29:08] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[05:29:08] [PASSED] Cannot be interrupted and sleeps
[05:29:08] [PASSED] Cannot be interrupted, locks straight away
[05:29:08] [PASSED] Can be interrupted, sleeps
[05:29:08] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[05:29:08] [PASSED] ttm_bo_reserve_locked_no_sleep
[05:29:08] [PASSED] ttm_bo_reserve_no_wait_ticket
[05:29:08] [PASSED] ttm_bo_reserve_double_resv
[05:29:08] [PASSED] ttm_bo_reserve_interrupted
[05:29:08] [PASSED] ttm_bo_reserve_deadlock
[05:29:08] [PASSED] ttm_bo_unreserve_basic
[05:29:08] [PASSED] ttm_bo_unreserve_pinned
[05:29:08] [PASSED] ttm_bo_unreserve_bulk
[05:29:08] [PASSED] ttm_bo_put_basic
[05:29:08] [PASSED] ttm_bo_put_shared_resv
[05:29:08] [PASSED] ttm_bo_pin_basic
[05:29:08] [PASSED] ttm_bo_pin_unpin_resource
[05:29:08] [PASSED] ttm_bo_multiple_pin_one_unpin
[05:29:08] ===================== [PASSED] ttm_bo ======================
[05:29:08] ============== ttm_bo_validate (21 subtests) ===============
[05:29:08] ============== ttm_bo_init_reserved_sys_man  ===============
[05:29:08] [PASSED] Buffer object for userspace
[05:29:08] [PASSED] Kernel buffer object
[05:29:08] [PASSED] Shared buffer object
[05:29:08] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[05:29:08] ============== ttm_bo_init_reserved_mock_man  ==============
[05:29:08] [PASSED] Buffer object for userspace
[05:29:08] [PASSED] Kernel buffer object
[05:29:08] [PASSED] Shared buffer object
[05:29:08] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[05:29:08] [PASSED] ttm_bo_init_reserved_resv
[05:29:08] ================== ttm_bo_validate_basic  ==================
[05:29:08] [PASSED] Buffer object for userspace
[05:29:08] [PASSED] Kernel buffer object
[05:29:08] [PASSED] Shared buffer object
[05:29:08] ============== [PASSED] ttm_bo_validate_basic ==============
[05:29:08] [PASSED] ttm_bo_validate_invalid_placement
[05:29:08] ============= ttm_bo_validate_same_placement  ==============
[05:29:08] [PASSED] System manager
[05:29:08] [PASSED] VRAM manager
[05:29:08] ========= [PASSED] ttm_bo_validate_same_placement ==========
[05:29:08] [PASSED] ttm_bo_validate_failed_alloc
[05:29:08] [PASSED] ttm_bo_validate_pinned
[05:29:08] [PASSED] ttm_bo_validate_busy_placement
[05:29:08] ================ ttm_bo_validate_multihop  =================
[05:29:08] [PASSED] Buffer object for userspace
[05:29:08] [PASSED] Kernel buffer object
[05:29:08] [PASSED] Shared buffer object
[05:29:08] ============ [PASSED] ttm_bo_validate_multihop =============
[05:29:08] ========== ttm_bo_validate_no_placement_signaled  ==========
[05:29:08] [PASSED] Buffer object in system domain, no page vector
[05:29:08] [PASSED] Buffer object in system domain with an existing page vector
[05:29:08] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[05:29:08] ======== ttm_bo_validate_no_placement_not_signaled  ========
[05:29:08] [PASSED] Buffer object for userspace
[05:29:08] [PASSED] Kernel buffer object
[05:29:08] [PASSED] Shared buffer object
[05:29:08] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[05:29:08] [PASSED] ttm_bo_validate_move_fence_signaled
[05:29:08] ========= ttm_bo_validate_move_fence_not_signaled  =========
[05:29:08] [PASSED] Waits for GPU
[05:29:08] [PASSED] Tries to lock straight away
[05:29:08] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[05:29:08] [PASSED] ttm_bo_validate_happy_evict
[05:29:08] [PASSED] ttm_bo_validate_all_pinned_evict
[05:29:08] [PASSED] ttm_bo_validate_allowed_only_evict
[05:29:08] [PASSED] ttm_bo_validate_deleted_evict
[05:29:08] [PASSED] ttm_bo_validate_busy_domain_evict
[05:29:08] [PASSED] ttm_bo_validate_evict_gutting
[05:29:08] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[05:29:08] ================= [PASSED] ttm_bo_validate =================
[05:29:08] ============================================================
[05:29:08] Testing complete. Ran 101 tests: passed: 101
[05:29:08] Elapsed time: 9.602s total, 1.673s configuring, 7.713s building, 0.187s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for Wait PSR idle before on dsb commit (rev2)

[Patchwork]

== Series Details ==

Series: Wait PSR idle before on dsb commit (rev2)
URL   : https://patchwork.freedesktop.org/series/152470/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast b61343d3704885afd253795a1e1084febbf7f354
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2018:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2018:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2018:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2018:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2018:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2018:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2018:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2018:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2018:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2018:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2031:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2031:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Wait PSR idle before on dsb commit (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1459 bytes --]

== Series Details ==

Series: Wait PSR idle before on dsb commit (rev2)
URL   : https://patchwork.freedesktop.org/series/152470/
State : success

== Summary ==

CI Bug Log - changes from xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c_BAT -> xe-pw-152470v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (8 -> 7)
------------------------------

  Missing    (1): bat-adlp-vm 

Known issues
------------

  Here are the changes found in xe-pw-152470v2_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@kms_flip@basic-plain-flip@c-edp1:
    - bat-adlp-7:         [DMESG-WARN][1] ([Intel XE#4543]) -> [PASS][2] +1 other test pass
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/bat-adlp-7/igt@kms_flip@basic-plain-flip@c-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/bat-adlp-7/igt@kms_flip@basic-plain-flip@c-edp1.html

  
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543


Build changes
-------------

  * Linux: xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c -> xe-pw-152470v2

  IGT_8487: 8487
  xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c: 7b7457e249a1f7db97122bc6b9384e5e2f45475c
  xe-pw-152470v2: 152470v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/index.html

[-- Attachment #2: Type: text/html, Size: 2024 bytes --]

✗ Xe.CI.Full: failure for Wait PSR idle before on dsb commit (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 31598 bytes --]

== Series Details ==

Series: Wait PSR idle before on dsb commit (rev2)
URL   : https://patchwork.freedesktop.org/series/152470/
State : failure

== Summary ==

CI Bug Log - changes from xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c_FULL -> xe-pw-152470v2_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-152470v2_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-152470v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-152470v2_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_exec_system_allocator@process-many-large-execqueues-malloc-bo-unmap-nomemset:
    - shard-bmg:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-5/igt@xe_exec_system_allocator@process-many-large-execqueues-malloc-bo-unmap-nomemset.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-5/igt@xe_exec_system_allocator@process-many-large-execqueues-malloc-bo-unmap-nomemset.html

  
Known issues
------------

  Here are the changes found in xe-pw-152470v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][3] ([Intel XE#316]) +1 other test skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-464/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-dg2-set2:     NOTRUN -> [SKIP][4] ([Intel XE#619])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#1124]) +2 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-8/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][6] ([Intel XE#1124]) +4 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-466/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][7] ([Intel XE#2191])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-464/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-1-displays-2560x1440p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][8] ([Intel XE#367])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][9] ([Intel XE#787]) +27 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-dp-4.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][10] ([Intel XE#455] / [Intel XE#787]) +7 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-4.html

  * igt@kms_chamelium_color@ctm-limited-range:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#306]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@kms_chamelium_color@ctm-limited-range.html

  * igt@kms_chamelium_edid@dp-edid-change-during-hibernate:
    - shard-dg2-set2:     NOTRUN -> [SKIP][12] ([Intel XE#373]) +4 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html

  * igt@kms_content_protection@lic-type-0:
    - shard-dg2-set2:     NOTRUN -> [FAIL][13] ([Intel XE#1178])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][14] ([Intel XE#1178])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-4/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][15] ([Intel XE#3304])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@kms_content_protection@lic-type-0@pipe-a-dp-4.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2321])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-8/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-max-size:
    - shard-dg2-set2:     NOTRUN -> [SKIP][17] ([Intel XE#455]) +4 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-466/igt@kms_cursor_crc@cursor-sliding-max-size.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][18] -> [SKIP][19] ([Intel XE#2291]) +4 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-4/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-bmg:          [PASS][20] -> [FAIL][21] ([Intel XE#1475])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][22] -> [FAIL][23] ([Intel XE#4633])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@single-move:
    - shard-dg2-set2:     [PASS][24] -> [DMESG-WARN][25] ([Intel XE#5666]) +1 other test dmesg-warn
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-dg2-463/igt@kms_cursor_legacy@single-move.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-435/igt@kms_cursor_legacy@single-move.html

  * igt@kms_dp_aux_dev:
    - shard-bmg:          [PASS][26] -> [SKIP][27] ([Intel XE#3009])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-4/igt@kms_dp_aux_dev.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-6/igt@kms_dp_aux_dev.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
    - shard-dg2-set2:     NOTRUN -> [SKIP][28] ([Intel XE#4422])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-464/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-adlp:         [PASS][29] -> [DMESG-WARN][30] ([Intel XE#2953] / [Intel XE#4173]) +2 other tests dmesg-warn
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-4/igt@kms_fbcon_fbt@fbc-suspend.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-adlp-9/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_feature_discovery@psr2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][31] ([Intel XE#1135])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-464/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-bmg:          [PASS][32] -> [SKIP][33] ([Intel XE#2316]) +3 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-7/igt@kms_flip@2x-flip-vs-dpms.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@basic-plain-flip@b-hdmi-a1:
    - shard-adlp:         [PASS][34] -> [DMESG-WARN][35] ([Intel XE#4543]) +5 other tests dmesg-warn
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-2/igt@kms_flip@basic-plain-flip@b-hdmi-a1.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-adlp-6/igt@kms_flip@basic-plain-flip@b-hdmi-a1.html

  * igt@kms_flip_tiling@flip-change-tiling:
    - shard-adlp:         [PASS][36] -> [DMESG-FAIL][37] ([Intel XE#4543]) +1 other test dmesg-fail
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-1/igt@kms_flip_tiling@flip-change-tiling.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][38] ([Intel XE#651]) +12 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#2311]) +3 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#2313]) +3 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][41] ([Intel XE#653]) +12 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-dg2-set2:     NOTRUN -> [SKIP][42] ([Intel XE#5020])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-dg2-set2:     NOTRUN -> [SKIP][43] ([Intel XE#870])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][44] ([Intel XE#1489]) +3 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr@psr-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-8/igt@kms_psr@psr-suspend.html

  * igt@kms_psr@psr2-basic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][46] ([Intel XE#2850] / [Intel XE#929]) +5 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-464/igt@kms_psr@psr2-basic.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [PASS][47] -> [FAIL][48] ([Intel XE#4459]) +1 other test fail
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-lnl-1/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-lnl-2/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@xe_compute_preempt@compute-preempt-many:
    - shard-dg2-set2:     NOTRUN -> [SKIP][49] ([Intel XE#1280] / [Intel XE#455]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-466/igt@xe_compute_preempt@compute-preempt-many.html

  * igt@xe_eudebug@basic-connect:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#4837])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-8/igt@xe_eudebug@basic-connect.html

  * igt@xe_eudebug_online@writes-caching-vram-bb-sram-target-sram:
    - shard-dg2-set2:     NOTRUN -> [SKIP][51] ([Intel XE#4837]) +2 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@xe_eudebug_online@writes-caching-vram-bb-sram-target-sram.html

  * igt@xe_exec_fault_mode@once-bindexecqueue-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][52] ([Intel XE#288]) +7 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@xe_exec_fault_mode@once-bindexecqueue-imm.html

  * igt@xe_exec_system_allocator@many-execqueues-mmap-new-huge:
    - shard-dg2-set2:     NOTRUN -> [SKIP][53] ([Intel XE#4915]) +106 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@xe_exec_system_allocator@many-execqueues-mmap-new-huge.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-new-huge:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#4943]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-new-huge.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset:
    - shard-lnl:          [PASS][55] -> [FAIL][56] ([Intel XE#5018])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-lnl-2/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-lnl-1/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html

  * igt@xe_media_fill@media-fill:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#2459] / [Intel XE#2596])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-8/igt@xe_media_fill@media-fill.html

  * igt@xe_oa@disabled-read-error:
    - shard-dg2-set2:     NOTRUN -> [SKIP][58] ([Intel XE#3573]) +2 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@xe_oa@disabled-read-error.html

  * igt@xe_pm@d3cold-i2c:
    - shard-dg2-set2:     NOTRUN -> [SKIP][59] ([Intel XE#5694])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-464/igt@xe_pm@d3cold-i2c.html

  * igt@xe_pxp@display-pxp-fb:
    - shard-dg2-set2:     NOTRUN -> [SKIP][60] ([Intel XE#4733]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@xe_pxp@display-pxp-fb.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#944])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-8/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  
#### Possible fixes ####

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-adlp:         [DMESG-FAIL][62] ([Intel XE#4543]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-adlp-9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][64] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124] / [Intel XE#4345]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][66] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124]) -> [PASS][67]
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
    - shard-bmg:          [SKIP][68] ([Intel XE#2291]) -> [PASS][69] +1 other test pass
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-1/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [FAIL][70] ([Intel XE#4633]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
    - shard-bmg:          [SKIP][72] ([Intel XE#2316]) -> [PASS][73] +1 other test pass
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-1/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html

  * igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][74] ([Intel XE#4543]) -> [PASS][75] +5 other tests pass
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-6/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-adlp-3/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html

  * igt@kms_hdr@static-toggle:
    - shard-bmg:          [SKIP][76] ([Intel XE#1503]) -> [PASS][77] +1 other test pass
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_hdr@static-toggle.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-4/igt@kms_hdr@static-toggle.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-bmg:          [SKIP][78] ([Intel XE#2571]) -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-1/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@kms_setmode@basic:
    - shard-lnl:          [FAIL][80] ([Intel XE#2883]) -> [PASS][81] +1 other test pass
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-lnl-4/igt@kms_setmode@basic.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-lnl-5/igt@kms_setmode@basic.html

  * igt@kms_vblank@query-forked-busy-hang@pipe-a-hdmi-a-1:
    - shard-adlp:         [DMESG-WARN][82] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][83] +2 other tests pass
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-3/igt@kms_vblank@query-forked-busy-hang@pipe-a-hdmi-a-1.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-adlp-9/igt@kms_vblank@query-forked-busy-hang@pipe-a-hdmi-a-1.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset:
    - shard-lnl:          [FAIL][84] ([Intel XE#5018]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-lnl-5/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-lnl-7/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-bo-map-nomemset:
    - shard-bmg:          [FAIL][86] ([Intel XE#4937]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-1/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-bo-map-nomemset.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-7/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-bo-map-nomemset.html

  
#### Warnings ####

  * igt@kms_content_protection@lic-type-0:
    - shard-bmg:          [SKIP][88] ([Intel XE#2341]) -> [FAIL][89] ([Intel XE#1178])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_content_protection@lic-type-0.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-4/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@srm:
    - shard-bmg:          [FAIL][90] ([Intel XE#1178]) -> [SKIP][91] ([Intel XE#2341])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-7/igt@kms_content_protection@srm.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-6/igt@kms_content_protection@srm.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][92] ([Intel XE#2311]) -> [SKIP][93] ([Intel XE#2312]) +9 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][94] ([Intel XE#2312]) -> [SKIP][95] ([Intel XE#2311]) +12 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][96] ([Intel XE#2312]) -> [SKIP][97] ([Intel XE#5390]) +5 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][98] ([Intel XE#5390]) -> [SKIP][99] ([Intel XE#2312]) +6 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][100] ([Intel XE#2313]) -> [SKIP][101] ([Intel XE#2312]) +10 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][102] ([Intel XE#2312]) -> [SKIP][103] ([Intel XE#2313]) +13 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][104] ([Intel XE#1729]) -> [SKIP][105] ([Intel XE#2426])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg2-set2:     [SKIP][106] ([Intel XE#1500]) -> [SKIP][107] ([Intel XE#362])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-dg2-464/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
  [Intel XE#1475]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1475
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
  [Intel XE#2571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2571
  [Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4937
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5018]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5018
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5666]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5666
  [Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
  [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c -> xe-pw-152470v2

  IGT_8487: 8487
  xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c: 7b7457e249a1f7db97122bc6b9384e5e2f45475c
  xe-pw-152470v2: 152470v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152470v2/index.html

[-- Attachment #2: Type: text/html, Size: 36025 bytes --]

RE: [PATCH v2 1/4] drm/i915/psr: Pass intel_crtc_state instead of intel_dp in wait_for_idle

[Kahola, Mika]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Jouni Högander
> Sent: Wednesday, 6 August 2025 8.22
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Hogander, Jouni <jouni.hogander@intel.com>
> Subject: [PATCH v2 1/4] drm/i915/psr: Pass intel_crtc_state instead of intel_dp in wait_for_idle
> 
> This is preparation to add own function for polling PSR being ready for update when doing dsb commit.
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 18 ++++++++++--------
>  1 file changed, 10 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 6bd3454bb00e..c2ab00fe2c20 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2982,10 +2982,11 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
>  	}
>  }
> 
> -static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
> +static int
> +_psr2_ready_for_pipe_update_locked(const struct intel_crtc_state
> +*new_crtc_state)
>  {
> -	struct intel_display *display = to_intel_display(intel_dp);
> -	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> +	struct intel_display *display = to_intel_display(new_crtc_state);
> +	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
> 
>  	/*
>  	 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough.
> @@ -2997,10 +2998,11 @@ static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
>  				       EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50);  }
> 
> -static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
> +static int
> +_psr1_ready_for_pipe_update_locked(const struct intel_crtc_state
> +*new_crtc_state)
>  {
> -	struct intel_display *display = to_intel_display(intel_dp);
> -	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> +	struct intel_display *display = to_intel_display(new_crtc_state);
> +	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
> 
>  	/*
>  	 * From bspec: Panel Self Refresh (BDW+) @@ -3039,9 +3041,9 @@ void intel_psr_wait_for_idle_locked(const struct
> intel_crtc_state *new_crtc_stat
>  			continue;
> 
>  		if (intel_dp->psr.sel_update_enabled)
> -			ret = _psr2_ready_for_pipe_update_locked(intel_dp);
> +			ret = _psr2_ready_for_pipe_update_locked(new_crtc_state);
>  		else
> -			ret = _psr1_ready_for_pipe_update_locked(intel_dp);
> +			ret = _psr1_ready_for_pipe_update_locked(new_crtc_state);
> 
>  		if (ret)
>  			drm_err(display->drm,
> --
> 2.43.0

RE: [PATCH v2 2/4] drm/i915/psr: Add new define for PSR idle timeout

[Kahola, Mika]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Jouni Högander
> Sent: Wednesday, 6 August 2025 8.22
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Hogander, Jouni <jouni.hogander@intel.com>
> Subject: [PATCH v2 2/4] drm/i915/psr: Add new define for PSR idle timeout
> 
> Currently we are using value 50ms as timeout for waiting PSR to idle. Add own define for this purpose.
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 20 ++++++++++++--------
>  1 file changed, 12 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index c2ab00fe2c20..172bc0c39968 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2982,6 +2982,14 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
>  	}
>  }
> 
> +/*
> + * From bspec: Panel Self Refresh (BDW+)
> + * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
> + * exit training time + 1.5 ms of aux channel handshake. 50 ms is
> + * defensive enough to cover everything.
> + */
> +#define PSR_IDLE_TIMEOUT_MS 50
> +
>  static int
>  _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state)  { @@ -2995,7 +3003,8 @@
> _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state
>  	 */
>  	return intel_de_wait_for_clear(display,
>  				       EDP_PSR2_STATUS(display, cpu_transcoder),
> -				       EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50);
> +				       EDP_PSR2_STATUS_STATE_DEEP_SLEEP,
> +				       PSR_IDLE_TIMEOUT_MS);
>  }
> 
>  static int
> @@ -3004,15 +3013,10 @@ _psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state
>  	struct intel_display *display = to_intel_display(new_crtc_state);
>  	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
> 
> -	/*
> -	 * From bspec: Panel Self Refresh (BDW+)
> -	 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
> -	 * exit training time + 1.5 ms of aux channel handshake. 50 ms is
> -	 * defensive enough to cover everything.
> -	 */
>  	return intel_de_wait_for_clear(display,
>  				       psr_status_reg(display, cpu_transcoder),
> -				       EDP_PSR_STATUS_STATE_MASK, 50);
> +				       EDP_PSR_STATUS_STATE_MASK,
> +				       PSR_IDLE_TIMEOUT_MS);
>  }
> 
>  /**
> --
> 2.43.0

Re: [PATCH v2 3/4] drm/i915/psr: New interface adding PSR idle poll into dsb commit

[Ville Syrjälä]

On Wed, Aug 06, 2025 at 08:22:12AM +0300, Jouni Högander wrote:
> We are currently observing crc failures after we started using dsb for PSR
> updates as well. This seems to happen because PSR HW is still sending
> couple of updates using old framebuffers on wake-up.
> 
> This patch is preparing to fix that by adding interface which can be used
> to add poll ensuring PSR HW is idle into dsb commit.
> 
> v2: add pass crtc_state->dsb_commit as parameter
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 40 +++++++++++++++++++++---
>  drivers/gpu/drm/i915/display/intel_psr.h |  1 +
>  2 files changed, 37 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 172bc0c39968..2254dd5a3ac4 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -42,6 +42,7 @@
>  #include "intel_dmc.h"
>  #include "intel_dp.h"
>  #include "intel_dp_aux.h"
> +#include "intel_dsb.h"
>  #include "intel_frontbuffer.h"
>  #include "intel_hdmi.h"
>  #include "intel_psr.h"
> @@ -2991,7 +2992,8 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
>  #define PSR_IDLE_TIMEOUT_MS 50
>  
>  static int
> -_psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state)
> +_psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state,
> +				   struct intel_dsb *dsb)
>  {
>  	struct intel_display *display = to_intel_display(new_crtc_state);
>  	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
> @@ -3001,6 +3003,13 @@ _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state
>  	 * As all higher states has bit 4 of PSR2 state set we can just wait for
>  	 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared.
>  	 */
> +	if (dsb) {
> +		intel_dsb_poll(dsb, EDP_PSR2_STATUS(display, cpu_transcoder),
> +			       EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 0, 200,
> +			       PSR_IDLE_TIMEOUT_MS * 1000 / 200);

The paramters look like they'll fit in the register. We should probably 
add some warns to intel_dsb_poll() to validate that though...

> +		return true;
> +	}
> +
>  	return intel_de_wait_for_clear(display,
>  				       EDP_PSR2_STATUS(display, cpu_transcoder),
>  				       EDP_PSR2_STATUS_STATE_DEEP_SLEEP,
> @@ -3008,11 +3017,19 @@ _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state
>  }
>  
>  static int
> -_psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state)
> +_psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state,
> +				   struct intel_dsb *dsb)
>  {
>  	struct intel_display *display = to_intel_display(new_crtc_state);
>  	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
>  
> +	if (dsb) {
> +		intel_dsb_poll(dsb, psr_status_reg(display, cpu_transcoder),
> +			       EDP_PSR_STATUS_STATE_MASK, 0, 200,
> +			       PSR_IDLE_TIMEOUT_MS * 1000 / 200);
> +		return true;
> +	}
> +
>  	return intel_de_wait_for_clear(display,
>  				       psr_status_reg(display, cpu_transcoder),
>  				       EDP_PSR_STATUS_STATE_MASK,
> @@ -3045,9 +3062,11 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat
>  			continue;
>  
>  		if (intel_dp->psr.sel_update_enabled)
> -			ret = _psr2_ready_for_pipe_update_locked(new_crtc_state);
> +			ret = _psr2_ready_for_pipe_update_locked(new_crtc_state,
> +								 NULL);
>  		else
> -			ret = _psr1_ready_for_pipe_update_locked(new_crtc_state);
> +			ret = _psr1_ready_for_pipe_update_locked(new_crtc_state,
> +								 NULL);
>  
>  		if (ret)
>  			drm_err(display->drm,
> @@ -3055,6 +3074,19 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat
>  	}
>  }
>  
> +void intel_psr_wait_for_idle_dsb(const struct intel_crtc_state *new_crtc_state)
> +{
> +	if (!new_crtc_state->has_psr || new_crtc_state->has_panel_replay)
> +		return;
> +
> +	if (new_crtc_state->has_sel_update)
> +		_psr2_ready_for_pipe_update_locked(new_crtc_state,
> +						   new_crtc_state->dsb_commit);

Please pass the dsb all the way from the top so that it's easier to
change the DSB usage model if needed.

Otherwise lgtm
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +	else
> +		_psr1_ready_for_pipe_update_locked(new_crtc_state,
> +						   new_crtc_state->dsb_commit);
> +}
> +
>  static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 9b061a22361f..0cd0542b2450 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -52,6 +52,7 @@ void intel_psr_get_config(struct intel_encoder *encoder,
>  void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
>  void intel_psr_short_pulse(struct intel_dp *intel_dp);
>  void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state);
> +void intel_psr_wait_for_idle_dsb(const struct intel_crtc_state *new_crtc_state);
>  bool intel_psr_enabled(struct intel_dp *intel_dp);
>  int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  				struct intel_crtc *crtc);
> -- 
> 2.43.0

-- 
Ville Syrjälä
Intel

Re: [PATCH v2 4/4] drm/i915/psr: Add poll for checking PSR is idle before starting update

[Ville Syrjälä]

On Wed, Aug 06, 2025 at 08:22:13AM +0300, Jouni Högander wrote:
> We are currently observing crc failures after we started using dsb for PSR
> updates as well. This seems to happen because PSR HW is still sending
> couple of updates using old framebuffers on wake-up.
> 
> Fix this by adding poll ensuring PSR is idle before starting update.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c1a3a95c65f0..411c74c73eae 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7271,6 +7271,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>  		intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit,
>  						     state, crtc);
>  
> +		intel_psr_wait_for_idle_dsb(new_crtc_state);
> +
>  		if (new_crtc_state->use_dsb)
>  			intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);

How come the 'evade scanline 0 + normal evasion' in intel_dsb_vblank_evade()
is not enough here?

-- 
Ville Syrjälä
Intel

Re: [PATCH v2 4/4] drm/i915/psr: Add poll for checking PSR is idle before starting update

[Hogander, Jouni]

On Tue, 2025-08-26 at 15:36 +0300, Ville Syrjälä wrote:
> On Wed, Aug 06, 2025 at 08:22:13AM +0300, Jouni Högander wrote:
> > We are currently observing crc failures after we started using dsb
> > for PSR
> > updates as well. This seems to happen because PSR HW is still
> > sending
> > couple of updates using old framebuffers on wake-up.
> > 
> > Fix this by adding poll ensuring PSR is idle before starting
> > update.
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index c1a3a95c65f0..411c74c73eae 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -7271,6 +7271,8 @@ static void intel_atomic_dsb_finish(struct
> > intel_atomic_state *state,
> >  		intel_psr_trigger_frame_change_event(new_crtc_stat
> > e->dsb_commit,
> >  						     state, crtc);
> >  
> > +		intel_psr_wait_for_idle_dsb(new_crtc_state);
> > +
> >  		if (new_crtc_state->use_dsb)
> >  			intel_dsb_vblank_evade(state,
> > new_crtc_state->dsb_commit);
> 
> How come the 'evade scanline 0 + normal evasion' in
> intel_dsb_vblank_evade()
> is not enough here?

the problem doesn't happen when PSR is in SRD_ENT/DEEP_SLEEP as
committing new changes is started. It seems to happen when PSR
transitioning into SRD_ENT/DEEP_SLEEP is ongoing when new changes are
being committed. In this case evasion passes and PSR is continuing
transitioning into SRD_ENT/DEEP_SLEEP. Then wake-up starts immediately
due to pending "Frame Change" event and in this case HW is sending a
frame using old plane configuration.

Bspec is saying this transition to SRD_ENT/DEEP_SLEEP can't be
interrupted.

BR,

Jouni Högander
> 

Re: [PATCH v2 4/4] drm/i915/psr: Add poll for checking PSR is idle before starting update

[Ville Syrjälä]

On Tue, Aug 26, 2025 at 02:30:50PM +0000, Hogander, Jouni wrote:
> On Tue, 2025-08-26 at 15:36 +0300, Ville Syrjälä wrote:
> > On Wed, Aug 06, 2025 at 08:22:13AM +0300, Jouni Högander wrote:
> > > We are currently observing crc failures after we started using dsb
> > > for PSR
> > > updates as well. This seems to happen because PSR HW is still
> > > sending
> > > couple of updates using old framebuffers on wake-up.
> > > 
> > > Fix this by adding poll ensuring PSR is idle before starting
> > > update.
> > > 
> > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c | 2 ++
> > >  1 file changed, 2 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index c1a3a95c65f0..411c74c73eae 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -7271,6 +7271,8 @@ static void intel_atomic_dsb_finish(struct
> > > intel_atomic_state *state,
> > >  		intel_psr_trigger_frame_change_event(new_crtc_stat
> > > e->dsb_commit,
> > >  						     state, crtc);
> > >  
> > > +		intel_psr_wait_for_idle_dsb(new_crtc_state);
> > > +
> > >  		if (new_crtc_state->use_dsb)
> > >  			intel_dsb_vblank_evade(state,
> > > new_crtc_state->dsb_commit);
> > 
> > How come the 'evade scanline 0 + normal evasion' in
> > intel_dsb_vblank_evade()
> > is not enough here?
> 
> the problem doesn't happen when PSR is in SRD_ENT/DEEP_SLEEP as
> committing new changes is started. It seems to happen when PSR
> transitioning into SRD_ENT/DEEP_SLEEP is ongoing when new changes are
> being committed. In this case evasion passes and PSR is continuing
> transitioning into SRD_ENT/DEEP_SLEEP. Then wake-up starts immediately
> due to pending "Frame Change" event and in this case HW is sending a
> frame using old plane configuration.

That's a bit weird. I think we are configuring things so that there
should be that extra vblank already for the first frame after PSR
exit. So I would expect things to latch properly even if we write
the registers during the PSR entry sequence.

Hmm, though the DSB itself never waits for the delayed vblank
directly. Maybe the delayed vblank does get suppressed for
one frame during the sequence somewhere, but the undelayed
vblank used by the DSB does not.

One could perhaps try to sample a timestamp from the DSB after
it thinks the vblank has happened, and sample another one from
the CPU delayed vblank interrupt (which I would expect to match
when the hardware really latches stuff), and compare how they
look. Though that does require one to enable the CPU interrupt
which itself will trigger the PSR exit (at least on some hw),
so not sure how easy it is to hit the exact conditions required.
I suppose one might try to wait for the PSR state machine to
be in the right state just before triggering the exit.

> 
> Bspec is saying this transition to SRD_ENT/DEEP_SLEEP can't be
> interrupted.
> 
> BR,
> 
> Jouni Högander
> > 
> 

-- 
Ville Syrjälä
Intel

Re: [PATCH v2 4/4] drm/i915/psr: Add poll for checking PSR is idle before starting update

[Hogander, Jouni]

On Wed, 2025-08-27 at 16:06 +0300, Ville Syrjälä wrote:
> On Tue, Aug 26, 2025 at 02:30:50PM +0000, Hogander, Jouni wrote:
> > On Tue, 2025-08-26 at 15:36 +0300, Ville Syrjälä wrote:
> > > On Wed, Aug 06, 2025 at 08:22:13AM +0300, Jouni Högander wrote:
> > > > We are currently observing crc failures after we started using
> > > > dsb
> > > > for PSR
> > > > updates as well. This seems to happen because PSR HW is still
> > > > sending
> > > > couple of updates using old framebuffers on wake-up.
> > > > 
> > > > Fix this by adding poll ensuring PSR is idle before starting
> > > > update.
> > > > 
> > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_display.c | 2 ++
> > > >  1 file changed, 2 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index c1a3a95c65f0..411c74c73eae 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -7271,6 +7271,8 @@ static void
> > > > intel_atomic_dsb_finish(struct
> > > > intel_atomic_state *state,
> > > >  		intel_psr_trigger_frame_change_event(new_crtc_
> > > > stat
> > > > e->dsb_commit,
> > > >  						     state,
> > > > crtc);
> > > >  
> > > > +		intel_psr_wait_for_idle_dsb(new_crtc_state);
> > > > +
> > > >  		if (new_crtc_state->use_dsb)
> > > >  			intel_dsb_vblank_evade(state,
> > > > new_crtc_state->dsb_commit);
> > > 
> > > How come the 'evade scanline 0 + normal evasion' in
> > > intel_dsb_vblank_evade()
> > > is not enough here?
> > 
> > the problem doesn't happen when PSR is in SRD_ENT/DEEP_SLEEP as
> > committing new changes is started. It seems to happen when PSR
> > transitioning into SRD_ENT/DEEP_SLEEP is ongoing when new changes
> > are
> > being committed. In this case evasion passes and PSR is continuing
> > transitioning into SRD_ENT/DEEP_SLEEP. Then wake-up starts
> > immediately
> > due to pending "Frame Change" event and in this case HW is sending
> > a
> > frame using old plane configuration.
> 
> That's a bit weird. I think we are configuring things so that there
> should be that extra vblank already for the first frame after PSR
> exit. So I would expect things to latch properly even if we write
> the registers during the PSR entry sequence.
> 
> Hmm, though the DSB itself never waits for the delayed vblank
> directly. Maybe the delayed vblank does get suppressed for
> one frame during the sequence somewhere, but the undelayed
> vblank used by the DSB does not.
> 
> One could perhaps try to sample a timestamp from the DSB after
> it thinks the vblank has happened, and sample another one from
> the CPU delayed vblank interrupt (which I would expect to match
> when the hardware really latches stuff), and compare how they
> look. Though that does require one to enable the CPU interrupt
> which itself will trigger the PSR exit (at least on some hw),
> so not sure how easy it is to hit the exact conditions required.
> I suppose one might try to wait for the PSR state machine to
> be in the right state just before triggering the exit.

Enabling the interrupt will trigger exit. Are you thinking that state
machine wait as a solution or as a experiment? :

Original issue this patch is targeted is triggering rarely in one
testcase and only with one specific panel. I found out that I can
reproduce the issue pretty much on any panel if I adjust idle_frames. I
.e. the configuration how many idle frames before transition to SRDENT
is started.

BR,

Jouni Högander
> 
> > 
> > Bspec is saying this transition to SRD_ENT/DEEP_SLEEP can't be
> > interrupted.
> > 
> > BR,
> > 
> > Jouni Högander
> > > 
> > 
> 

Re: [PATCH v2 4/4] drm/i915/psr: Add poll for checking PSR is idle before starting update

[Ville Syrjälä]

On Wed, Aug 27, 2025 at 01:22:28PM +0000, Hogander, Jouni wrote:
> On Wed, 2025-08-27 at 16:06 +0300, Ville Syrjälä wrote:
> > On Tue, Aug 26, 2025 at 02:30:50PM +0000, Hogander, Jouni wrote:
> > > On Tue, 2025-08-26 at 15:36 +0300, Ville Syrjälä wrote:
> > > > On Wed, Aug 06, 2025 at 08:22:13AM +0300, Jouni Högander wrote:
> > > > > We are currently observing crc failures after we started using
> > > > > dsb
> > > > > for PSR
> > > > > updates as well. This seems to happen because PSR HW is still
> > > > > sending
> > > > > couple of updates using old framebuffers on wake-up.
> > > > > 
> > > > > Fix this by adding poll ensuring PSR is idle before starting
> > > > > update.
> > > > > 
> > > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/display/intel_display.c | 2 ++
> > > > >  1 file changed, 2 insertions(+)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index c1a3a95c65f0..411c74c73eae 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -7271,6 +7271,8 @@ static void
> > > > > intel_atomic_dsb_finish(struct
> > > > > intel_atomic_state *state,
> > > > >  		intel_psr_trigger_frame_change_event(new_crtc_
> > > > > stat
> > > > > e->dsb_commit,
> > > > >  						     state,
> > > > > crtc);
> > > > >  
> > > > > +		intel_psr_wait_for_idle_dsb(new_crtc_state);
> > > > > +
> > > > >  		if (new_crtc_state->use_dsb)
> > > > >  			intel_dsb_vblank_evade(state,
> > > > > new_crtc_state->dsb_commit);
> > > > 
> > > > How come the 'evade scanline 0 + normal evasion' in
> > > > intel_dsb_vblank_evade()
> > > > is not enough here?
> > > 
> > > the problem doesn't happen when PSR is in SRD_ENT/DEEP_SLEEP as
> > > committing new changes is started. It seems to happen when PSR
> > > transitioning into SRD_ENT/DEEP_SLEEP is ongoing when new changes
> > > are
> > > being committed. In this case evasion passes and PSR is continuing
> > > transitioning into SRD_ENT/DEEP_SLEEP. Then wake-up starts
> > > immediately
> > > due to pending "Frame Change" event and in this case HW is sending
> > > a
> > > frame using old plane configuration.
> > 
> > That's a bit weird. I think we are configuring things so that there
> > should be that extra vblank already for the first frame after PSR
> > exit. So I would expect things to latch properly even if we write
> > the registers during the PSR entry sequence.
> > 
> > Hmm, though the DSB itself never waits for the delayed vblank
> > directly. Maybe the delayed vblank does get suppressed for
> > one frame during the sequence somewhere, but the undelayed
> > vblank used by the DSB does not.
> > 
> > One could perhaps try to sample a timestamp from the DSB after
> > it thinks the vblank has happened, and sample another one from
> > the CPU delayed vblank interrupt (which I would expect to match
> > when the hardware really latches stuff), and compare how they
> > look. Though that does require one to enable the CPU interrupt
> > which itself will trigger the PSR exit (at least on some hw),
> > so not sure how easy it is to hit the exact conditions required.
> > I suppose one might try to wait for the PSR state machine to
> > be in the right state just before triggering the exit.
> 
> Enabling the interrupt will trigger exit. Are you thinking that state
> machine wait as a solution or as a experiment? :

Just as an experiment to make sure we understand what's going on.

I suppose if my theory about the undelayed vblank holds there should
also be no way to hit this when not using the DSB since the mmio path
always completes the flips based on the delayed vblank. But I suppose
that's harder to use as any kind of proof since it'll be much harder
to hit the exact time window with the CPU anyway.

-- 
Ville Syrjälä
Intel

Re: [PATCH v2 4/4] drm/i915/psr: Add poll for checking PSR is idle before starting update

[Hogander, Jouni]

On Wed, 2025-08-27 at 22:19 +0300, Ville Syrjälä wrote:
> On Wed, Aug 27, 2025 at 01:22:28PM +0000, Hogander, Jouni wrote:
> > On Wed, 2025-08-27 at 16:06 +0300, Ville Syrjälä wrote:
> > > On Tue, Aug 26, 2025 at 02:30:50PM +0000, Hogander, Jouni wrote:
> > > > On Tue, 2025-08-26 at 15:36 +0300, Ville Syrjälä wrote:
> > > > > On Wed, Aug 06, 2025 at 08:22:13AM +0300, Jouni Högander
> > > > > wrote:
> > > > > > We are currently observing crc failures after we started
> > > > > > using
> > > > > > dsb
> > > > > > for PSR
> > > > > > updates as well. This seems to happen because PSR HW is
> > > > > > still
> > > > > > sending
> > > > > > couple of updates using old framebuffers on wake-up.
> > > > > > 
> > > > > > Fix this by adding poll ensuring PSR is idle before
> > > > > > starting
> > > > > > update.
> > > > > > 
> > > > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/display/intel_display.c | 2 ++
> > > > > >  1 file changed, 2 insertions(+)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > index c1a3a95c65f0..411c74c73eae 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > @@ -7271,6 +7271,8 @@ static void
> > > > > > intel_atomic_dsb_finish(struct
> > > > > > intel_atomic_state *state,
> > > > > >  		intel_psr_trigger_frame_change_event(new_c
> > > > > > rtc_
> > > > > > stat
> > > > > > e->dsb_commit,
> > > > > >  						    
> > > > > > state,
> > > > > > crtc);
> > > > > >  
> > > > > > +		intel_psr_wait_for_idle_dsb(new_crtc_state
> > > > > > );
> > > > > > +
> > > > > >  		if (new_crtc_state->use_dsb)
> > > > > >  			intel_dsb_vblank_evade(state,
> > > > > > new_crtc_state->dsb_commit);
> > > > > 
> > > > > How come the 'evade scanline 0 + normal evasion' in
> > > > > intel_dsb_vblank_evade()
> > > > > is not enough here?
> > > > 
> > > > the problem doesn't happen when PSR is in SRD_ENT/DEEP_SLEEP as
> > > > committing new changes is started. It seems to happen when PSR
> > > > transitioning into SRD_ENT/DEEP_SLEEP is ongoing when new
> > > > changes
> > > > are
> > > > being committed. In this case evasion passes and PSR is
> > > > continuing
> > > > transitioning into SRD_ENT/DEEP_SLEEP. Then wake-up starts
> > > > immediately
> > > > due to pending "Frame Change" event and in this case HW is
> > > > sending
> > > > a
> > > > frame using old plane configuration.
> > > 
> > > That's a bit weird. I think we are configuring things so that
> > > there
> > > should be that extra vblank already for the first frame after PSR
> > > exit. So I would expect things to latch properly even if we write
> > > the registers during the PSR entry sequence.
> > > 
> > > Hmm, though the DSB itself never waits for the delayed vblank
> > > directly. Maybe the delayed vblank does get suppressed for
> > > one frame during the sequence somewhere, but the undelayed
> > > vblank used by the DSB does not.
> > > 
> > > One could perhaps try to sample a timestamp from the DSB after
> > > it thinks the vblank has happened, and sample another one from
> > > the CPU delayed vblank interrupt (which I would expect to match
> > > when the hardware really latches stuff), and compare how they
> > > look. Though that does require one to enable the CPU interrupt
> > > which itself will trigger the PSR exit (at least on some hw),
> > > so not sure how easy it is to hit the exact conditions required.
> > > I suppose one might try to wait for the PSR state machine to
> > > be in the right state just before triggering the exit.
> > 
> > Enabling the interrupt will trigger exit. Are you thinking that
> > state
> > machine wait as a solution or as a experiment? :
> 
> Just as an experiment to make sure we understand what's going on.
> 
> I suppose if my theory about the undelayed vblank holds there should
> also be no way to hit this when not using the DSB since the mmio path
> always completes the flips based on the delayed vblank.

I can actually reproduce this issue in non-dsb case as well by removing
PSR idle wait from that path.

BR,

Jouni Högander

> But I suppose
> that's harder to use as any kind of proof since it'll be much harder
> to hit the exact time window with the CPU anyway.
>