From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Xin Wang <x.wang@intel.com>, Raag Jadav <raag.jadav@intel.com>
Cc: <intel-xe@lists.freedesktop.org>, <karthik.poosa@intel.com>,
<james.xiong@intel.com>, <stuart.summers@intel.com>,
<shuicheng.lin@intel.com>, <vinay.belgaumkar@intel.com>
Subject: Re: [PATCH 2/2] drm/xe: Ensure GT is in C0 during resumes
Date: Mon, 25 Aug 2025 14:19:40 -0400 [thread overview]
Message-ID: <aKypPHMI88W4bogh@intel.com> (raw)
In-Reply-To: <20250825165759.1263546-3-x.wang@intel.com>
On Mon, Aug 25, 2025 at 09:57:59AM -0700, Xin Wang wrote:
> This patch ensures the gt will be awake for the entire duration
> of the resume sequences until GuCRC takes over and GT-C6 gets
> re-enabled.
>
> Before suspending GT-C6 is kept enabled, but upon resume, GuCRC
> is not yet alive to properly control the exits and some cases of
> instability and corruption related to GT-C6 can be observed.
>
> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/4037
>
> Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Xin Wang <x.wang@intel.com>
> ---
> drivers/gpu/drm/xe/xe_pm.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c
> index 51934d5dc44f..a2e85030b7f4 100644
> --- a/drivers/gpu/drm/xe/xe_pm.c
> +++ b/drivers/gpu/drm/xe/xe_pm.c
> @@ -18,7 +18,7 @@
> #include "xe_device.h"
> #include "xe_ggtt.h"
> #include "xe_gt.h"
> -#include "xe_guc.h"
> +#include "xe_gt_idle.h"
> #include "xe_i2c.h"
> #include "xe_irq.h"
> #include "xe_pcode.h"
> @@ -177,6 +177,9 @@ int xe_pm_resume(struct xe_device *xe)
> drm_dbg(&xe->drm, "Resuming device\n");
> trace_xe_pm_resume(xe, __builtin_return_address(0));
>
> + for_each_gt(gt, xe, id)
> + xe_gt_idle_disable_c6(gt);
> +
> for_each_tile(tile, xe, id)
> xe_wa_apply_tile_workarounds(tile);
>
> @@ -533,6 +536,9 @@ int xe_pm_runtime_resume(struct xe_device *xe)
>
> xe_rpm_lockmap_acquire(xe);
>
> + for_each_gt(gt, xe, id)
> + xe_gt_idle_disable_c6(gt);
Cc: Raag Jadav <raag.jadav@intel.com>
who is working to avoid GuC reload when we didn't lose power.
So, these lines will likely need to probably move to inside below if
when we have that code in place.
But for this patch with current code:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> +
> if (xe->d3cold.allowed) {
> err = xe_pcode_ready(xe, true);
> if (err)
> --
> 2.43.0
>
next prev parent reply other threads:[~2025-08-25 18:19 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-25 16:57 [PATCH 0/2] Ensure GT is in C0 during resumes Xin Wang
2025-08-25 16:57 ` [PATCH 1/2] drm/xe: make xe_gt_idle_disable_c6() handle the forcewake internally Xin Wang
2025-08-25 18:15 ` Rodrigo Vivi
2025-08-25 18:28 ` Wang, X
2025-08-25 18:34 ` Vivi, Rodrigo
2025-08-25 16:57 ` [PATCH 2/2] drm/xe: Ensure GT is in C0 during resumes Xin Wang
2025-08-25 18:19 ` Rodrigo Vivi [this message]
2025-08-25 18:25 ` ✓ CI.KUnit: success for Ensure GT is in C0 during resumes (rev2) Patchwork
2025-08-25 19:04 ` ✓ Xe.CI.BAT: " Patchwork
2025-08-26 3:20 ` ✗ Xe.CI.Full: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2025-08-27 0:06 [PATCH 0/2] Ensure GT is in C0 during resumes Xin Wang
2025-08-27 0:06 ` [PATCH 2/2] drm/xe: " Xin Wang
2025-09-04 13:45 ` Poosa, Karthik
2025-08-22 19:53 [PATCH 0/2] " Xin Wang
2025-08-22 19:53 ` [PATCH 2/2] drm/xe: " Xin Wang
2025-08-22 20:17 ` Rodrigo Vivi
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