From: Heikki Krogerus <heikki.krogerus@linux.intel.com>
To: Raag Jadav <raag.jadav@intel.com>
Cc: lucas.demarchi@intel.com, rodrigo.vivi@intel.com,
intel-xe@lists.freedesktop.org, riana.tauro@intel.com
Subject: Re: [PATCH v1] drm/xe/i2c: Enable bus mastering
Date: Tue, 9 Sep 2025 13:11:16 +0300 [thread overview]
Message-ID: <aL_9RGTUQoljhf8Z@kuha.fi.intel.com> (raw)
In-Reply-To: <20250908055320.2549722-1-raag.jadav@intel.com>
On Mon, Sep 08, 2025 at 11:23:20AM +0530, Raag Jadav wrote:
> Enable bus mastering for I2C controller to support device initiated
> in-band transactions.
>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
FWIW:
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
> ---
> drivers/gpu/drm/xe/xe_i2c.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_i2c.c b/drivers/gpu/drm/xe/xe_i2c.c
> index 044dda517b7c..48dfcb41fa08 100644
> --- a/drivers/gpu/drm/xe/xe_i2c.c
> +++ b/drivers/gpu/drm/xe/xe_i2c.c
> @@ -259,7 +259,7 @@ void xe_i2c_pm_resume(struct xe_device *xe, bool d3cold)
> return;
>
> if (d3cold)
> - xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, 0, PCI_COMMAND_MEMORY);
> + xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, 0, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
>
> xe_mmio_rmw32(mmio, I2C_CONFIG_PMCSR, PCI_PM_CTRL_STATE_MASK, (__force u32)PCI_D0);
> drm_dbg(&xe->drm, "pmcsr: 0x%08x\n", xe_mmio_read32(mmio, I2C_CONFIG_PMCSR));
> --
> 2.34.1
--
heikki
next prev parent reply other threads:[~2025-09-09 10:11 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-08 5:53 [PATCH v1] drm/xe/i2c: Enable bus mastering Raag Jadav
2025-09-08 6:00 ` ✓ CI.KUnit: success for " Patchwork
2025-09-08 6:32 ` ✓ Xe.CI.BAT: " Patchwork
2025-09-08 7:43 ` ✗ Xe.CI.Full: failure " Patchwork
2025-09-09 10:11 ` Heikki Krogerus [this message]
2025-09-09 13:41 ` [PATCH v1] " Lucas De Marchi
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