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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
	Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Subject: Re: [PATCH 10/15] drm/i915/skl_watermark: Remove redundant latency checks from vblank validation
Date: Thu, 11 Sep 2025 17:22:07 +0300	[thread overview]
Message-ID: <aMLbD4g6iB9s_FWU@intel.com> (raw)
In-Reply-To: <20250911024554.692469-11-ankit.k.nautiyal@intel.com>

On Thu, Sep 11, 2025 at 08:15:49AM +0530, Ankit Nautiyal wrote:
> Drop DSC and scaler prefill latency checks from skl_is_vblank_too_short().
> These are now covered by the guardband validation added during the atomic
> CRTC check phase.
> 
> This cleanup prepares for future changes where the guardband will be
> optimized independently of vblank length, making vblank-based checks
> obsolete.

This looks very wrong, at least for platforms that don't have a
programmable guardband.

> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 79 --------------------
>  1 file changed, 79 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 83ac26004f05..07589096b143 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -28,7 +28,6 @@
>  #include "intel_flipq.h"
>  #include "intel_pcode.h"
>  #include "intel_plane.h"
> -#include "intel_vrr.h"
>  #include "intel_wm.h"
>  #include "skl_universal_plane_regs.h"
>  #include "skl_scaler.h"
> @@ -2159,93 +2158,15 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
>  	return 0;
>  }
>  
> -static int
> -cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_display *display = to_intel_display(crtc_state);
> -	struct intel_atomic_state *state =
> -		to_intel_atomic_state(crtc_state->uapi.state);
> -	const struct intel_cdclk_state *cdclk_state;
> -
> -	cdclk_state = intel_atomic_get_cdclk_state(state);
> -	if (IS_ERR(cdclk_state)) {
> -		drm_WARN_ON(display->drm, PTR_ERR(cdclk_state));
> -		return 1;
> -	}
> -
> -	return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
> -				   2 * intel_cdclk_logical(cdclk_state)));
> -}
> -
> -static int
> -dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
> -{
> -	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
> -	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	int num_scaler_users = hweight32(scaler_state->scaler_users);
> -	u64 hscale_k[ARRAY_SIZE(scaler_state->scalers)];
> -	u64 vscale_k[ARRAY_SIZE(scaler_state->scalers)];
> -	u32 dsc_prefill_latency = 0;
> -
> -	if (!crtc_state->dsc.compression_enable ||
> -	    !num_scaler_users ||
> -	    num_scaler_users > crtc->num_scalers)
> -		return dsc_prefill_latency;
> -
> -	for (int i = 0; i < num_scaler_users; i++) {
> -		hscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
> -		vscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
> -	}
> -
> -	dsc_prefill_latency =
> -		intel_vrr_guardband_dsc_latency(num_scaler_users, hscale_k, vscale_k,
> -						chroma_downscaling_factor,
> -						cdclk_prefill_adjustment(crtc_state),
> -						linetime);
> -
> -	return dsc_prefill_latency;
> -}
> -
> -static int
> -scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
> -{
> -	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
> -	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
> -	int num_scaler_users = hweight32(scaler_state->scaler_users);
> -	u64 hscale_k = 0, vscale_k = 0;
> -	int scaler_prefill_latency = 0;
> -
> -	if (!num_scaler_users)
> -		return scaler_prefill_latency;
> -
> -	if (num_scaler_users > 1) {
> -		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
> -		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
> -	}
> -
> -	scaler_prefill_latency =
> -		intel_vrr_guardband_scaler_latency(num_scaler_users, hscale_k, vscale_k,
> -						   chroma_downscaling_factor,
> -						   cdclk_prefill_adjustment(crtc_state),
> -						   linetime);
> -
> -	return scaler_prefill_latency;
> -}
> -
>  static bool
>  skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
>  			int wm0_lines, int latency)
>  {
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
> -	int linetime = DIV_ROUND_UP(1000 * adjusted_mode->htotal,
> -				    adjusted_mode->clock);
>  
>  	return crtc_state->framestart_delay +
>  		intel_usecs_to_scanlines(adjusted_mode, latency) +
> -		DIV_ROUND_UP(scaler_prefill_latency(crtc_state, linetime), linetime) +
> -		DIV_ROUND_UP(dsc_prefill_latency(crtc_state, linetime), linetime) +
>  		wm0_lines >
>  		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
>  }
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2025-09-11 14:22 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-11  2:45 [PATCH 00/15] Optimize vrr.guardband and fix LRR Ankit Nautiyal
2025-09-11  2:45 ` [PATCH 01/15] drm/i915/vrr: Use crtc_vsync_start/end for computing vrr.vsync_start/end Ankit Nautiyal
2025-09-11  2:45 ` [PATCH 02/15] drm/i915/skl_watermark: Fix the scaling factor for chroma subsampling Ankit Nautiyal
2025-09-11  2:45 ` [PATCH 03/15] drm/i915/skl_watermark: Pass linetime as argument to latency helpers Ankit Nautiyal
2025-09-11 13:58   ` Ville Syrjälä
2025-09-14  6:00     ` Nautiyal, Ankit K
2025-09-11  2:45 ` [PATCH 04/15] drm/i915/skl_scaler: Introduce helper for chroma downscale factor Ankit Nautiyal
2025-09-11  2:45 ` [PATCH 05/15] drm/i915/display: Extract helpers to set dsc/scaler prefill latencies Ankit Nautiyal
2025-09-11 14:01   ` Ville Syrjälä
2025-09-14  6:02     ` Nautiyal, Ankit K
2025-09-11  2:45 ` [PATCH 06/15] drm/i915/dp: Add SDP latency computation helper Ankit Nautiyal
2025-09-11 14:14   ` Ville Syrjälä
2025-09-14  6:03     ` Nautiyal, Ankit K
2025-09-11  2:45 ` [PATCH 07/15] drm/i915/alpm: Add function to compute max link-wake latency Ankit Nautiyal
2025-09-11  2:45 ` [PATCH 08/15] drm/i915/vrr: Use vrr.sync_start for getting vtotal Ankit Nautiyal
2025-09-11  2:45 ` [PATCH 09/15] drm/i915/display: Add guardband check for feature latencies Ankit Nautiyal
2025-09-11  2:45 ` [PATCH 10/15] drm/i915/skl_watermark: Remove redundant latency checks from vblank validation Ankit Nautiyal
2025-09-11 14:22   ` Ville Syrjälä [this message]
2025-09-14  6:04     ` Nautiyal, Ankit K
2025-09-11  2:45 ` [PATCH 11/15] drm/i915/display: Use vrr.guardband to derive vblank_start Ankit Nautiyal
2025-09-11 14:25   ` Ville Syrjälä
2025-09-14  5:59     ` Nautiyal, Ankit K
2025-09-15 12:32       ` Ville Syrjälä
2025-09-16 14:30         ` Nautiyal, Ankit K
2025-09-16 14:38           ` Nautiyal, Ankit K
2025-09-16 18:56             ` Ville Syrjälä
2025-09-17 10:38               ` Nautiyal, Ankit K
2025-09-17 12:36                 ` Ville Syrjälä
2025-09-17 10:51               ` Ville Syrjälä
2025-09-17 12:07                 ` Shankar, Uma
2025-09-17 20:51                 ` Ville Syrjälä
2025-09-17 21:12                   ` Ville Syrjälä
2025-09-11  2:45 ` [PATCH 12/15] drm/i915/vrr: Introduce helper to compute min static guardband Ankit Nautiyal
2025-09-11  2:45 ` [PATCH 13/15] drm/i915/display: Use optimized guardband to set vblank start Ankit Nautiyal
2025-09-11  2:45 ` [PATCH 14/15] drm/i915/panel: Refactor helper to get highest fixed mode Ankit Nautiyal
2025-09-11 14:37   ` Ville Syrjälä
2025-09-14  6:08     ` Nautiyal, Ankit K
2025-09-11  2:45 ` [PATCH 15/15] drm/i915/vrr: Fix seamless_mn drrs for PTL Ankit Nautiyal
2025-09-11 14:41   ` Ville Syrjälä
2025-09-14  6:07     ` Nautiyal, Ankit K
2025-09-15 13:25       ` Ville Syrjälä
2025-09-11  3:11 ` ✓ CI.KUnit: success for Optimize vrr.guardband and fix LRR (rev11) Patchwork
2025-09-11  3:47 ` ✓ Xe.CI.BAT: " Patchwork
2025-09-11  9:27 ` ✓ Xe.CI.Full: " Patchwork
2025-09-12 14:03 ` [PATCH 00/15] Optimize vrr.guardband and fix LRR Ville Syrjälä
2025-09-14  6:24   ` Nautiyal, Ankit K

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