[PATCH 00/15] Optimize vrr.guardband and fix LRR

[PATCH 00/15] Optimize vrr.guardband and fix LRR

[Ankit Nautiyal]

Instead of setting vrr.guardband to vblank, use optimal guardband that
works for most of the cases. This will help in avoiding need of change
in guardband and fix the LRR feature that needs seamless switching to
a lower refresh rate.

First few patches fix/refactor and extract common functions required for
dsc/scaler prefill time computation. Later patches use these helpers to
compute an optimized guardband.

Also, for seamless_mn where vtotal is same but mode clock is changed to
seamlessly switch to lower rate, re-compute the vrr timings.

Few things that still need work:
-The timestamps corresponding with next start of vactive still need to be
fixed with the new scheme.
-Re-enabling CMRR

Rev2:
-Address comments from Mitul.
-Extract helpers for dsc/scaler prefill latencies.
-Fix downscaling factor for chroma subsampling.
-Use missing pkg C max latency.
-Fix guardband computation for seamless mn, always use vblank for
higher resolution.

Rev3:
-Drop patches for computing and storing PSR/Panel Replay wake times
latencies and use existing helpers to compute these in intel_alpm.c.
-Drop patch to change the Vmin as it was not required.

Rev4:
-Rebase
-Drop patch for checking bounds for scaler array access.
-Use a new flag for setting vrr timings for seamless drrs.

Rev5:
-Address comments from Mitul, Jani:
-Refactor few helpers for computing latencies.
-Rename the helper to check the guardband to intel_crtc_guardband_atomic_check()
-Refactor the helper intel_panel_highest_mode().

Rev6:
-Rebase
-Address review comments from Mitul.
-Improve documentation for and other minor fixes in Patch#12

Rev7:
-Address comments from Jani.
-Move the latency helpers from intel_display.c to intel_vrr.c and rename
the helpers appropriately.
-Drop redundant check for HAS_VRR with intel_vrr_possible().

Rev8:
-Fix CI issues.
-For fixed RR wait for delayed vblank before dsb interrupt.

Rev9:
-Fix vrr.vsync_start/end timings for 3D modes (patch#1)
-Rewrite the patch to wait for delayed vblank before dsb interrupt
(patch #11)
-Fix the flipline and vmin timings with optimized guardband (patch#12)

Rev10:
-Address comments from Ville: Use min guardband computation for setting
the vblank delay and set the crtc_vblank_start to delayed vblank.
(Patch#13)
-Modify the TRANS_SET_CONTEXT_LATENCY as per new guardband and use
vrr.guardband to readback vblank_start. (Patch#11)

-From previous revision:
->Drop patch#11 "drm/i915/dsb: Align flipdone with delayed vblank using
guardband wait", as this is no longer required.
->Modify Patch#12 "drm/i915/vrr: Use static guardband to support seamless
LRR switching" to only introduce a helper to compute the fix guardband.
Modify the commit message and the subject.

Ankit Nautiyal (15):
  drm/i915/vrr: Use crtc_vsync_start/end for computing
    vrr.vsync_start/end
  drm/i915/skl_watermark: Fix the scaling factor for chroma subsampling
  drm/i915/skl_watermark: Pass linetime as argument to latency helpers
  drm/i915/skl_scaler: Introduce helper for chroma downscale factor
  drm/i915/display: Extract helpers to set dsc/scaler prefill latencies
  drm/i915/dp: Add SDP latency computation helper
  drm/i915/alpm: Add function to compute max link-wake latency
  drm/i915/vrr: Use vrr.sync_start for getting vtotal
  drm/i915/display: Add guardband check for feature latencies
  drm/i915/skl_watermark: Remove redundant latency checks from vblank
    validation
  drm/i915/display: Use vrr.guardband to derive vblank_start
  drm/i915/vrr: Introduce helper to compute min static guardband
  drm/i915/display: Use optimized guardband to set vblank start
  drm/i915/panel: Refactor helper to get highest fixed mode
  drm/i915/vrr: Fix seamless_mn drrs for PTL

 drivers/gpu/drm/i915/display/intel_alpm.c     |  15 +
 drivers/gpu/drm/i915/display/intel_alpm.h     |   2 +
 drivers/gpu/drm/i915/display/intel_display.c  | 236 ++++++++++++++-
 .../drm/i915/display/intel_display_types.h    |   2 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  63 +++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   3 +
 drivers/gpu/drm/i915/display/intel_panel.c    |  11 +-
 drivers/gpu/drm/i915/display/intel_panel.h    |   3 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 272 ++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_vrr.h      |  10 +
 drivers/gpu/drm/i915/display/skl_scaler.c     |   5 +
 drivers/gpu/drm/i915/display/skl_scaler.h     |   3 +
 drivers/gpu/drm/i915/display/skl_watermark.c  |  89 +-----
 drivers/gpu/drm/i915/display/skl_watermark.h  |   1 +
 14 files changed, 586 insertions(+), 129 deletions(-)

-- 
2.45.2

[PATCH 01/15] drm/i915/vrr: Use crtc_vsync_start/end for computing vrr.vsync_start/end

[Ankit Nautiyal]

Use adjusted_mode->crtc_vsync_start/end instead of
adjusted_mode->vsync_start while computing vrr.vsync_start/end.
For most modes, these are same but for 3D/stereo modes the
crtc_vsync_start is different than vsync_start.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 3eed37f271b0..266cf5e1859d 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -406,10 +406,10 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	if (HAS_AS_SDP(display)) {
 		crtc_state->vrr.vsync_start =
 			(crtc_state->hw.adjusted_mode.crtc_vtotal -
-			 crtc_state->hw.adjusted_mode.vsync_start);
+			 crtc_state->hw.adjusted_mode.crtc_vsync_start);
 		crtc_state->vrr.vsync_end =
 			(crtc_state->hw.adjusted_mode.crtc_vtotal -
-			 crtc_state->hw.adjusted_mode.vsync_end);
+			 crtc_state->hw.adjusted_mode.crtc_vsync_end);
 	}
 }
 
-- 
2.45.2

[PATCH 02/15] drm/i915/skl_watermark: Fix the scaling factor for chroma subsampling

[Ankit Nautiyal]

The Bspec:70151, mentions Chroma subsampling is a 2x downscale
operation. This means that the downscale factor is 2 in each direction.
So correct the downscaling factor to 4.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index d74cbb43ae6f..51548447f4aa 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2185,7 +2185,7 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state)
 				    crtc_state->hw.adjusted_mode.clock);
 	int num_scaler_users = hweight32(scaler_state->scaler_users);
 	int chroma_downscaling_factor =
-		crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
+		crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 4 : 1;
 	u32 dsc_prefill_latency = 0;
 
 	if (!crtc_state->dsc.compression_enable ||
@@ -2228,7 +2228,7 @@ scaler_prefill_latency(const struct intel_crtc_state *crtc_state)
 		u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
 		u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
 		int chroma_downscaling_factor =
-			crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
+			crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 4 : 1;
 		int latency;
 
 		latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k *
-- 
2.45.2

[PATCH 03/15] drm/i915/skl_watermark: Pass linetime as argument to latency helpers

[Ankit Nautiyal]

Refactor dsc_prefill_latency and scaler_prefill_latency to take
linetime as an explicit parameter instead of computing it internally.

This avoids redundant calculations and simplifies scanline conversion
logic in skl_is_vblank_too_short().

This change also facilitates future extraction of these helpers for use
cases where latencies are computed for an optimized guardband, based on the
highest resolution mode, rather than the current mode.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 51548447f4aa..49d424f5b305 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2176,13 +2176,11 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
 }
 
 static int
-dsc_prefill_latency(const struct intel_crtc_state *crtc_state)
+dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct intel_crtc_scaler_state *scaler_state =
 					&crtc_state->scaler_state;
-	int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
-				    crtc_state->hw.adjusted_mode.clock);
 	int num_scaler_users = hweight32(scaler_state->scaler_users);
 	int chroma_downscaling_factor =
 		crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 4 : 1;
@@ -2206,18 +2204,16 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state)
 
 	dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
 
-	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, dsc_prefill_latency);
+	return dsc_prefill_latency;
 }
 
 static int
-scaler_prefill_latency(const struct intel_crtc_state *crtc_state)
+scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
 {
 	const struct intel_crtc_scaler_state *scaler_state =
 					&crtc_state->scaler_state;
 	int num_scaler_users = hweight32(scaler_state->scaler_users);
 	int scaler_prefill_latency = 0;
-	int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
-				    crtc_state->hw.adjusted_mode.clock);
 
 	if (!num_scaler_users)
 		return scaler_prefill_latency;
@@ -2238,7 +2234,7 @@ scaler_prefill_latency(const struct intel_crtc_state *crtc_state)
 
 	scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
 
-	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, scaler_prefill_latency);
+	return scaler_prefill_latency;
 }
 
 static bool
@@ -2247,11 +2243,13 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
 {
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
+	int linetime = DIV_ROUND_UP(1000 * adjusted_mode->htotal,
+				    adjusted_mode->clock);
 
 	return crtc_state->framestart_delay +
 		intel_usecs_to_scanlines(adjusted_mode, latency) +
-		scaler_prefill_latency(crtc_state) +
-		dsc_prefill_latency(crtc_state) +
+		DIV_ROUND_UP(scaler_prefill_latency(crtc_state, linetime), linetime) +
+		DIV_ROUND_UP(dsc_prefill_latency(crtc_state, linetime), linetime) +
 		wm0_lines >
 		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
 }
-- 
2.45.2

[PATCH 04/15] drm/i915/skl_scaler: Introduce helper for chroma downscale factor

[Ankit Nautiyal]

For 444 to 420 output format conversion, scaler uses 2x downscaling in
each direction. Introduce skl_scaler_chroma_downscale_factor() to
encapsulate the chroma subsampling adjustment used in scaler/dsc
pre-fill latency calculations.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/skl_scaler.c    | 5 +++++
 drivers/gpu/drm/i915/display/skl_scaler.h    | 3 +++
 drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++----
 3 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index c6cccf170ff1..af2cbd54c32e 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -968,3 +968,8 @@ void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state)
 			  1);
 	intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, 0);
 }
+
+int skl_scaler_chroma_downscale_factor(const struct intel_crtc_state *crtc_state)
+{
+	return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 4 : 1;
+}
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h
index 12a19016c5f6..257330d4c329 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.h
+++ b/drivers/gpu/drm/i915/display/skl_scaler.h
@@ -45,4 +45,7 @@ skl_scaler_mode_valid(struct intel_display *display,
 void adl_scaler_ecc_mask(const struct intel_crtc_state *crtc_state);
 
 void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state);
+
+int skl_scaler_chroma_downscale_factor(const struct intel_crtc_state *crtc_state);
+
 #endif
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 49d424f5b305..3d322c39ce21 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -30,6 +30,7 @@
 #include "intel_plane.h"
 #include "intel_wm.h"
 #include "skl_universal_plane_regs.h"
+#include "skl_scaler.h"
 #include "skl_watermark.h"
 #include "skl_watermark_regs.h"
 
@@ -2182,8 +2183,7 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
 	const struct intel_crtc_scaler_state *scaler_state =
 					&crtc_state->scaler_state;
 	int num_scaler_users = hweight32(scaler_state->scaler_users);
-	int chroma_downscaling_factor =
-		crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 4 : 1;
+	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
 	u32 dsc_prefill_latency = 0;
 
 	if (!crtc_state->dsc.compression_enable ||
@@ -2223,8 +2223,7 @@ scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
 	if (num_scaler_users > 1) {
 		u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
 		u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
-		int chroma_downscaling_factor =
-			crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 4 : 1;
+		int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
 		int latency;
 
 		latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k *
-- 
2.45.2

[PATCH 05/15] drm/i915/display: Extract helpers to set dsc/scaler prefill latencies

[Ankit Nautiyal]

Currently dsc/scaler prefill latencies are handled during watermark
calculations. With the optimized guardband, we need to compute the
latencies to find the minimum guardband that works for most cases.
Extract the helpers to compute these latencies, so that they can be used
while computing vrr guardband.

While at it, put declarations in reverse xmas tree order for better
redability.

v2: Initialize {h,v}scale_k to 0, and simplify the check in
intel_display_scaler_prefill_latency(). (Mitul)
v3: Move helpers from intel_display.c to intel_vrr.c as they are specific
to account for latencies to program vrr guardband. (Jani)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c     | 33 ++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h     |  8 ++++
 drivers/gpu/drm/i915/display/skl_watermark.c | 47 +++++++++-----------
 3 files changed, 63 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 266cf5e1859d..fd690de5b45b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -772,3 +772,36 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	if (crtc_state->vrr.enable)
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
+
+int intel_vrr_guardband_scaler_latency(int num_scaler_users, u64 hscale, u64 vscale,
+				       int chroma_downscaling_factor,
+				       int cdclk_prefill_adjustment,
+				       int linetime)
+{
+	int scaler_prefill_latency;
+
+	scaler_prefill_latency = 4 * linetime +
+				 DIV_ROUND_UP_ULL((4 * linetime * hscale * vscale *
+						   chroma_downscaling_factor), 1000000);
+
+	scaler_prefill_latency *= cdclk_prefill_adjustment;
+
+	return scaler_prefill_latency;
+}
+
+int intel_vrr_guardband_dsc_latency(int num_scaler_users, u64 *hscale, u64 *vscale,
+				    int chroma_downscaling_factor,
+				    int cdclk_prefill_adjustment,
+				    int linetime)
+{
+	int dsc_prefill_latency;
+
+	dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10);
+
+	for (int i = 0; i < num_scaler_users; i++)
+		dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale[i] * vscale[i],
+						       1000000);
+	dsc_prefill_latency *= cdclk_prefill_adjustment;
+
+	return dsc_prefill_latency;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 38bf9996b883..950041647e47 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -41,5 +41,13 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
 bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
+int intel_vrr_guardband_scaler_latency(int num_scaler_users, u64 hscale, u64 vscale,
+				       int chroma_downscaling_factor,
+				       int cdclk_prefill_adjustment,
+				       int linetime);
+int intel_vrr_guardband_dsc_latency(int num_scaler_users, u64 *hscale, u64 *vscale,
+				    int chroma_downscaling_factor,
+				    int cdclk_prefill_adjustment,
+				    int linetime);
 
 #endif /* __INTEL_VRR_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 3d322c39ce21..1ff2b4d9a35e 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -28,6 +28,7 @@
 #include "intel_flipq.h"
 #include "intel_pcode.h"
 #include "intel_plane.h"
+#include "intel_vrr.h"
 #include "intel_wm.h"
 #include "skl_universal_plane_regs.h"
 #include "skl_scaler.h"
@@ -2179,11 +2180,12 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
 static int
 dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
 {
+	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
+	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	const struct intel_crtc_scaler_state *scaler_state =
-					&crtc_state->scaler_state;
 	int num_scaler_users = hweight32(scaler_state->scaler_users);
-	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
+	u64 hscale_k[ARRAY_SIZE(scaler_state->scalers)];
+	u64 vscale_k[ARRAY_SIZE(scaler_state->scalers)];
 	u32 dsc_prefill_latency = 0;
 
 	if (!crtc_state->dsc.compression_enable ||
@@ -2191,18 +2193,16 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
 	    num_scaler_users > crtc->num_scalers)
 		return dsc_prefill_latency;
 
-	dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10);
-
 	for (int i = 0; i < num_scaler_users; i++) {
-		u64 hscale_k, vscale_k;
-
-		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
-		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
-		dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale_k * vscale_k,
-						       1000000);
+		hscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
+		vscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
 	}
 
-	dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
+	dsc_prefill_latency =
+		intel_vrr_guardband_dsc_latency(num_scaler_users, hscale_k, vscale_k,
+						chroma_downscaling_factor,
+						cdclk_prefill_adjustment(crtc_state),
+						linetime);
 
 	return dsc_prefill_latency;
 }
@@ -2210,28 +2210,25 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
 static int
 scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
 {
-	const struct intel_crtc_scaler_state *scaler_state =
-					&crtc_state->scaler_state;
+	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
+	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
 	int num_scaler_users = hweight32(scaler_state->scaler_users);
+	u64 hscale_k = 0, vscale_k = 0;
 	int scaler_prefill_latency = 0;
 
 	if (!num_scaler_users)
 		return scaler_prefill_latency;
 
-	scaler_prefill_latency = 4 * linetime;
-
 	if (num_scaler_users > 1) {
-		u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
-		u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
-		int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
-		int latency;
-
-		latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k *
-					    chroma_downscaling_factor), 1000000);
-		scaler_prefill_latency += latency;
+		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
+		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
 	}
 
-	scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
+	scaler_prefill_latency =
+		intel_vrr_guardband_scaler_latency(num_scaler_users, hscale_k, vscale_k,
+						   chroma_downscaling_factor,
+						   cdclk_prefill_adjustment(crtc_state),
+						   linetime);
 
 	return scaler_prefill_latency;
 }
-- 
2.45.2

[PATCH 06/15] drm/i915/dp: Add SDP latency computation helper

[Ankit Nautiyal]

Add a helper to compute vblank time needed for transmitting specific
DisplayPort SDPs like PPS, GAMUT_METADATA, and VSC_EXT. Latency is
based on line count per packet type and current line time.

Used to ensure adequate vblank when features like DSC/HDR are enabled.

Bspec: 70151
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h |  2 ++
 2 files changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2eab591a8ef5..83c46e4680b3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6857,3 +6857,50 @@ void intel_dp_mst_resume(struct intel_display *display)
 		}
 	}
 }
+
+static
+int intel_dp_get_sdp_latency(u32 type, int linetime_us)
+{
+	int lines;
+
+	switch (type) {
+	case DP_SDP_VSC_EXT_VESA:
+	case DP_SDP_VSC_EXT_CEA:
+		lines = 10;
+		break;
+	case HDMI_PACKET_TYPE_GAMUT_METADATA:
+		lines = 8;
+		break;
+	case DP_SDP_PPS:
+		lines = 6;
+		break;
+	default:
+		lines = 0;
+		break;
+	}
+
+	return lines * linetime_us;
+}
+
+int intel_dp_compute_sdp_latency(const struct intel_crtc_state *crtc_state,
+				 bool assume_all_enabled)
+{
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	int sdp_latency = 0;
+	int linetime_us;
+
+	linetime_us = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000,
+				   adjusted_mode->crtc_clock);
+	if (assume_all_enabled ||
+	    crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
+		sdp_latency = max(sdp_latency,
+				  intel_dp_get_sdp_latency(HDMI_PACKET_TYPE_GAMUT_METADATA,
+							   linetime_us));
+
+	if (assume_all_enabled || crtc_state->dsc.compression_enable)
+		sdp_latency = max(sdp_latency,
+				  intel_dp_get_sdp_latency(DP_SDP_PPS, linetime_us));
+
+	return sdp_latency;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index f90cfd1dbbd0..d222749b191c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -215,5 +215,7 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
 int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector);
 void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
 bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
+int intel_dp_compute_sdp_latency(const struct intel_crtc_state *crtc_state,
+				 bool assume_all_enabled);
 
 #endif /* __INTEL_DP_H__ */
-- 
2.45.2

[PATCH 07/15] drm/i915/alpm: Add function to compute max link-wake latency

[Ankit Nautiyal]

Introduce a helper to compute the max link wake latency when using
Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF features.

This will be used to compute the minimum guardband so that the link wake
latencies are accounted and these features work smoothly for higher
refresh rate panels.

Bspec: 70151, 71477
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/display/intel_alpm.h |  2 ++
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index ed7a7ed486b5..c7d865d7c971 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -611,3 +611,18 @@ bool intel_alpm_get_error(struct intel_dp *intel_dp)
 
 	return false;
 }
+
+int intel_alpm_compute_max_link_wake_latency(const struct intel_crtc_state *crtc_state,
+					     bool assume_all_enabled)
+{
+	int psr2_vblank_time = 0;
+	int auxless_wake_time = 0;
+
+	if (assume_all_enabled || crtc_state->has_sel_update)
+		psr2_vblank_time =  io_buffer_wake_time(crtc_state);
+
+	if (assume_all_enabled || crtc_state->has_panel_replay)
+		auxless_wake_time = _lnl_compute_aux_less_wake_time(crtc_state);
+
+	return max(psr2_vblank_time, auxless_wake_time);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index a861c20b5d79..b371827af356 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -38,4 +38,6 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
 				 const struct intel_crtc_state *crtc_state);
 void intel_alpm_disable(struct intel_dp *intel_dp);
 bool intel_alpm_get_error(struct intel_dp *intel_dp);
+int intel_alpm_compute_max_link_wake_latency(const struct intel_crtc_state *crtc_state,
+					     bool assume_all_enabled);
 #endif
-- 
2.45.2

[PATCH 08/15] drm/i915/vrr: Use vrr.sync_start for getting vtotal

[Ankit Nautiyal]

Currently, in intel_vrr_get_config() crtc_vtotal is computed from
vrr.vmin vtotal, since the VTOTAL.Vtotal bits are deprecated.
Since vmin is currently set to crtc_vtotal, this gives us the vtotal.
However, as we move to optimized guardband, vmin will be modified to set
to the minimum Vtotal for highest refresh rate supported.

Instead of depending on vmin, compute vtotal from crtc_vsync_start and
vrr.vsync_start. This works since vrr.vsync_start is measured from the
end of vblank, and crtc_vsync_start is measured from start of the
scanline. Together their sum is equal to the crtc_vtotal.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index fd690de5b45b..855974174afd 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -735,17 +735,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 						     TRANS_VRR_VMAX(display, cpu_transcoder)) + 1;
 		crtc_state->vrr.vmin = intel_de_read(display,
 						     TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;
-
-		/*
-		 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
-		 * bits are not filled. Since for these platforms TRAN_VMIN is always
-		 * filled with crtc_vtotal, use TRAN_VRR_VMIN to get the vtotal for
-		 * adjusted_mode.
-		 */
-		if (intel_vrr_always_use_vrr_tg(display))
-			crtc_state->hw.adjusted_mode.crtc_vtotal =
-				intel_vrr_vmin_vtotal(crtc_state);
-
 		if (HAS_AS_SDP(display)) {
 			trans_vrr_vsync =
 				intel_de_read(display,
@@ -755,6 +744,16 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 			crtc_state->vrr.vsync_end =
 				REG_FIELD_GET(VRR_VSYNC_END_MASK, trans_vrr_vsync);
 		}
+		/*
+		 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
+		 * bits are not filled. Since vrr.vsync_start is computed as:
+		 * crtc_vtotal - crtc_vsync_start, we can derive vtotal from
+		 * vrr.vsync_start and crtc_vsync_start.
+		 */
+		if (intel_vrr_always_use_vrr_tg(display))
+			crtc_state->hw.adjusted_mode.crtc_vtotal =
+				crtc_state->hw.adjusted_mode.crtc_vsync_start +
+				crtc_state->vrr.vsync_start;
 	}
 
 	vrr_enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
-- 
2.45.2

[PATCH 09/15] drm/i915/display: Add guardband check for feature latencies

[Ankit Nautiyal]

Add a check during atomic crtc check phase to ensure the programmed VRR
guardband is sufficient to cover latencies introduced by enabled features
such as DSC, PSR/PR, scalers, and DP SDPs.

Currently, the guardband is programmed to match the vblank length, so
existing checks in skl_is_vblank_too_short() are valid. However, upcoming
changes will optimize the guardband independently of vblank, making those
checks incorrect.

Introduce an explicit guardband check to prepare for future updates
that will remove checking against the vblank length and later program an
optimized guardband.

v2: Use new helper for PSR2/Panel Replay latency.

v3:
-Align the name of helper with intel_crtc_atomic_check and rename it to
intel_crtc_guardband_atomic_check(). (Jani)
-Simplify checks in the helper. (Mitul)
-Make a separate helper to compute wm0 prefill time. (Mitul)

v4: Drop redundant HAS_VRR() check. (Jani).

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 142 +++++++++++++++++++
 drivers/gpu/drm/i915/display/skl_watermark.c |   2 +-
 drivers/gpu/drm/i915/display/skl_watermark.h |   1 +
 3 files changed, 144 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5dca7f96b425..55bea1374dc4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4227,6 +4227,142 @@ static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
 	return 0;
 }
 
+static int
+cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_atomic_state *state =
+		to_intel_atomic_state(crtc_state->uapi.state);
+	const struct intel_cdclk_state *cdclk_state;
+
+	cdclk_state = intel_atomic_get_cdclk_state(state);
+	if (IS_ERR(cdclk_state)) {
+		drm_WARN_ON(display->drm, PTR_ERR(cdclk_state));
+		return 1;
+	}
+
+	return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
+				   2 * intel_cdclk_logical(cdclk_state)));
+}
+
+static int
+dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
+{
+	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
+	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	int num_scaler_users = hweight32(scaler_state->scaler_users);
+	u64 hscale_k[ARRAY_SIZE(scaler_state->scalers)];
+	u64 vscale_k[ARRAY_SIZE(scaler_state->scalers)];
+	u32 dsc_prefill_latency = 0;
+
+	if (!crtc_state->dsc.compression_enable ||
+	    !num_scaler_users ||
+	    num_scaler_users > crtc->num_scalers)
+		return dsc_prefill_latency;
+
+	for (int i = 0; i < num_scaler_users; i++) {
+		hscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
+		vscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
+	}
+
+	dsc_prefill_latency =
+		intel_vrr_guardband_dsc_latency(num_scaler_users, hscale_k, vscale_k,
+						chroma_downscaling_factor,
+						cdclk_prefill_adjustment(crtc_state),
+						linetime);
+
+	return dsc_prefill_latency;
+}
+
+static int
+scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
+{
+	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
+	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
+	int num_scaler_users = hweight32(scaler_state->scaler_users);
+	u64 hscale_k = 0, vscale_k = 0;
+	int scaler_prefill_latency = 0;
+
+	if (!num_scaler_users)
+		return scaler_prefill_latency;
+
+	if (num_scaler_users > 1) {
+		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
+		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
+	}
+
+	scaler_prefill_latency =
+		intel_vrr_guardband_scaler_latency(num_scaler_users, hscale_k, vscale_k,
+						   chroma_downscaling_factor,
+						   cdclk_prefill_adjustment(crtc_state),
+						   linetime);
+
+	return scaler_prefill_latency;
+}
+
+static int
+wm0_prefill_latency(int linetime_us, int max_wm0_lines)
+{
+	return 20 + linetime_us * max_wm0_lines;
+}
+
+static int intel_crtc_guardband_atomic_check(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	int dsc_prefill_time = 0;
+	int scaler_prefill_time;
+	int wm0_prefill_time;
+	int pkgc_max_latency;
+	int psr2_pr_latency;
+	int min_guardband;
+	int guardband_us;
+	int sagv_latency;
+	int linetime_us;
+	int sdp_latency;
+	int pm_delay;
+
+	if (!crtc_state->vrr.enable && !intel_vrr_always_use_vrr_tg(display))
+		return 0;
+
+	if (!adjusted_mode->crtc_clock)
+		return 0;
+
+	linetime_us = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000,
+				   adjusted_mode->crtc_clock);
+
+	pkgc_max_latency = skl_watermark_max_latency(display, 1);
+	sagv_latency = display->sagv.block_time_us;
+
+	wm0_prefill_time = wm0_prefill_latency(linetime_us, skl_max_wm0_lines(crtc_state));
+
+	scaler_prefill_time = scaler_prefill_latency(crtc_state, linetime_us);
+
+	dsc_prefill_time = dsc_prefill_latency(crtc_state, linetime_us);
+
+	pm_delay = crtc_state->framestart_delay +
+		   max(sagv_latency, pkgc_max_latency) +
+		   wm0_prefill_time +
+		   scaler_prefill_time +
+		   dsc_prefill_time;
+
+	psr2_pr_latency = intel_alpm_compute_max_link_wake_latency(crtc_state, false);
+	sdp_latency = intel_dp_compute_sdp_latency(crtc_state, false);
+
+	guardband_us = max(sdp_latency, psr2_pr_latency);
+	guardband_us = max(guardband_us, pm_delay);
+	min_guardband = DIV_ROUND_UP(guardband_us, linetime_us);
+
+	if (crtc_state->vrr.guardband < min_guardband) {
+		drm_dbg_kms(display->drm, "vrr.guardband %d < min guardband %d\n",
+			    crtc_state->vrr.guardband, min_guardband);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 				   struct intel_crtc *crtc)
 {
@@ -4289,6 +4425,12 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 	if (ret)
 		return ret;
 
+	if (intel_vrr_possible(crtc_state)) {
+		ret = intel_crtc_guardband_atomic_check(crtc_state);
+		if (ret)
+			return ret;
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 1ff2b4d9a35e..83ac26004f05 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2250,7 +2250,7 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
 		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
 }
 
-static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
+int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum plane_id plane_id;
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index 62790816f030..8706c2010ebe 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -78,6 +78,7 @@ void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
 void intel_program_dpkgc_latency(struct intel_atomic_state *state);
 
 bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state);
+int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state);
 
 #endif /* __SKL_WATERMARK_H__ */
 
-- 
2.45.2

[PATCH 10/15] drm/i915/skl_watermark: Remove redundant latency checks from vblank validation

[Ankit Nautiyal]

Drop DSC and scaler prefill latency checks from skl_is_vblank_too_short().
These are now covered by the guardband validation added during the atomic
CRTC check phase.

This cleanup prepares for future changes where the guardband will be
optimized independently of vblank length, making vblank-based checks
obsolete.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 79 --------------------
 1 file changed, 79 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 83ac26004f05..07589096b143 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -28,7 +28,6 @@
 #include "intel_flipq.h"
 #include "intel_pcode.h"
 #include "intel_plane.h"
-#include "intel_vrr.h"
 #include "intel_wm.h"
 #include "skl_universal_plane_regs.h"
 #include "skl_scaler.h"
@@ -2159,93 +2158,15 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
-static int
-cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_display *display = to_intel_display(crtc_state);
-	struct intel_atomic_state *state =
-		to_intel_atomic_state(crtc_state->uapi.state);
-	const struct intel_cdclk_state *cdclk_state;
-
-	cdclk_state = intel_atomic_get_cdclk_state(state);
-	if (IS_ERR(cdclk_state)) {
-		drm_WARN_ON(display->drm, PTR_ERR(cdclk_state));
-		return 1;
-	}
-
-	return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
-				   2 * intel_cdclk_logical(cdclk_state)));
-}
-
-static int
-dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
-{
-	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
-	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	int num_scaler_users = hweight32(scaler_state->scaler_users);
-	u64 hscale_k[ARRAY_SIZE(scaler_state->scalers)];
-	u64 vscale_k[ARRAY_SIZE(scaler_state->scalers)];
-	u32 dsc_prefill_latency = 0;
-
-	if (!crtc_state->dsc.compression_enable ||
-	    !num_scaler_users ||
-	    num_scaler_users > crtc->num_scalers)
-		return dsc_prefill_latency;
-
-	for (int i = 0; i < num_scaler_users; i++) {
-		hscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
-		vscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
-	}
-
-	dsc_prefill_latency =
-		intel_vrr_guardband_dsc_latency(num_scaler_users, hscale_k, vscale_k,
-						chroma_downscaling_factor,
-						cdclk_prefill_adjustment(crtc_state),
-						linetime);
-
-	return dsc_prefill_latency;
-}
-
-static int
-scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
-{
-	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
-	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
-	int num_scaler_users = hweight32(scaler_state->scaler_users);
-	u64 hscale_k = 0, vscale_k = 0;
-	int scaler_prefill_latency = 0;
-
-	if (!num_scaler_users)
-		return scaler_prefill_latency;
-
-	if (num_scaler_users > 1) {
-		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
-		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
-	}
-
-	scaler_prefill_latency =
-		intel_vrr_guardband_scaler_latency(num_scaler_users, hscale_k, vscale_k,
-						   chroma_downscaling_factor,
-						   cdclk_prefill_adjustment(crtc_state),
-						   linetime);
-
-	return scaler_prefill_latency;
-}
-
 static bool
 skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
 			int wm0_lines, int latency)
 {
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
-	int linetime = DIV_ROUND_UP(1000 * adjusted_mode->htotal,
-				    adjusted_mode->clock);
 
 	return crtc_state->framestart_delay +
 		intel_usecs_to_scanlines(adjusted_mode, latency) +
-		DIV_ROUND_UP(scaler_prefill_latency(crtc_state, linetime), linetime) +
-		DIV_ROUND_UP(dsc_prefill_latency(crtc_state, linetime), linetime) +
 		wm0_lines >
 		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
 }
-- 
2.45.2

[PATCH 11/15] drm/i915/display: Use vrr.guardband to derive vblank_start

[Ankit Nautiyal]

When VRR TG is always enabled and an optimized guardband is used, the pipe
vblank start is derived from the guardband.
Currently TRANS_SET_CONTEXT_LATENCY is programmed with crtc_vblank_start -
crtc_vdisplay, which is ~1 when guardband matches the vblank length.
With shorter guardband this become a large window.

To avoid misprogramming TRANS_SET_CONTEXT_LATENCY, clamp the scl value to 1
when using optimized guardband.

Also update the VRR get config logic to set crtc_vblank_start based on
vtotal - guardband, during readback.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 36 ++++++++++++++++----
 drivers/gpu/drm/i915/display/intel_vrr.c     |  9 ++++-
 2 files changed, 38 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 55bea1374dc4..73aec6d4686a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2638,6 +2638,30 @@ transcoder_has_vrr(const struct intel_crtc_state *crtc_state)
 	return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
 }
 
+static int intel_set_context_latency(const struct intel_crtc_state *crtc_state,
+				     int crtc_vblank_start,
+				     int crtc_vdisplay)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	/*
+	 * When VRR TG is always on and optimized guardband is used,
+	 * the pipe vblank start is based on the guardband,
+	 * TRANS_SET_CONTEXT_LATENCY cannot be used to configure it.
+	 */
+	if (intel_vrr_always_use_vrr_tg(display))
+		return clamp(crtc_vblank_start - crtc_vdisplay, 0, 1);
+
+	/*
+	 * VBLANK_START no longer works on ADL+, instead we must use
+	 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
+	 */
+	if (DISPLAY_VER(display) >= 13)
+		return crtc_vblank_start - crtc_vdisplay;
+
+	return 0;
+}
+
 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -2671,14 +2695,12 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 			vsyncshift += adjusted_mode->crtc_htotal;
 	}
 
-	/*
-	 * VBLANK_START no longer works on ADL+, instead we must use
-	 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
-	 */
 	if (DISPLAY_VER(display) >= 13) {
 		intel_de_write(display,
 			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
-			       crtc_vblank_start - crtc_vdisplay);
+			       intel_set_context_latency(crtc_state,
+							 crtc_vblank_start,
+							 crtc_vdisplay));
 
 		/*
 		 * VBLANK_START not used by hw, just clear it
@@ -2768,7 +2790,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 	if (DISPLAY_VER(display) >= 13) {
 		intel_de_write(display,
 			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
-			       crtc_vblank_start - crtc_vdisplay);
+			       intel_set_context_latency(crtc_state,
+							 crtc_vblank_start,
+							 crtc_vdisplay));
 
 		/*
 		 * VBLANK_START not used by hw, just clear it
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 855974174afd..e124ef4e0ff4 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -749,11 +749,18 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 		 * bits are not filled. Since vrr.vsync_start is computed as:
 		 * crtc_vtotal - crtc_vsync_start, we can derive vtotal from
 		 * vrr.vsync_start and crtc_vsync_start.
+		 *
+		 * With Optimized guardband, the vblank start is Vtotal - guardband
 		 */
-		if (intel_vrr_always_use_vrr_tg(display))
+		if (intel_vrr_always_use_vrr_tg(display)) {
 			crtc_state->hw.adjusted_mode.crtc_vtotal =
 				crtc_state->hw.adjusted_mode.crtc_vsync_start +
 				crtc_state->vrr.vsync_start;
+
+			crtc_state->hw.adjusted_mode.crtc_vblank_start =
+				crtc_state->hw.adjusted_mode.crtc_vtotal -
+				crtc_state->vrr.guardband;
+		}
 	}
 
 	vrr_enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
-- 
2.45.2

[PATCH 12/15] drm/i915/vrr: Introduce helper to compute min static guardband

[Ankit Nautiyal]

In the current VRR implementation, vrr.vmin and vrr.guardband are set such
that they do not need to change when switching from fixed refresh rate to
variable refresh rate. Specifically, vrr.guardband is always set to match
the vblank length. This approach works for most cases, but not for LRR,
where the guardband would need to change while the VRR timing generator is
still active.

With the VRR TG always active, live updates to guardband are unsafe and not
recommended. To ensure hardware safety, guardband was moved out of the
!fastset block, meaning any change now requires a full modeset.
This breaks seamless LRR switching, which was previously supported.

Since the problem arises from guardband being matched to the vblank length,
solution is to use a minimal, sufficient static value, instead. So we use a
static guardband defined during mode-set that fits within the smallest
expected vblank and remains unchanged in case of features like LRR where
vtotal changes. To compute this minimum guardband we take into account
latencies/delays due to different features as mentioned in the Bspec.

Introduce a helper to compute the minimal sufficient guardband.

v2:
-Use helpers for dsc/scaler prefill latencies. (Mitul)
-Account for pkgc latency and take max of pkgc and sagv latencies.
v3: Use new helper for PSR2/Panel Replay latency.
v4: Avoid re-setting the Vmin/Flipline for optimized guardband.
v5:
-Refactor the function to make it as a helper which can be used to
update crtc_vblank_start and guardband can then be derived from it.
(Ville)
-Modify the subject and commit message for the same.

Bspec: 70151
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> (#v3)
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 117 +++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h |   2 +
 2 files changed, 119 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index e124ef4e0ff4..002165026a20 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -6,12 +6,15 @@
 
 #include <drm/drm_print.h>
 
+#include "intel_alpm.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_vrr.h"
 #include "intel_vrr_regs.h"
+#include "skl_scaler.h"
+#include "skl_watermark.h"
 
 #define FIXED_POINT_PRECISION		100
 #define CMRR_PRECISION_TOLERANCE	10
@@ -811,3 +814,117 @@ int intel_vrr_guardband_dsc_latency(int num_scaler_users, u64 *hscale, u64 *vsca
 
 	return dsc_prefill_latency;
 }
+
+static
+int scaler_prefill_latency(struct intel_crtc_state *crtc_state, int linetime_us)
+{
+	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
+	u64 hscale_k, vscale_k;
+	int cdclk_adjustment;
+	int num_scaler_users;
+
+	/*
+	 * Assuming:
+	 * Both scaler enabled.
+	 * scaler 1 downscaling factor as 2 x 2 (Horiz x Vert)
+	 * scaler 2 downscaling factor as 2 x 1 (Horiz x Vert)
+	 * Cdclk Adjustment : 1
+	 */
+	num_scaler_users = 2;
+	hscale_k = 2 * 1000;
+	vscale_k = 2 * 1000;
+	cdclk_adjustment = 1;
+
+	return intel_vrr_guardband_scaler_latency(num_scaler_users, hscale_k, vscale_k,
+						  chroma_downscaling_factor,
+						  cdclk_adjustment,
+						  linetime_us);
+}
+
+static
+int dsc_prefill_latency(struct intel_crtc_state *crtc_state, int linetime_us)
+{
+#define MAX_SCALERS 2
+	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
+	u64 hscale_k[MAX_SCALERS], vscale_k[MAX_SCALERS];
+	int cdclk_adjustment;
+	int num_scaler_users;
+
+	/*
+	 * Assuming:
+	 * Both scaler enabled.
+	 * scaler 1 downscaling factor as 2 x 2 (Horiz x Vert)
+	 * scaler 2 downscaling factor as 2 x 1 (Horiz x Vert)
+	 * Cdclk Adjustment : 1
+	 */
+	num_scaler_users = MAX_SCALERS;
+	hscale_k[0] = 2 * 1000;
+	vscale_k[0] = 2 * 1000;
+	hscale_k[1] = 2 * 1000;
+	vscale_k[1] = 1 * 1000;
+
+	cdclk_adjustment = 1;
+
+	return intel_vrr_guardband_dsc_latency(num_scaler_users, hscale_k, vscale_k,
+					       chroma_downscaling_factor,
+					       cdclk_adjustment,
+					       linetime_us);
+}
+
+int intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state,
+				struct intel_connector *connector)
+{
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	struct intel_display *display = to_intel_display(crtc_state);
+	int dsc_prefill_time = 0;
+	int psr2_pr_latency = 0;
+	int scaler_prefill_time;
+	int wm0_prefill_time;
+	int pkgc_max_latency;
+	int sagv_latency;
+	int sdp_latency = 0;
+	int guardband_us;
+	int linetime_us;
+	int guardband;
+	int pm_delay;
+
+	linetime_us = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000,
+				   adjusted_mode->crtc_clock);
+
+	pkgc_max_latency = skl_watermark_max_latency(display, 1);
+	sagv_latency = display->sagv.block_time_us;
+
+	/* Assuming max wm0 lines = 4 */
+	wm0_prefill_time = 4 * linetime_us + 20;
+
+	scaler_prefill_time = scaler_prefill_latency(crtc_state, linetime_us);
+
+	if (crtc_state->dsc.compression_enable)
+		dsc_prefill_time = dsc_prefill_latency(crtc_state, linetime_us);
+
+	pm_delay = crtc_state->framestart_delay +
+		   max(sagv_latency, pkgc_max_latency) +
+		   wm0_prefill_time +
+		   scaler_prefill_time +
+		   dsc_prefill_time;
+
+	switch (connector->base.connector_type) {
+	case DRM_MODE_CONNECTOR_eDP:
+	case DRM_MODE_CONNECTOR_DisplayPort:
+		psr2_pr_latency = intel_alpm_compute_max_link_wake_latency(crtc_state, true);
+		sdp_latency = intel_dp_compute_sdp_latency(crtc_state, true);
+		break;
+	default:
+		break;
+	}
+
+	guardband_us = max(sdp_latency, psr2_pr_latency);
+	guardband_us = max(guardband_us, pm_delay);
+
+	guardband = DIV_ROUND_UP(guardband_us, linetime_us);
+
+	/* guardband cannot be more than the Vmax vblank */
+	guardband = min(guardband, crtc_state->vrr.vmax - adjusted_mode->crtc_vblank_start);
+
+	return guardband;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 950041647e47..70a6063ebfb9 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -49,5 +49,7 @@ int intel_vrr_guardband_dsc_latency(int num_scaler_users, u64 *hscale, u64 *vsca
 				    int chroma_downscaling_factor,
 				    int cdclk_prefill_adjustment,
 				    int linetime);
+int intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state,
+				struct intel_connector *connector);
 
 #endif /* __INTEL_VRR_H__ */
-- 
2.45.2

[PATCH 13/15] drm/i915/display: Use optimized guardband to set vblank start

[Ankit Nautiyal]

As we move towards using a shorter, optimized guardband, we need to adjust
how the delayed vblank start is computed.

Use the helper intel_vrr_compute_guardband() to calculate the optimized
guardband. Since this is measured from the vblank end, we shift the
vblank-start accordingly.

Calculate the minimum delay required based on the guardband and apply it
in intel_crtc_vblank_delay() to update crtc_vblank_start.

Additionally, allow vblank delay adjustment during fastset even when
the CRTC state is not inherited, for platforms where vrr timing generator
(and the static guardband) is used. This ensures correct behavior for LRR
scenarios where vtotal changes but the guardband remains static, allowing
seamless mode transitions.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 58 ++++++++++++++++++--
 1 file changed, 53 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 73aec6d4686a..d0265391d660 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2422,14 +2422,55 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
-static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state)
+static
+int intel_crtc_min_guardband_delay(struct intel_atomic_state *state,
+				   struct intel_crtc *crtc)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+	struct drm_connector_state *conn_state;
+	struct drm_connector *drm_connector;
+	int guardband_delay = 0;
+	int vblank_length;
+	int i;
+
+	vblank_length = adjusted_mode->crtc_vblank_end -
+			adjusted_mode->crtc_vblank_start;
+
+	for_each_new_connector_in_state(&state->base,
+					drm_connector,
+					conn_state, i) {
+		int guardband;
+		struct intel_connector *connector;
+
+		if (conn_state->crtc != &crtc->base)
+			continue;
+
+		connector = to_intel_connector(drm_connector);
+		guardband = intel_vrr_compute_guardband(crtc_state,
+							connector);
+		guardband_delay = vblank_length - guardband;
+	}
+
+	return guardband_delay;
+}
+
+static int intel_crtc_vblank_delay(struct intel_atomic_state *state,
+				   struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(state);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 	int vblank_delay = 0;
 
 	if (!HAS_DSB(display))
 		return 0;
 
+	if (intel_vrr_always_use_vrr_tg(display))
+		vblank_delay = intel_crtc_min_guardband_delay(state, crtc);
+
 	vblank_delay = max(vblank_delay, intel_psr_min_vblank_delay(crtc_state));
 
 	return vblank_delay;
@@ -2445,7 +2486,7 @@ static int intel_crtc_compute_vblank_delay(struct intel_atomic_state *state,
 		&crtc_state->hw.adjusted_mode;
 	int vblank_delay, max_vblank_delay;
 
-	vblank_delay = intel_crtc_vblank_delay(crtc_state);
+	vblank_delay = intel_crtc_vblank_delay(state, crtc);
 	max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1;
 
 	if (vblank_delay > max_vblank_delay) {
@@ -5162,9 +5203,16 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s
 	 * Allow fastboot to fix up vblank delay (handled via LRR
 	 * codepaths), a bit dodgy as the registers aren't
 	 * double buffered but seems to be working more or less...
+	 *
+	 * Also allow this when the VRR timing generator is always on,
+	 * which implies optimized guardband is used. In such cases,
+	 * vblank delay may vary even without inherited state, but it's
+	 * still safe as VRR guardband is still same.
 	 */
-	return HAS_LRR(display) && old_crtc_state->inherited &&
-		!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
+	return HAS_LRR(display) &&
+	       (old_crtc_state->inherited ||
+		intel_vrr_always_use_vrr_tg(display)) &&
+	       !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
 }
 
 bool
-- 
2.45.2

[PATCH 14/15] drm/i915/panel: Refactor helper to get highest fixed mode

[Ankit Nautiyal]

Refactor intel_panel_highest_mode() to return the fixed mode with the
highest pixel clock, removing the fallback to the adjusted mode. This makes
the function semantics clearer and better suited for future use cases where
fallback is not desirable.

Update the caller in intel_dp_mode_clock() to handle the NULL case
explicitly by falling back to the adjusted mode's crtc_clock. This also
addresses the existing FIXME comment about ambiguity between clock and
crtc_clock, by using mode->clock for fixed modes and mode->crtc_clock for
adjusted modes.

v2: Avoid introducing a new function and refactor existing one instead.
(Jani).

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c    | 14 +++++++++-----
 drivers/gpu/drm/i915/display/intel_panel.c | 11 +++++------
 drivers/gpu/drm/i915/display/intel_panel.h |  3 +--
 3 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 83c46e4680b3..f74ac98062d4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1760,11 +1760,15 @@ static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
 	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 
-	/* FIXME a bit of a mess wrt clock vs. crtc_clock */
-	if (has_seamless_m_n(connector))
-		return intel_panel_highest_mode(connector, adjusted_mode)->clock;
-	else
-		return adjusted_mode->crtc_clock;
+	if (has_seamless_m_n(connector)) {
+		const struct drm_display_mode *highest_mode;
+
+		highest_mode = intel_panel_highest_mode(connector);
+		if (highest_mode)
+			return highest_mode->clock;
+	}
+
+	return adjusted_mode->crtc_clock;
 }
 
 /* Optimize link config in order: max bpp, min clock, min lanes */
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 2a20aaaaac39..ac0f04073ecb 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -144,18 +144,17 @@ intel_panel_downclock_mode(struct intel_connector *connector,
 }
 
 const struct drm_display_mode *
-intel_panel_highest_mode(struct intel_connector *connector,
-			 const struct drm_display_mode *adjusted_mode)
+intel_panel_highest_mode(struct intel_connector *connector)
 {
-	const struct drm_display_mode *fixed_mode, *best_mode = adjusted_mode;
+	const struct drm_display_mode *fixed_mode, *highest_mode = NULL;
 
 	/* pick the fixed_mode that has the highest clock */
 	list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) {
-		if (fixed_mode->clock > best_mode->clock)
-			best_mode = fixed_mode;
+		if (!highest_mode || fixed_mode->clock > highest_mode->clock)
+			highest_mode = fixed_mode;
 	}
 
-	return best_mode;
+	return highest_mode;
 }
 
 int intel_panel_get_modes(struct intel_connector *connector)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm/i915/display/intel_panel.h
index 56a6412cf0fb..8a17600e46a3 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.h
+++ b/drivers/gpu/drm/i915/display/intel_panel.h
@@ -37,8 +37,7 @@ const struct drm_display_mode *
 intel_panel_downclock_mode(struct intel_connector *connector,
 			   const struct drm_display_mode *adjusted_mode);
 const struct drm_display_mode *
-intel_panel_highest_mode(struct intel_connector *connector,
-			 const struct drm_display_mode *adjusted_mode);
+intel_panel_highest_mode(struct intel_connector *connector);
 int intel_panel_get_modes(struct intel_connector *connector);
 enum drrs_type intel_panel_drrs_type(struct intel_connector *connector);
 enum drm_mode_status
-- 
2.45.2

[PATCH 15/15] drm/i915/vrr: Fix seamless_mn drrs for PTL

[Ankit Nautiyal]

With VRR timing generator always on, the fixed refresh rate is achieved
by setting vrr.flipline and vrr.vmax as the vtotal for the desired mode.

This creates a problem for seamless_mn drrs feature, where user can
seamlessly set a lower mode on the supporting panels. With VRR timing
generator, the vrr.flipline and vrr.vmax are set to vtotal, but that
corresponds to the higher mode.

To fix this, re-compute the vrr timings when seamless_mn drrs is in
picture. At the same time make sure that the vrr.guardband is set as
per the highest mode for such panels, so that switching between higher
to lower mode, does not change the vrr.guardband.

v2: Add a new member `use_highest_mode` to vrr struct to help set the
vrr timings for highest mode for the seamless_mn drrs case.
v3:
-Modify existing function to compute fixed refresh rate timings instead
of adding a new function. (Mitul)
-Tweak computation for scaling the vtotal and use DIV_ROUND_UP_ULL.
-Improve documentation.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  2 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
 drivers/gpu/drm/i915/display/intel_dp.h       |  1 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 90 ++++++++++++++++++-
 4 files changed, 90 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 358ab922d7a7..9796c7b855d0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1321,6 +1321,8 @@ struct intel_crtc_state {
 		u8 pipeline_full;
 		u16 flipline, vmin, vmax, guardband;
 		u32 vsync_end, vsync_start;
+		/* Indicates VRR timing is scaled to highest mode for seamless M/N */
+		bool use_highest_mode;
 	} vrr;
 
 	/* Content Match Refresh Rate state */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f74ac98062d4..5c29c696c83e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1742,7 +1742,7 @@ static int intel_dp_max_bpp(struct intel_dp *intel_dp,
 	return bpp;
 }
 
-static bool has_seamless_m_n(struct intel_connector *connector)
+bool has_seamless_m_n(struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(connector);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index d222749b191c..6da0196c23d1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -217,5 +217,6 @@ void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
 bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
 int intel_dp_compute_sdp_latency(const struct intel_crtc_state *crtc_state,
 				 bool assume_all_enabled);
+bool has_seamless_m_n(struct intel_connector *connector);
 
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 002165026a20..80bbe4b1ef7f 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -11,6 +11,7 @@
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
+#include "intel_panel.h"
 #include "intel_vrr.h"
 #include "intel_vrr_regs.h"
 #include "skl_scaler.h"
@@ -299,6 +300,16 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
+	if (crtc_state->vrr.use_highest_mode) {
+		intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
+			       crtc_state->vrr.vmin - 1);
+		intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
+			       crtc_state->vrr.vmax - 1);
+		intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
+			       crtc_state->vrr.flipline - 1);
+		return;
+	}
+
 	intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
 		       intel_vrr_fixed_rr_vmin(crtc_state) - 1);
 	intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
@@ -307,15 +318,69 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
 		       intel_vrr_fixed_rr_flipline(crtc_state) - 1);
 }
 
+static bool needs_seamless_m_n_timings(struct intel_crtc_state *crtc_state,
+				       struct intel_connector *connector)
+{
+	if (!has_seamless_m_n(connector) || crtc_state->joiner_pipes)
+		return false;
+
+	return true;
+}
+
+static int intel_vrr_scale_vtotal_for_seamless_m_n(struct intel_crtc_state *crtc_state,
+						   struct intel_connector *connector)
+{
+	const struct drm_display_mode *highest_mode = intel_panel_highest_mode(connector);
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	int vtotal = adjusted_mode->crtc_vtotal;
+
+	/*
+	 * For panels with seamless_m_n drrs, the user can seamlessly switch to
+	 * a lower mode, which has a lower clock. This works with legacy timing
+	 * generator, but not with the VRR timing generator.
+	 *
+	 * The VRR timing generator requires flipline and vmax to be equal for
+	 * fixed refresh rate operation. The default fixed RR computation sets
+	 * these to the current mode's vtotal. However, when switching to a
+	 * lower clock mode, this would result in a higher refresh rate than
+	 * desired.
+	 *
+	 * To simulate the lower refresh rate correctly, we scale the vtotal
+	 * based on the ratio of the highest mode's clock to the current mode's
+	 * clock.
+	 *
+	 * When switching to a higher clock mode, the current vtotal already
+	 * results in the desired refresh rate, so no scaling is needed.
+	 *
+	 * So compute the scaled vtotal if required, and update vrr.vmin to
+	 * the scaled value. Also, set vrr.use_highest_mode to indicate that
+	 * VRR timings are based on the highest mode.
+	 */
+	if (highest_mode && adjusted_mode->crtc_clock < highest_mode->clock) {
+		vtotal = DIV_ROUND_UP_ULL(vtotal * highest_mode->clock,
+					  adjusted_mode->crtc_clock);
+		crtc_state->vrr.vmin = vtotal;
+		crtc_state->vrr.use_highest_mode = true;
+	}
+
+	return vtotal;
+}
+
 static
-void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state)
+void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state,
+					struct intel_connector *connector)
 {
+	int vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
+
+	if (needs_seamless_m_n_timings(crtc_state, connector))
+		vtotal = intel_vrr_scale_vtotal_for_seamless_m_n(crtc_state, connector);
+
 	/*
 	 * For fixed rr,  vmin = vmax = flipline.
 	 * vmin is already set to crtc_vtotal set vmax and flipline the same.
 	 */
-	crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.crtc_vtotal;
-	crtc_state->vrr.flipline = crtc_state->hw.adjusted_mode.crtc_vtotal;
+	crtc_state->vrr.vmax = vtotal;
+	crtc_state->vrr.flipline = vtotal;
 }
 
 static
@@ -397,7 +462,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	else if (is_cmrr_frac_required(crtc_state) && is_edp)
 		intel_vrr_compute_cmrr_timings(crtc_state);
 	else
-		intel_vrr_compute_fixed_rr_timings(crtc_state);
+		intel_vrr_compute_fixed_rr_timings(crtc_state, connector);
 
 	/*
 	 * flipline determines the min vblank length the hardware will
@@ -876,6 +941,7 @@ int intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state,
 {
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	struct intel_display *display = to_intel_display(crtc_state);
+	const struct drm_display_mode *highest_mode;
 	int dsc_prefill_time = 0;
 	int psr2_pr_latency = 0;
 	int scaler_prefill_time;
@@ -888,6 +954,22 @@ int intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state,
 	int guardband;
 	int pm_delay;
 
+	/*
+	 * For seamless m_n the clock is changed while other modeline
+	 * parameters are same. In that case the linetime_us will change,
+	 * causing the guardband to change, and the seamless switch to
+	 * lower mode would not take place.
+	 * To avoid this, take the highest mode where panel supports
+	 * seamless drrs and make guardband equal to the vblank length
+	 * for the highest mode.
+	 */
+	highest_mode = intel_panel_highest_mode(connector);
+	if (needs_seamless_m_n_timings(crtc_state, connector) && highest_mode) {
+		guardband = highest_mode->vtotal - highest_mode->vdisplay;
+
+		return guardband;
+	}
+
 	linetime_us = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000,
 				   adjusted_mode->crtc_clock);
 
-- 
2.45.2

✓ CI.KUnit: success for Optimize vrr.guardband and fix LRR (rev11)

[Patchwork]

== Series Details ==

Series: Optimize vrr.guardband and fix LRR (rev11)
URL   : https://patchwork.freedesktop.org/series/151244/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[03:10:15] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[03:10:20] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[03:10:49] Starting KUnit Kernel (1/1)...
[03:10:49] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[03:10:49] ================== guc_buf (11 subtests) ===================
[03:10:49] [PASSED] test_smallest
[03:10:49] [PASSED] test_largest
[03:10:49] [PASSED] test_granular
[03:10:49] [PASSED] test_unique
[03:10:49] [PASSED] test_overlap
[03:10:49] [PASSED] test_reusable
[03:10:49] [PASSED] test_too_big
[03:10:49] [PASSED] test_flush
[03:10:49] [PASSED] test_lookup
[03:10:49] [PASSED] test_data
[03:10:49] [PASSED] test_class
[03:10:49] ===================== [PASSED] guc_buf =====================
[03:10:49] =================== guc_dbm (7 subtests) ===================
[03:10:49] [PASSED] test_empty
[03:10:49] [PASSED] test_default
[03:10:49] ======================== test_size  ========================
[03:10:49] [PASSED] 4
[03:10:49] [PASSED] 8
[03:10:49] [PASSED] 32
[03:10:49] [PASSED] 256
[03:10:49] ==================== [PASSED] test_size ====================
[03:10:49] ======================= test_reuse  ========================
[03:10:49] [PASSED] 4
[03:10:49] [PASSED] 8
[03:10:49] [PASSED] 32
[03:10:49] [PASSED] 256
[03:10:49] =================== [PASSED] test_reuse ====================
[03:10:49] =================== test_range_overlap  ====================
[03:10:49] [PASSED] 4
[03:10:49] [PASSED] 8
[03:10:49] [PASSED] 32
[03:10:49] [PASSED] 256
[03:10:49] =============== [PASSED] test_range_overlap ================
[03:10:49] =================== test_range_compact  ====================
[03:10:49] [PASSED] 4
[03:10:49] [PASSED] 8
[03:10:49] [PASSED] 32
[03:10:49] [PASSED] 256
[03:10:49] =============== [PASSED] test_range_compact ================
[03:10:49] ==================== test_range_spare  =====================
[03:10:49] [PASSED] 4
[03:10:49] [PASSED] 8
[03:10:49] [PASSED] 32
[03:10:49] [PASSED] 256
[03:10:49] ================ [PASSED] test_range_spare =================
[03:10:49] ===================== [PASSED] guc_dbm =====================
[03:10:49] =================== guc_idm (6 subtests) ===================
[03:10:49] [PASSED] bad_init
[03:10:49] [PASSED] no_init
[03:10:49] [PASSED] init_fini
[03:10:49] [PASSED] check_used
[03:10:49] [PASSED] check_quota
[03:10:49] [PASSED] check_all
[03:10:49] ===================== [PASSED] guc_idm =====================
[03:10:49] ================== no_relay (3 subtests) ===================
[03:10:49] [PASSED] xe_drops_guc2pf_if_not_ready
[03:10:49] [PASSED] xe_drops_guc2vf_if_not_ready
[03:10:49] [PASSED] xe_rejects_send_if_not_ready
[03:10:49] ==================== [PASSED] no_relay =====================
[03:10:49] ================== pf_relay (14 subtests) ==================
[03:10:49] [PASSED] pf_rejects_guc2pf_too_short
[03:10:49] [PASSED] pf_rejects_guc2pf_too_long
[03:10:49] [PASSED] pf_rejects_guc2pf_no_payload
[03:10:49] [PASSED] pf_fails_no_payload
[03:10:49] [PASSED] pf_fails_bad_origin
[03:10:49] [PASSED] pf_fails_bad_type
[03:10:49] [PASSED] pf_txn_reports_error
[03:10:49] [PASSED] pf_txn_sends_pf2guc
[03:10:49] [PASSED] pf_sends_pf2guc
[03:10:49] [SKIPPED] pf_loopback_nop
[03:10:49] [SKIPPED] pf_loopback_echo
[03:10:49] [SKIPPED] pf_loopback_fail
[03:10:49] [SKIPPED] pf_loopback_busy
[03:10:49] [SKIPPED] pf_loopback_retry
[03:10:49] ==================== [PASSED] pf_relay =====================
[03:10:49] ================== vf_relay (3 subtests) ===================
[03:10:49] [PASSED] vf_rejects_guc2vf_too_short
[03:10:49] [PASSED] vf_rejects_guc2vf_too_long
[03:10:49] [PASSED] vf_rejects_guc2vf_no_payload
[03:10:49] ==================== [PASSED] vf_relay =====================
[03:10:49] ===================== lmtt (1 subtest) =====================
[03:10:49] ======================== test_ops  =========================
[03:10:49] [PASSED] 2-level
[03:10:49] [PASSED] multi-level
[03:10:49] ==================== [PASSED] test_ops =====================
[03:10:49] ====================== [PASSED] lmtt =======================
[03:10:49] ================= pf_service (11 subtests) =================
[03:10:49] [PASSED] pf_negotiate_any
[03:10:49] [PASSED] pf_negotiate_base_match
[03:10:49] [PASSED] pf_negotiate_base_newer
[03:10:49] [PASSED] pf_negotiate_base_next
[03:10:49] [SKIPPED] pf_negotiate_base_older
[03:10:49] [PASSED] pf_negotiate_base_prev
[03:10:49] [PASSED] pf_negotiate_latest_match
[03:10:49] [PASSED] pf_negotiate_latest_newer
[03:10:49] [PASSED] pf_negotiate_latest_next
[03:10:49] [SKIPPED] pf_negotiate_latest_older
[03:10:49] [SKIPPED] pf_negotiate_latest_prev
[03:10:49] =================== [PASSED] pf_service ====================
[03:10:49] =================== xe_mocs (2 subtests) ===================
[03:10:49] ================ xe_live_mocs_kernel_kunit  ================
[03:10:49] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[03:10:49] ================ xe_live_mocs_reset_kunit  =================
[03:10:49] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[03:10:49] ==================== [SKIPPED] xe_mocs =====================
[03:10:49] ================= xe_migrate (2 subtests) ==================
[03:10:49] ================= xe_migrate_sanity_kunit  =================
[03:10:49] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[03:10:49] ================== xe_validate_ccs_kunit  ==================
[03:10:49] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[03:10:49] =================== [SKIPPED] xe_migrate ===================
[03:10:49] ================== xe_dma_buf (1 subtest) ==================
[03:10:49] ==================== xe_dma_buf_kunit  =====================
[03:10:49] ================ [SKIPPED] xe_dma_buf_kunit ================
[03:10:49] =================== [SKIPPED] xe_dma_buf ===================
[03:10:49] ================= xe_bo_shrink (1 subtest) =================
[03:10:49] =================== xe_bo_shrink_kunit  ====================
[03:10:49] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[03:10:49] ================== [SKIPPED] xe_bo_shrink ==================
[03:10:49] ==================== xe_bo (2 subtests) ====================
[03:10:49] ================== xe_ccs_migrate_kunit  ===================
[03:10:49] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[03:10:49] ==================== xe_bo_evict_kunit  ====================
[03:10:49] =============== [SKIPPED] xe_bo_evict_kunit ================
[03:10:49] ===================== [SKIPPED] xe_bo ======================
[03:10:49] ==================== args (11 subtests) ====================
[03:10:49] [PASSED] count_args_test
[03:10:49] [PASSED] call_args_example
[03:10:49] [PASSED] call_args_test
[03:10:49] [PASSED] drop_first_arg_example
[03:10:49] [PASSED] drop_first_arg_test
[03:10:49] [PASSED] first_arg_example
[03:10:49] [PASSED] first_arg_test
[03:10:49] [PASSED] last_arg_example
[03:10:49] [PASSED] last_arg_test
[03:10:49] [PASSED] pick_arg_example
[03:10:49] [PASSED] sep_comma_example
[03:10:49] ====================== [PASSED] args =======================
[03:10:49] =================== xe_pci (3 subtests) ====================
[03:10:49] ==================== check_graphics_ip  ====================
[03:10:49] [PASSED] 12.70 Xe_LPG
[03:10:49] [PASSED] 12.71 Xe_LPG
[03:10:49] [PASSED] 12.74 Xe_LPG+
[03:10:49] [PASSED] 20.01 Xe2_HPG
[03:10:49] [PASSED] 20.02 Xe2_HPG
[03:10:49] [PASSED] 20.04 Xe2_LPG
[03:10:49] [PASSED] 30.00 Xe3_LPG
[03:10:49] [PASSED] 30.01 Xe3_LPG
[03:10:49] [PASSED] 30.03 Xe3_LPG
[03:10:49] ================ [PASSED] check_graphics_ip ================
[03:10:49] ===================== check_media_ip  ======================
[03:10:49] [PASSED] 13.00 Xe_LPM+
[03:10:49] [PASSED] 13.01 Xe2_HPM
[03:10:49] [PASSED] 20.00 Xe2_LPM
[03:10:49] [PASSED] 30.00 Xe3_LPM
[03:10:49] [PASSED] 30.02 Xe3_LPM
[03:10:49] ================= [PASSED] check_media_ip ==================
[03:10:49] ================= check_platform_gt_count  =================
[03:10:49] [PASSED] 0x9A60 (TIGERLAKE)
[03:10:49] [PASSED] 0x9A68 (TIGERLAKE)
[03:10:49] [PASSED] 0x9A70 (TIGERLAKE)
[03:10:49] [PASSED] 0x9A40 (TIGERLAKE)
[03:10:49] [PASSED] 0x9A49 (TIGERLAKE)
[03:10:49] [PASSED] 0x9A59 (TIGERLAKE)
[03:10:49] [PASSED] 0x9A78 (TIGERLAKE)
[03:10:49] [PASSED] 0x9AC0 (TIGERLAKE)
[03:10:49] [PASSED] 0x9AC9 (TIGERLAKE)
[03:10:49] [PASSED] 0x9AD9 (TIGERLAKE)
[03:10:49] [PASSED] 0x9AF8 (TIGERLAKE)
[03:10:49] [PASSED] 0x4C80 (ROCKETLAKE)
[03:10:49] [PASSED] 0x4C8A (ROCKETLAKE)
[03:10:49] [PASSED] 0x4C8B (ROCKETLAKE)
[03:10:49] [PASSED] 0x4C8C (ROCKETLAKE)
[03:10:49] [PASSED] 0x4C90 (ROCKETLAKE)
[03:10:49] [PASSED] 0x4C9A (ROCKETLAKE)
[03:10:49] [PASSED] 0x4680 (ALDERLAKE_S)
[03:10:49] [PASSED] 0x4682 (ALDERLAKE_S)
[03:10:49] [PASSED] 0x4688 (ALDERLAKE_S)
[03:10:49] [PASSED] 0x468A (ALDERLAKE_S)
[03:10:49] [PASSED] 0x468B (ALDERLAKE_S)
[03:10:49] [PASSED] 0x4690 (ALDERLAKE_S)
[03:10:49] [PASSED] 0x4692 (ALDERLAKE_S)
[03:10:49] [PASSED] 0x4693 (ALDERLAKE_S)
[03:10:49] [PASSED] 0x46A0 (ALDERLAKE_P)
[03:10:49] [PASSED] 0x46A1 (ALDERLAKE_P)
[03:10:49] [PASSED] 0x46A2 (ALDERLAKE_P)
[03:10:49] [PASSED] 0x46A3 (ALDERLAKE_P)
[03:10:49] [PASSED] 0x46A6 (ALDERLAKE_P)
[03:10:49] [PASSED] 0x46A8 (ALDERLAKE_P)
[03:10:49] [PASSED] 0x46AA (ALDERLAKE_P)
[03:10:49] [PASSED] 0x462A (ALDERLAKE_P)
[03:10:49] [PASSED] 0x4626 (ALDERLAKE_P)
[03:10:49] [PASSED] 0x4628 (ALDERLAKE_P)
[03:10:49] [PASSED] 0x46B0 (ALDERLAKE_P)
[03:10:49] [PASSED] 0x46B1 (ALDERLAKE_P)
[03:10:49] [PASSED] 0x46B2 (ALDERLAKE_P)
[03:10:49] [PASSED] 0x46B3 (ALDERLAKE_P)
[03:10:49] [PASSED] 0x46C0 (ALDERLAKE_P)
[03:10:49] [PASSED] 0x46C1 (ALDERLAKE_P)
[03:10:49] [PASSED] 0x46C2 (ALDERLAKE_P)
[03:10:49] [PASSED] 0x46C3 (ALDERLAKE_P)
[03:10:49] [PASSED] 0x46D0 (ALDERLAKE_N)
[03:10:49] [PASSED] 0x46D1 (ALDERLAKE_N)
[03:10:49] [PASSED] 0x46D2 (ALDERLAKE_N)
[03:10:49] [PASSED] 0x46D3 (ALDERLAKE_N)
[03:10:49] [PASSED] 0x46D4 (ALDERLAKE_N)
[03:10:49] [PASSED] 0xA721 (ALDERLAKE_P)
[03:10:49] [PASSED] 0xA7A1 (ALDERLAKE_P)
[03:10:49] [PASSED] 0xA7A9 (ALDERLAKE_P)
[03:10:49] [PASSED] 0xA7AC (ALDERLAKE_P)
[03:10:49] [PASSED] 0xA7AD (ALDERLAKE_P)
[03:10:49] [PASSED] 0xA720 (ALDERLAKE_P)
[03:10:49] [PASSED] 0xA7A0 (ALDERLAKE_P)
[03:10:49] [PASSED] 0xA7A8 (ALDERLAKE_P)
[03:10:49] [PASSED] 0xA7AA (ALDERLAKE_P)
[03:10:49] [PASSED] 0xA7AB (ALDERLAKE_P)
[03:10:49] [PASSED] 0xA780 (ALDERLAKE_S)
[03:10:49] [PASSED] 0xA781 (ALDERLAKE_S)
[03:10:49] [PASSED] 0xA782 (ALDERLAKE_S)
[03:10:49] [PASSED] 0xA783 (ALDERLAKE_S)
[03:10:49] [PASSED] 0xA788 (ALDERLAKE_S)
[03:10:49] [PASSED] 0xA789 (ALDERLAKE_S)
[03:10:49] [PASSED] 0xA78A (ALDERLAKE_S)
[03:10:49] [PASSED] 0xA78B (ALDERLAKE_S)
[03:10:49] [PASSED] 0x4905 (DG1)
[03:10:49] [PASSED] 0x4906 (DG1)
[03:10:49] [PASSED] 0x4907 (DG1)
[03:10:49] [PASSED] 0x4908 (DG1)
[03:10:49] [PASSED] 0x4909 (DG1)
[03:10:49] [PASSED] 0x56C0 (DG2)
[03:10:49] [PASSED] 0x56C2 (DG2)
[03:10:49] [PASSED] 0x56C1 (DG2)
[03:10:49] [PASSED] 0x7D51 (METEORLAKE)
[03:10:49] [PASSED] 0x7DD1 (METEORLAKE)
[03:10:49] [PASSED] 0x7D41 (METEORLAKE)
[03:10:49] [PASSED] 0x7D67 (METEORLAKE)
[03:10:49] [PASSED] 0xB640 (METEORLAKE)
[03:10:49] [PASSED] 0x56A0 (DG2)
[03:10:49] [PASSED] 0x56A1 (DG2)
[03:10:49] [PASSED] 0x56A2 (DG2)
[03:10:49] [PASSED] 0x56BE (DG2)
[03:10:49] [PASSED] 0x56BF (DG2)
[03:10:49] [PASSED] 0x5690 (DG2)
[03:10:49] [PASSED] 0x5691 (DG2)
[03:10:49] [PASSED] 0x5692 (DG2)
[03:10:49] [PASSED] 0x56A5 (DG2)
[03:10:49] [PASSED] 0x56A6 (DG2)
[03:10:49] [PASSED] 0x56B0 (DG2)
[03:10:49] [PASSED] 0x56B1 (DG2)
[03:10:49] [PASSED] 0x56BA (DG2)
[03:10:49] [PASSED] 0x56BB (DG2)
[03:10:49] [PASSED] 0x56BC (DG2)
[03:10:49] [PASSED] 0x56BD (DG2)
[03:10:49] [PASSED] 0x5693 (DG2)
[03:10:49] [PASSED] 0x5694 (DG2)
[03:10:49] [PASSED] 0x5695 (DG2)
[03:10:49] [PASSED] 0x56A3 (DG2)
[03:10:49] [PASSED] 0x56A4 (DG2)
[03:10:49] [PASSED] 0x56B2 (DG2)
[03:10:49] [PASSED] 0x56B3 (DG2)
[03:10:49] [PASSED] 0x5696 (DG2)
[03:10:49] [PASSED] 0x5697 (DG2)
[03:10:49] [PASSED] 0xB69 (PVC)
[03:10:49] [PASSED] 0xB6E (PVC)
[03:10:49] [PASSED] 0xBD4 (PVC)
[03:10:49] [PASSED] 0xBD5 (PVC)
[03:10:49] [PASSED] 0xBD6 (PVC)
[03:10:49] [PASSED] 0xBD7 (PVC)
[03:10:49] [PASSED] 0xBD8 (PVC)
[03:10:49] [PASSED] 0xBD9 (PVC)
[03:10:49] [PASSED] 0xBDA (PVC)
[03:10:49] [PASSED] 0xBDB (PVC)
[03:10:49] [PASSED] 0xBE0 (PVC)
[03:10:49] [PASSED] 0xBE1 (PVC)
[03:10:49] [PASSED] 0xBE5 (PVC)
[03:10:49] [PASSED] 0x7D40 (METEORLAKE)
[03:10:49] [PASSED] 0x7D45 (METEORLAKE)
[03:10:49] [PASSED] 0x7D55 (METEORLAKE)
[03:10:49] [PASSED] 0x7D60 (METEORLAKE)
[03:10:49] [PASSED] 0x7DD5 (METEORLAKE)
[03:10:49] [PASSED] 0x6420 (LUNARLAKE)
[03:10:49] [PASSED] 0x64A0 (LUNARLAKE)
[03:10:49] [PASSED] 0x64B0 (LUNARLAKE)
[03:10:49] [PASSED] 0xE202 (BATTLEMAGE)
[03:10:49] [PASSED] 0xE209 (BATTLEMAGE)
[03:10:49] [PASSED] 0xE20B (BATTLEMAGE)
[03:10:49] [PASSED] 0xE20C (BATTLEMAGE)
[03:10:49] [PASSED] 0xE20D (BATTLEMAGE)
[03:10:49] [PASSED] 0xE210 (BATTLEMAGE)
[03:10:49] [PASSED] 0xE211 (BATTLEMAGE)
[03:10:49] [PASSED] 0xE212 (BATTLEMAGE)
[03:10:49] [PASSED] 0xE216 (BATTLEMAGE)
[03:10:49] [PASSED] 0xE220 (BATTLEMAGE)
[03:10:49] [PASSED] 0xE221 (BATTLEMAGE)
[03:10:49] [PASSED] 0xE222 (BATTLEMAGE)
[03:10:49] [PASSED] 0xE223 (BATTLEMAGE)
[03:10:49] [PASSED] 0xB080 (PANTHERLAKE)
[03:10:49] [PASSED] 0xB081 (PANTHERLAKE)
[03:10:49] [PASSED] 0xB082 (PANTHERLAKE)
[03:10:49] [PASSED] 0xB083 (PANTHERLAKE)
[03:10:49] [PASSED] 0xB084 (PANTHERLAKE)
[03:10:49] [PASSED] 0xB085 (PANTHERLAKE)
[03:10:49] [PASSED] 0xB086 (PANTHERLAKE)
[03:10:49] [PASSED] 0xB087 (PANTHERLAKE)
[03:10:49] [PASSED] 0xB08F (PANTHERLAKE)
[03:10:49] [PASSED] 0xB090 (PANTHERLAKE)
[03:10:49] [PASSED] 0xB0A0 (PANTHERLAKE)
[03:10:49] [PASSED] 0xB0B0 (PANTHERLAKE)
[03:10:49] [PASSED] 0xFD80 (PANTHERLAKE)
[03:10:49] [PASSED] 0xFD81 (PANTHERLAKE)
[03:10:49] ============= [PASSED] check_platform_gt_count =============
[03:10:49] ===================== [PASSED] xe_pci ======================
[03:10:49] =================== xe_rtp (2 subtests) ====================
[03:10:49] =============== xe_rtp_process_to_sr_tests  ================
[03:10:49] [PASSED] coalesce-same-reg
[03:10:49] [PASSED] no-match-no-add
[03:10:49] [PASSED] match-or
[03:10:49] [PASSED] match-or-xfail
[03:10:49] [PASSED] no-match-no-add-multiple-rules
[03:10:49] [PASSED] two-regs-two-entries
[03:10:49] [PASSED] clr-one-set-other
[03:10:49] [PASSED] set-field
[03:10:49] [PASSED] conflict-duplicate
[03:10:49] [PASSED] conflict-not-disjoint
[03:10:49] [PASSED] conflict-reg-type
[03:10:49] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[03:10:49] ================== xe_rtp_process_tests  ===================
[03:10:49] [PASSED] active1
[03:10:49] [PASSED] active2
[03:10:49] [PASSED] active-inactive
[03:10:49] [PASSED] inactive-active
[03:10:49] [PASSED] inactive-1st_or_active-inactive
[03:10:49] [PASSED] inactive-2nd_or_active-inactive
[03:10:49] [PASSED] inactive-last_or_active-inactive
[03:10:49] [PASSED] inactive-no_or_active-inactive
[03:10:49] ============== [PASSED] xe_rtp_process_tests ===============
[03:10:49] ===================== [PASSED] xe_rtp ======================
[03:10:49] ==================== xe_wa (1 subtest) =====================
[03:10:49] ======================== xe_wa_gt  =========================
[03:10:49] [PASSED] TIGERLAKE B0
[03:10:49] [PASSED] DG1 A0
[03:10:49] [PASSED] DG1 B0
[03:10:49] [PASSED] ALDERLAKE_S A0
[03:10:49] [PASSED] ALDERLAKE_S B0
[03:10:49] [PASSED] ALDERLAKE_S C0
[03:10:49] [PASSED] ALDERLAKE_S D0
[03:10:49] [PASSED] ALDERLAKE_P A0
[03:10:49] [PASSED] ALDERLAKE_P B0
[03:10:49] [PASSED] ALDERLAKE_P C0
[03:10:49] [PASSED] ALDERLAKE_S RPLS D0
[03:10:49] [PASSED] ALDERLAKE_P RPLU E0
[03:10:49] [PASSED] DG2 G10 C0
[03:10:49] [PASSED] DG2 G11 B1
[03:10:49] [PASSED] DG2 G12 A1
[03:10:49] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[03:10:49] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[03:10:49] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[03:10:49] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
stty: 'standard input': Inappropriate ioctl for device
[03:10:49] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[03:10:49] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[03:10:49] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[03:10:49] ==================== [PASSED] xe_wa_gt =====================
[03:10:49] ====================== [PASSED] xe_wa ======================
[03:10:49] ============================================================
[03:10:49] Testing complete. Ran 298 tests: passed: 282, skipped: 16
[03:10:49] Elapsed time: 33.803s total, 4.189s configuring, 29.247s building, 0.324s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[03:10:49] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[03:10:51] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[03:11:14] Starting KUnit Kernel (1/1)...
[03:11:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[03:11:14] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[03:11:14] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[03:11:14] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[03:11:14] =========== drm_validate_clone_mode (2 subtests) ===========
[03:11:14] ============== drm_test_check_in_clone_mode  ===============
[03:11:14] [PASSED] in_clone_mode
[03:11:14] [PASSED] not_in_clone_mode
[03:11:14] ========== [PASSED] drm_test_check_in_clone_mode ===========
[03:11:14] =============== drm_test_check_valid_clones  ===============
[03:11:14] [PASSED] not_in_clone_mode
[03:11:14] [PASSED] valid_clone
[03:11:14] [PASSED] invalid_clone
[03:11:14] =========== [PASSED] drm_test_check_valid_clones ===========
[03:11:14] ============= [PASSED] drm_validate_clone_mode =============
[03:11:14] ============= drm_validate_modeset (1 subtest) =============
[03:11:14] [PASSED] drm_test_check_connector_changed_modeset
[03:11:14] ============== [PASSED] drm_validate_modeset ===============
[03:11:14] ====== drm_test_bridge_get_current_state (2 subtests) ======
[03:11:14] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[03:11:14] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[03:11:14] ======== [PASSED] drm_test_bridge_get_current_state ========
[03:11:14] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[03:11:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[03:11:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[03:11:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[03:11:14] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[03:11:14] ============== drm_bridge_alloc (2 subtests) ===============
[03:11:14] [PASSED] drm_test_drm_bridge_alloc_basic
[03:11:14] [PASSED] drm_test_drm_bridge_alloc_get_put
[03:11:14] ================ [PASSED] drm_bridge_alloc =================
[03:11:14] ================== drm_buddy (7 subtests) ==================
[03:11:14] [PASSED] drm_test_buddy_alloc_limit
[03:11:14] [PASSED] drm_test_buddy_alloc_optimistic
[03:11:14] [PASSED] drm_test_buddy_alloc_pessimistic
[03:11:14] [PASSED] drm_test_buddy_alloc_pathological
[03:11:14] [PASSED] drm_test_buddy_alloc_contiguous
[03:11:14] [PASSED] drm_test_buddy_alloc_clear
[03:11:14] [PASSED] drm_test_buddy_alloc_range_bias
[03:11:14] ==================== [PASSED] drm_buddy ====================
[03:11:14] ============= drm_cmdline_parser (40 subtests) =============
[03:11:14] [PASSED] drm_test_cmdline_force_d_only
[03:11:14] [PASSED] drm_test_cmdline_force_D_only_dvi
[03:11:14] [PASSED] drm_test_cmdline_force_D_only_hdmi
[03:11:14] [PASSED] drm_test_cmdline_force_D_only_not_digital
[03:11:14] [PASSED] drm_test_cmdline_force_e_only
[03:11:14] [PASSED] drm_test_cmdline_res
[03:11:14] [PASSED] drm_test_cmdline_res_vesa
[03:11:14] [PASSED] drm_test_cmdline_res_vesa_rblank
[03:11:14] [PASSED] drm_test_cmdline_res_rblank
[03:11:14] [PASSED] drm_test_cmdline_res_bpp
[03:11:14] [PASSED] drm_test_cmdline_res_refresh
[03:11:14] [PASSED] drm_test_cmdline_res_bpp_refresh
[03:11:14] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[03:11:14] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[03:11:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[03:11:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[03:11:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[03:11:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[03:11:14] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[03:11:14] [PASSED] drm_test_cmdline_res_margins_force_on
[03:11:14] [PASSED] drm_test_cmdline_res_vesa_margins
[03:11:14] [PASSED] drm_test_cmdline_name
[03:11:14] [PASSED] drm_test_cmdline_name_bpp
[03:11:14] [PASSED] drm_test_cmdline_name_option
[03:11:14] [PASSED] drm_test_cmdline_name_bpp_option
[03:11:14] [PASSED] drm_test_cmdline_rotate_0
[03:11:14] [PASSED] drm_test_cmdline_rotate_90
[03:11:14] [PASSED] drm_test_cmdline_rotate_180
[03:11:14] [PASSED] drm_test_cmdline_rotate_270
[03:11:14] [PASSED] drm_test_cmdline_hmirror
[03:11:14] [PASSED] drm_test_cmdline_vmirror
[03:11:14] [PASSED] drm_test_cmdline_margin_options
[03:11:14] [PASSED] drm_test_cmdline_multiple_options
[03:11:14] [PASSED] drm_test_cmdline_bpp_extra_and_option
[03:11:14] [PASSED] drm_test_cmdline_extra_and_option
[03:11:14] [PASSED] drm_test_cmdline_freestanding_options
[03:11:14] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[03:11:14] [PASSED] drm_test_cmdline_panel_orientation
[03:11:14] ================ drm_test_cmdline_invalid  =================
[03:11:14] [PASSED] margin_only
[03:11:14] [PASSED] interlace_only
[03:11:14] [PASSED] res_missing_x
[03:11:14] [PASSED] res_missing_y
[03:11:14] [PASSED] res_bad_y
[03:11:14] [PASSED] res_missing_y_bpp
[03:11:14] [PASSED] res_bad_bpp
[03:11:14] [PASSED] res_bad_refresh
[03:11:14] [PASSED] res_bpp_refresh_force_on_off
[03:11:14] [PASSED] res_invalid_mode
[03:11:14] [PASSED] res_bpp_wrong_place_mode
[03:11:14] [PASSED] name_bpp_refresh
[03:11:14] [PASSED] name_refresh
[03:11:14] [PASSED] name_refresh_wrong_mode
[03:11:14] [PASSED] name_refresh_invalid_mode
[03:11:14] [PASSED] rotate_multiple
[03:11:14] [PASSED] rotate_invalid_val
[03:11:14] [PASSED] rotate_truncated
[03:11:14] [PASSED] invalid_option
[03:11:14] [PASSED] invalid_tv_option
[03:11:14] [PASSED] truncated_tv_option
[03:11:14] ============ [PASSED] drm_test_cmdline_invalid =============
[03:11:14] =============== drm_test_cmdline_tv_options  ===============
[03:11:14] [PASSED] NTSC
[03:11:14] [PASSED] NTSC_443
[03:11:14] [PASSED] NTSC_J
[03:11:14] [PASSED] PAL
[03:11:14] [PASSED] PAL_M
[03:11:14] [PASSED] PAL_N
[03:11:14] [PASSED] SECAM
[03:11:14] [PASSED] MONO_525
[03:11:14] [PASSED] MONO_625
[03:11:14] =========== [PASSED] drm_test_cmdline_tv_options ===========
[03:11:14] =============== [PASSED] drm_cmdline_parser ================
[03:11:14] ========== drmm_connector_hdmi_init (20 subtests) ==========
[03:11:14] [PASSED] drm_test_connector_hdmi_init_valid
[03:11:14] [PASSED] drm_test_connector_hdmi_init_bpc_8
[03:11:14] [PASSED] drm_test_connector_hdmi_init_bpc_10
[03:11:14] [PASSED] drm_test_connector_hdmi_init_bpc_12
[03:11:14] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[03:11:14] [PASSED] drm_test_connector_hdmi_init_bpc_null
[03:11:14] [PASSED] drm_test_connector_hdmi_init_formats_empty
[03:11:14] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[03:11:14] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[03:11:14] [PASSED] supported_formats=0x9 yuv420_allowed=1
[03:11:14] [PASSED] supported_formats=0x9 yuv420_allowed=0
[03:11:14] [PASSED] supported_formats=0x3 yuv420_allowed=1
[03:11:14] [PASSED] supported_formats=0x3 yuv420_allowed=0
[03:11:14] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[03:11:14] [PASSED] drm_test_connector_hdmi_init_null_ddc
[03:11:14] [PASSED] drm_test_connector_hdmi_init_null_product
[03:11:14] [PASSED] drm_test_connector_hdmi_init_null_vendor
[03:11:14] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[03:11:14] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[03:11:14] [PASSED] drm_test_connector_hdmi_init_product_valid
[03:11:14] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[03:11:14] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[03:11:14] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[03:11:14] ========= drm_test_connector_hdmi_init_type_valid  =========
[03:11:14] [PASSED] HDMI-A
[03:11:14] [PASSED] HDMI-B
[03:11:14] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[03:11:14] ======== drm_test_connector_hdmi_init_type_invalid  ========
[03:11:14] [PASSED] Unknown
[03:11:14] [PASSED] VGA
[03:11:14] [PASSED] DVI-I
[03:11:14] [PASSED] DVI-D
[03:11:14] [PASSED] DVI-A
[03:11:14] [PASSED] Composite
[03:11:14] [PASSED] SVIDEO
[03:11:14] [PASSED] LVDS
[03:11:14] [PASSED] Component
[03:11:14] [PASSED] DIN
[03:11:14] [PASSED] DP
[03:11:14] [PASSED] TV
[03:11:14] [PASSED] eDP
[03:11:14] [PASSED] Virtual
[03:11:14] [PASSED] DSI
[03:11:14] [PASSED] DPI
[03:11:14] [PASSED] Writeback
[03:11:14] [PASSED] SPI
[03:11:14] [PASSED] USB
[03:11:14] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[03:11:14] ============ [PASSED] drmm_connector_hdmi_init =============
[03:11:14] ============= drmm_connector_init (3 subtests) =============
[03:11:14] [PASSED] drm_test_drmm_connector_init
[03:11:14] [PASSED] drm_test_drmm_connector_init_null_ddc
[03:11:14] ========= drm_test_drmm_connector_init_type_valid  =========
[03:11:14] [PASSED] Unknown
[03:11:14] [PASSED] VGA
[03:11:14] [PASSED] DVI-I
[03:11:14] [PASSED] DVI-D
[03:11:14] [PASSED] DVI-A
[03:11:14] [PASSED] Composite
[03:11:14] [PASSED] SVIDEO
[03:11:14] [PASSED] LVDS
[03:11:14] [PASSED] Component
[03:11:14] [PASSED] DIN
[03:11:14] [PASSED] DP
[03:11:14] [PASSED] HDMI-A
[03:11:14] [PASSED] HDMI-B
[03:11:14] [PASSED] TV
[03:11:14] [PASSED] eDP
[03:11:14] [PASSED] Virtual
[03:11:14] [PASSED] DSI
[03:11:14] [PASSED] DPI
[03:11:14] [PASSED] Writeback
[03:11:14] [PASSED] SPI
[03:11:14] [PASSED] USB
[03:11:14] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[03:11:14] =============== [PASSED] drmm_connector_init ===============
[03:11:14] ========= drm_connector_dynamic_init (6 subtests) ==========
[03:11:14] [PASSED] drm_test_drm_connector_dynamic_init
[03:11:14] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[03:11:14] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[03:11:14] [PASSED] drm_test_drm_connector_dynamic_init_properties
[03:11:14] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[03:11:14] [PASSED] Unknown
[03:11:14] [PASSED] VGA
[03:11:14] [PASSED] DVI-I
[03:11:14] [PASSED] DVI-D
[03:11:14] [PASSED] DVI-A
[03:11:14] [PASSED] Composite
[03:11:14] [PASSED] SVIDEO
[03:11:14] [PASSED] LVDS
[03:11:14] [PASSED] Component
[03:11:14] [PASSED] DIN
[03:11:14] [PASSED] DP
[03:11:14] [PASSED] HDMI-A
[03:11:14] [PASSED] HDMI-B
[03:11:14] [PASSED] TV
[03:11:14] [PASSED] eDP
[03:11:14] [PASSED] Virtual
[03:11:14] [PASSED] DSI
[03:11:14] [PASSED] DPI
[03:11:14] [PASSED] Writeback
[03:11:14] [PASSED] SPI
[03:11:14] [PASSED] USB
[03:11:14] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[03:11:14] ======== drm_test_drm_connector_dynamic_init_name  =========
[03:11:14] [PASSED] Unknown
[03:11:14] [PASSED] VGA
[03:11:14] [PASSED] DVI-I
[03:11:14] [PASSED] DVI-D
[03:11:14] [PASSED] DVI-A
[03:11:14] [PASSED] Composite
[03:11:14] [PASSED] SVIDEO
[03:11:14] [PASSED] LVDS
[03:11:14] [PASSED] Component
[03:11:14] [PASSED] DIN
[03:11:14] [PASSED] DP
[03:11:14] [PASSED] HDMI-A
[03:11:14] [PASSED] HDMI-B
[03:11:14] [PASSED] TV
[03:11:14] [PASSED] eDP
[03:11:14] [PASSED] Virtual
[03:11:14] [PASSED] DSI
[03:11:14] [PASSED] DPI
[03:11:14] [PASSED] Writeback
[03:11:14] [PASSED] SPI
[03:11:14] [PASSED] USB
[03:11:14] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[03:11:14] =========== [PASSED] drm_connector_dynamic_init ============
[03:11:14] ==== drm_connector_dynamic_register_early (4 subtests) =====
[03:11:14] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[03:11:14] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[03:11:14] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[03:11:14] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[03:11:14] ====== [PASSED] drm_connector_dynamic_register_early =======
[03:11:14] ======= drm_connector_dynamic_register (7 subtests) ========
[03:11:14] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[03:11:14] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[03:11:14] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[03:11:14] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[03:11:14] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[03:11:14] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[03:11:14] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[03:11:14] ========= [PASSED] drm_connector_dynamic_register ==========
[03:11:14] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[03:11:14] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[03:11:14] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[03:11:14] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[03:11:14] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[03:11:14] ========== drm_test_get_tv_mode_from_name_valid  ===========
[03:11:14] [PASSED] NTSC
[03:11:14] [PASSED] NTSC-443
[03:11:14] [PASSED] NTSC-J
[03:11:14] [PASSED] PAL
[03:11:14] [PASSED] PAL-M
[03:11:14] [PASSED] PAL-N
[03:11:14] [PASSED] SECAM
[03:11:14] [PASSED] Mono
[03:11:14] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[03:11:14] [PASSED] drm_test_get_tv_mode_from_name_truncated
[03:11:14] ============ [PASSED] drm_get_tv_mode_from_name ============
[03:11:14] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[03:11:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[03:11:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[03:11:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[03:11:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[03:11:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[03:11:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[03:11:14] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[03:11:14] [PASSED] VIC 96
[03:11:14] [PASSED] VIC 97
[03:11:14] [PASSED] VIC 101
[03:11:14] [PASSED] VIC 102
[03:11:14] [PASSED] VIC 106
[03:11:14] [PASSED] VIC 107
[03:11:14] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[03:11:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[03:11:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[03:11:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[03:11:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[03:11:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[03:11:14] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[03:11:14] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[03:11:14] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[03:11:14] [PASSED] Automatic
[03:11:14] [PASSED] Full
[03:11:14] [PASSED] Limited 16:235
[03:11:14] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[03:11:14] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[03:11:14] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[03:11:14] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[03:11:14] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[03:11:14] [PASSED] RGB
[03:11:14] [PASSED] YUV 4:2:0
[03:11:14] [PASSED] YUV 4:2:2
[03:11:14] [PASSED] YUV 4:4:4
[03:11:14] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[03:11:14] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[03:11:14] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[03:11:14] ============= drm_damage_helper (21 subtests) ==============
[03:11:14] [PASSED] drm_test_damage_iter_no_damage
[03:11:14] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[03:11:14] [PASSED] drm_test_damage_iter_no_damage_src_moved
[03:11:14] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[03:11:14] [PASSED] drm_test_damage_iter_no_damage_not_visible
[03:11:14] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[03:11:14] [PASSED] drm_test_damage_iter_no_damage_no_fb
[03:11:14] [PASSED] drm_test_damage_iter_simple_damage
[03:11:14] [PASSED] drm_test_damage_iter_single_damage
[03:11:14] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[03:11:14] [PASSED] drm_test_damage_iter_single_damage_outside_src
[03:11:14] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[03:11:14] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[03:11:14] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[03:11:14] [PASSED] drm_test_damage_iter_single_damage_src_moved
[03:11:14] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[03:11:14] [PASSED] drm_test_damage_iter_damage
[03:11:14] [PASSED] drm_test_damage_iter_damage_one_intersect
[03:11:14] [PASSED] drm_test_damage_iter_damage_one_outside
[03:11:14] [PASSED] drm_test_damage_iter_damage_src_moved
[03:11:14] [PASSED] drm_test_damage_iter_damage_not_visible
[03:11:14] ================ [PASSED] drm_damage_helper ================
[03:11:14] ============== drm_dp_mst_helper (3 subtests) ==============
[03:11:14] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[03:11:14] [PASSED] Clock 154000 BPP 30 DSC disabled
[03:11:14] [PASSED] Clock 234000 BPP 30 DSC disabled
[03:11:14] [PASSED] Clock 297000 BPP 24 DSC disabled
[03:11:14] [PASSED] Clock 332880 BPP 24 DSC enabled
[03:11:14] [PASSED] Clock 324540 BPP 24 DSC enabled
[03:11:14] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[03:11:14] ============== drm_test_dp_mst_calc_pbn_div  ===============
[03:11:14] [PASSED] Link rate 2000000 lane count 4
[03:11:14] [PASSED] Link rate 2000000 lane count 2
[03:11:14] [PASSED] Link rate 2000000 lane count 1
[03:11:14] [PASSED] Link rate 1350000 lane count 4
[03:11:14] [PASSED] Link rate 1350000 lane count 2
[03:11:14] [PASSED] Link rate 1350000 lane count 1
[03:11:14] [PASSED] Link rate 1000000 lane count 4
[03:11:14] [PASSED] Link rate 1000000 lane count 2
[03:11:14] [PASSED] Link rate 1000000 lane count 1
[03:11:14] [PASSED] Link rate 810000 lane count 4
[03:11:14] [PASSED] Link rate 810000 lane count 2
[03:11:14] [PASSED] Link rate 810000 lane count 1
[03:11:14] [PASSED] Link rate 540000 lane count 4
[03:11:14] [PASSED] Link rate 540000 lane count 2
[03:11:14] [PASSED] Link rate 540000 lane count 1
[03:11:14] [PASSED] Link rate 270000 lane count 4
[03:11:14] [PASSED] Link rate 270000 lane count 2
[03:11:14] [PASSED] Link rate 270000 lane count 1
[03:11:14] [PASSED] Link rate 162000 lane count 4
[03:11:14] [PASSED] Link rate 162000 lane count 2
[03:11:14] [PASSED] Link rate 162000 lane count 1
[03:11:14] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[03:11:14] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[03:11:14] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[03:11:14] [PASSED] DP_POWER_UP_PHY with port number
[03:11:14] [PASSED] DP_POWER_DOWN_PHY with port number
[03:11:14] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[03:11:14] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[03:11:14] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[03:11:14] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[03:11:14] [PASSED] DP_QUERY_PAYLOAD with port number
[03:11:14] [PASSED] DP_QUERY_PAYLOAD with VCPI
[03:11:14] [PASSED] DP_REMOTE_DPCD_READ with port number
[03:11:14] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[03:11:14] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[03:11:14] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[03:11:14] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[03:11:14] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[03:11:14] [PASSED] DP_REMOTE_I2C_READ with port number
[03:11:14] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[03:11:14] [PASSED] DP_REMOTE_I2C_READ with transactions array
[03:11:14] [PASSED] DP_REMOTE_I2C_WRITE with port number
[03:11:14] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[03:11:14] [PASSED] DP_REMOTE_I2C_WRITE with data array
[03:11:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[03:11:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[03:11:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[03:11:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[03:11:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[03:11:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[03:11:14] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[03:11:14] ================ [PASSED] drm_dp_mst_helper ================
[03:11:14] ================== drm_exec (7 subtests) ===================
[03:11:14] [PASSED] sanitycheck
[03:11:14] [PASSED] test_lock
[03:11:14] [PASSED] test_lock_unlock
[03:11:14] [PASSED] test_duplicates
[03:11:14] [PASSED] test_prepare
[03:11:14] [PASSED] test_prepare_array
[03:11:14] [PASSED] test_multiple_loops
[03:11:14] ==================== [PASSED] drm_exec =====================
[03:11:14] =========== drm_format_helper_test (17 subtests) ===========
[03:11:14] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[03:11:14] [PASSED] single_pixel_source_buffer
[03:11:14] [PASSED] single_pixel_clip_rectangle
[03:11:14] [PASSED] well_known_colors
[03:11:14] [PASSED] destination_pitch
[03:11:14] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[03:11:14] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[03:11:14] [PASSED] single_pixel_source_buffer
[03:11:14] [PASSED] single_pixel_clip_rectangle
[03:11:14] [PASSED] well_known_colors
[03:11:14] [PASSED] destination_pitch
[03:11:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[03:11:14] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[03:11:14] [PASSED] single_pixel_source_buffer
[03:11:14] [PASSED] single_pixel_clip_rectangle
[03:11:14] [PASSED] well_known_colors
[03:11:14] [PASSED] destination_pitch
[03:11:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[03:11:14] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[03:11:14] [PASSED] single_pixel_source_buffer
[03:11:14] [PASSED] single_pixel_clip_rectangle
[03:11:14] [PASSED] well_known_colors
[03:11:14] [PASSED] destination_pitch
[03:11:14] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[03:11:14] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[03:11:14] [PASSED] single_pixel_source_buffer
[03:11:14] [PASSED] single_pixel_clip_rectangle
[03:11:14] [PASSED] well_known_colors
[03:11:14] [PASSED] destination_pitch
[03:11:14] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[03:11:14] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[03:11:14] [PASSED] single_pixel_source_buffer
[03:11:14] [PASSED] single_pixel_clip_rectangle
[03:11:14] [PASSED] well_known_colors
[03:11:14] [PASSED] destination_pitch
[03:11:14] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[03:11:14] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[03:11:14] [PASSED] single_pixel_source_buffer
[03:11:14] [PASSED] single_pixel_clip_rectangle
[03:11:14] [PASSED] well_known_colors
[03:11:14] [PASSED] destination_pitch
[03:11:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[03:11:14] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[03:11:14] [PASSED] single_pixel_source_buffer
[03:11:14] [PASSED] single_pixel_clip_rectangle
[03:11:14] [PASSED] well_known_colors
[03:11:14] [PASSED] destination_pitch
[03:11:14] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[03:11:14] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[03:11:14] [PASSED] single_pixel_source_buffer
[03:11:14] [PASSED] single_pixel_clip_rectangle
[03:11:14] [PASSED] well_known_colors
[03:11:14] [PASSED] destination_pitch
[03:11:14] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[03:11:14] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[03:11:14] [PASSED] single_pixel_source_buffer
[03:11:14] [PASSED] single_pixel_clip_rectangle
[03:11:14] [PASSED] well_known_colors
[03:11:14] [PASSED] destination_pitch
[03:11:14] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[03:11:14] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[03:11:14] [PASSED] single_pixel_source_buffer
[03:11:14] [PASSED] single_pixel_clip_rectangle
[03:11:14] [PASSED] well_known_colors
[03:11:14] [PASSED] destination_pitch
[03:11:14] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[03:11:14] ============== drm_test_fb_xrgb8888_to_mono  ===============
[03:11:14] [PASSED] single_pixel_source_buffer
[03:11:14] [PASSED] single_pixel_clip_rectangle
[03:11:14] [PASSED] well_known_colors
[03:11:14] [PASSED] destination_pitch
[03:11:14] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[03:11:14] ==================== drm_test_fb_swab  =====================
[03:11:14] [PASSED] single_pixel_source_buffer
[03:11:14] [PASSED] single_pixel_clip_rectangle
[03:11:14] [PASSED] well_known_colors
[03:11:14] [PASSED] destination_pitch
[03:11:14] ================ [PASSED] drm_test_fb_swab =================
[03:11:14] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[03:11:14] [PASSED] single_pixel_source_buffer
[03:11:14] [PASSED] single_pixel_clip_rectangle
[03:11:14] [PASSED] well_known_colors
[03:11:14] [PASSED] destination_pitch
[03:11:14] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[03:11:14] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[03:11:14] [PASSED] single_pixel_source_buffer
[03:11:14] [PASSED] single_pixel_clip_rectangle
[03:11:14] [PASSED] well_known_colors
[03:11:14] [PASSED] destination_pitch
[03:11:14] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[03:11:14] ================= drm_test_fb_clip_offset  =================
[03:11:14] [PASSED] pass through
[03:11:14] [PASSED] horizontal offset
[03:11:14] [PASSED] vertical offset
[03:11:14] [PASSED] horizontal and vertical offset
[03:11:14] [PASSED] horizontal offset (custom pitch)
[03:11:14] [PASSED] vertical offset (custom pitch)
[03:11:14] [PASSED] horizontal and vertical offset (custom pitch)
[03:11:14] ============= [PASSED] drm_test_fb_clip_offset =============
[03:11:14] =================== drm_test_fb_memcpy  ====================
[03:11:14] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[03:11:14] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[03:11:14] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[03:11:14] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[03:11:14] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[03:11:14] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[03:11:14] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[03:11:14] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[03:11:14] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[03:11:14] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[03:11:14] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[03:11:14] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[03:11:14] =============== [PASSED] drm_test_fb_memcpy ================
[03:11:14] ============= [PASSED] drm_format_helper_test ==============
[03:11:14] ================= drm_format (18 subtests) =================
[03:11:14] [PASSED] drm_test_format_block_width_invalid
[03:11:14] [PASSED] drm_test_format_block_width_one_plane
[03:11:14] [PASSED] drm_test_format_block_width_two_plane
[03:11:14] [PASSED] drm_test_format_block_width_three_plane
[03:11:14] [PASSED] drm_test_format_block_width_tiled
[03:11:14] [PASSED] drm_test_format_block_height_invalid
[03:11:14] [PASSED] drm_test_format_block_height_one_plane
[03:11:14] [PASSED] drm_test_format_block_height_two_plane
[03:11:14] [PASSED] drm_test_format_block_height_three_plane
[03:11:14] [PASSED] drm_test_format_block_height_tiled
[03:11:14] [PASSED] drm_test_format_min_pitch_invalid
[03:11:14] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[03:11:14] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[03:11:14] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[03:11:14] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[03:11:14] [PASSED] drm_test_format_min_pitch_two_plane
[03:11:14] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[03:11:14] [PASSED] drm_test_format_min_pitch_tiled
[03:11:14] =================== [PASSED] drm_format ====================
[03:11:14] ============== drm_framebuffer (10 subtests) ===============
[03:11:14] ========== drm_test_framebuffer_check_src_coords  ==========
[03:11:14] [PASSED] Success: source fits into fb
[03:11:14] [PASSED] Fail: overflowing fb with x-axis coordinate
[03:11:14] [PASSED] Fail: overflowing fb with y-axis coordinate
[03:11:14] [PASSED] Fail: overflowing fb with source width
[03:11:14] [PASSED] Fail: overflowing fb with source height
[03:11:14] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[03:11:14] [PASSED] drm_test_framebuffer_cleanup
[03:11:14] =============== drm_test_framebuffer_create  ===============
[03:11:14] [PASSED] ABGR8888 normal sizes
[03:11:14] [PASSED] ABGR8888 max sizes
[03:11:14] [PASSED] ABGR8888 pitch greater than min required
[03:11:14] [PASSED] ABGR8888 pitch less than min required
[03:11:14] [PASSED] ABGR8888 Invalid width
[03:11:14] [PASSED] ABGR8888 Invalid buffer handle
[03:11:14] [PASSED] No pixel format
[03:11:14] [PASSED] ABGR8888 Width 0
[03:11:14] [PASSED] ABGR8888 Height 0
[03:11:14] [PASSED] ABGR8888 Out of bound height * pitch combination
[03:11:14] [PASSED] ABGR8888 Large buffer offset
[03:11:14] [PASSED] ABGR8888 Buffer offset for inexistent plane
[03:11:14] [PASSED] ABGR8888 Invalid flag
[03:11:14] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[03:11:14] [PASSED] ABGR8888 Valid buffer modifier
[03:11:14] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[03:11:14] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[03:11:14] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[03:11:14] [PASSED] NV12 Normal sizes
[03:11:14] [PASSED] NV12 Max sizes
[03:11:14] [PASSED] NV12 Invalid pitch
[03:11:14] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[03:11:14] [PASSED] NV12 different  modifier per-plane
[03:11:14] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[03:11:14] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[03:11:14] [PASSED] NV12 Modifier for inexistent plane
[03:11:14] [PASSED] NV12 Handle for inexistent plane
[03:11:14] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[03:11:14] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[03:11:14] [PASSED] YVU420 Normal sizes
[03:11:14] [PASSED] YVU420 Max sizes
[03:11:14] [PASSED] YVU420 Invalid pitch
[03:11:14] [PASSED] YVU420 Different pitches
[03:11:14] [PASSED] YVU420 Different buffer offsets/pitches
[03:11:14] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[03:11:14] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[03:11:14] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[03:11:14] [PASSED] YVU420 Valid modifier
[03:11:14] [PASSED] YVU420 Different modifiers per plane
[03:11:14] [PASSED] YVU420 Modifier for inexistent plane
[03:11:14] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[03:11:14] [PASSED] X0L2 Normal sizes
[03:11:14] [PASSED] X0L2 Max sizes
[03:11:14] [PASSED] X0L2 Invalid pitch
[03:11:14] [PASSED] X0L2 Pitch greater than minimum required
[03:11:14] [PASSED] X0L2 Handle for inexistent plane
[03:11:14] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[03:11:14] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[03:11:14] [PASSED] X0L2 Valid modifier
[03:11:14] [PASSED] X0L2 Modifier for inexistent plane
[03:11:14] =========== [PASSED] drm_test_framebuffer_create ===========
[03:11:14] [PASSED] drm_test_framebuffer_free
[03:11:14] [PASSED] drm_test_framebuffer_init
[03:11:14] [PASSED] drm_test_framebuffer_init_bad_format
[03:11:14] [PASSED] drm_test_framebuffer_init_dev_mismatch
[03:11:14] [PASSED] drm_test_framebuffer_lookup
[03:11:14] [PASSED] drm_test_framebuffer_lookup_inexistent
[03:11:14] [PASSED] drm_test_framebuffer_modifiers_not_supported
[03:11:14] ================= [PASSED] drm_framebuffer =================
[03:11:14] ================ drm_gem_shmem (8 subtests) ================
[03:11:14] [PASSED] drm_gem_shmem_test_obj_create
[03:11:14] [PASSED] drm_gem_shmem_test_obj_create_private
[03:11:14] [PASSED] drm_gem_shmem_test_pin_pages
[03:11:14] [PASSED] drm_gem_shmem_test_vmap
[03:11:14] [PASSED] drm_gem_shmem_test_get_pages_sgt
[03:11:14] [PASSED] drm_gem_shmem_test_get_sg_table
[03:11:14] [PASSED] drm_gem_shmem_test_madvise
[03:11:14] [PASSED] drm_gem_shmem_test_purge
[03:11:14] ================== [PASSED] drm_gem_shmem ==================
[03:11:14] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[03:11:14] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[03:11:14] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[03:11:14] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[03:11:14] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[03:11:14] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[03:11:14] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[03:11:14] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[03:11:14] [PASSED] Automatic
[03:11:14] [PASSED] Full
[03:11:14] [PASSED] Limited 16:235
[03:11:14] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[03:11:14] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[03:11:14] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[03:11:14] [PASSED] drm_test_check_disable_connector
[03:11:14] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[03:11:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[03:11:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[03:11:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[03:11:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[03:11:14] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[03:11:14] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[03:11:14] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[03:11:14] [PASSED] drm_test_check_output_bpc_dvi
[03:11:14] [PASSED] drm_test_check_output_bpc_format_vic_1
[03:11:14] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[03:11:14] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[03:11:14] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[03:11:14] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[03:11:14] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[03:11:14] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[03:11:14] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[03:11:14] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[03:11:14] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[03:11:14] [PASSED] drm_test_check_broadcast_rgb_value
[03:11:14] [PASSED] drm_test_check_bpc_8_value
[03:11:14] [PASSED] drm_test_check_bpc_10_value
[03:11:14] [PASSED] drm_test_check_bpc_12_value
[03:11:14] [PASSED] drm_test_check_format_value
[03:11:14] [PASSED] drm_test_check_tmds_char_value
[03:11:14] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[03:11:14] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[03:11:14] [PASSED] drm_test_check_mode_valid
[03:11:14] [PASSED] drm_test_check_mode_valid_reject
[03:11:14] [PASSED] drm_test_check_mode_valid_reject_rate
[03:11:14] [PASSED] drm_test_check_mode_valid_reject_max_clock
[03:11:14] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[03:11:14] ================= drm_managed (2 subtests) =================
[03:11:14] [PASSED] drm_test_managed_release_action
[03:11:14] [PASSED] drm_test_managed_run_action
[03:11:14] =================== [PASSED] drm_managed ===================
[03:11:14] =================== drm_mm (6 subtests) ====================
[03:11:14] [PASSED] drm_test_mm_init
[03:11:14] [PASSED] drm_test_mm_debug
[03:11:14] [PASSED] drm_test_mm_align32
[03:11:14] [PASSED] drm_test_mm_align64
[03:11:14] [PASSED] drm_test_mm_lowest
[03:11:14] [PASSED] drm_test_mm_highest
[03:11:14] ===================== [PASSED] drm_mm ======================
[03:11:14] ============= drm_modes_analog_tv (5 subtests) =============
[03:11:14] [PASSED] drm_test_modes_analog_tv_mono_576i
[03:11:14] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[03:11:14] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[03:11:14] [PASSED] drm_test_modes_analog_tv_pal_576i
[03:11:14] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[03:11:14] =============== [PASSED] drm_modes_analog_tv ===============
[03:11:14] ============== drm_plane_helper (2 subtests) ===============
[03:11:14] =============== drm_test_check_plane_state  ================
[03:11:14] [PASSED] clipping_simple
[03:11:14] [PASSED] clipping_rotate_reflect
[03:11:14] [PASSED] positioning_simple
[03:11:14] [PASSED] upscaling
[03:11:14] [PASSED] downscaling
[03:11:14] [PASSED] rounding1
[03:11:14] [PASSED] rounding2
[03:11:14] [PASSED] rounding3
[03:11:14] [PASSED] rounding4
[03:11:14] =========== [PASSED] drm_test_check_plane_state ============
[03:11:14] =========== drm_test_check_invalid_plane_state  ============
[03:11:14] [PASSED] positioning_invalid
[03:11:14] [PASSED] upscaling_invalid
[03:11:14] [PASSED] downscaling_invalid
[03:11:14] ======= [PASSED] drm_test_check_invalid_plane_state ========
[03:11:14] ================ [PASSED] drm_plane_helper =================
[03:11:14] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[03:11:14] ====== drm_test_connector_helper_tv_get_modes_check  =======
[03:11:14] [PASSED] None
[03:11:14] [PASSED] PAL
[03:11:14] [PASSED] NTSC
[03:11:14] [PASSED] Both, NTSC Default
[03:11:14] [PASSED] Both, PAL Default
[03:11:14] [PASSED] Both, NTSC Default, with PAL on command-line
[03:11:14] [PASSED] Both, PAL Default, with NTSC on command-line
[03:11:14] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[03:11:14] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[03:11:14] ================== drm_rect (9 subtests) ===================
[03:11:14] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[03:11:14] [PASSED] drm_test_rect_clip_scaled_not_clipped
[03:11:14] [PASSED] drm_test_rect_clip_scaled_clipped
[03:11:14] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[03:11:14] ================= drm_test_rect_intersect  =================
[03:11:14] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[03:11:14] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[03:11:14] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[03:11:14] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[03:11:14] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[03:11:14] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[03:11:14] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[03:11:14] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[03:11:14] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[03:11:14] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[03:11:14] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[03:11:14] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[03:11:14] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[03:11:14] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[03:11:14] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[03:11:14] ============= [PASSED] drm_test_rect_intersect =============
[03:11:14] ================ drm_test_rect_calc_hscale  ================
[03:11:14] [PASSED] normal use
[03:11:14] [PASSED] out of max range
[03:11:14] [PASSED] out of min range
[03:11:14] [PASSED] zero dst
[03:11:14] [PASSED] negative src
[03:11:14] [PASSED] negative dst
[03:11:14] ============ [PASSED] drm_test_rect_calc_hscale ============
[03:11:14] ================ drm_test_rect_calc_vscale  ================
[03:11:14] [PASSED] normal use
[03:11:14] [PASSED] out of max range
[03:11:14] [PASSED] out of min range
[03:11:14] [PASSED] zero dst
[03:11:14] [PASSED] negative src
[03:11:14] [PASSED] negative dst
[03:11:14] ============ [PASSED] drm_test_rect_calc_vscale ============
[03:11:14] ================== drm_test_rect_rotate  ===================
[03:11:14] [PASSED] reflect-x
[03:11:14] [PASSED] reflect-y
[03:11:14] [PASSED] rotate-0
[03:11:14] [PASSED] rotate-90
[03:11:14] [PASSED] rotate-180
[03:11:14] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[03:11:14] ============== [PASSED] drm_test_rect_rotate ===============
[03:11:14] ================ drm_test_rect_rotate_inv  =================
[03:11:14] [PASSED] reflect-x
[03:11:14] [PASSED] reflect-y
[03:11:14] [PASSED] rotate-0
[03:11:14] [PASSED] rotate-90
[03:11:14] [PASSED] rotate-180
[03:11:14] [PASSED] rotate-270
[03:11:14] ============ [PASSED] drm_test_rect_rotate_inv =============
[03:11:14] ==================== [PASSED] drm_rect =====================
[03:11:14] ============ drm_sysfb_modeset_test (1 subtest) ============
[03:11:14] ============ drm_test_sysfb_build_fourcc_list  =============
[03:11:14] [PASSED] no native formats
[03:11:14] [PASSED] XRGB8888 as native format
[03:11:14] [PASSED] remove duplicates
[03:11:14] [PASSED] convert alpha formats
[03:11:14] [PASSED] random formats
[03:11:14] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[03:11:14] ============= [PASSED] drm_sysfb_modeset_test ==============
[03:11:14] ============================================================
[03:11:14] Testing complete. Ran 616 tests: passed: 616
[03:11:14] Elapsed time: 24.966s total, 1.713s configuring, 23.035s building, 0.195s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[03:11:14] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[03:11:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[03:11:24] Starting KUnit Kernel (1/1)...
[03:11:24] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[03:11:24] ================= ttm_device (5 subtests) ==================
[03:11:24] [PASSED] ttm_device_init_basic
[03:11:24] [PASSED] ttm_device_init_multiple
[03:11:24] [PASSED] ttm_device_fini_basic
[03:11:24] [PASSED] ttm_device_init_no_vma_man
[03:11:24] ================== ttm_device_init_pools  ==================
[03:11:24] [PASSED] No DMA allocations, no DMA32 required
[03:11:24] [PASSED] DMA allocations, DMA32 required
[03:11:24] [PASSED] No DMA allocations, DMA32 required
[03:11:24] [PASSED] DMA allocations, no DMA32 required
[03:11:24] ============== [PASSED] ttm_device_init_pools ==============
[03:11:24] =================== [PASSED] ttm_device ====================
[03:11:24] ================== ttm_pool (8 subtests) ===================
[03:11:24] ================== ttm_pool_alloc_basic  ===================
[03:11:24] [PASSED] One page
[03:11:24] [PASSED] More than one page
[03:11:24] [PASSED] Above the allocation limit
[03:11:24] [PASSED] One page, with coherent DMA mappings enabled
[03:11:24] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[03:11:24] ============== [PASSED] ttm_pool_alloc_basic ===============
[03:11:24] ============== ttm_pool_alloc_basic_dma_addr  ==============
[03:11:24] [PASSED] One page
[03:11:24] [PASSED] More than one page
[03:11:24] [PASSED] Above the allocation limit
[03:11:24] [PASSED] One page, with coherent DMA mappings enabled
[03:11:24] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[03:11:24] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[03:11:24] [PASSED] ttm_pool_alloc_order_caching_match
[03:11:24] [PASSED] ttm_pool_alloc_caching_mismatch
[03:11:24] [PASSED] ttm_pool_alloc_order_mismatch
[03:11:24] [PASSED] ttm_pool_free_dma_alloc
[03:11:24] [PASSED] ttm_pool_free_no_dma_alloc
[03:11:24] [PASSED] ttm_pool_fini_basic
[03:11:24] ==================== [PASSED] ttm_pool =====================
[03:11:24] ================ ttm_resource (8 subtests) =================
[03:11:24] ================= ttm_resource_init_basic  =================
[03:11:24] [PASSED] Init resource in TTM_PL_SYSTEM
[03:11:24] [PASSED] Init resource in TTM_PL_VRAM
[03:11:24] [PASSED] Init resource in a private placement
[03:11:24] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[03:11:24] ============= [PASSED] ttm_resource_init_basic =============
[03:11:24] [PASSED] ttm_resource_init_pinned
[03:11:24] [PASSED] ttm_resource_fini_basic
[03:11:24] [PASSED] ttm_resource_manager_init_basic
[03:11:24] [PASSED] ttm_resource_manager_usage_basic
[03:11:24] [PASSED] ttm_resource_manager_set_used_basic
[03:11:24] [PASSED] ttm_sys_man_alloc_basic
[03:11:24] [PASSED] ttm_sys_man_free_basic
[03:11:24] ================== [PASSED] ttm_resource ===================
[03:11:24] =================== ttm_tt (15 subtests) ===================
[03:11:24] ==================== ttm_tt_init_basic  ====================
[03:11:24] [PASSED] Page-aligned size
[03:11:24] [PASSED] Extra pages requested
[03:11:24] ================ [PASSED] ttm_tt_init_basic ================
[03:11:24] [PASSED] ttm_tt_init_misaligned
[03:11:24] [PASSED] ttm_tt_fini_basic
[03:11:24] [PASSED] ttm_tt_fini_sg
[03:11:24] [PASSED] ttm_tt_fini_shmem
[03:11:24] [PASSED] ttm_tt_create_basic
[03:11:24] [PASSED] ttm_tt_create_invalid_bo_type
[03:11:24] [PASSED] ttm_tt_create_ttm_exists
[03:11:24] [PASSED] ttm_tt_create_failed
[03:11:24] [PASSED] ttm_tt_destroy_basic
[03:11:24] [PASSED] ttm_tt_populate_null_ttm
[03:11:24] [PASSED] ttm_tt_populate_populated_ttm
[03:11:24] [PASSED] ttm_tt_unpopulate_basic
[03:11:24] [PASSED] ttm_tt_unpopulate_empty_ttm
[03:11:24] [PASSED] ttm_tt_swapin_basic
[03:11:24] ===================== [PASSED] ttm_tt ======================
[03:11:24] =================== ttm_bo (14 subtests) ===================
[03:11:24] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[03:11:24] [PASSED] Cannot be interrupted and sleeps
[03:11:24] [PASSED] Cannot be interrupted, locks straight away
[03:11:24] [PASSED] Can be interrupted, sleeps
[03:11:24] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[03:11:24] [PASSED] ttm_bo_reserve_locked_no_sleep
[03:11:24] [PASSED] ttm_bo_reserve_no_wait_ticket
[03:11:24] [PASSED] ttm_bo_reserve_double_resv
[03:11:24] [PASSED] ttm_bo_reserve_interrupted
[03:11:24] [PASSED] ttm_bo_reserve_deadlock
[03:11:24] [PASSED] ttm_bo_unreserve_basic
[03:11:24] [PASSED] ttm_bo_unreserve_pinned
[03:11:24] [PASSED] ttm_bo_unreserve_bulk
[03:11:24] [PASSED] ttm_bo_put_basic
[03:11:24] [PASSED] ttm_bo_put_shared_resv
[03:11:24] [PASSED] ttm_bo_pin_basic
[03:11:24] [PASSED] ttm_bo_pin_unpin_resource
[03:11:24] [PASSED] ttm_bo_multiple_pin_one_unpin
[03:11:24] ===================== [PASSED] ttm_bo ======================
[03:11:24] ============== ttm_bo_validate (21 subtests) ===============
[03:11:24] ============== ttm_bo_init_reserved_sys_man  ===============
[03:11:24] [PASSED] Buffer object for userspace
[03:11:24] [PASSED] Kernel buffer object
[03:11:24] [PASSED] Shared buffer object
[03:11:24] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[03:11:24] ============== ttm_bo_init_reserved_mock_man  ==============
[03:11:24] [PASSED] Buffer object for userspace
[03:11:24] [PASSED] Kernel buffer object
[03:11:24] [PASSED] Shared buffer object
[03:11:24] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[03:11:24] [PASSED] ttm_bo_init_reserved_resv
[03:11:24] ================== ttm_bo_validate_basic  ==================
[03:11:24] [PASSED] Buffer object for userspace
[03:11:24] [PASSED] Kernel buffer object
[03:11:24] [PASSED] Shared buffer object
[03:11:24] ============== [PASSED] ttm_bo_validate_basic ==============
[03:11:24] [PASSED] ttm_bo_validate_invalid_placement
[03:11:24] ============= ttm_bo_validate_same_placement  ==============
[03:11:24] [PASSED] System manager
[03:11:24] [PASSED] VRAM manager
[03:11:24] ========= [PASSED] ttm_bo_validate_same_placement ==========
[03:11:24] [PASSED] ttm_bo_validate_failed_alloc
[03:11:24] [PASSED] ttm_bo_validate_pinned
[03:11:24] [PASSED] ttm_bo_validate_busy_placement
[03:11:24] ================ ttm_bo_validate_multihop  =================
[03:11:24] [PASSED] Buffer object for userspace
[03:11:24] [PASSED] Kernel buffer object
[03:11:24] [PASSED] Shared buffer object
[03:11:24] ============ [PASSED] ttm_bo_validate_multihop =============
[03:11:24] ========== ttm_bo_validate_no_placement_signaled  ==========
[03:11:24] [PASSED] Buffer object in system domain, no page vector
[03:11:24] [PASSED] Buffer object in system domain with an existing page vector
[03:11:24] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[03:11:24] ======== ttm_bo_validate_no_placement_not_signaled  ========
[03:11:24] [PASSED] Buffer object for userspace
[03:11:24] [PASSED] Kernel buffer object
[03:11:24] [PASSED] Shared buffer object
[03:11:24] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[03:11:24] [PASSED] ttm_bo_validate_move_fence_signaled
[03:11:24] ========= ttm_bo_validate_move_fence_not_signaled  =========
[03:11:24] [PASSED] Waits for GPU
[03:11:24] [PASSED] Tries to lock straight away
[03:11:24] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[03:11:24] [PASSED] ttm_bo_validate_happy_evict
[03:11:24] [PASSED] ttm_bo_validate_all_pinned_evict
[03:11:24] [PASSED] ttm_bo_validate_allowed_only_evict
[03:11:24] [PASSED] ttm_bo_validate_deleted_evict
[03:11:24] [PASSED] ttm_bo_validate_busy_domain_evict
[03:11:24] [PASSED] ttm_bo_validate_evict_gutting
[03:11:24] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[03:11:24] ================= [PASSED] ttm_bo_validate =================
[03:11:24] ============================================================
[03:11:24] Testing complete. Ran 101 tests: passed: 101
[03:11:24] Elapsed time: 9.922s total, 1.733s configuring, 7.923s building, 0.230s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Optimize vrr.guardband and fix LRR (rev11)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1280 bytes --]

== Series Details ==

Series: Optimize vrr.guardband and fix LRR (rev11)
URL   : https://patchwork.freedesktop.org/series/151244/
State : success

== Summary ==

CI Bug Log - changes from xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225_BAT -> xe-pw-151244v11_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-151244v11_BAT that come from known issues:

### IGT changes ###

  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#5783]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5783


Build changes
-------------

  * Linux: xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225 -> xe-pw-151244v11

  IGT_8532: 3b9f234d6efe0529a233b81bb0d5ffee5adddb01 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225: e925396dbb0b8094e00ca3d47a375538d429b225
  xe-pw-151244v11: 151244v11

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/index.html

[-- Attachment #2: Type: text/html, Size: 1758 bytes --]

✓ Xe.CI.Full: success for Optimize vrr.guardband and fix LRR (rev11)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 63718 bytes --]

== Series Details ==

Series: Optimize vrr.guardband and fix LRR (rev11)
URL   : https://patchwork.freedesktop.org/series/151244/
State : success

== Summary ==

CI Bug Log - changes from xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225_FULL -> xe-pw-151244v11_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

New tests
---------

  New tests have been introduced between xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225_FULL and xe-pw-151244v11_FULL:

### New IGT tests (3) ###

  * igt@kms_cursor_crc@cursor-offscreen-128x42@pipe-d-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [2.33] s

  * igt@kms_cursor_crc@cursor-onscreen-128x42@pipe-d-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [2.34] s

  * igt@kms_plane_multiple@tiling-x@pipe-d-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.75] s

  

Known issues
------------

  Here are the changes found in xe-pw-151244v11_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@read:
    - shard-dg2-set2:     [PASS][1] -> [SKIP][2] ([Intel XE#2134]) +3 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@fbdev@read.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@fbdev@read.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][3] ([Intel XE#316])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-adlp:         [PASS][4] -> [DMESG-FAIL][5] ([Intel XE#4543])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-adlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-adlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-0:
    - shard-adlp:         [PASS][6] -> [DMESG-WARN][7] ([Intel XE#2953] / [Intel XE#4173]) +7 other tests dmesg-warn
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-adlp-4/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-adlp-3/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-180:
    - shard-dg2-set2:     NOTRUN -> [SKIP][8] ([Intel XE#1124]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-433/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html

  * igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
    - shard-bmg:          [PASS][9] -> [SKIP][10] ([Intel XE#2314] / [Intel XE#2894])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#2191]) +2 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][12] ([Intel XE#787]) +125 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-433/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [PASS][13] -> [SKIP][14] ([Intel XE#2351] / [Intel XE#4208]) +15 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-435/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs@pipe-b-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-4/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs@pipe-b-dp-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-d-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][16] ([Intel XE#455] / [Intel XE#787]) +21 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-d-dp-2.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][17] -> [INCOMPLETE][18] ([Intel XE#2705] / [Intel XE#4212])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html

  * igt@kms_cdclk@plane-scaling@pipe-b-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][19] ([Intel XE#4416]) +3 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@kms_cdclk@plane-scaling@pipe-b-dp-2.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - shard-dg2-set2:     NOTRUN -> [SKIP][20] ([Intel XE#373]) +2 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-433/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][21] ([Intel XE#1178])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-5/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][22] ([Intel XE#3304])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-464/igt@kms_content_protection@lic-type-0@pipe-a-dp-4.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-dg2-set2:     NOTRUN -> [SKIP][23] ([Intel XE#308])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-433/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][24] -> [DMESG-WARN][25] ([Intel XE#5354])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-4/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
    - shard-bmg:          [PASS][26] -> [SKIP][27] ([Intel XE#2291]) +3 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-dg2-set2:     NOTRUN -> [SKIP][28] ([Intel XE#4331])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-dg2-set2:     NOTRUN -> [SKIP][29] ([Intel XE#776])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@display-3x:
    - shard-dg2-set2:     NOTRUN -> [SKIP][30] ([Intel XE#703])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@kms_feature_discovery@display-3x.html

  * igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset:
    - shard-bmg:          [PASS][31] -> [SKIP][32] ([Intel XE#2316]) +6 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-4/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-6/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html

  * igt@kms_flip@flip-vs-dpms-on-nop-interruptible:
    - shard-adlp:         [PASS][33] -> [DMESG-WARN][34] ([Intel XE#4543]) +4 other tests dmesg-warn
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-adlp-6/igt@kms_flip@flip-vs-dpms-on-nop-interruptible.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-adlp-4/igt@kms_flip@flip-vs-dpms-on-nop-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-dg2-set2:     [PASS][35] -> [FAIL][36] ([Intel XE#301]) +1 other test fail
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-464/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [PASS][37] -> [FAIL][38] ([Intel XE#301])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [PASS][39] -> [FAIL][40] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][41] ([Intel XE#455]) +6 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-433/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-pgflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][42] ([Intel XE#651]) +11 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][43] ([Intel XE#653]) +5 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg2-set2:     [PASS][44] -> [SKIP][45] ([Intel XE#455])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-463/igt@kms_hdr@invalid-hdr.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-433/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-bmg:          [PASS][46] -> [SKIP][47] ([Intel XE#1503]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-4/igt@kms_hdr@invalid-metadata-sizes.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-6/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-dg2-set2:     NOTRUN -> [SKIP][48] ([Intel XE#4359])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_pm_rpm@universal-planes:
    - shard-adlp:         [PASS][49] -> [DMESG-WARN][50] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#5750])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-adlp-4/igt@kms_pm_rpm@universal-planes.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-adlp-3/igt@kms_pm_rpm@universal-planes.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][51] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-433/igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf.html

  * igt@kms_psr@pr-sprite-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][52] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +2 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@kms_psr@pr-sprite-render.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][53] ([Intel XE#3414]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@xe_copy_basic@mem-copy-linear-0x3fff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][54] ([Intel XE#1123])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-433/igt@xe_copy_basic@mem-copy-linear-0x3fff.html

  * igt@xe_eudebug@vma-ufence-faultable:
    - shard-dg2-set2:     NOTRUN -> [SKIP][55] ([Intel XE#4837]) +6 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@xe_eudebug@vma-ufence-faultable.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind:
    - shard-dg2-set2:     NOTRUN -> [SKIP][56] ([Intel XE#1392])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race:
    - shard-dg2-set2:     [PASS][57] -> [SKIP][58] ([Intel XE#1392]) +4 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_basic@once-userptr-invalidate-race:
    - shard-dg2-set2:     [PASS][59] -> [SKIP][60] ([Intel XE#4208]) +392 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@xe_exec_basic@once-userptr-invalidate-race.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_exec_basic@once-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@once-userptr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][61] ([Intel XE#288]) +8 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-433/igt@xe_exec_fault_mode@once-userptr.html

  * igt@xe_exec_system_allocator@process-many-mmap-free-race-nomemset:
    - shard-dg2-set2:     NOTRUN -> [SKIP][62] ([Intel XE#4915]) +78 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-433/igt@xe_exec_system_allocator@process-many-mmap-free-race-nomemset.html

  * igt@xe_module_load@reload:
    - shard-dg2-set2:     [PASS][63] -> [FAIL][64] ([Intel XE#4208]) +1 other test fail
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@xe_module_load@reload.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_module_load@reload.html

  * igt@xe_oa@oa-regs-whitelisted:
    - shard-dg2-set2:     NOTRUN -> [SKIP][65] ([Intel XE#3573]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-433/igt@xe_oa@oa-regs-whitelisted.html

  * igt@xe_pxp@pxp-termination-key-update-post-rpm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][66] ([Intel XE#4733]) +2 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@xe_pxp@pxp-termination-key-update-post-rpm.html

  * igt@xe_query@multigpu-query-oa-units:
    - shard-dg2-set2:     NOTRUN -> [SKIP][67] ([Intel XE#944])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@xe_query@multigpu-query-oa-units.html

  * igt@xe_sriov_flr@flr-vf1-clear:
    - shard-dg2-set2:     NOTRUN -> [SKIP][68] ([Intel XE#3342])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@xe_sriov_flr@flr-vf1-clear.html

  
#### Possible fixes ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][69] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124] / [Intel XE#4345]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [ABORT][71] ([Intel XE#1727]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][73] ([Intel XE#3124]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [DMESG-WARN][75] ([Intel XE#1727] / [Intel XE#3113]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-bmg:          [SKIP][77] ([Intel XE#2291]) -> [PASS][78] +3 other tests pass
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-3/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-bmg:          [SKIP][79] ([Intel XE#4294]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-6/igt@kms_dp_linktrain_fallback@dp-fallback.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-4/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_feature_discovery@display-2x:
    - shard-bmg:          [SKIP][81] ([Intel XE#2373]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-6/igt@kms_feature_discovery@display-2x.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-5/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-bmg:          [SKIP][83] ([Intel XE#2316]) -> [PASS][84] +2 other tests pass
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-5/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-dg2-set2:     [INCOMPLETE][85] ([Intel XE#2049]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@kms_flip@2x-nonexisting-fb.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-432/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][87] ([Intel XE#301]) -> [PASS][88] +1 other test pass
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend@d-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][89] ([Intel XE#4543]) -> [PASS][90] +1 other test pass
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-adlp-4/igt@kms_flip@flip-vs-suspend@d-hdmi-a1.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-adlp-6/igt@kms_flip@flip-vs-suspend@d-hdmi-a1.html

  * igt@xe_exec_basic@multigpu-once-null:
    - shard-dg2-set2:     [SKIP][91] ([Intel XE#1392]) -> [PASS][92] +5 other tests pass
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-432/igt@xe_exec_basic@multigpu-once-null.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-466/igt@xe_exec_basic@multigpu-once-null.html

  
#### Warnings ####

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][93] ([Intel XE#316]) -> [SKIP][94] ([Intel XE#2351] / [Intel XE#4208]) +2 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_big_fb@linear-16bpp-rotate-90.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     [SKIP][95] ([Intel XE#316]) -> [SKIP][96] ([Intel XE#4208]) +5 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-463/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-dg2-set2:     [SKIP][97] ([Intel XE#607]) -> [SKIP][98] ([Intel XE#2351] / [Intel XE#4208])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-463/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
    - shard-dg2-set2:     [SKIP][99] ([Intel XE#1124]) -> [SKIP][100] ([Intel XE#4208]) +10 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-dg2-set2:     [SKIP][101] ([Intel XE#1124]) -> [SKIP][102] ([Intel XE#2351] / [Intel XE#4208]) +4 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p:
    - shard-dg2-set2:     [SKIP][103] ([Intel XE#2191]) -> [SKIP][104] ([Intel XE#4208])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-4-displays-2560x1440p:
    - shard-dg2-set2:     [SKIP][105] ([Intel XE#367]) -> [SKIP][106] ([Intel XE#4208]) +4 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs:
    - shard-dg2-set2:     [SKIP][107] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][108] ([Intel XE#4208]) +16 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs:
    - shard-dg2-set2:     [SKIP][109] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][110] ([Intel XE#2351] / [Intel XE#4208]) +5 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-dg2-set2:     [SKIP][111] ([Intel XE#3442]) -> [SKIP][112] ([Intel XE#4208])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-435/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][113] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [INCOMPLETE][114] ([Intel XE#2705] / [Intel XE#4212] / [Intel XE#4345])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-dg2-set2:     [SKIP][115] ([Intel XE#4418]) -> [SKIP][116] ([Intel XE#2351] / [Intel XE#4208])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@kms_cdclk@mode-transition-all-outputs.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_chamelium_color@gamma:
    - shard-dg2-set2:     [SKIP][117] ([Intel XE#306]) -> [SKIP][118] ([Intel XE#4208]) +1 other test skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_chamelium_color@gamma.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_chamelium_color@gamma.html

  * igt@kms_chamelium_hpd@vga-hpd:
    - shard-dg2-set2:     [SKIP][119] ([Intel XE#373]) -> [SKIP][120] ([Intel XE#4208]) +14 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_chamelium_hpd@vga-hpd.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_chamelium_hpd@vga-hpd.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-dg2-set2:     [SKIP][121] ([Intel XE#307]) -> [SKIP][122] ([Intel XE#4208])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-435/igt@kms_content_protection@dp-mst-lic-type-1.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@legacy:
    - shard-dg2-set2:     [FAIL][123] ([Intel XE#1178]) -> [SKIP][124] ([Intel XE#4208])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_content_protection@legacy.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@lic-type-0:
    - shard-bmg:          [SKIP][125] ([Intel XE#2341]) -> [FAIL][126] ([Intel XE#1178])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-6/igt@kms_content_protection@lic-type-0.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-5/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@uevent:
    - shard-bmg:          [FAIL][127] ([Intel XE#1188]) -> [SKIP][128] ([Intel XE#2341])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-4/igt@kms_content_protection@uevent.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-6/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-dg2-set2:     [SKIP][129] ([Intel XE#308]) -> [SKIP][130] ([Intel XE#4208]) +1 other test skip
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-435/igt@kms_cursor_crc@cursor-onscreen-512x170.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-dg2-set2:     [SKIP][131] ([Intel XE#323]) -> [SKIP][132] ([Intel XE#4208])
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-dg2-set2:     [SKIP][133] ([Intel XE#4354]) -> [SKIP][134] ([Intel XE#4208])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-464/igt@kms_dp_link_training@non-uhbr-mst.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
    - shard-dg2-set2:     [SKIP][135] ([Intel XE#4422]) -> [SKIP][136] ([Intel XE#4208])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html

  * igt@kms_feature_discovery@chamelium:
    - shard-dg2-set2:     [SKIP][137] ([Intel XE#701]) -> [SKIP][138] ([Intel XE#4208])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_feature_discovery@chamelium.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_feature_discovery@chamelium.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-adlp:         [DMESG-WARN][139] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543]) -> [DMESG-WARN][140] ([Intel XE#4543]) +1 other test dmesg-warn
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-adlp-6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-adlp-4/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg2-set2:     [SKIP][141] ([Intel XE#455]) -> [SKIP][142] ([Intel XE#2351] / [Intel XE#4208]) +1 other test skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff:
    - shard-dg2-set2:     [SKIP][143] ([Intel XE#651]) -> [SKIP][144] ([Intel XE#4208]) +28 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][145] ([Intel XE#2312]) -> [SKIP][146] ([Intel XE#2311]) +8 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen:
    - shard-dg2-set2:     [SKIP][147] ([Intel XE#651]) -> [SKIP][148] ([Intel XE#2351] / [Intel XE#4208]) +15 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][149] ([Intel XE#5390]) -> [SKIP][150] ([Intel XE#2312]) +4 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt:
    - shard-bmg:          [SKIP][151] ([Intel XE#2312]) -> [SKIP][152] ([Intel XE#5390]) +2 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][153] ([Intel XE#2311]) -> [SKIP][154] ([Intel XE#2312]) +12 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff:
    - shard-dg2-set2:     [SKIP][155] ([Intel XE#653]) -> [SKIP][156] ([Intel XE#4208]) +33 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][157] ([Intel XE#2312]) -> [SKIP][158] ([Intel XE#2313]) +11 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@plane-fbc-rte:
    - shard-dg2-set2:     [SKIP][159] ([Intel XE#1158]) -> [SKIP][160] ([Intel XE#4208])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_frontbuffer_tracking@plane-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     [SKIP][161] ([Intel XE#653]) -> [SKIP][162] ([Intel XE#2351] / [Intel XE#4208]) +11 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          [SKIP][163] ([Intel XE#2313]) -> [SKIP][164] ([Intel XE#2312]) +12 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-dg2-set2:     [SKIP][165] ([Intel XE#2925]) -> [SKIP][166] ([Intel XE#4208])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-464/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-dg2-set2:     [SKIP][167] ([Intel XE#356]) -> [SKIP][168] ([Intel XE#4208])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-464/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-bmg:          [SKIP][169] ([Intel XE#4596]) -> [SKIP][170] ([Intel XE#5021])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-yf.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-dg2-set2:     [SKIP][171] ([Intel XE#5020]) -> [SKIP][172] ([Intel XE#4208])
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_plane_multiple@tiling-yf.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-dg2-set2:     [SKIP][173] ([Intel XE#2938]) -> [SKIP][174] ([Intel XE#4208])
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_pm_backlight@brightness-with-dpms.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-dg2-set2:     [SKIP][175] ([Intel XE#870]) -> [SKIP][176] ([Intel XE#4208])
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-435/igt@kms_pm_backlight@fade-with-dpms.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-dg2-set2:     [SKIP][177] ([Intel XE#3309]) -> [SKIP][178] ([Intel XE#4208])
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-463/igt@kms_pm_dc@dc5-retention-flops.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-dg2-set2:     [SKIP][179] ([Intel XE#908]) -> [SKIP][180] ([Intel XE#4208])
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@kms_pm_dc@deep-pkgc.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
    - shard-dg2-set2:     [SKIP][181] ([Intel XE#1406] / [Intel XE#1489]) -> [SKIP][182] ([Intel XE#1406] / [Intel XE#4208]) +11 other tests skip
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-464/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-dg2-set2:     [SKIP][183] ([Intel XE#1122] / [Intel XE#1406]) -> [SKIP][184] ([Intel XE#1406] / [Intel XE#4208]) +1 other test skip
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@kms_psr2_su@page_flip-p010.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-psr2-sprite-plane-move:
    - shard-dg2-set2:     [SKIP][185] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) -> [SKIP][186] ([Intel XE#1406] / [Intel XE#4208]) +10 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@kms_psr@fbc-psr2-sprite-plane-move.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_psr@fbc-psr2-sprite-plane-move.html

  * igt@kms_psr@pr-dpms:
    - shard-dg2-set2:     [SKIP][187] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) -> [SKIP][188] ([Intel XE#1406] / [Intel XE#2351] / [Intel XE#4208]) +8 other tests skip
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_psr@pr-dpms.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_psr@pr-dpms.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-dg2-set2:     [SKIP][189] ([Intel XE#3414]) -> [SKIP][190] ([Intel XE#4208]) +2 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_rotation_crc@bad-pixel-format.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-dg2-set2:     [SKIP][191] ([Intel XE#1127]) -> [SKIP][192] ([Intel XE#4208])
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg2-set2:     [FAIL][193] ([Intel XE#1729]) -> [SKIP][194] ([Intel XE#4208])
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@kms_tiled_display@basic-test-pattern.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][195] ([Intel XE#2509]) -> [SKIP][196] ([Intel XE#2426])
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flip-dpms:
    - shard-dg2-set2:     [SKIP][197] ([Intel XE#455]) -> [SKIP][198] ([Intel XE#4208]) +15 other tests skip
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@kms_vrr@flip-dpms.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_vrr@flip-dpms.html

  * igt@kms_vrr@lobf:
    - shard-dg2-set2:     [SKIP][199] ([Intel XE#2168]) -> [SKIP][200] ([Intel XE#4208]) +1 other test skip
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-464/igt@kms_vrr@lobf.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@kms_vrr@lobf.html

  * igt@xe_compute_preempt@compute-preempt:
    - shard-dg2-set2:     [SKIP][201] ([Intel XE#1280] / [Intel XE#455]) -> [SKIP][202] ([Intel XE#4208])
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@xe_compute_preempt@compute-preempt.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_compute_preempt@compute-preempt.html

  * igt@xe_copy_basic@mem-copy-linear-0x369:
    - shard-dg2-set2:     [SKIP][203] ([Intel XE#1123]) -> [SKIP][204] ([Intel XE#4208])
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-463/igt@xe_copy_basic@mem-copy-linear-0x369.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_copy_basic@mem-copy-linear-0x369.html

  * igt@xe_copy_basic@mem-set-linear-0xfd:
    - shard-dg2-set2:     [SKIP][205] ([Intel XE#1126]) -> [SKIP][206] ([Intel XE#4208])
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-463/igt@xe_copy_basic@mem-set-linear-0xfd.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_copy_basic@mem-set-linear-0xfd.html

  * igt@xe_eu_stall@invalid-gt-id:
    - shard-dg2-set2:     [SKIP][207] ([Intel XE#5626]) -> [SKIP][208] ([Intel XE#4208]) +1 other test skip
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@xe_eu_stall@invalid-gt-id.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_eu_stall@invalid-gt-id.html

  * igt@xe_exec_fault_mode@twice-userptr-rebind-imm:
    - shard-dg2-set2:     [SKIP][209] ([Intel XE#288]) -> [SKIP][210] ([Intel XE#4208]) +37 other tests skip
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html

  * igt@xe_exec_sip_eudebug@breakpoint-writesip:
    - shard-dg2-set2:     [SKIP][211] ([Intel XE#4837]) -> [SKIP][212] ([Intel XE#4208]) +21 other tests skip
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@xe_exec_sip_eudebug@breakpoint-writesip.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_exec_sip_eudebug@breakpoint-writesip.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-malloc:
    - shard-dg2-set2:     [SKIP][213] ([Intel XE#4915]) -> [SKIP][214] ([Intel XE#4208]) +366 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@xe_exec_system_allocator@threads-shared-vm-many-large-malloc.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_exec_system_allocator@threads-shared-vm-many-large-malloc.html

  * igt@xe_oa@buffer-size:
    - shard-dg2-set2:     [SKIP][215] ([Intel XE#6032]) -> [SKIP][216] ([Intel XE#4208])
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-463/igt@xe_oa@buffer-size.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_oa@buffer-size.html

  * igt@xe_oa@oa-unit-exclusive-stream-sample-oa:
    - shard-dg2-set2:     [SKIP][217] ([Intel XE#3573]) -> [SKIP][218] ([Intel XE#4208]) +8 other tests skip
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html

  * igt@xe_pat@pat-index-xe2:
    - shard-dg2-set2:     [SKIP][219] ([Intel XE#977]) -> [SKIP][220] ([Intel XE#4208])
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@xe_pat@pat-index-xe2.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_pat@pat-index-xe2.html

  * igt@xe_pm@d3cold-i2c:
    - shard-dg2-set2:     [SKIP][221] ([Intel XE#5694]) -> [SKIP][222] ([Intel XE#4208])
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@xe_pm@d3cold-i2c.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_pm@d3cold-i2c.html

  * igt@xe_pm@d3cold-mmap-vram:
    - shard-dg2-set2:     [SKIP][223] ([Intel XE#2284] / [Intel XE#366]) -> [SKIP][224] ([Intel XE#4208]) +2 other tests skip
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-434/igt@xe_pm@d3cold-mmap-vram.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_pm@d3cold-mmap-vram.html

  * igt@xe_pm@vram-d3cold-threshold:
    - shard-dg2-set2:     [SKIP][225] ([Intel XE#579]) -> [SKIP][226] ([Intel XE#4208])
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-463/igt@xe_pm@vram-d3cold-threshold.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_pm@vram-d3cold-threshold.html

  * igt@xe_pmu@fn-engine-activity-load:
    - shard-dg2-set2:     [SKIP][227] ([Intel XE#4650]) -> [SKIP][228] ([Intel XE#4208])
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-464/igt@xe_pmu@fn-engine-activity-load.html
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_pmu@fn-engine-activity-load.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq:
    - shard-dg2-set2:     [SKIP][229] ([Intel XE#4733]) -> [SKIP][230] ([Intel XE#4208]) +5 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-435/igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq.html
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq.html

  * igt@xe_query@multigpu-query-pxp-status:
    - shard-dg2-set2:     [SKIP][231] ([Intel XE#944]) -> [SKIP][232] ([Intel XE#4208]) +1 other test skip
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@xe_query@multigpu-query-pxp-status.html
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_query@multigpu-query-pxp-status.html

  * igt@xe_sriov_auto_provisioning@exclusive-ranges:
    - shard-dg2-set2:     [SKIP][233] ([Intel XE#4130]) -> [SKIP][234] ([Intel XE#4208]) +1 other test skip
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-463/igt@xe_sriov_auto_provisioning@exclusive-ranges.html
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_sriov_auto_provisioning@exclusive-ranges.html

  * igt@xe_sriov_flr@flr-twice:
    - shard-dg2-set2:     [SKIP][235] ([Intel XE#4273]) -> [SKIP][236] ([Intel XE#4208])
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225/shard-dg2-466/igt@xe_sriov_flr@flr-twice.html
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/shard-dg2-434/igt@xe_sriov_flr@flr-twice.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1158]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1158
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
  [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
  [Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
  [Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
  [Intel XE#356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/356
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4208
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
  [Intel XE#4294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4294
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4359]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4359
  [Intel XE#4416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4416
  [Intel XE#4418]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4418
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
  [Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5624
  [Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
  [Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
  [Intel XE#5750]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5750
  [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
  [Intel XE#5890]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5890
  [Intel XE#6032]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6032
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
  [Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977


Build changes
-------------

  * Linux: xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225 -> xe-pw-151244v11

  IGT_8532: 3b9f234d6efe0529a233b81bb0d5ffee5adddb01 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3721-e925396dbb0b8094e00ca3d47a375538d429b225: e925396dbb0b8094e00ca3d47a375538d429b225
  xe-pw-151244v11: 151244v11

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v11/index.html

[-- Attachment #2: Type: text/html, Size: 78393 bytes --]

Re: [PATCH 03/15] drm/i915/skl_watermark: Pass linetime as argument to latency helpers

[Ville Syrjälä]

On Thu, Sep 11, 2025 at 08:15:42AM +0530, Ankit Nautiyal wrote:
> Refactor dsc_prefill_latency and scaler_prefill_latency to take
> linetime as an explicit parameter instead of computing it internally.
> 
> This avoids redundant calculations and simplifies scanline conversion
> logic in skl_is_vblank_too_short().
> 
> This change also facilitates future extraction of these helpers for use
> cases where latencies are computed for an optimized guardband, based on the
> highest resolution mode, rather than the current mode.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 18 ++++++++----------
>  1 file changed, 8 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 51548447f4aa..49d424f5b305 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2176,13 +2176,11 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
>  }
>  
>  static int
> -dsc_prefill_latency(const struct intel_crtc_state *crtc_state)
> +dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct intel_crtc_scaler_state *scaler_state =
>  					&crtc_state->scaler_state;
> -	int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
> -				    crtc_state->hw.adjusted_mode.clock);
>  	int num_scaler_users = hweight32(scaler_state->scaler_users);
>  	int chroma_downscaling_factor =
>  		crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 4 : 1;
> @@ -2206,18 +2204,16 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state)
>  
>  	dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
>  
> -	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, dsc_prefill_latency);
> +	return dsc_prefill_latency;
>  }
>  
>  static int
> -scaler_prefill_latency(const struct intel_crtc_state *crtc_state)
> +scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
>  {
>  	const struct intel_crtc_scaler_state *scaler_state =
>  					&crtc_state->scaler_state;
>  	int num_scaler_users = hweight32(scaler_state->scaler_users);
>  	int scaler_prefill_latency = 0;
> -	int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
> -				    crtc_state->hw.adjusted_mode.clock);
>  
>  	if (!num_scaler_users)
>  		return scaler_prefill_latency;
> @@ -2238,7 +2234,7 @@ scaler_prefill_latency(const struct intel_crtc_state *crtc_state)
>  
>  	scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
>  
> -	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, scaler_prefill_latency);
> +	return scaler_prefill_latency;
>  }
>  
>  static bool
> @@ -2247,11 +2243,13 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
>  {
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
> +	int linetime = DIV_ROUND_UP(1000 * adjusted_mode->htotal,
> +				    adjusted_mode->clock);
>  
>  	return crtc_state->framestart_delay +
>  		intel_usecs_to_scanlines(adjusted_mode, latency) +
> -		scaler_prefill_latency(crtc_state) +
> -		dsc_prefill_latency(crtc_state) +
> +		DIV_ROUND_UP(scaler_prefill_latency(crtc_state, linetime), linetime) +
> +		DIV_ROUND_UP(dsc_prefill_latency(crtc_state, linetime), linetime) +

Looks like you could just add up all the usec latency numbers and
convert the whole thing with a single intel_usecs_to_scanlines() call
instead of this mismash of hand rolled and non-hand rolled stuff.

>  		wm0_lines >
>  		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
>  }
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 05/15] drm/i915/display: Extract helpers to set dsc/scaler prefill latencies

[Ville Syrjälä]

On Thu, Sep 11, 2025 at 08:15:44AM +0530, Ankit Nautiyal wrote:
> Currently dsc/scaler prefill latencies are handled during watermark
> calculations. With the optimized guardband, we need to compute the
> latencies to find the minimum guardband that works for most cases.
> Extract the helpers to compute these latencies, so that they can be used
> while computing vrr guardband.
> 
> While at it, put declarations in reverse xmas tree order for better
> redability.
> 
> v2: Initialize {h,v}scale_k to 0, and simplify the check in
> intel_display_scaler_prefill_latency(). (Mitul)
> v3: Move helpers from intel_display.c to intel_vrr.c as they are specific
> to account for latencies to program vrr guardband. (Jani)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c     | 33 ++++++++++++++
>  drivers/gpu/drm/i915/display/intel_vrr.h     |  8 ++++
>  drivers/gpu/drm/i915/display/skl_watermark.c | 47 +++++++++-----------
>  3 files changed, 63 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 266cf5e1859d..fd690de5b45b 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -772,3 +772,36 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>  	if (crtc_state->vrr.enable)
>  		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>  }
> +
> +int intel_vrr_guardband_scaler_latency(int num_scaler_users, u64 hscale, u64 vscale,
> +				       int chroma_downscaling_factor,
> +				       int cdclk_prefill_adjustment,
> +				       int linetime)
> +{
> +	int scaler_prefill_latency;
> +
> +	scaler_prefill_latency = 4 * linetime +
> +				 DIV_ROUND_UP_ULL((4 * linetime * hscale * vscale *
> +						   chroma_downscaling_factor), 1000000);
> +
> +	scaler_prefill_latency *= cdclk_prefill_adjustment;
> +
> +	return scaler_prefill_latency;
> +}
> +
> +int intel_vrr_guardband_dsc_latency(int num_scaler_users, u64 *hscale, u64 *vscale,
> +				    int chroma_downscaling_factor,
> +				    int cdclk_prefill_adjustment,
> +				    int linetime)
> +{
> +	int dsc_prefill_latency;
> +
> +	dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10);
> +
> +	for (int i = 0; i < num_scaler_users; i++)
> +		dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale[i] * vscale[i],
> +						       1000000);
> +	dsc_prefill_latency *= cdclk_prefill_adjustment;
> +
> +	return dsc_prefill_latency;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 38bf9996b883..950041647e47 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -41,5 +41,13 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
>  void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
>  void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
>  bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
> +int intel_vrr_guardband_scaler_latency(int num_scaler_users, u64 hscale, u64 vscale,
> +				       int chroma_downscaling_factor,
> +				       int cdclk_prefill_adjustment,
> +				       int linetime);
> +int intel_vrr_guardband_dsc_latency(int num_scaler_users, u64 *hscale, u64 *vscale,
> +				    int chroma_downscaling_factor,
> +				    int cdclk_prefill_adjustment,
> +				    int linetime);
>  
>  #endif /* __INTEL_VRR_H__ */
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 3d322c39ce21..1ff2b4d9a35e 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -28,6 +28,7 @@
>  #include "intel_flipq.h"
>  #include "intel_pcode.h"
>  #include "intel_plane.h"
> +#include "intel_vrr.h"
>  #include "intel_wm.h"
>  #include "skl_universal_plane_regs.h"
>  #include "skl_scaler.h"
> @@ -2179,11 +2180,12 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
>  static int
>  dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
>  {
> +	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
> +	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	const struct intel_crtc_scaler_state *scaler_state =
> -					&crtc_state->scaler_state;
>  	int num_scaler_users = hweight32(scaler_state->scaler_users);
> -	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
> +	u64 hscale_k[ARRAY_SIZE(scaler_state->scalers)];
> +	u64 vscale_k[ARRAY_SIZE(scaler_state->scalers)];
>  	u32 dsc_prefill_latency = 0;
>  
>  	if (!crtc_state->dsc.compression_enable ||
> @@ -2191,18 +2193,16 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
>  	    num_scaler_users > crtc->num_scalers)
>  		return dsc_prefill_latency;
>  
> -	dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10);
> -
>  	for (int i = 0; i < num_scaler_users; i++) {
> -		u64 hscale_k, vscale_k;
> -
> -		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
> -		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
> -		dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale_k * vscale_k,
> -						       1000000);
> +		hscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
> +		vscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
>  	}
>  
> -	dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
> +	dsc_prefill_latency =
> +		intel_vrr_guardband_dsc_latency(num_scaler_users, hscale_k, vscale_k,
> +						chroma_downscaling_factor,
> +						cdclk_prefill_adjustment(crtc_state),
> +						linetime);

Calling vrr stuff for non-vrr stuff feels completely backwards.
I suspect we should move these prefill latency calculations into
the relevant scaler/dsc/etc files instead.


>  
>  	return dsc_prefill_latency;
>  }
> @@ -2210,28 +2210,25 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
>  static int
>  scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
>  {
> -	const struct intel_crtc_scaler_state *scaler_state =
> -					&crtc_state->scaler_state;
> +	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
> +	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
>  	int num_scaler_users = hweight32(scaler_state->scaler_users);
> +	u64 hscale_k = 0, vscale_k = 0;
>  	int scaler_prefill_latency = 0;
>  
>  	if (!num_scaler_users)
>  		return scaler_prefill_latency;
>  
> -	scaler_prefill_latency = 4 * linetime;
> -
>  	if (num_scaler_users > 1) {
> -		u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
> -		u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
> -		int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
> -		int latency;
> -
> -		latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k *
> -					    chroma_downscaling_factor), 1000000);
> -		scaler_prefill_latency += latency;
> +		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
> +		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
>  	}
>  
> -	scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
> +	scaler_prefill_latency =
> +		intel_vrr_guardband_scaler_latency(num_scaler_users, hscale_k, vscale_k,
> +						   chroma_downscaling_factor,
> +						   cdclk_prefill_adjustment(crtc_state),
> +						   linetime);
>  
>  	return scaler_prefill_latency;
>  }
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 06/15] drm/i915/dp: Add SDP latency computation helper

[Ville Syrjälä]

On Thu, Sep 11, 2025 at 08:15:45AM +0530, Ankit Nautiyal wrote:
> Add a helper to compute vblank time needed for transmitting specific
> DisplayPort SDPs like PPS, GAMUT_METADATA, and VSC_EXT. Latency is
> based on line count per packet type and current line time.
> 
> Used to ensure adequate vblank when features like DSC/HDR are enabled.
> 
> Bspec: 70151
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h |  2 ++
>  2 files changed, 49 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2eab591a8ef5..83c46e4680b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6857,3 +6857,50 @@ void intel_dp_mst_resume(struct intel_display *display)
>  		}
>  	}
>  }
> +
> +static
> +int intel_dp_get_sdp_latency(u32 type, int linetime_us)

The "get" in the name is redundant.

> +{
> +	int lines;
> +
> +	switch (type) {
> +	case DP_SDP_VSC_EXT_VESA:
> +	case DP_SDP_VSC_EXT_CEA:
> +		lines = 10;
> +		break;
> +	case HDMI_PACKET_TYPE_GAMUT_METADATA:
> +		lines = 8;
> +		break;
> +	case DP_SDP_PPS:
> +		lines = 6;
> +		break;
> +	default:
> +		lines = 0;
> +		break;
> +	}

We should probably calculate these properly instead of
just hardcoding annoying magic numbers. But I suppose
these are supposed to be some kind of semi worst case
numbers so perhaps OK for now.

> +
> +	return lines * linetime_us;
> +}
> +
> +int intel_dp_compute_sdp_latency(const struct intel_crtc_state *crtc_state,
> +				 bool assume_all_enabled)
> +{
> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +	int sdp_latency = 0;
> +	int linetime_us;
> +
> +	linetime_us = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000,
> +				   adjusted_mode->crtc_clock);
> +	if (assume_all_enabled ||
> +	    crtc_state->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
> +		sdp_latency = max(sdp_latency,
> +				  intel_dp_get_sdp_latency(HDMI_PACKET_TYPE_GAMUT_METADATA,
> +							   linetime_us));
> +
> +	if (assume_all_enabled || crtc_state->dsc.compression_enable)
> +		sdp_latency = max(sdp_latency,
> +				  intel_dp_get_sdp_latency(DP_SDP_PPS, linetime_us));
> +
> +	return sdp_latency;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index f90cfd1dbbd0..d222749b191c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -215,5 +215,7 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
>  int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector);
>  void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
>  bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
> +int intel_dp_compute_sdp_latency(const struct intel_crtc_state *crtc_state,
> +				 bool assume_all_enabled);
>  
>  #endif /* __INTEL_DP_H__ */
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 10/15] drm/i915/skl_watermark: Remove redundant latency checks from vblank validation

[Ville Syrjälä]

On Thu, Sep 11, 2025 at 08:15:49AM +0530, Ankit Nautiyal wrote:
> Drop DSC and scaler prefill latency checks from skl_is_vblank_too_short().
> These are now covered by the guardband validation added during the atomic
> CRTC check phase.
> 
> This cleanup prepares for future changes where the guardband will be
> optimized independently of vblank length, making vblank-based checks
> obsolete.

This looks very wrong, at least for platforms that don't have a
programmable guardband.

> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 79 --------------------
>  1 file changed, 79 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 83ac26004f05..07589096b143 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -28,7 +28,6 @@
>  #include "intel_flipq.h"
>  #include "intel_pcode.h"
>  #include "intel_plane.h"
> -#include "intel_vrr.h"
>  #include "intel_wm.h"
>  #include "skl_universal_plane_regs.h"
>  #include "skl_scaler.h"
> @@ -2159,93 +2158,15 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
>  	return 0;
>  }
>  
> -static int
> -cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_display *display = to_intel_display(crtc_state);
> -	struct intel_atomic_state *state =
> -		to_intel_atomic_state(crtc_state->uapi.state);
> -	const struct intel_cdclk_state *cdclk_state;
> -
> -	cdclk_state = intel_atomic_get_cdclk_state(state);
> -	if (IS_ERR(cdclk_state)) {
> -		drm_WARN_ON(display->drm, PTR_ERR(cdclk_state));
> -		return 1;
> -	}
> -
> -	return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
> -				   2 * intel_cdclk_logical(cdclk_state)));
> -}
> -
> -static int
> -dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
> -{
> -	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
> -	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	int num_scaler_users = hweight32(scaler_state->scaler_users);
> -	u64 hscale_k[ARRAY_SIZE(scaler_state->scalers)];
> -	u64 vscale_k[ARRAY_SIZE(scaler_state->scalers)];
> -	u32 dsc_prefill_latency = 0;
> -
> -	if (!crtc_state->dsc.compression_enable ||
> -	    !num_scaler_users ||
> -	    num_scaler_users > crtc->num_scalers)
> -		return dsc_prefill_latency;
> -
> -	for (int i = 0; i < num_scaler_users; i++) {
> -		hscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
> -		vscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
> -	}
> -
> -	dsc_prefill_latency =
> -		intel_vrr_guardband_dsc_latency(num_scaler_users, hscale_k, vscale_k,
> -						chroma_downscaling_factor,
> -						cdclk_prefill_adjustment(crtc_state),
> -						linetime);
> -
> -	return dsc_prefill_latency;
> -}
> -
> -static int
> -scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
> -{
> -	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
> -	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
> -	int num_scaler_users = hweight32(scaler_state->scaler_users);
> -	u64 hscale_k = 0, vscale_k = 0;
> -	int scaler_prefill_latency = 0;
> -
> -	if (!num_scaler_users)
> -		return scaler_prefill_latency;
> -
> -	if (num_scaler_users > 1) {
> -		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
> -		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
> -	}
> -
> -	scaler_prefill_latency =
> -		intel_vrr_guardband_scaler_latency(num_scaler_users, hscale_k, vscale_k,
> -						   chroma_downscaling_factor,
> -						   cdclk_prefill_adjustment(crtc_state),
> -						   linetime);
> -
> -	return scaler_prefill_latency;
> -}
> -
>  static bool
>  skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
>  			int wm0_lines, int latency)
>  {
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
> -	int linetime = DIV_ROUND_UP(1000 * adjusted_mode->htotal,
> -				    adjusted_mode->clock);
>  
>  	return crtc_state->framestart_delay +
>  		intel_usecs_to_scanlines(adjusted_mode, latency) +
> -		DIV_ROUND_UP(scaler_prefill_latency(crtc_state, linetime), linetime) +
> -		DIV_ROUND_UP(dsc_prefill_latency(crtc_state, linetime), linetime) +
>  		wm0_lines >
>  		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
>  }
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 11/15] drm/i915/display: Use vrr.guardband to derive vblank_start

[Ville Syrjälä]

On Thu, Sep 11, 2025 at 08:15:50AM +0530, Ankit Nautiyal wrote:
> When VRR TG is always enabled and an optimized guardband is used, the pipe
> vblank start is derived from the guardband.
> Currently TRANS_SET_CONTEXT_LATENCY is programmed with crtc_vblank_start -
> crtc_vdisplay, which is ~1 when guardband matches the vblank length.
> With shorter guardband this become a large window.
> 
> To avoid misprogramming TRANS_SET_CONTEXT_LATENCY, clamp the scl value to 1
> when using optimized guardband.
> 
> Also update the VRR get config logic to set crtc_vblank_start based on
> vtotal - guardband, during readback.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 36 ++++++++++++++++----
>  drivers/gpu/drm/i915/display/intel_vrr.c     |  9 ++++-
>  2 files changed, 38 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 55bea1374dc4..73aec6d4686a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2638,6 +2638,30 @@ transcoder_has_vrr(const struct intel_crtc_state *crtc_state)
>  	return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
>  }
>  
> +static int intel_set_context_latency(const struct intel_crtc_state *crtc_state,
> +				     int crtc_vblank_start,
> +				     int crtc_vdisplay)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	/*
> +	 * When VRR TG is always on and optimized guardband is used,
> +	 * the pipe vblank start is based on the guardband,
> +	 * TRANS_SET_CONTEXT_LATENCY cannot be used to configure it.
> +	 */
> +	if (intel_vrr_always_use_vrr_tg(display))
> +		return clamp(crtc_vblank_start - crtc_vdisplay, 0, 1);

What are you trying to achieve with this? As in what problem are you
seeing with the current SCL programming?

> +
> +	/*
> +	 * VBLANK_START no longer works on ADL+, instead we must use
> +	 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
> +	 */
> +	if (DISPLAY_VER(display) >= 13)
> +		return crtc_vblank_start - crtc_vdisplay;
> +
> +	return 0;
> +}
> +
>  static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> @@ -2671,14 +2695,12 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  			vsyncshift += adjusted_mode->crtc_htotal;
>  	}
>  
> -	/*
> -	 * VBLANK_START no longer works on ADL+, instead we must use
> -	 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
> -	 */
>  	if (DISPLAY_VER(display) >= 13) {
>  		intel_de_write(display,
>  			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
> -			       crtc_vblank_start - crtc_vdisplay);
> +			       intel_set_context_latency(crtc_state,
> +							 crtc_vblank_start,
> +							 crtc_vdisplay));
>  
>  		/*
>  		 * VBLANK_START not used by hw, just clear it
> @@ -2768,7 +2790,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
>  	if (DISPLAY_VER(display) >= 13) {
>  		intel_de_write(display,
>  			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
> -			       crtc_vblank_start - crtc_vdisplay);
> +			       intel_set_context_latency(crtc_state,
> +							 crtc_vblank_start,
> +							 crtc_vdisplay));
>  
>  		/*
>  		 * VBLANK_START not used by hw, just clear it
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 855974174afd..e124ef4e0ff4 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -749,11 +749,18 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>  		 * bits are not filled. Since vrr.vsync_start is computed as:
>  		 * crtc_vtotal - crtc_vsync_start, we can derive vtotal from
>  		 * vrr.vsync_start and crtc_vsync_start.
> +		 *
> +		 * With Optimized guardband, the vblank start is Vtotal - guardband
>  		 */
> -		if (intel_vrr_always_use_vrr_tg(display))
> +		if (intel_vrr_always_use_vrr_tg(display)) {
>  			crtc_state->hw.adjusted_mode.crtc_vtotal =
>  				crtc_state->hw.adjusted_mode.crtc_vsync_start +
>  				crtc_state->vrr.vsync_start;
> +
> +			crtc_state->hw.adjusted_mode.crtc_vblank_start =
> +				crtc_state->hw.adjusted_mode.crtc_vtotal -
> +				crtc_state->vrr.guardband;
> +		}
>  	}
>  
>  	vrr_enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 14/15] drm/i915/panel: Refactor helper to get highest fixed mode

[Ville Syrjälä]

On Thu, Sep 11, 2025 at 08:15:53AM +0530, Ankit Nautiyal wrote:
> Refactor intel_panel_highest_mode() to return the fixed mode with the
> highest pixel clock, removing the fallback to the adjusted mode. This makes
> the function semantics clearer and better suited for future use cases where
> fallback is not desirable.
> 
> Update the caller in intel_dp_mode_clock() to handle the NULL case
> explicitly by falling back to the adjusted mode's crtc_clock. This also
> addresses the existing FIXME comment about ambiguity between clock and
> crtc_clock, by using mode->clock for fixed modes and mode->crtc_clock for
> adjusted modes.
> 
> v2: Avoid introducing a new function and refactor existing one instead.
> (Jani).
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c    | 14 +++++++++-----
>  drivers/gpu/drm/i915/display/intel_panel.c | 11 +++++------
>  drivers/gpu/drm/i915/display/intel_panel.h |  3 +--
>  3 files changed, 15 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 83c46e4680b3..f74ac98062d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1760,11 +1760,15 @@ static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
>  	struct intel_connector *connector = to_intel_connector(conn_state->connector);
>  	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  
> -	/* FIXME a bit of a mess wrt clock vs. crtc_clock */
> -	if (has_seamless_m_n(connector))
> -		return intel_panel_highest_mode(connector, adjusted_mode)->clock;
> -	else
> -		return adjusted_mode->crtc_clock;
> +	if (has_seamless_m_n(connector)) {
> +		const struct drm_display_mode *highest_mode;
> +
> +		highest_mode = intel_panel_highest_mode(connector);
> +		if (highest_mode)
> +			return highest_mode->clock;
> +	}
> +
> +	return adjusted_mode->crtc_clock;
>  }
>  
>  /* Optimize link config in order: max bpp, min clock, min lanes */
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
> index 2a20aaaaac39..ac0f04073ecb 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -144,18 +144,17 @@ intel_panel_downclock_mode(struct intel_connector *connector,
>  }
>  
>  const struct drm_display_mode *
> -intel_panel_highest_mode(struct intel_connector *connector,
> -			 const struct drm_display_mode *adjusted_mode)
> +intel_panel_highest_mode(struct intel_connector *connector)
>  {
> -	const struct drm_display_mode *fixed_mode, *best_mode = adjusted_mode;
> +	const struct drm_display_mode *fixed_mode, *highest_mode = NULL;
>  
>  	/* pick the fixed_mode that has the highest clock */
>  	list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) {
> -		if (fixed_mode->clock > best_mode->clock)
> -			best_mode = fixed_mode;
> +		if (!highest_mode || fixed_mode->clock > highest_mode->clock)
> +			highest_mode = fixed_mode;

This looks broken now as it will always return some kind of mode
from the list, but whether or not it's better than the adjusted_mode
is no logner guaranteed.

>  	}
>  
> -	return best_mode;
> +	return highest_mode;
>  }
>  
>  int intel_panel_get_modes(struct intel_connector *connector)
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm/i915/display/intel_panel.h
> index 56a6412cf0fb..8a17600e46a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.h
> +++ b/drivers/gpu/drm/i915/display/intel_panel.h
> @@ -37,8 +37,7 @@ const struct drm_display_mode *
>  intel_panel_downclock_mode(struct intel_connector *connector,
>  			   const struct drm_display_mode *adjusted_mode);
>  const struct drm_display_mode *
> -intel_panel_highest_mode(struct intel_connector *connector,
> -			 const struct drm_display_mode *adjusted_mode);
> +intel_panel_highest_mode(struct intel_connector *connector);
>  int intel_panel_get_modes(struct intel_connector *connector);
>  enum drrs_type intel_panel_drrs_type(struct intel_connector *connector);
>  enum drm_mode_status
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 15/15] drm/i915/vrr: Fix seamless_mn drrs for PTL

[Ville Syrjälä]

On Thu, Sep 11, 2025 at 08:15:54AM +0530, Ankit Nautiyal wrote:
> With VRR timing generator always on, the fixed refresh rate is achieved
> by setting vrr.flipline and vrr.vmax as the vtotal for the desired mode.
> 
> This creates a problem for seamless_mn drrs feature, where user can
> seamlessly set a lower mode on the supporting panels. With VRR timing
> generator, the vrr.flipline and vrr.vmax are set to vtotal, but that
> corresponds to the higher mode.
> 
> To fix this, re-compute the vrr timings when seamless_mn drrs is in
> picture. At the same time make sure that the vrr.guardband is set as
> per the highest mode for such panels, so that switching between higher
> to lower mode, does not change the vrr.guardband.
> 
> v2: Add a new member `use_highest_mode` to vrr struct to help set the
> vrr timings for highest mode for the seamless_mn drrs case.
> v3:
> -Modify existing function to compute fixed refresh rate timings instead
> of adding a new function. (Mitul)
> -Tweak computation for scaling the vtotal and use DIV_ROUND_UP_ULL.
> -Improve documentation.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  2 +
>  drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
>  drivers/gpu/drm/i915/display/intel_dp.h       |  1 +
>  drivers/gpu/drm/i915/display/intel_vrr.c      | 90 ++++++++++++++++++-
>  4 files changed, 90 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 358ab922d7a7..9796c7b855d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1321,6 +1321,8 @@ struct intel_crtc_state {
>  		u8 pipeline_full;
>  		u16 flipline, vmin, vmax, guardband;
>  		u32 vsync_end, vsync_start;
> +		/* Indicates VRR timing is scaled to highest mode for seamless M/N */
> +		bool use_highest_mode;
>  	} vrr;
>  
>  	/* Content Match Refresh Rate state */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index f74ac98062d4..5c29c696c83e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1742,7 +1742,7 @@ static int intel_dp_max_bpp(struct intel_dp *intel_dp,
>  	return bpp;
>  }
>  
> -static bool has_seamless_m_n(struct intel_connector *connector)
> +bool has_seamless_m_n(struct intel_connector *connector)
>  {
>  	struct intel_display *display = to_intel_display(connector);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index d222749b191c..6da0196c23d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -217,5 +217,6 @@ void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
>  bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
>  int intel_dp_compute_sdp_latency(const struct intel_crtc_state *crtc_state,
>  				 bool assume_all_enabled);
> +bool has_seamless_m_n(struct intel_connector *connector);
>  
>  #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 002165026a20..80bbe4b1ef7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -11,6 +11,7 @@
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
>  #include "intel_dp.h"
> +#include "intel_panel.h"
>  #include "intel_vrr.h"
>  #include "intel_vrr_regs.h"
>  #include "skl_scaler.h"
> @@ -299,6 +300,16 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
>  	if (!intel_vrr_possible(crtc_state))
>  		return;
>  
> +	if (crtc_state->vrr.use_highest_mode) {
> +		intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
> +			       crtc_state->vrr.vmin - 1);
> +		intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
> +			       crtc_state->vrr.vmax - 1);
> +		intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
> +			       crtc_state->vrr.flipline - 1);
> +		return;
> +	}
> +
>  	intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
>  		       intel_vrr_fixed_rr_vmin(crtc_state) - 1);
>  	intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
> @@ -307,15 +318,69 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
>  		       intel_vrr_fixed_rr_flipline(crtc_state) - 1);
>  }
>  
> +static bool needs_seamless_m_n_timings(struct intel_crtc_state *crtc_state,
> +				       struct intel_connector *connector)
> +{
> +	if (!has_seamless_m_n(connector) || crtc_state->joiner_pipes)
> +		return false;
> +
> +	return true;
> +}
> +
> +static int intel_vrr_scale_vtotal_for_seamless_m_n(struct intel_crtc_state *crtc_state,
> +						   struct intel_connector *connector)
> +{
> +	const struct drm_display_mode *highest_mode = intel_panel_highest_mode(connector);
> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +	int vtotal = adjusted_mode->crtc_vtotal;
> +
> +	/*
> +	 * For panels with seamless_m_n drrs, the user can seamlessly switch to
> +	 * a lower mode, which has a lower clock. This works with legacy timing
> +	 * generator, but not with the VRR timing generator.
> +	 *
> +	 * The VRR timing generator requires flipline and vmax to be equal for
> +	 * fixed refresh rate operation. The default fixed RR computation sets
> +	 * these to the current mode's vtotal. However, when switching to a
> +	 * lower clock mode, this would result in a higher refresh rate than
> +	 * desired.
> +	 *
> +	 * To simulate the lower refresh rate correctly, we scale the vtotal
> +	 * based on the ratio of the highest mode's clock to the current mode's
> +	 * clock.
> +	 *
> +	 * When switching to a higher clock mode, the current vtotal already
> +	 * results in the desired refresh rate, so no scaling is needed.
> +	 *
> +	 * So compute the scaled vtotal if required, and update vrr.vmin to
> +	 * the scaled value. Also, set vrr.use_highest_mode to indicate that
> +	 * VRR timings are based on the highest mode.
> +	 */
> +	if (highest_mode && adjusted_mode->crtc_clock < highest_mode->clock) {
> +		vtotal = DIV_ROUND_UP_ULL(vtotal * highest_mode->clock,
> +					  adjusted_mode->crtc_clock);
> +		crtc_state->vrr.vmin = vtotal;
> +		crtc_state->vrr.use_highest_mode = true;
> +	}

I have no idea what is happening here. I think the only thing we should
be aiming for is a fixed guardband length, but this is now doing all kinds
of otehr massaging of VRR parameters. Why?

> +
> +	return vtotal;
> +}
> +
>  static
> -void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state)
> +void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state,
> +					struct intel_connector *connector)
>  {
> +	int vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
> +
> +	if (needs_seamless_m_n_timings(crtc_state, connector))
> +		vtotal = intel_vrr_scale_vtotal_for_seamless_m_n(crtc_state, connector);
> +
>  	/*
>  	 * For fixed rr,  vmin = vmax = flipline.
>  	 * vmin is already set to crtc_vtotal set vmax and flipline the same.
>  	 */
> -	crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.crtc_vtotal;
> -	crtc_state->vrr.flipline = crtc_state->hw.adjusted_mode.crtc_vtotal;
> +	crtc_state->vrr.vmax = vtotal;
> +	crtc_state->vrr.flipline = vtotal;
>  }
>  
>  static
> @@ -397,7 +462,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>  	else if (is_cmrr_frac_required(crtc_state) && is_edp)
>  		intel_vrr_compute_cmrr_timings(crtc_state);
>  	else
> -		intel_vrr_compute_fixed_rr_timings(crtc_state);
> +		intel_vrr_compute_fixed_rr_timings(crtc_state, connector);
>  
>  	/*
>  	 * flipline determines the min vblank length the hardware will
> @@ -876,6 +941,7 @@ int intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state,
>  {
>  	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	struct intel_display *display = to_intel_display(crtc_state);
> +	const struct drm_display_mode *highest_mode;
>  	int dsc_prefill_time = 0;
>  	int psr2_pr_latency = 0;
>  	int scaler_prefill_time;
> @@ -888,6 +954,22 @@ int intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state,
>  	int guardband;
>  	int pm_delay;
>  
> +	/*
> +	 * For seamless m_n the clock is changed while other modeline
> +	 * parameters are same. In that case the linetime_us will change,
> +	 * causing the guardband to change, and the seamless switch to
> +	 * lower mode would not take place.
> +	 * To avoid this, take the highest mode where panel supports
> +	 * seamless drrs and make guardband equal to the vblank length
> +	 * for the highest mode.
> +	 */
> +	highest_mode = intel_panel_highest_mode(connector);
> +	if (needs_seamless_m_n_timings(crtc_state, connector) && highest_mode) {
> +		guardband = highest_mode->vtotal - highest_mode->vdisplay;
> +
> +		return guardband;
> +	}
> +
>  	linetime_us = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000,
>  				   adjusted_mode->crtc_clock);
>  
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 00/15] Optimize vrr.guardband and fix LRR

[Ville Syrjälä]

On Thu, Sep 11, 2025 at 08:15:39AM +0530, Ankit Nautiyal wrote:
> Instead of setting vrr.guardband to vblank, use optimal guardband that
> works for most of the cases. This will help in avoiding need of change
> in guardband and fix the LRR feature that needs seamless switching to
> a lower refresh rate.

I think the _only_ thing we need for that is intel_crtc_vblank_delay()
to return a different number. But this series is doing all kinds of
stuff to other VRR logic that I don't understand at all.

> 
> First few patches fix/refactor and extract common functions required for
> dsc/scaler prefill time computation. Later patches use these helpers to
> compute an optimized guardband.
> 
> Also, for seamless_mn where vtotal is same but mode clock is changed to
> seamlessly switch to lower rate, re-compute the vrr timings.

As Art pointed out that stuff is defeatured on LNL+ (just sent
a patch for that) so we don't need to worry about it too much.

> 
> Few things that still need work:
> -The timestamps corresponding with next start of vactive still need to be
> fixed with the new scheme.
> -Re-enabling CMRR
> 
> Rev2:
> -Address comments from Mitul.
> -Extract helpers for dsc/scaler prefill latencies.
> -Fix downscaling factor for chroma subsampling.
> -Use missing pkg C max latency.
> -Fix guardband computation for seamless mn, always use vblank for
> higher resolution.
> 
> Rev3:
> -Drop patches for computing and storing PSR/Panel Replay wake times
> latencies and use existing helpers to compute these in intel_alpm.c.
> -Drop patch to change the Vmin as it was not required.
> 
> Rev4:
> -Rebase
> -Drop patch for checking bounds for scaler array access.
> -Use a new flag for setting vrr timings for seamless drrs.
> 
> Rev5:
> -Address comments from Mitul, Jani:
> -Refactor few helpers for computing latencies.
> -Rename the helper to check the guardband to intel_crtc_guardband_atomic_check()
> -Refactor the helper intel_panel_highest_mode().
> 
> Rev6:
> -Rebase
> -Address review comments from Mitul.
> -Improve documentation for and other minor fixes in Patch#12
> 
> Rev7:
> -Address comments from Jani.
> -Move the latency helpers from intel_display.c to intel_vrr.c and rename
> the helpers appropriately.
> -Drop redundant check for HAS_VRR with intel_vrr_possible().
> 
> Rev8:
> -Fix CI issues.
> -For fixed RR wait for delayed vblank before dsb interrupt.
> 
> Rev9:
> -Fix vrr.vsync_start/end timings for 3D modes (patch#1)
> -Rewrite the patch to wait for delayed vblank before dsb interrupt
> (patch #11)
> -Fix the flipline and vmin timings with optimized guardband (patch#12)
> 
> Rev10:
> -Address comments from Ville: Use min guardband computation for setting
> the vblank delay and set the crtc_vblank_start to delayed vblank.
> (Patch#13)
> -Modify the TRANS_SET_CONTEXT_LATENCY as per new guardband and use
> vrr.guardband to readback vblank_start. (Patch#11)
> 
> -From previous revision:
> ->Drop patch#11 "drm/i915/dsb: Align flipdone with delayed vblank using
> guardband wait", as this is no longer required.
> ->Modify Patch#12 "drm/i915/vrr: Use static guardband to support seamless
> LRR switching" to only introduce a helper to compute the fix guardband.
> Modify the commit message and the subject.
> 
> Ankit Nautiyal (15):
>   drm/i915/vrr: Use crtc_vsync_start/end for computing
>     vrr.vsync_start/end
>   drm/i915/skl_watermark: Fix the scaling factor for chroma subsampling
>   drm/i915/skl_watermark: Pass linetime as argument to latency helpers
>   drm/i915/skl_scaler: Introduce helper for chroma downscale factor
>   drm/i915/display: Extract helpers to set dsc/scaler prefill latencies
>   drm/i915/dp: Add SDP latency computation helper
>   drm/i915/alpm: Add function to compute max link-wake latency
>   drm/i915/vrr: Use vrr.sync_start for getting vtotal
>   drm/i915/display: Add guardband check for feature latencies
>   drm/i915/skl_watermark: Remove redundant latency checks from vblank
>     validation
>   drm/i915/display: Use vrr.guardband to derive vblank_start
>   drm/i915/vrr: Introduce helper to compute min static guardband
>   drm/i915/display: Use optimized guardband to set vblank start
>   drm/i915/panel: Refactor helper to get highest fixed mode
>   drm/i915/vrr: Fix seamless_mn drrs for PTL
> 
>  drivers/gpu/drm/i915/display/intel_alpm.c     |  15 +
>  drivers/gpu/drm/i915/display/intel_alpm.h     |   2 +
>  drivers/gpu/drm/i915/display/intel_display.c  | 236 ++++++++++++++-
>  .../drm/i915/display/intel_display_types.h    |   2 +
>  drivers/gpu/drm/i915/display/intel_dp.c       |  63 +++-
>  drivers/gpu/drm/i915/display/intel_dp.h       |   3 +
>  drivers/gpu/drm/i915/display/intel_panel.c    |  11 +-
>  drivers/gpu/drm/i915/display/intel_panel.h    |   3 +-
>  drivers/gpu/drm/i915/display/intel_vrr.c      | 272 ++++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_vrr.h      |  10 +
>  drivers/gpu/drm/i915/display/skl_scaler.c     |   5 +
>  drivers/gpu/drm/i915/display/skl_scaler.h     |   3 +
>  drivers/gpu/drm/i915/display/skl_watermark.c  |  89 +-----
>  drivers/gpu/drm/i915/display/skl_watermark.h  |   1 +
>  14 files changed, 586 insertions(+), 129 deletions(-)
> 
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 11/15] drm/i915/display: Use vrr.guardband to derive vblank_start

[Nautiyal, Ankit K]

On 9/11/2025 7:55 PM, Ville Syrjälä wrote:
> On Thu, Sep 11, 2025 at 08:15:50AM +0530, Ankit Nautiyal wrote:
>> When VRR TG is always enabled and an optimized guardband is used, the pipe
>> vblank start is derived from the guardband.
>> Currently TRANS_SET_CONTEXT_LATENCY is programmed with crtc_vblank_start -
>> crtc_vdisplay, which is ~1 when guardband matches the vblank length.
>> With shorter guardband this become a large window.
>>
>> To avoid misprogramming TRANS_SET_CONTEXT_LATENCY, clamp the scl value to 1
>> when using optimized guardband.
>>
>> Also update the VRR get config logic to set crtc_vblank_start based on
>> vtotal - guardband, during readback.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 36 ++++++++++++++++----
>>   drivers/gpu/drm/i915/display/intel_vrr.c     |  9 ++++-
>>   2 files changed, 38 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 55bea1374dc4..73aec6d4686a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -2638,6 +2638,30 @@ transcoder_has_vrr(const struct intel_crtc_state *crtc_state)
>>   	return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
>>   }
>>   
>> +static int intel_set_context_latency(const struct intel_crtc_state *crtc_state,
>> +				     int crtc_vblank_start,
>> +				     int crtc_vdisplay)
>> +{
>> +	struct intel_display *display = to_intel_display(crtc_state);
>> +
>> +	/*
>> +	 * When VRR TG is always on and optimized guardband is used,
>> +	 * the pipe vblank start is based on the guardband,
>> +	 * TRANS_SET_CONTEXT_LATENCY cannot be used to configure it.
>> +	 */
>> +	if (intel_vrr_always_use_vrr_tg(display))
>> +		return clamp(crtc_vblank_start - crtc_vdisplay, 0, 1);
> What are you trying to achieve with this? As in what problem are you
> seeing with the current SCL programming?

In VRR TG mode with optimized guardband, the guardband is shortened and 
vblank start is moved to match the delayed vblank position.

The SCL value which we are currently writing as difference between 
delayed vblank and undelayed vblank becomes quite large.

With this large SCL, the flipline decision boundary which is given by 
delayed vblank start and SCL lines is same as the undelayed vblank.

It seems that intel_dsb_wait_vblank_delay() (in turn 
intel_dsb_wait_usec()) does not behave correctly within the W2 window 
(between flipdone decision boundary and delayed vblank start).

It seems to return prematurely. Since the push bit hasn’t cleared yet, 
this leads to DSB poll errors.


AFAIU we are not using the SCL (Set Context Latency) lines to write 
registers via DSB.

The evasion logic ensures we write within a separate window, making the 
actual SCL value less critical for register programming.

So I have clamped the SCL value to (0,1). With this after the push is 
sent the send push bit is cleared after (0,1) lines.

But we still need to wait for the delayed vblank. For this we need 
either intel_dsb_wait_vblank_delay() or dsb_wait_for_scanline_in().


Do you have any ideas, what could have been going wrong or if anything 
we might have been missing?


Regards,

Ankit


>
>> +
>> +	/*
>> +	 * VBLANK_START no longer works on ADL+, instead we must use
>> +	 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
>> +	 */
>> +	if (DISPLAY_VER(display) >= 13)
>> +		return crtc_vblank_start - crtc_vdisplay;
>> +
>> +	return 0;
>> +}
>> +
>>   static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>>   {
>>   	struct intel_display *display = to_intel_display(crtc_state);
>> @@ -2671,14 +2695,12 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>>   			vsyncshift += adjusted_mode->crtc_htotal;
>>   	}
>>   
>> -	/*
>> -	 * VBLANK_START no longer works on ADL+, instead we must use
>> -	 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
>> -	 */
>>   	if (DISPLAY_VER(display) >= 13) {
>>   		intel_de_write(display,
>>   			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
>> -			       crtc_vblank_start - crtc_vdisplay);
>> +			       intel_set_context_latency(crtc_state,
>> +							 crtc_vblank_start,
>> +							 crtc_vdisplay));
>>   
>>   		/*
>>   		 * VBLANK_START not used by hw, just clear it
>> @@ -2768,7 +2790,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
>>   	if (DISPLAY_VER(display) >= 13) {
>>   		intel_de_write(display,
>>   			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
>> -			       crtc_vblank_start - crtc_vdisplay);
>> +			       intel_set_context_latency(crtc_state,
>> +							 crtc_vblank_start,
>> +							 crtc_vdisplay));
>>   
>>   		/*
>>   		 * VBLANK_START not used by hw, just clear it
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 855974174afd..e124ef4e0ff4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -749,11 +749,18 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>>   		 * bits are not filled. Since vrr.vsync_start is computed as:
>>   		 * crtc_vtotal - crtc_vsync_start, we can derive vtotal from
>>   		 * vrr.vsync_start and crtc_vsync_start.
>> +		 *
>> +		 * With Optimized guardband, the vblank start is Vtotal - guardband
>>   		 */
>> -		if (intel_vrr_always_use_vrr_tg(display))
>> +		if (intel_vrr_always_use_vrr_tg(display)) {
>>   			crtc_state->hw.adjusted_mode.crtc_vtotal =
>>   				crtc_state->hw.adjusted_mode.crtc_vsync_start +
>>   				crtc_state->vrr.vsync_start;
>> +
>> +			crtc_state->hw.adjusted_mode.crtc_vblank_start =
>> +				crtc_state->hw.adjusted_mode.crtc_vtotal -
>> +				crtc_state->vrr.guardband;
>> +		}
>>   	}
>>   
>>   	vrr_enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
>> -- 
>> 2.45.2

Re: [PATCH 03/15] drm/i915/skl_watermark: Pass linetime as argument to latency helpers

[Nautiyal, Ankit K]

On 9/11/2025 7:28 PM, Ville Syrjälä wrote:
> On Thu, Sep 11, 2025 at 08:15:42AM +0530, Ankit Nautiyal wrote:
>> Refactor dsc_prefill_latency and scaler_prefill_latency to take
>> linetime as an explicit parameter instead of computing it internally.
>>
>> This avoids redundant calculations and simplifies scanline conversion
>> logic in skl_is_vblank_too_short().
>>
>> This change also facilitates future extraction of these helpers for use
>> cases where latencies are computed for an optimized guardband, based on the
>> highest resolution mode, rather than the current mode.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/skl_watermark.c | 18 ++++++++----------
>>   1 file changed, 8 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>> index 51548447f4aa..49d424f5b305 100644
>> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
>> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>> @@ -2176,13 +2176,11 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
>>   }
>>   
>>   static int
>> -dsc_prefill_latency(const struct intel_crtc_state *crtc_state)
>> +dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
>>   {
>>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>   	const struct intel_crtc_scaler_state *scaler_state =
>>   					&crtc_state->scaler_state;
>> -	int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
>> -				    crtc_state->hw.adjusted_mode.clock);
>>   	int num_scaler_users = hweight32(scaler_state->scaler_users);
>>   	int chroma_downscaling_factor =
>>   		crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 4 : 1;
>> @@ -2206,18 +2204,16 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state)
>>   
>>   	dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
>>   
>> -	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, dsc_prefill_latency);
>> +	return dsc_prefill_latency;
>>   }
>>   
>>   static int
>> -scaler_prefill_latency(const struct intel_crtc_state *crtc_state)
>> +scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
>>   {
>>   	const struct intel_crtc_scaler_state *scaler_state =
>>   					&crtc_state->scaler_state;
>>   	int num_scaler_users = hweight32(scaler_state->scaler_users);
>>   	int scaler_prefill_latency = 0;
>> -	int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
>> -				    crtc_state->hw.adjusted_mode.clock);
>>   
>>   	if (!num_scaler_users)
>>   		return scaler_prefill_latency;
>> @@ -2238,7 +2234,7 @@ scaler_prefill_latency(const struct intel_crtc_state *crtc_state)
>>   
>>   	scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
>>   
>> -	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, scaler_prefill_latency);
>> +	return scaler_prefill_latency;
>>   }
>>   
>>   static bool
>> @@ -2247,11 +2243,13 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
>>   {
>>   	const struct drm_display_mode *adjusted_mode =
>>   		&crtc_state->hw.adjusted_mode;
>> +	int linetime = DIV_ROUND_UP(1000 * adjusted_mode->htotal,
>> +				    adjusted_mode->clock);
>>   
>>   	return crtc_state->framestart_delay +
>>   		intel_usecs_to_scanlines(adjusted_mode, latency) +
>> -		scaler_prefill_latency(crtc_state) +
>> -		dsc_prefill_latency(crtc_state) +
>> +		DIV_ROUND_UP(scaler_prefill_latency(crtc_state, linetime), linetime) +
>> +		DIV_ROUND_UP(dsc_prefill_latency(crtc_state, linetime), linetime) +
> Looks like you could just add up all the usec latency numbers and
> convert the whole thing with a single intel_usecs_to_scanlines() call
> instead of this mismash of hand rolled and non-hand rolled stuff.

Hmm.. sure can use intel_usecs_to_scanlines() here. Will change this in 
next revision.


Regards,

Ankit

>>   		wm0_lines >
>>   		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
>>   }
>> -- 
>> 2.45.2

Re: [PATCH 05/15] drm/i915/display: Extract helpers to set dsc/scaler prefill latencies

[Nautiyal, Ankit K]

On 9/11/2025 7:31 PM, Ville Syrjälä wrote:
> On Thu, Sep 11, 2025 at 08:15:44AM +0530, Ankit Nautiyal wrote:
>> Currently dsc/scaler prefill latencies are handled during watermark
>> calculations. With the optimized guardband, we need to compute the
>> latencies to find the minimum guardband that works for most cases.
>> Extract the helpers to compute these latencies, so that they can be used
>> while computing vrr guardband.
>>
>> While at it, put declarations in reverse xmas tree order for better
>> redability.
>>
>> v2: Initialize {h,v}scale_k to 0, and simplify the check in
>> intel_display_scaler_prefill_latency(). (Mitul)
>> v3: Move helpers from intel_display.c to intel_vrr.c as they are specific
>> to account for latencies to program vrr guardband. (Jani)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_vrr.c     | 33 ++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_vrr.h     |  8 ++++
>>   drivers/gpu/drm/i915/display/skl_watermark.c | 47 +++++++++-----------
>>   3 files changed, 63 insertions(+), 25 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 266cf5e1859d..fd690de5b45b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -772,3 +772,36 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>>   	if (crtc_state->vrr.enable)
>>   		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>>   }
>> +
>> +int intel_vrr_guardband_scaler_latency(int num_scaler_users, u64 hscale, u64 vscale,
>> +				       int chroma_downscaling_factor,
>> +				       int cdclk_prefill_adjustment,
>> +				       int linetime)
>> +{
>> +	int scaler_prefill_latency;
>> +
>> +	scaler_prefill_latency = 4 * linetime +
>> +				 DIV_ROUND_UP_ULL((4 * linetime * hscale * vscale *
>> +						   chroma_downscaling_factor), 1000000);
>> +
>> +	scaler_prefill_latency *= cdclk_prefill_adjustment;
>> +
>> +	return scaler_prefill_latency;
>> +}
>> +
>> +int intel_vrr_guardband_dsc_latency(int num_scaler_users, u64 *hscale, u64 *vscale,
>> +				    int chroma_downscaling_factor,
>> +				    int cdclk_prefill_adjustment,
>> +				    int linetime)
>> +{
>> +	int dsc_prefill_latency;
>> +
>> +	dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10);
>> +
>> +	for (int i = 0; i < num_scaler_users; i++)
>> +		dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale[i] * vscale[i],
>> +						       1000000);
>> +	dsc_prefill_latency *= cdclk_prefill_adjustment;
>> +
>> +	return dsc_prefill_latency;
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
>> index 38bf9996b883..950041647e47 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
>> @@ -41,5 +41,13 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
>>   void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
>>   void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
>>   bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
>> +int intel_vrr_guardband_scaler_latency(int num_scaler_users, u64 hscale, u64 vscale,
>> +				       int chroma_downscaling_factor,
>> +				       int cdclk_prefill_adjustment,
>> +				       int linetime);
>> +int intel_vrr_guardband_dsc_latency(int num_scaler_users, u64 *hscale, u64 *vscale,
>> +				    int chroma_downscaling_factor,
>> +				    int cdclk_prefill_adjustment,
>> +				    int linetime);
>>   
>>   #endif /* __INTEL_VRR_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>> index 3d322c39ce21..1ff2b4d9a35e 100644
>> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
>> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>> @@ -28,6 +28,7 @@
>>   #include "intel_flipq.h"
>>   #include "intel_pcode.h"
>>   #include "intel_plane.h"
>> +#include "intel_vrr.h"
>>   #include "intel_wm.h"
>>   #include "skl_universal_plane_regs.h"
>>   #include "skl_scaler.h"
>> @@ -2179,11 +2180,12 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
>>   static int
>>   dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
>>   {
>> +	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
>> +	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
>>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> -	const struct intel_crtc_scaler_state *scaler_state =
>> -					&crtc_state->scaler_state;
>>   	int num_scaler_users = hweight32(scaler_state->scaler_users);
>> -	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
>> +	u64 hscale_k[ARRAY_SIZE(scaler_state->scalers)];
>> +	u64 vscale_k[ARRAY_SIZE(scaler_state->scalers)];
>>   	u32 dsc_prefill_latency = 0;
>>   
>>   	if (!crtc_state->dsc.compression_enable ||
>> @@ -2191,18 +2193,16 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
>>   	    num_scaler_users > crtc->num_scalers)
>>   		return dsc_prefill_latency;
>>   
>> -	dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10);
>> -
>>   	for (int i = 0; i < num_scaler_users; i++) {
>> -		u64 hscale_k, vscale_k;
>> -
>> -		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
>> -		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
>> -		dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale_k * vscale_k,
>> -						       1000000);
>> +		hscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
>> +		vscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
>>   	}
>>   
>> -	dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
>> +	dsc_prefill_latency =
>> +		intel_vrr_guardband_dsc_latency(num_scaler_users, hscale_k, vscale_k,
>> +						chroma_downscaling_factor,
>> +						cdclk_prefill_adjustment(crtc_state),
>> +						linetime);
> Calling vrr stuff for non-vrr stuff feels completely backwards.
> I suspect we should move these prefill latency calculations into
> the relevant scaler/dsc/etc files instead.

I can do that. Since these were only used to compute the vrr guardband, 
I had kept in intel_vrr.c, but you are right these are specific feature 
latencies, should belong to their respective files.

Aside from this, for functions in skl_scaler.c, what should be sensible 
naming for the functions/helpers: skl_scaler_prefill_latency doesn’t 
seem to be right as this is not related to skl.

Regards,

Ankit


>
>
>>   
>>   	return dsc_prefill_latency;
>>   }
>> @@ -2210,28 +2210,25 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
>>   static int
>>   scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
>>   {
>> -	const struct intel_crtc_scaler_state *scaler_state =
>> -					&crtc_state->scaler_state;
>> +	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
>> +	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
>>   	int num_scaler_users = hweight32(scaler_state->scaler_users);
>> +	u64 hscale_k = 0, vscale_k = 0;
>>   	int scaler_prefill_latency = 0;
>>   
>>   	if (!num_scaler_users)
>>   		return scaler_prefill_latency;
>>   
>> -	scaler_prefill_latency = 4 * linetime;
>> -
>>   	if (num_scaler_users > 1) {
>> -		u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
>> -		u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
>> -		int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
>> -		int latency;
>> -
>> -		latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k *
>> -					    chroma_downscaling_factor), 1000000);
>> -		scaler_prefill_latency += latency;
>> +		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
>> +		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
>>   	}
>>   
>> -	scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
>> +	scaler_prefill_latency =
>> +		intel_vrr_guardband_scaler_latency(num_scaler_users, hscale_k, vscale_k,
>> +						   chroma_downscaling_factor,
>> +						   cdclk_prefill_adjustment(crtc_state),
>> +						   linetime);
>>   
>>   	return scaler_prefill_latency;
>>   }
>> -- 
>> 2.45.2

Re: [PATCH 06/15] drm/i915/dp: Add SDP latency computation helper

[Nautiyal, Ankit K]

On 9/11/2025 7:44 PM, Ville Syrjälä wrote:
> On Thu, Sep 11, 2025 at 08:15:45AM +0530, Ankit Nautiyal wrote:
>> Add a helper to compute vblank time needed for transmitting specific
>> DisplayPort SDPs like PPS, GAMUT_METADATA, and VSC_EXT. Latency is
>> based on line count per packet type and current line time.
>>
>> Used to ensure adequate vblank when features like DSC/HDR are enabled.
>>
>> Bspec: 70151
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_dp.h |  2 ++
>>   2 files changed, 49 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 2eab591a8ef5..83c46e4680b3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -6857,3 +6857,50 @@ void intel_dp_mst_resume(struct intel_display *display)
>>   		}
>>   	}
>>   }
>> +
>> +static
>> +int intel_dp_get_sdp_latency(u32 type, int linetime_us)
> The "get" in the name is redundant.

Hmm ok, we can simply have intel_dp_sdp_latency().


>
>> +{
>> +	int lines;
>> +
>> +	switch (type) {
>> +	case DP_SDP_VSC_EXT_VESA:
>> +	case DP_SDP_VSC_EXT_CEA:
>> +		lines = 10;
>> +		break;
>> +	case HDMI_PACKET_TYPE_GAMUT_METADATA:
>> +		lines = 8;
>> +		break;
>> +	case DP_SDP_PPS:
>> +		lines = 6;
>> +		break;
>> +	default:
>> +		lines = 0;
>> +		break;
>> +	}
> We should probably calculate these properly instead of
> just hardcoding annoying magic numbers. But I suppose
> these are supposed to be some kind of semi worst case
> numbers so perhaps OK for now.

Yeah these are the numbers for worst case as mentioned in Bspec.

Regards,

Ankit


>
>> +
>> +	return lines * linetime_us;
>> +}
>> +
>> +int intel_dp_compute_sdp_latency(const struct intel_crtc_state *crtc_state,
>> +				 bool assume_all_enabled)
>> +{
>> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>> +	int sdp_latency = 0;
>> +	int linetime_us;
>> +
>> +	linetime_us = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000,
>> +				   adjusted_mode->crtc_clock);
>> +	if (assume_all_enabled ||
>> +	    crtc_state->infoframes.enable &
>> +	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
>> +		sdp_latency = max(sdp_latency,
>> +				  intel_dp_get_sdp_latency(HDMI_PACKET_TYPE_GAMUT_METADATA,
>> +							   linetime_us));
>> +
>> +	if (assume_all_enabled || crtc_state->dsc.compression_enable)
>> +		sdp_latency = max(sdp_latency,
>> +				  intel_dp_get_sdp_latency(DP_SDP_PPS, linetime_us));
>> +
>> +	return sdp_latency;
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> index f90cfd1dbbd0..d222749b191c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -215,5 +215,7 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
>>   int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector);
>>   void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
>>   bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
>> +int intel_dp_compute_sdp_latency(const struct intel_crtc_state *crtc_state,
>> +				 bool assume_all_enabled);
>>   
>>   #endif /* __INTEL_DP_H__ */
>> -- 
>> 2.45.2

Re: [PATCH 10/15] drm/i915/skl_watermark: Remove redundant latency checks from vblank validation

[Nautiyal, Ankit K]

On 9/11/2025 7:52 PM, Ville Syrjälä wrote:
> On Thu, Sep 11, 2025 at 08:15:49AM +0530, Ankit Nautiyal wrote:
>> Drop DSC and scaler prefill latency checks from skl_is_vblank_too_short().
>> These are now covered by the guardband validation added during the atomic
>> CRTC check phase.
>>
>> This cleanup prepares for future changes where the guardband will be
>> optimized independently of vblank length, making vblank-based checks
>> obsolete.
> This looks very wrong, at least for platforms that don't have a
> programmable guardband.

As far as I understand we need to take care of these latencies only for 
guardband and we had put these checks in vblank check because guardband 
was matching vblank length, so that, If we check for vblank length we 
are good for guardband.
I can either let these changes as it is for other platforms in 
skl_watermark.c.
Or else , In the previous patch I can remove the check 
intel_vrr_always_use_vrr_tg() so that we have new checks for all 
platforms that support VRR and guardband.

Regards,

Ankit


>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/skl_watermark.c | 79 --------------------
>>   1 file changed, 79 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>> index 83ac26004f05..07589096b143 100644
>> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
>> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>> @@ -28,7 +28,6 @@
>>   #include "intel_flipq.h"
>>   #include "intel_pcode.h"
>>   #include "intel_plane.h"
>> -#include "intel_vrr.h"
>>   #include "intel_wm.h"
>>   #include "skl_universal_plane_regs.h"
>>   #include "skl_scaler.h"
>> @@ -2159,93 +2158,15 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
>>   	return 0;
>>   }
>>   
>> -static int
>> -cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
>> -{
>> -	struct intel_display *display = to_intel_display(crtc_state);
>> -	struct intel_atomic_state *state =
>> -		to_intel_atomic_state(crtc_state->uapi.state);
>> -	const struct intel_cdclk_state *cdclk_state;
>> -
>> -	cdclk_state = intel_atomic_get_cdclk_state(state);
>> -	if (IS_ERR(cdclk_state)) {
>> -		drm_WARN_ON(display->drm, PTR_ERR(cdclk_state));
>> -		return 1;
>> -	}
>> -
>> -	return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
>> -				   2 * intel_cdclk_logical(cdclk_state)));
>> -}
>> -
>> -static int
>> -dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
>> -{
>> -	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
>> -	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
>> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> -	int num_scaler_users = hweight32(scaler_state->scaler_users);
>> -	u64 hscale_k[ARRAY_SIZE(scaler_state->scalers)];
>> -	u64 vscale_k[ARRAY_SIZE(scaler_state->scalers)];
>> -	u32 dsc_prefill_latency = 0;
>> -
>> -	if (!crtc_state->dsc.compression_enable ||
>> -	    !num_scaler_users ||
>> -	    num_scaler_users > crtc->num_scalers)
>> -		return dsc_prefill_latency;
>> -
>> -	for (int i = 0; i < num_scaler_users; i++) {
>> -		hscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
>> -		vscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
>> -	}
>> -
>> -	dsc_prefill_latency =
>> -		intel_vrr_guardband_dsc_latency(num_scaler_users, hscale_k, vscale_k,
>> -						chroma_downscaling_factor,
>> -						cdclk_prefill_adjustment(crtc_state),
>> -						linetime);
>> -
>> -	return dsc_prefill_latency;
>> -}
>> -
>> -static int
>> -scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
>> -{
>> -	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
>> -	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
>> -	int num_scaler_users = hweight32(scaler_state->scaler_users);
>> -	u64 hscale_k = 0, vscale_k = 0;
>> -	int scaler_prefill_latency = 0;
>> -
>> -	if (!num_scaler_users)
>> -		return scaler_prefill_latency;
>> -
>> -	if (num_scaler_users > 1) {
>> -		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
>> -		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
>> -	}
>> -
>> -	scaler_prefill_latency =
>> -		intel_vrr_guardband_scaler_latency(num_scaler_users, hscale_k, vscale_k,
>> -						   chroma_downscaling_factor,
>> -						   cdclk_prefill_adjustment(crtc_state),
>> -						   linetime);
>> -
>> -	return scaler_prefill_latency;
>> -}
>> -
>>   static bool
>>   skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
>>   			int wm0_lines, int latency)
>>   {
>>   	const struct drm_display_mode *adjusted_mode =
>>   		&crtc_state->hw.adjusted_mode;
>> -	int linetime = DIV_ROUND_UP(1000 * adjusted_mode->htotal,
>> -				    adjusted_mode->clock);
>>   
>>   	return crtc_state->framestart_delay +
>>   		intel_usecs_to_scanlines(adjusted_mode, latency) +
>> -		DIV_ROUND_UP(scaler_prefill_latency(crtc_state, linetime), linetime) +
>> -		DIV_ROUND_UP(dsc_prefill_latency(crtc_state, linetime), linetime) +
>>   		wm0_lines >
>>   		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
>>   }
>> -- 
>> 2.45.2

Re: [PATCH 15/15] drm/i915/vrr: Fix seamless_mn drrs for PTL

[Nautiyal, Ankit K]

On 9/11/2025 8:11 PM, Ville Syrjälä wrote:
> On Thu, Sep 11, 2025 at 08:15:54AM +0530, Ankit Nautiyal wrote:
>> With VRR timing generator always on, the fixed refresh rate is achieved
>> by setting vrr.flipline and vrr.vmax as the vtotal for the desired mode.
>>
>> This creates a problem for seamless_mn drrs feature, where user can
>> seamlessly set a lower mode on the supporting panels. With VRR timing
>> generator, the vrr.flipline and vrr.vmax are set to vtotal, but that
>> corresponds to the higher mode.
>>
>> To fix this, re-compute the vrr timings when seamless_mn drrs is in
>> picture. At the same time make sure that the vrr.guardband is set as
>> per the highest mode for such panels, so that switching between higher
>> to lower mode, does not change the vrr.guardband.
>>
>> v2: Add a new member `use_highest_mode` to vrr struct to help set the
>> vrr timings for highest mode for the seamless_mn drrs case.
>> v3:
>> -Modify existing function to compute fixed refresh rate timings instead
>> of adding a new function. (Mitul)
>> -Tweak computation for scaling the vtotal and use DIV_ROUND_UP_ULL.
>> -Improve documentation.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>> ---
>>   .../drm/i915/display/intel_display_types.h    |  2 +
>>   drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
>>   drivers/gpu/drm/i915/display/intel_dp.h       |  1 +
>>   drivers/gpu/drm/i915/display/intel_vrr.c      | 90 ++++++++++++++++++-
>>   4 files changed, 90 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 358ab922d7a7..9796c7b855d0 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1321,6 +1321,8 @@ struct intel_crtc_state {
>>   		u8 pipeline_full;
>>   		u16 flipline, vmin, vmax, guardband;
>>   		u32 vsync_end, vsync_start;
>> +		/* Indicates VRR timing is scaled to highest mode for seamless M/N */
>> +		bool use_highest_mode;
>>   	} vrr;
>>   
>>   	/* Content Match Refresh Rate state */
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index f74ac98062d4..5c29c696c83e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1742,7 +1742,7 @@ static int intel_dp_max_bpp(struct intel_dp *intel_dp,
>>   	return bpp;
>>   }
>>   
>> -static bool has_seamless_m_n(struct intel_connector *connector)
>> +bool has_seamless_m_n(struct intel_connector *connector)
>>   {
>>   	struct intel_display *display = to_intel_display(connector);
>>   
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> index d222749b191c..6da0196c23d1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -217,5 +217,6 @@ void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
>>   bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
>>   int intel_dp_compute_sdp_latency(const struct intel_crtc_state *crtc_state,
>>   				 bool assume_all_enabled);
>> +bool has_seamless_m_n(struct intel_connector *connector);
>>   
>>   #endif /* __INTEL_DP_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 002165026a20..80bbe4b1ef7f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -11,6 +11,7 @@
>>   #include "intel_display_regs.h"
>>   #include "intel_display_types.h"
>>   #include "intel_dp.h"
>> +#include "intel_panel.h"
>>   #include "intel_vrr.h"
>>   #include "intel_vrr_regs.h"
>>   #include "skl_scaler.h"
>> @@ -299,6 +300,16 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
>>   	if (!intel_vrr_possible(crtc_state))
>>   		return;
>>   
>> +	if (crtc_state->vrr.use_highest_mode) {
>> +		intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
>> +			       crtc_state->vrr.vmin - 1);
>> +		intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
>> +			       crtc_state->vrr.vmax - 1);
>> +		intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
>> +			       crtc_state->vrr.flipline - 1);
>> +		return;
>> +	}
>> +
>>   	intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
>>   		       intel_vrr_fixed_rr_vmin(crtc_state) - 1);
>>   	intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
>> @@ -307,15 +318,69 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
>>   		       intel_vrr_fixed_rr_flipline(crtc_state) - 1);
>>   }
>>   
>> +static bool needs_seamless_m_n_timings(struct intel_crtc_state *crtc_state,
>> +				       struct intel_connector *connector)
>> +{
>> +	if (!has_seamless_m_n(connector) || crtc_state->joiner_pipes)
>> +		return false;
>> +
>> +	return true;
>> +}
>> +
>> +static int intel_vrr_scale_vtotal_for_seamless_m_n(struct intel_crtc_state *crtc_state,
>> +						   struct intel_connector *connector)
>> +{
>> +	const struct drm_display_mode *highest_mode = intel_panel_highest_mode(connector);
>> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>> +	int vtotal = adjusted_mode->crtc_vtotal;
>> +
>> +	/*
>> +	 * For panels with seamless_m_n drrs, the user can seamlessly switch to
>> +	 * a lower mode, which has a lower clock. This works with legacy timing
>> +	 * generator, but not with the VRR timing generator.
>> +	 *
>> +	 * The VRR timing generator requires flipline and vmax to be equal for
>> +	 * fixed refresh rate operation. The default fixed RR computation sets
>> +	 * these to the current mode's vtotal. However, when switching to a
>> +	 * lower clock mode, this would result in a higher refresh rate than
>> +	 * desired.
>> +	 *
>> +	 * To simulate the lower refresh rate correctly, we scale the vtotal
>> +	 * based on the ratio of the highest mode's clock to the current mode's
>> +	 * clock.
>> +	 *
>> +	 * When switching to a higher clock mode, the current vtotal already
>> +	 * results in the desired refresh rate, so no scaling is needed.
>> +	 *
>> +	 * So compute the scaled vtotal if required, and update vrr.vmin to
>> +	 * the scaled value. Also, set vrr.use_highest_mode to indicate that
>> +	 * VRR timings are based on the highest mode.
>> +	 */
>> +	if (highest_mode && adjusted_mode->crtc_clock < highest_mode->clock) {
>> +		vtotal = DIV_ROUND_UP_ULL(vtotal * highest_mode->clock,
>> +					  adjusted_mode->crtc_clock);
>> +		crtc_state->vrr.vmin = vtotal;
>> +		crtc_state->vrr.use_highest_mode = true;
>> +	}
> I have no idea what is happening here. I think the only thing we should
> be aiming for is a fixed guardband length, but this is now doing all kinds
> of otehr massaging of VRR parameters. Why?


The idea was to support Seamless M/N DRRS with VRR timing generator.

Currently if user sets the lower mode i.e. same mode with lower clock we 
were able to seamlessly switch with legacy timing generator.

With VRR Timing generator this doesn’t work as we need to change the 
flipline/Vmax vtotal to achieve the same effect.

I was trying to do something like that.

But apparently Seamless M/N DRRS is defeatured, so perhaps I will drop 
this and the previous patch.

Thanks again for clearing this up with the Hw team and for the required 
patch.

Regards,
Ankit


>> +
>> +	return vtotal;
>> +}
>> +
>>   static
>> -void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state)
>> +void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state,
>> +					struct intel_connector *connector)
>>   {
>> +	int vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
>> +
>> +	if (needs_seamless_m_n_timings(crtc_state, connector))
>> +		vtotal = intel_vrr_scale_vtotal_for_seamless_m_n(crtc_state, connector);
>> +
>>   	/*
>>   	 * For fixed rr,  vmin = vmax = flipline.
>>   	 * vmin is already set to crtc_vtotal set vmax and flipline the same.
>>   	 */
>> -	crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.crtc_vtotal;
>> -	crtc_state->vrr.flipline = crtc_state->hw.adjusted_mode.crtc_vtotal;
>> +	crtc_state->vrr.vmax = vtotal;
>> +	crtc_state->vrr.flipline = vtotal;
>>   }
>>   
>>   static
>> @@ -397,7 +462,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>>   	else if (is_cmrr_frac_required(crtc_state) && is_edp)
>>   		intel_vrr_compute_cmrr_timings(crtc_state);
>>   	else
>> -		intel_vrr_compute_fixed_rr_timings(crtc_state);
>> +		intel_vrr_compute_fixed_rr_timings(crtc_state, connector);
>>   
>>   	/*
>>   	 * flipline determines the min vblank length the hardware will
>> @@ -876,6 +941,7 @@ int intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state,
>>   {
>>   	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>>   	struct intel_display *display = to_intel_display(crtc_state);
>> +	const struct drm_display_mode *highest_mode;
>>   	int dsc_prefill_time = 0;
>>   	int psr2_pr_latency = 0;
>>   	int scaler_prefill_time;
>> @@ -888,6 +954,22 @@ int intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state,
>>   	int guardband;
>>   	int pm_delay;
>>   
>> +	/*
>> +	 * For seamless m_n the clock is changed while other modeline
>> +	 * parameters are same. In that case the linetime_us will change,
>> +	 * causing the guardband to change, and the seamless switch to
>> +	 * lower mode would not take place.
>> +	 * To avoid this, take the highest mode where panel supports
>> +	 * seamless drrs and make guardband equal to the vblank length
>> +	 * for the highest mode.
>> +	 */
>> +	highest_mode = intel_panel_highest_mode(connector);
>> +	if (needs_seamless_m_n_timings(crtc_state, connector) && highest_mode) {
>> +		guardband = highest_mode->vtotal - highest_mode->vdisplay;
>> +
>> +		return guardband;
>> +	}
>> +
>>   	linetime_us = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000,
>>   				   adjusted_mode->crtc_clock);
>>   
>> -- 
>> 2.45.2

Re: [PATCH 14/15] drm/i915/panel: Refactor helper to get highest fixed mode

[Nautiyal, Ankit K]

On 9/11/2025 8:07 PM, Ville Syrjälä wrote:
> On Thu, Sep 11, 2025 at 08:15:53AM +0530, Ankit Nautiyal wrote:
>> Refactor intel_panel_highest_mode() to return the fixed mode with the
>> highest pixel clock, removing the fallback to the adjusted mode. This makes
>> the function semantics clearer and better suited for future use cases where
>> fallback is not desirable.
>>
>> Update the caller in intel_dp_mode_clock() to handle the NULL case
>> explicitly by falling back to the adjusted mode's crtc_clock. This also
>> addresses the existing FIXME comment about ambiguity between clock and
>> crtc_clock, by using mode->clock for fixed modes and mode->crtc_clock for
>> adjusted modes.
>>
>> v2: Avoid introducing a new function and refactor existing one instead.
>> (Jani).
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c    | 14 +++++++++-----
>>   drivers/gpu/drm/i915/display/intel_panel.c | 11 +++++------
>>   drivers/gpu/drm/i915/display/intel_panel.h |  3 +--
>>   3 files changed, 15 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 83c46e4680b3..f74ac98062d4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1760,11 +1760,15 @@ static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
>>   	struct intel_connector *connector = to_intel_connector(conn_state->connector);
>>   	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>>   
>> -	/* FIXME a bit of a mess wrt clock vs. crtc_clock */
>> -	if (has_seamless_m_n(connector))
>> -		return intel_panel_highest_mode(connector, adjusted_mode)->clock;
>> -	else
>> -		return adjusted_mode->crtc_clock;
>> +	if (has_seamless_m_n(connector)) {
>> +		const struct drm_display_mode *highest_mode;
>> +
>> +		highest_mode = intel_panel_highest_mode(connector);
>> +		if (highest_mode)
>> +			return highest_mode->clock;
>> +	}
>> +
>> +	return adjusted_mode->crtc_clock;
>>   }
>>   
>>   /* Optimize link config in order: max bpp, min clock, min lanes */
>> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
>> index 2a20aaaaac39..ac0f04073ecb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_panel.c
>> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
>> @@ -144,18 +144,17 @@ intel_panel_downclock_mode(struct intel_connector *connector,
>>   }
>>   
>>   const struct drm_display_mode *
>> -intel_panel_highest_mode(struct intel_connector *connector,
>> -			 const struct drm_display_mode *adjusted_mode)
>> +intel_panel_highest_mode(struct intel_connector *connector)
>>   {
>> -	const struct drm_display_mode *fixed_mode, *best_mode = adjusted_mode;
>> +	const struct drm_display_mode *fixed_mode, *highest_mode = NULL;
>>   
>>   	/* pick the fixed_mode that has the highest clock */
>>   	list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) {
>> -		if (fixed_mode->clock > best_mode->clock)
>> -			best_mode = fixed_mode;
>> +		if (!highest_mode || fixed_mode->clock > highest_mode->clock)
>> +			highest_mode = fixed_mode;
> This looks broken now as it will always return some kind of mode
> from the list, but whether or not it's better than the adjusted_mode
> is no logner guaranteed.


This was in relation to supporting seamless MN DRRS with VRR timing 
generator.
As mentioned in the response to the following patch, this is not 
required and I will drop this patch from the series.

Regards,
Ankit

>
>>   	}
>>   
>> -	return best_mode;
>> +	return highest_mode;
>>   }
>>   
>>   int intel_panel_get_modes(struct intel_connector *connector)
>> diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm/i915/display/intel_panel.h
>> index 56a6412cf0fb..8a17600e46a3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_panel.h
>> +++ b/drivers/gpu/drm/i915/display/intel_panel.h
>> @@ -37,8 +37,7 @@ const struct drm_display_mode *
>>   intel_panel_downclock_mode(struct intel_connector *connector,
>>   			   const struct drm_display_mode *adjusted_mode);
>>   const struct drm_display_mode *
>> -intel_panel_highest_mode(struct intel_connector *connector,
>> -			 const struct drm_display_mode *adjusted_mode);
>> +intel_panel_highest_mode(struct intel_connector *connector);
>>   int intel_panel_get_modes(struct intel_connector *connector);
>>   enum drrs_type intel_panel_drrs_type(struct intel_connector *connector);
>>   enum drm_mode_status
>> -- 
>> 2.45.2

Re: [PATCH 00/15] Optimize vrr.guardband and fix LRR

[Nautiyal, Ankit K]

On 9/12/2025 7:33 PM, Ville Syrjälä wrote:
> On Thu, Sep 11, 2025 at 08:15:39AM +0530, Ankit Nautiyal wrote:
>> Instead of setting vrr.guardband to vblank, use optimal guardband that
>> works for most of the cases. This will help in avoiding need of change
>> in guardband and fix the LRR feature that needs seamless switching to
>> a lower refresh rate.
> I think the _only_ thing we need for that is intel_crtc_vblank_delay()
> to return a different number. But this series is doing all kinds of
> stuff to other VRR logic that I don't understand at all.

There are couple of things which are done apart from 
intel_crtc_vblank_delay:

1. The delay calculation based on the pipe fill latencies as given in Bspec.

There were some checks which were already there, I have moved them into 
different place and added new checks.

There are still some things like PKG_C_LATENCY which might need a relook.

2. The SCL value is shortened as we see some issue with the 
dsb_wait_for_usec just after the push if its in the SCL window.

I am still looking into this one to root cause, but somewhere seems to 
be related to DSB_CHICKEN_BIT 15 wait for safe window.

I agree with the changes you have suggested in other patches, and will 
send new version with those addressed.

Will get rid of other changes that are not required now.


>
>> First few patches fix/refactor and extract common functions required for
>> dsc/scaler prefill time computation. Later patches use these helpers to
>> compute an optimized guardband.
>>
>> Also, for seamless_mn where vtotal is same but mode clock is changed to
>> seamlessly switch to lower rate, re-compute the vrr timings.
> As Art pointed out that stuff is defeatured on LNL+ (just sent
> a patch for that) so we don't need to worry about it too much.

Thanks for the patch, looks good to me.

I will drop the patches related to this.


Thanks again for looking into the series and to provide suggestions and 
corrections.

Regards,

Ankit

>
>> Few things that still need work:
>> -The timestamps corresponding with next start of vactive still need to be
>> fixed with the new scheme.
>> -Re-enabling CMRR
>>
>> Rev2:
>> -Address comments from Mitul.
>> -Extract helpers for dsc/scaler prefill latencies.
>> -Fix downscaling factor for chroma subsampling.
>> -Use missing pkg C max latency.
>> -Fix guardband computation for seamless mn, always use vblank for
>> higher resolution.
>>
>> Rev3:
>> -Drop patches for computing and storing PSR/Panel Replay wake times
>> latencies and use existing helpers to compute these in intel_alpm.c.
>> -Drop patch to change the Vmin as it was not required.
>>
>> Rev4:
>> -Rebase
>> -Drop patch for checking bounds for scaler array access.
>> -Use a new flag for setting vrr timings for seamless drrs.
>>
>> Rev5:
>> -Address comments from Mitul, Jani:
>> -Refactor few helpers for computing latencies.
>> -Rename the helper to check the guardband to intel_crtc_guardband_atomic_check()
>> -Refactor the helper intel_panel_highest_mode().
>>
>> Rev6:
>> -Rebase
>> -Address review comments from Mitul.
>> -Improve documentation for and other minor fixes in Patch#12
>>
>> Rev7:
>> -Address comments from Jani.
>> -Move the latency helpers from intel_display.c to intel_vrr.c and rename
>> the helpers appropriately.
>> -Drop redundant check for HAS_VRR with intel_vrr_possible().
>>
>> Rev8:
>> -Fix CI issues.
>> -For fixed RR wait for delayed vblank before dsb interrupt.
>>
>> Rev9:
>> -Fix vrr.vsync_start/end timings for 3D modes (patch#1)
>> -Rewrite the patch to wait for delayed vblank before dsb interrupt
>> (patch #11)
>> -Fix the flipline and vmin timings with optimized guardband (patch#12)
>>
>> Rev10:
>> -Address comments from Ville: Use min guardband computation for setting
>> the vblank delay and set the crtc_vblank_start to delayed vblank.
>> (Patch#13)
>> -Modify the TRANS_SET_CONTEXT_LATENCY as per new guardband and use
>> vrr.guardband to readback vblank_start. (Patch#11)
>>
>> -From previous revision:
>> ->Drop patch#11 "drm/i915/dsb: Align flipdone with delayed vblank using
>> guardband wait", as this is no longer required.
>> ->Modify Patch#12 "drm/i915/vrr: Use static guardband to support seamless
>> LRR switching" to only introduce a helper to compute the fix guardband.
>> Modify the commit message and the subject.
>>
>> Ankit Nautiyal (15):
>>    drm/i915/vrr: Use crtc_vsync_start/end for computing
>>      vrr.vsync_start/end
>>    drm/i915/skl_watermark: Fix the scaling factor for chroma subsampling
>>    drm/i915/skl_watermark: Pass linetime as argument to latency helpers
>>    drm/i915/skl_scaler: Introduce helper for chroma downscale factor
>>    drm/i915/display: Extract helpers to set dsc/scaler prefill latencies
>>    drm/i915/dp: Add SDP latency computation helper
>>    drm/i915/alpm: Add function to compute max link-wake latency
>>    drm/i915/vrr: Use vrr.sync_start for getting vtotal
>>    drm/i915/display: Add guardband check for feature latencies
>>    drm/i915/skl_watermark: Remove redundant latency checks from vblank
>>      validation
>>    drm/i915/display: Use vrr.guardband to derive vblank_start
>>    drm/i915/vrr: Introduce helper to compute min static guardband
>>    drm/i915/display: Use optimized guardband to set vblank start
>>    drm/i915/panel: Refactor helper to get highest fixed mode
>>    drm/i915/vrr: Fix seamless_mn drrs for PTL
>>
>>   drivers/gpu/drm/i915/display/intel_alpm.c     |  15 +
>>   drivers/gpu/drm/i915/display/intel_alpm.h     |   2 +
>>   drivers/gpu/drm/i915/display/intel_display.c  | 236 ++++++++++++++-
>>   .../drm/i915/display/intel_display_types.h    |   2 +
>>   drivers/gpu/drm/i915/display/intel_dp.c       |  63 +++-
>>   drivers/gpu/drm/i915/display/intel_dp.h       |   3 +
>>   drivers/gpu/drm/i915/display/intel_panel.c    |  11 +-
>>   drivers/gpu/drm/i915/display/intel_panel.h    |   3 +-
>>   drivers/gpu/drm/i915/display/intel_vrr.c      | 272 ++++++++++++++++--
>>   drivers/gpu/drm/i915/display/intel_vrr.h      |  10 +
>>   drivers/gpu/drm/i915/display/skl_scaler.c     |   5 +
>>   drivers/gpu/drm/i915/display/skl_scaler.h     |   3 +
>>   drivers/gpu/drm/i915/display/skl_watermark.c  |  89 +-----
>>   drivers/gpu/drm/i915/display/skl_watermark.h  |   1 +
>>   14 files changed, 586 insertions(+), 129 deletions(-)
>>
>> -- 
>> 2.45.2

Re: [PATCH 11/15] drm/i915/display: Use vrr.guardband to derive vblank_start

[Ville Syrjälä]

On Sun, Sep 14, 2025 at 11:29:10AM +0530, Nautiyal, Ankit K wrote:
> 
> On 9/11/2025 7:55 PM, Ville Syrjälä wrote:
> > On Thu, Sep 11, 2025 at 08:15:50AM +0530, Ankit Nautiyal wrote:
> >> When VRR TG is always enabled and an optimized guardband is used, the pipe
> >> vblank start is derived from the guardband.
> >> Currently TRANS_SET_CONTEXT_LATENCY is programmed with crtc_vblank_start -
> >> crtc_vdisplay, which is ~1 when guardband matches the vblank length.
> >> With shorter guardband this become a large window.
> >>
> >> To avoid misprogramming TRANS_SET_CONTEXT_LATENCY, clamp the scl value to 1
> >> when using optimized guardband.
> >>
> >> Also update the VRR get config logic to set crtc_vblank_start based on
> >> vtotal - guardband, during readback.
> >>
> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/display/intel_display.c | 36 ++++++++++++++++----
> >>   drivers/gpu/drm/i915/display/intel_vrr.c     |  9 ++++-
> >>   2 files changed, 38 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> >> index 55bea1374dc4..73aec6d4686a 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -2638,6 +2638,30 @@ transcoder_has_vrr(const struct intel_crtc_state *crtc_state)
> >>   	return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
> >>   }
> >>   
> >> +static int intel_set_context_latency(const struct intel_crtc_state *crtc_state,
> >> +				     int crtc_vblank_start,
> >> +				     int crtc_vdisplay)
> >> +{
> >> +	struct intel_display *display = to_intel_display(crtc_state);
> >> +
> >> +	/*
> >> +	 * When VRR TG is always on and optimized guardband is used,
> >> +	 * the pipe vblank start is based on the guardband,
> >> +	 * TRANS_SET_CONTEXT_LATENCY cannot be used to configure it.
> >> +	 */
> >> +	if (intel_vrr_always_use_vrr_tg(display))
> >> +		return clamp(crtc_vblank_start - crtc_vdisplay, 0, 1);
> > What are you trying to achieve with this? As in what problem are you
> > seeing with the current SCL programming?
> 
> In VRR TG mode with optimized guardband, the guardband is shortened and 
> vblank start is moved to match the delayed vblank position.
> 
> The SCL value which we are currently writing as difference between 
> delayed vblank and undelayed vblank becomes quite large.
> 
> With this large SCL, the flipline decision boundary which is given by 
> delayed vblank start and SCL lines is same as the undelayed vblank.

Everything should match the undelayed vblank.

> 
> It seems that intel_dsb_wait_vblank_delay() (in turn 
> intel_dsb_wait_usec()) does not behave correctly within the W2 window 
> (between flipdone decision boundary and delayed vblank start).
> 
> It seems to return prematurely. Since the push bit hasn’t cleared yet, 
> this leads to DSB poll errors.

That doesn't make any sense. That command is supposed to simply wait
for the specifid number of microseconds. It should not care at all
what is happening with the scanout. If that is not the case then we
need to write a synthetic test to reproduce it, and report the
problem to the hardware folks.

> AFAIU we are not using the SCL (Set Context Latency) lines to write 
> registers via DSB.
> 
> The evasion logic ensures we write within a separate window, making the 
> actual SCL value less critical for register programming.
> 
> So I have clamped the SCL value to (0,1). With this after the push is 
> sent the send push bit is cleared after (0,1) lines.
> 
> But we still need to wait for the delayed vblank. For this we need 
> either intel_dsb_wait_vblank_delay() or dsb_wait_for_scanline_in().
> 
> 
> Do you have any ideas, what could have been going wrong or if anything 
> we might have been missing?

Was your crtc_vblank_start even correct (== undelayed vblank)
when you were testing that?

-- 
Ville Syrjälä
Intel

Re: [PATCH 15/15] drm/i915/vrr: Fix seamless_mn drrs for PTL

[Ville Syrjälä]

On Sun, Sep 14, 2025 at 11:37:09AM +0530, Nautiyal, Ankit K wrote:
> 
> On 9/11/2025 8:11 PM, Ville Syrjälä wrote:
> > On Thu, Sep 11, 2025 at 08:15:54AM +0530, Ankit Nautiyal wrote:
> >> With VRR timing generator always on, the fixed refresh rate is achieved
> >> by setting vrr.flipline and vrr.vmax as the vtotal for the desired mode.
> >>
> >> This creates a problem for seamless_mn drrs feature, where user can
> >> seamlessly set a lower mode on the supporting panels. With VRR timing
> >> generator, the vrr.flipline and vrr.vmax are set to vtotal, but that
> >> corresponds to the higher mode.
> >>
> >> To fix this, re-compute the vrr timings when seamless_mn drrs is in
> >> picture. At the same time make sure that the vrr.guardband is set as
> >> per the highest mode for such panels, so that switching between higher
> >> to lower mode, does not change the vrr.guardband.
> >>
> >> v2: Add a new member `use_highest_mode` to vrr struct to help set the
> >> vrr timings for highest mode for the seamless_mn drrs case.
> >> v3:
> >> -Modify existing function to compute fixed refresh rate timings instead
> >> of adding a new function. (Mitul)
> >> -Tweak computation for scaling the vtotal and use DIV_ROUND_UP_ULL.
> >> -Improve documentation.
> >>
> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> >> ---
> >>   .../drm/i915/display/intel_display_types.h    |  2 +
> >>   drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
> >>   drivers/gpu/drm/i915/display/intel_dp.h       |  1 +
> >>   drivers/gpu/drm/i915/display/intel_vrr.c      | 90 ++++++++++++++++++-
> >>   4 files changed, 90 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> index 358ab922d7a7..9796c7b855d0 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> @@ -1321,6 +1321,8 @@ struct intel_crtc_state {
> >>   		u8 pipeline_full;
> >>   		u16 flipline, vmin, vmax, guardband;
> >>   		u32 vsync_end, vsync_start;
> >> +		/* Indicates VRR timing is scaled to highest mode for seamless M/N */
> >> +		bool use_highest_mode;
> >>   	} vrr;
> >>   
> >>   	/* Content Match Refresh Rate state */
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> >> index f74ac98062d4..5c29c696c83e 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> @@ -1742,7 +1742,7 @@ static int intel_dp_max_bpp(struct intel_dp *intel_dp,
> >>   	return bpp;
> >>   }
> >>   
> >> -static bool has_seamless_m_n(struct intel_connector *connector)
> >> +bool has_seamless_m_n(struct intel_connector *connector)
> >>   {
> >>   	struct intel_display *display = to_intel_display(connector);
> >>   
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> >> index d222749b191c..6da0196c23d1 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> >> @@ -217,5 +217,6 @@ void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
> >>   bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
> >>   int intel_dp_compute_sdp_latency(const struct intel_crtc_state *crtc_state,
> >>   				 bool assume_all_enabled);
> >> +bool has_seamless_m_n(struct intel_connector *connector);
> >>   
> >>   #endif /* __INTEL_DP_H__ */
> >> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> >> index 002165026a20..80bbe4b1ef7f 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> >> @@ -11,6 +11,7 @@
> >>   #include "intel_display_regs.h"
> >>   #include "intel_display_types.h"
> >>   #include "intel_dp.h"
> >> +#include "intel_panel.h"
> >>   #include "intel_vrr.h"
> >>   #include "intel_vrr_regs.h"
> >>   #include "skl_scaler.h"
> >> @@ -299,6 +300,16 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
> >>   	if (!intel_vrr_possible(crtc_state))
> >>   		return;
> >>   
> >> +	if (crtc_state->vrr.use_highest_mode) {
> >> +		intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
> >> +			       crtc_state->vrr.vmin - 1);
> >> +		intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
> >> +			       crtc_state->vrr.vmax - 1);
> >> +		intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
> >> +			       crtc_state->vrr.flipline - 1);
> >> +		return;
> >> +	}
> >> +
> >>   	intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
> >>   		       intel_vrr_fixed_rr_vmin(crtc_state) - 1);
> >>   	intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
> >> @@ -307,15 +318,69 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
> >>   		       intel_vrr_fixed_rr_flipline(crtc_state) - 1);
> >>   }
> >>   
> >> +static bool needs_seamless_m_n_timings(struct intel_crtc_state *crtc_state,
> >> +				       struct intel_connector *connector)
> >> +{
> >> +	if (!has_seamless_m_n(connector) || crtc_state->joiner_pipes)
> >> +		return false;
> >> +
> >> +	return true;
> >> +}
> >> +
> >> +static int intel_vrr_scale_vtotal_for_seamless_m_n(struct intel_crtc_state *crtc_state,
> >> +						   struct intel_connector *connector)
> >> +{
> >> +	const struct drm_display_mode *highest_mode = intel_panel_highest_mode(connector);
> >> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> >> +	int vtotal = adjusted_mode->crtc_vtotal;
> >> +
> >> +	/*
> >> +	 * For panels with seamless_m_n drrs, the user can seamlessly switch to
> >> +	 * a lower mode, which has a lower clock. This works with legacy timing
> >> +	 * generator, but not with the VRR timing generator.
> >> +	 *
> >> +	 * The VRR timing generator requires flipline and vmax to be equal for
> >> +	 * fixed refresh rate operation. The default fixed RR computation sets
> >> +	 * these to the current mode's vtotal. However, when switching to a
> >> +	 * lower clock mode, this would result in a higher refresh rate than
> >> +	 * desired.
> >> +	 *
> >> +	 * To simulate the lower refresh rate correctly, we scale the vtotal
> >> +	 * based on the ratio of the highest mode's clock to the current mode's
> >> +	 * clock.
> >> +	 *
> >> +	 * When switching to a higher clock mode, the current vtotal already
> >> +	 * results in the desired refresh rate, so no scaling is needed.
> >> +	 *
> >> +	 * So compute the scaled vtotal if required, and update vrr.vmin to
> >> +	 * the scaled value. Also, set vrr.use_highest_mode to indicate that
> >> +	 * VRR timings are based on the highest mode.
> >> +	 */
> >> +	if (highest_mode && adjusted_mode->crtc_clock < highest_mode->clock) {
> >> +		vtotal = DIV_ROUND_UP_ULL(vtotal * highest_mode->clock,
> >> +					  adjusted_mode->crtc_clock);
> >> +		crtc_state->vrr.vmin = vtotal;
> >> +		crtc_state->vrr.use_highest_mode = true;
> >> +	}
> > I have no idea what is happening here. I think the only thing we should
> > be aiming for is a fixed guardband length, but this is now doing all kinds
> > of otehr massaging of VRR parameters. Why?
> 
> 
> The idea was to support Seamless M/N DRRS with VRR timing generator.
> 
> Currently if user sets the lower mode i.e. same mode with lower clock we 
> were able to seamlessly switch with legacy timing generator.
> 
> With VRR Timing generator this doesn’t work as we need to change the 
> flipline/Vmax vtotal to achieve the same effect.
> 
> I was trying to do something like that.

We definitely don't want to sneakily start converting M/N changes
into some kind of VRR changes in low level code. If we did ever
want to do something like then it should be done in some high level
code by simply adjusting the mode. And we already do that for eDP
to some degree since there the userspace mode is partly a lie.

I don't think we should seriously even be thinking about such
things for external panels. Although one idea I've had occasionally
is to allow userspace to provide separate "fixed mode" timings
also for external panels, at which point we could handle external
panels similar to internal panels where the actual timings are
specified by the "fixed mode" and the normal mode just provides
the crtc dimensions and vrefresh.

-- 
Ville Syrjälä
Intel

Re: [PATCH 11/15] drm/i915/display: Use vrr.guardband to derive vblank_start

[Nautiyal, Ankit K]

On 9/15/2025 6:02 PM, Ville Syrjälä wrote:
> On Sun, Sep 14, 2025 at 11:29:10AM +0530, Nautiyal, Ankit K wrote:
>> On 9/11/2025 7:55 PM, Ville Syrjälä wrote:
>>> On Thu, Sep 11, 2025 at 08:15:50AM +0530, Ankit Nautiyal wrote:
>>>> When VRR TG is always enabled and an optimized guardband is used, the pipe
>>>> vblank start is derived from the guardband.
>>>> Currently TRANS_SET_CONTEXT_LATENCY is programmed with crtc_vblank_start -
>>>> crtc_vdisplay, which is ~1 when guardband matches the vblank length.
>>>> With shorter guardband this become a large window.
>>>>
>>>> To avoid misprogramming TRANS_SET_CONTEXT_LATENCY, clamp the scl value to 1
>>>> when using optimized guardband.
>>>>
>>>> Also update the VRR get config logic to set crtc_vblank_start based on
>>>> vtotal - guardband, during readback.
>>>>
>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/display/intel_display.c | 36 ++++++++++++++++----
>>>>    drivers/gpu/drm/i915/display/intel_vrr.c     |  9 ++++-
>>>>    2 files changed, 38 insertions(+), 7 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>>> index 55bea1374dc4..73aec6d4686a 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>>> @@ -2638,6 +2638,30 @@ transcoder_has_vrr(const struct intel_crtc_state *crtc_state)
>>>>    	return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
>>>>    }
>>>>    
>>>> +static int intel_set_context_latency(const struct intel_crtc_state *crtc_state,
>>>> +				     int crtc_vblank_start,
>>>> +				     int crtc_vdisplay)
>>>> +{
>>>> +	struct intel_display *display = to_intel_display(crtc_state);
>>>> +
>>>> +	/*
>>>> +	 * When VRR TG is always on and optimized guardband is used,
>>>> +	 * the pipe vblank start is based on the guardband,
>>>> +	 * TRANS_SET_CONTEXT_LATENCY cannot be used to configure it.
>>>> +	 */
>>>> +	if (intel_vrr_always_use_vrr_tg(display))
>>>> +		return clamp(crtc_vblank_start - crtc_vdisplay, 0, 1);
>>> What are you trying to achieve with this? As in what problem are you
>>> seeing with the current SCL programming?
>> In VRR TG mode with optimized guardband, the guardband is shortened and
>> vblank start is moved to match the delayed vblank position.
>>
>> The SCL value which we are currently writing as difference between
>> delayed vblank and undelayed vblank becomes quite large.
>>
>> With this large SCL, the flipline decision boundary which is given by
>> delayed vblank start and SCL lines is same as the undelayed vblank.
> Everything should match the undelayed vblank.
>
>> It seems that intel_dsb_wait_vblank_delay() (in turn
>> intel_dsb_wait_usec()) does not behave correctly within the W2 window
>> (between flipdone decision boundary and delayed vblank start).
>>
>> It seems to return prematurely. Since the push bit hasn’t cleared yet,
>> this leads to DSB poll errors.
> That doesn't make any sense. That command is supposed to simply wait
> for the specifid number of microseconds. It should not care at all
> what is happening with the scanout. If that is not the case then we
> need to write a synthetic test to reproduce it, and report the
> problem to the hardware folks.

You are right, on debugging further I noticed that intel_dsb_wait_usec() 
and intel_dsb_wait_vblank_delay() are working correctly.

Due to large SCL, the the intel_dsb_wait_vblanks() is not waiting till 
the undelayed vblank but the safe window, apparently undelayed vblank - 
SCL lines.

We are setting DSB_CHICKEN_REG bits 14-15 : which says: Wait for Vblank 
instruction will use only safe window signal from dptunit in DSB HW to 
complete the wait for vblank instruction.

I am not exactly sure if its mentioned in Bspec that safe window start = 
undelayed vblank start - SCL lines.

Observation:

For example with eDP panel VRR range 40-60 and below mode:

Mode: "2880x1800": 60 347710 2880 2928 2960 3040 1800 1803 1809 1906

Before optimization:

guardband = vblank length = 106; Undelayed vblank start =1800; Delayed 
vblank start = 1906 - 106 = 1800

SCL = 1800 - 1800 = 0

Flipline decision boundary is = 1800

After optimization:

vblank length = 106; guardband = 38; Undelayed Vblank start = 1800; 
Delayed Vblank start = 1868 (1906 - 38)

SCL = 1868 - 1800 = 68

Flipline decision boundary = 1868 - 68 = 1800

Consider lines in  intel_atomic_dsb_finish() :

  intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);                 
/* If flip is earlier than 1732 (1800 - 68) this waits till 1732.*/

                 intel_vrr_send_push(new_crtc_state->dsb_commit, 
new_crtc_state);    /* Push happens immediately*/
                 intel_dsb_wait_vblank_delay(state, 
new_crtc_state->dsb_commit);        /* Waits for duration (delayed 
vblank start - undelayed vblank start) ie. 68 lines ie. till we reach 
1732 + 68 = 1800*/
intel_vrr_check_push_sent(new_crtc_state->dsb_commit,               /* 
Push is not clear yet as delayed vblank start (1868) is not reach yet, 
we get DSB POLL error */
                                           new_crtc_state);
intel_dsb_interrupt(new_crtc_state->dsb_commit);                     /* 
DSB interrupt is fired earlier */


This explains the observation that if we call 
intel_dsb_wait_vblank_delay() twice, it reaches delayed vblank and works.

So I think we dont need to set SCL as the difference between undelayed 
vblank - delayed vblank and clamp it between 0,1.

In any case the above lines should be modified to something like:

intel_dsb_wait_vblanks()

intel_vrr_send_push()

wait for scanline in range [delayed vblank start, vmax decision 
boundary] /* To ensure we have atelast past the delayed vblank start */

wait for SCL lines /* Only for VRR case, to ensure send push is cleared */

intel_vrr_check_push_sent()

intel_dsb_interrupt(new_crtc_state->dsb_commit);


>
>> AFAIU we are not using the SCL (Set Context Latency) lines to write
>> registers via DSB.
>>
>> The evasion logic ensures we write within a separate window, making the
>> actual SCL value less critical for register programming.
>>
>> So I have clamped the SCL value to (0,1). With this after the push is
>> sent the send push bit is cleared after (0,1) lines.
>>
>> But we still need to wait for the delayed vblank. For this we need
>> either intel_dsb_wait_vblank_delay() or dsb_wait_for_scanline_in().
>>
>>
>> Do you have any ideas, what could have been going wrong or if anything
>> we might have been missing?
> Was your crtc_vblank_start even correct (== undelayed vblank)
> when you were testing that?

I think the new crtc_vblank_start should be equal to the delayed vblank.

So we get guardband = Vmin Vtotal (=Flipline Vtotal) - crtc_vblank_start 
as mentioned in below lines which I am not changing now.

                 crtc_state->vrr.guardband =
                         crtc_state->vrr.vmin - 
adjusted_mode->crtc_vblank_start;


Regards,

Ankit

>

Re: [PATCH 11/15] drm/i915/display: Use vrr.guardband to derive vblank_start

[Nautiyal, Ankit K]

On 9/16/2025 8:00 PM, Nautiyal, Ankit K wrote:
>
> On 9/15/2025 6:02 PM, Ville Syrjälä wrote:
>> On Sun, Sep 14, 2025 at 11:29:10AM +0530, Nautiyal, Ankit K wrote:
>>> On 9/11/2025 7:55 PM, Ville Syrjälä wrote:
>>>> On Thu, Sep 11, 2025 at 08:15:50AM +0530, Ankit Nautiyal wrote:
>>>>> When VRR TG is always enabled and an optimized guardband is used, 
>>>>> the pipe
>>>>> vblank start is derived from the guardband.
>>>>> Currently TRANS_SET_CONTEXT_LATENCY is programmed with 
>>>>> crtc_vblank_start -
>>>>> crtc_vdisplay, which is ~1 when guardband matches the vblank length.
>>>>> With shorter guardband this become a large window.
>>>>>
>>>>> To avoid misprogramming TRANS_SET_CONTEXT_LATENCY, clamp the scl 
>>>>> value to 1
>>>>> when using optimized guardband.
>>>>>
>>>>> Also update the VRR get config logic to set crtc_vblank_start 
>>>>> based on
>>>>> vtotal - guardband, during readback.
>>>>>
>>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>>> ---
>>>>>    drivers/gpu/drm/i915/display/intel_display.c | 36 
>>>>> ++++++++++++++++----
>>>>>    drivers/gpu/drm/i915/display/intel_vrr.c     |  9 ++++-
>>>>>    2 files changed, 38 insertions(+), 7 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
>>>>> b/drivers/gpu/drm/i915/display/intel_display.c
>>>>> index 55bea1374dc4..73aec6d4686a 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>>>> @@ -2638,6 +2638,30 @@ transcoder_has_vrr(const struct 
>>>>> intel_crtc_state *crtc_state)
>>>>>        return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
>>>>>    }
>>>>>    +static int intel_set_context_latency(const struct 
>>>>> intel_crtc_state *crtc_state,
>>>>> +                     int crtc_vblank_start,
>>>>> +                     int crtc_vdisplay)
>>>>> +{
>>>>> +    struct intel_display *display = to_intel_display(crtc_state);
>>>>> +
>>>>> +    /*
>>>>> +     * When VRR TG is always on and optimized guardband is used,
>>>>> +     * the pipe vblank start is based on the guardband,
>>>>> +     * TRANS_SET_CONTEXT_LATENCY cannot be used to configure it.
>>>>> +     */
>>>>> +    if (intel_vrr_always_use_vrr_tg(display))
>>>>> +        return clamp(crtc_vblank_start - crtc_vdisplay, 0, 1);
>>>> What are you trying to achieve with this? As in what problem are you
>>>> seeing with the current SCL programming?
>>> In VRR TG mode with optimized guardband, the guardband is shortened and
>>> vblank start is moved to match the delayed vblank position.
>>>
>>> The SCL value which we are currently writing as difference between
>>> delayed vblank and undelayed vblank becomes quite large.
>>>
>>> With this large SCL, the flipline decision boundary which is given by
>>> delayed vblank start and SCL lines is same as the undelayed vblank.
>> Everything should match the undelayed vblank.
>>
>>> It seems that intel_dsb_wait_vblank_delay() (in turn
>>> intel_dsb_wait_usec()) does not behave correctly within the W2 window
>>> (between flipdone decision boundary and delayed vblank start).
>>>
>>> It seems to return prematurely. Since the push bit hasn’t cleared yet,
>>> this leads to DSB poll errors.
>> That doesn't make any sense. That command is supposed to simply wait
>> for the specifid number of microseconds. It should not care at all
>> what is happening with the scanout. If that is not the case then we
>> need to write a synthetic test to reproduce it, and report the
>> problem to the hardware folks.
>
> You are right, on debugging further I noticed that 
> intel_dsb_wait_usec() and intel_dsb_wait_vblank_delay() are working 
> correctly.
>
> Due to large SCL, the the intel_dsb_wait_vblanks() is not waiting till 
> the undelayed vblank but the safe window, apparently undelayed vblank 
> - SCL lines.
>
> We are setting DSB_CHICKEN_REG bits 14-15 : which says: Wait for 
> Vblank instruction will use only safe window signal from dptunit in 
> DSB HW to complete the wait for vblank instruction.
>
> I am not exactly sure if its mentioned in Bspec that safe window start 
> = undelayed vblank start - SCL lines.
>
> Observation:
>
> For example with eDP panel VRR range 40-60 and below mode:
>
> Mode: "2880x1800": 60 347710 2880 2928 2960 3040 1800 1803 1809 1906
>
> Before optimization:
>
> guardband = vblank length = 106; Undelayed vblank start =1800; Delayed 
> vblank start = 1906 - 106 = 1800
>
> SCL = 1800 - 1800 = 0
>
> Flipline decision boundary is = 1800
>
> After optimization:
>
> vblank length = 106; guardband = 38; Undelayed Vblank start = 1800; 
> Delayed Vblank start = 1868 (1906 - 38)
>
> SCL = 1868 - 1800 = 68
>
> Flipline decision boundary = 1868 - 68 = 1800
>
> Consider lines in  intel_atomic_dsb_finish() :
>
>  intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);         /* If 
> flip is earlier than 1732 (1800 - 68) this waits till 1732.*/
>
>                 intel_vrr_send_push(new_crtc_state->dsb_commit, 
> new_crtc_state);    /* Push happens immediately*/
>                 intel_dsb_wait_vblank_delay(state, 
> new_crtc_state->dsb_commit);        /* Waits for duration (delayed 
> vblank start - undelayed vblank start) ie. 68 lines ie. till we reach 
> 1732 + 68 = 1800*/
> intel_vrr_check_push_sent(new_crtc_state->dsb_commit,     /* Push is 
> not clear yet as delayed vblank start (1868) is not reach yet, we get 
> DSB POLL error */
>                                           new_crtc_state);
> intel_dsb_interrupt(new_crtc_state->dsb_commit);       /* DSB 
> interrupt is fired earlier */


Sorry for the bad formatting, perhaps this will be more readable:


  intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);

/* If flip is earlier than 1732 (1800 - 68) this waits till 1732.*/


intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);

/* Push happens immediately*/


intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);

/* Waits for duration (delayed vblank start - undelayed vblank start) 
ie. 68 lines ie. till we reach 1732 + 68 = 1800*/


intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state);

/* Push is not clear yet as delayed vblank start (1868) is not reach 
yet, we get DSB POLL error */


intel_dsb_interrupt(new_crtc_state->dsb_commit);

/* DSB interrupt is fired earlier */



>
>
> This explains the observation that if we call 
> intel_dsb_wait_vblank_delay() twice, it reaches delayed vblank and works.
>
> So I think we dont need to set SCL as the difference between undelayed 
> vblank - delayed vblank and clamp it between 0,1.
>
> In any case the above lines should be modified to something like:
>
> intel_dsb_wait_vblanks()
>
> intel_vrr_send_push()
>
> wait for scanline in range [delayed vblank start, vmax decision 
> boundary] /* To ensure we have atelast past the delayed vblank start */
>
> wait for SCL lines /* Only for VRR case, to ensure send push is 
> cleared */
>
> intel_vrr_check_push_sent()
>
> intel_dsb_interrupt(new_crtc_state->dsb_commit);


intel_dsb_wait_vblanks()

intel_vrr_send_push()

wait for scanline in range [delayed vblank start, vmax decision boundary]

/* To ensure we have atelast past the delayed vblank start */

wait for SCL lines

/* Only for VRR case, to ensure send push is cleared */

intel_vrr_check_push_sent()

intel_dsb_interrupt(new_crtc_state->dsb_commit);


Regards,

Ankit

>
>
>>
>>> AFAIU we are not using the SCL (Set Context Latency) lines to write
>>> registers via DSB.
>>>
>>> The evasion logic ensures we write within a separate window, making the
>>> actual SCL value less critical for register programming.
>>>
>>> So I have clamped the SCL value to (0,1). With this after the push is
>>> sent the send push bit is cleared after (0,1) lines.
>>>
>>> But we still need to wait for the delayed vblank. For this we need
>>> either intel_dsb_wait_vblank_delay() or dsb_wait_for_scanline_in().
>>>
>>>
>>> Do you have any ideas, what could have been going wrong or if anything
>>> we might have been missing?
>> Was your crtc_vblank_start even correct (== undelayed vblank)
>> when you were testing that?
>
> I think the new crtc_vblank_start should be equal to the delayed vblank.
>
> So we get guardband = Vmin Vtotal (=Flipline Vtotal) - 
> crtc_vblank_start as mentioned in below lines which I am not changing 
> now.
>
>                 crtc_state->vrr.guardband =
>                         crtc_state->vrr.vmin - 
> adjusted_mode->crtc_vblank_start;
>
>
> Regards,
>
> Ankit
>
>>

Re: [PATCH 11/15] drm/i915/display: Use vrr.guardband to derive vblank_start

[Ville Syrjälä]

On Tue, Sep 16, 2025 at 08:08:01PM +0530, Nautiyal, Ankit K wrote:
> 
> On 9/16/2025 8:00 PM, Nautiyal, Ankit K wrote:
> >
> > On 9/15/2025 6:02 PM, Ville Syrjälä wrote:
> >> On Sun, Sep 14, 2025 at 11:29:10AM +0530, Nautiyal, Ankit K wrote:
> >>> On 9/11/2025 7:55 PM, Ville Syrjälä wrote:
> >>>> On Thu, Sep 11, 2025 at 08:15:50AM +0530, Ankit Nautiyal wrote:
> >>>>> When VRR TG is always enabled and an optimized guardband is used, 
> >>>>> the pipe
> >>>>> vblank start is derived from the guardband.
> >>>>> Currently TRANS_SET_CONTEXT_LATENCY is programmed with 
> >>>>> crtc_vblank_start -
> >>>>> crtc_vdisplay, which is ~1 when guardband matches the vblank length.
> >>>>> With shorter guardband this become a large window.
> >>>>>
> >>>>> To avoid misprogramming TRANS_SET_CONTEXT_LATENCY, clamp the scl 
> >>>>> value to 1
> >>>>> when using optimized guardband.
> >>>>>
> >>>>> Also update the VRR get config logic to set crtc_vblank_start 
> >>>>> based on
> >>>>> vtotal - guardband, during readback.
> >>>>>
> >>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >>>>> ---
> >>>>>    drivers/gpu/drm/i915/display/intel_display.c | 36 
> >>>>> ++++++++++++++++----
> >>>>>    drivers/gpu/drm/i915/display/intel_vrr.c     |  9 ++++-
> >>>>>    2 files changed, 38 insertions(+), 7 deletions(-)
> >>>>>
> >>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> >>>>> b/drivers/gpu/drm/i915/display/intel_display.c
> >>>>> index 55bea1374dc4..73aec6d4686a 100644
> >>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >>>>> @@ -2638,6 +2638,30 @@ transcoder_has_vrr(const struct 
> >>>>> intel_crtc_state *crtc_state)
> >>>>>        return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
> >>>>>    }
> >>>>>    +static int intel_set_context_latency(const struct 
> >>>>> intel_crtc_state *crtc_state,
> >>>>> +                     int crtc_vblank_start,
> >>>>> +                     int crtc_vdisplay)
> >>>>> +{
> >>>>> +    struct intel_display *display = to_intel_display(crtc_state);
> >>>>> +
> >>>>> +    /*
> >>>>> +     * When VRR TG is always on and optimized guardband is used,
> >>>>> +     * the pipe vblank start is based on the guardband,
> >>>>> +     * TRANS_SET_CONTEXT_LATENCY cannot be used to configure it.
> >>>>> +     */
> >>>>> +    if (intel_vrr_always_use_vrr_tg(display))
> >>>>> +        return clamp(crtc_vblank_start - crtc_vdisplay, 0, 1);
> >>>> What are you trying to achieve with this? As in what problem are you
> >>>> seeing with the current SCL programming?
> >>> In VRR TG mode with optimized guardband, the guardband is shortened and
> >>> vblank start is moved to match the delayed vblank position.
> >>>
> >>> The SCL value which we are currently writing as difference between
> >>> delayed vblank and undelayed vblank becomes quite large.
> >>>
> >>> With this large SCL, the flipline decision boundary which is given by
> >>> delayed vblank start and SCL lines is same as the undelayed vblank.
> >> Everything should match the undelayed vblank.
> >>
> >>> It seems that intel_dsb_wait_vblank_delay() (in turn
> >>> intel_dsb_wait_usec()) does not behave correctly within the W2 window
> >>> (between flipdone decision boundary and delayed vblank start).
> >>>
> >>> It seems to return prematurely. Since the push bit hasn’t cleared yet,
> >>> this leads to DSB poll errors.
> >> That doesn't make any sense. That command is supposed to simply wait
> >> for the specifid number of microseconds. It should not care at all
> >> what is happening with the scanout. If that is not the case then we
> >> need to write a synthetic test to reproduce it, and report the
> >> problem to the hardware folks.
> >
> > You are right, on debugging further I noticed that 
> > intel_dsb_wait_usec() and intel_dsb_wait_vblank_delay() are working 
> > correctly.
> >
> > Due to large SCL, the the intel_dsb_wait_vblanks() is not waiting till 
> > the undelayed vblank but the safe window, apparently undelayed vblank 
> > - SCL lines.
> >
> > We are setting DSB_CHICKEN_REG bits 14-15 : which says: Wait for 
> > Vblank instruction will use only safe window signal from dptunit in 
> > DSB HW to complete the wait for vblank instruction.
> >
> > I am not exactly sure if its mentioned in Bspec that safe window start 
> > = undelayed vblank start - SCL lines.
> >
> > Observation:
> >
> > For example with eDP panel VRR range 40-60 and below mode:
> >
> > Mode: "2880x1800": 60 347710 2880 2928 2960 3040 1800 1803 1809 1906
> >
> > Before optimization:
> >
> > guardband = vblank length = 106; Undelayed vblank start =1800; Delayed 
> > vblank start = 1906 - 106 = 1800
> >
> > SCL = 1800 - 1800 = 0
> >
> > Flipline decision boundary is = 1800
> >
> > After optimization:
> >
> > vblank length = 106; guardband = 38; Undelayed Vblank start = 1800; 
> > Delayed Vblank start = 1868 (1906 - 38)
> >
> > SCL = 1868 - 1800 = 68
> >
> > Flipline decision boundary = 1868 - 68 = 1800
> >
> > Consider lines in  intel_atomic_dsb_finish() :
> >
> >  intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);         /* If 
> > flip is earlier than 1732 (1800 - 68) this waits till 1732.*/
> >
> >                 intel_vrr_send_push(new_crtc_state->dsb_commit, 
> > new_crtc_state);    /* Push happens immediately*/
> >                 intel_dsb_wait_vblank_delay(state, 
> > new_crtc_state->dsb_commit);        /* Waits for duration (delayed 
> > vblank start - undelayed vblank start) ie. 68 lines ie. till we reach 
> > 1732 + 68 = 1800*/
> > intel_vrr_check_push_sent(new_crtc_state->dsb_commit,     /* Push is 
> > not clear yet as delayed vblank start (1868) is not reach yet, we get 
> > DSB POLL error */
> >                                           new_crtc_state);
> > intel_dsb_interrupt(new_crtc_state->dsb_commit);       /* DSB 
> > interrupt is fired earlier */
> 
> 
> Sorry for the bad formatting, perhaps this will be more readable:
> 
> 
>   intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
> 
> /* If flip is earlier than 1732 (1800 - 68) this waits till 1732.*/

That does not seem right, or at least it's not how it works on LNL.
I just hacked some DSB_STATUS stuff into intel_display_poller [1],
and when running that on LNL the safe window always starts at the
undelayed vblank.

So if we look at the vmax case then I think the diagram should look
like this:

    udelayed vblank 
    ^               vmax decision boudnary
    |               ^           delayed vblank
    |               |           ^                 vmax
    |               |           |                 ^
    | <- stretch -> | <- scl -> | <- guardband - >|
     _______________
..._/               \______________________________... safe window

... push affects curent frame ->|<- push affects next frame ...
                                |
				v
				push send bit clears if set

And then for the maximum vrefresh case (defined by flipline instead
of vnax) the "stretch" part is something between 0 and 
delayed_vblank-undelayed_vblank, depending on how we configure SCL.

Additionally if a push is sent during the scl window just
after the vmax decisioun bondary, said push will still affect
the current frame (ie. such a frame will not have a full
scl/w2 window). Only a push sent after the delayed vblank
will in fact get deferred to the next frame. That particular
scenatio isn't really described in the bspec timing diagrams.
Though since we always precede the push with a "wait for safe
window" for us the push would get deferred to the next frame
anyway.

Now, I suppose PTL may have changed how the safe window works to 
support that "SCL during vactive" stuff. I think a bit more poking
might be needed to get to the bottom of this...

[1] https://github.com/vsyrjala/intel-gpu-tools.git dsb_status_poller

-- 
Ville Syrjälä
Intel

Re: [PATCH 11/15] drm/i915/display: Use vrr.guardband to derive vblank_start

[Nautiyal, Ankit K]

On 9/17/2025 12:26 AM, Ville Syrjälä wrote:
> On Tue, Sep 16, 2025 at 08:08:01PM +0530, Nautiyal, Ankit K wrote:
>> On 9/16/2025 8:00 PM, Nautiyal, Ankit K wrote:
>>> On 9/15/2025 6:02 PM, Ville Syrjälä wrote:
>>>> On Sun, Sep 14, 2025 at 11:29:10AM +0530, Nautiyal, Ankit K wrote:
>>>>> On 9/11/2025 7:55 PM, Ville Syrjälä wrote:
>>>>>> On Thu, Sep 11, 2025 at 08:15:50AM +0530, Ankit Nautiyal wrote:
>>>>>>> When VRR TG is always enabled and an optimized guardband is used,
>>>>>>> the pipe
>>>>>>> vblank start is derived from the guardband.
>>>>>>> Currently TRANS_SET_CONTEXT_LATENCY is programmed with
>>>>>>> crtc_vblank_start -
>>>>>>> crtc_vdisplay, which is ~1 when guardband matches the vblank length.
>>>>>>> With shorter guardband this become a large window.
>>>>>>>
>>>>>>> To avoid misprogramming TRANS_SET_CONTEXT_LATENCY, clamp the scl
>>>>>>> value to 1
>>>>>>> when using optimized guardband.
>>>>>>>
>>>>>>> Also update the VRR get config logic to set crtc_vblank_start
>>>>>>> based on
>>>>>>> vtotal - guardband, during readback.
>>>>>>>
>>>>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>>>>> ---
>>>>>>>     drivers/gpu/drm/i915/display/intel_display.c | 36
>>>>>>> ++++++++++++++++----
>>>>>>>     drivers/gpu/drm/i915/display/intel_vrr.c     |  9 ++++-
>>>>>>>     2 files changed, 38 insertions(+), 7 deletions(-)
>>>>>>>
>>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>>>>>>> b/drivers/gpu/drm/i915/display/intel_display.c
>>>>>>> index 55bea1374dc4..73aec6d4686a 100644
>>>>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>>>>>> @@ -2638,6 +2638,30 @@ transcoder_has_vrr(const struct
>>>>>>> intel_crtc_state *crtc_state)
>>>>>>>         return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
>>>>>>>     }
>>>>>>>     +static int intel_set_context_latency(const struct
>>>>>>> intel_crtc_state *crtc_state,
>>>>>>> +                     int crtc_vblank_start,
>>>>>>> +                     int crtc_vdisplay)
>>>>>>> +{
>>>>>>> +    struct intel_display *display = to_intel_display(crtc_state);
>>>>>>> +
>>>>>>> +    /*
>>>>>>> +     * When VRR TG is always on and optimized guardband is used,
>>>>>>> +     * the pipe vblank start is based on the guardband,
>>>>>>> +     * TRANS_SET_CONTEXT_LATENCY cannot be used to configure it.
>>>>>>> +     */
>>>>>>> +    if (intel_vrr_always_use_vrr_tg(display))
>>>>>>> +        return clamp(crtc_vblank_start - crtc_vdisplay, 0, 1);
>>>>>> What are you trying to achieve with this? As in what problem are you
>>>>>> seeing with the current SCL programming?
>>>>> In VRR TG mode with optimized guardband, the guardband is shortened and
>>>>> vblank start is moved to match the delayed vblank position.
>>>>>
>>>>> The SCL value which we are currently writing as difference between
>>>>> delayed vblank and undelayed vblank becomes quite large.
>>>>>
>>>>> With this large SCL, the flipline decision boundary which is given by
>>>>> delayed vblank start and SCL lines is same as the undelayed vblank.
>>>> Everything should match the undelayed vblank.
>>>>
>>>>> It seems that intel_dsb_wait_vblank_delay() (in turn
>>>>> intel_dsb_wait_usec()) does not behave correctly within the W2 window
>>>>> (between flipdone decision boundary and delayed vblank start).
>>>>>
>>>>> It seems to return prematurely. Since the push bit hasn’t cleared yet,
>>>>> this leads to DSB poll errors.
>>>> That doesn't make any sense. That command is supposed to simply wait
>>>> for the specifid number of microseconds. It should not care at all
>>>> what is happening with the scanout. If that is not the case then we
>>>> need to write a synthetic test to reproduce it, and report the
>>>> problem to the hardware folks.
>>> You are right, on debugging further I noticed that
>>> intel_dsb_wait_usec() and intel_dsb_wait_vblank_delay() are working
>>> correctly.
>>>
>>> Due to large SCL, the the intel_dsb_wait_vblanks() is not waiting till
>>> the undelayed vblank but the safe window, apparently undelayed vblank
>>> - SCL lines.
>>>
>>> We are setting DSB_CHICKEN_REG bits 14-15 : which says: Wait for
>>> Vblank instruction will use only safe window signal from dptunit in
>>> DSB HW to complete the wait for vblank instruction.
>>>
>>> I am not exactly sure if its mentioned in Bspec that safe window start
>>> = undelayed vblank start - SCL lines.
>>>
>>> Observation:
>>>
>>> For example with eDP panel VRR range 40-60 and below mode:
>>>
>>> Mode: "2880x1800": 60 347710 2880 2928 2960 3040 1800 1803 1809 1906
>>>
>>> Before optimization:
>>>
>>> guardband = vblank length = 106; Undelayed vblank start =1800; Delayed
>>> vblank start = 1906 - 106 = 1800
>>>
>>> SCL = 1800 - 1800 = 0
>>>
>>> Flipline decision boundary is = 1800
>>>
>>> After optimization:
>>>
>>> vblank length = 106; guardband = 38; Undelayed Vblank start = 1800;
>>> Delayed Vblank start = 1868 (1906 - 38)
>>>
>>> SCL = 1868 - 1800 = 68
>>>
>>> Flipline decision boundary = 1868 - 68 = 1800
>>>
>>> Consider lines in  intel_atomic_dsb_finish() :
>>>
>>>   intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);         /* If
>>> flip is earlier than 1732 (1800 - 68) this waits till 1732.*/
>>>
>>>                  intel_vrr_send_push(new_crtc_state->dsb_commit,
>>> new_crtc_state);    /* Push happens immediately*/
>>>                  intel_dsb_wait_vblank_delay(state,
>>> new_crtc_state->dsb_commit);        /* Waits for duration (delayed
>>> vblank start - undelayed vblank start) ie. 68 lines ie. till we reach
>>> 1732 + 68 = 1800*/
>>> intel_vrr_check_push_sent(new_crtc_state->dsb_commit,     /* Push is
>>> not clear yet as delayed vblank start (1868) is not reach yet, we get
>>> DSB POLL error */
>>>                                            new_crtc_state);
>>> intel_dsb_interrupt(new_crtc_state->dsb_commit);       /* DSB
>>> interrupt is fired earlier */
>>
>> Sorry for the bad formatting, perhaps this will be more readable:
>>
>>
>>    intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
>>
>> /* If flip is earlier than 1732 (1800 - 68) this waits till 1732.*/
> That does not seem right, or at least it's not how it works on LNL.
> I just hacked some DSB_STATUS stuff into intel_display_poller [1],
> and when running that on LNL the safe window always starts at the
> undelayed vblank.
>
> So if we look at the vmax case then I think the diagram should look
> like this:
>
>      udelayed vblank
>      ^               vmax decision boudnary
>      |               ^           delayed vblank
>      |               |           ^                 vmax
>      |               |           |                 ^
>      | <- stretch -> | <- scl -> | <- guardband - >|
>       _______________
> ..._/               \______________________________... safe window
>
> ... push affects curent frame ->|<- push affects next frame ...
>                                  |
> 				v
> 				push send bit clears if set
>
> And then for the maximum vrefresh case (defined by flipline instead
> of vnax) the "stretch" part is something between 0 and
> delayed_vblank-undelayed_vblank, depending on how we configure SCL.
>
> Additionally if a push is sent during the scl window just
> after the vmax decisioun bondary, said push will still affect
> the current frame (ie. such a frame will not have a full
> scl/w2 window). Only a push sent after the delayed vblank
> will in fact get deferred to the next frame. That particular
> scenatio isn't really described in the bspec timing diagrams.
> Though since we always precede the push with a "wait for safe
> window" for us the push would get deferred to the next frame
> anyway.
>
> Now, I suppose PTL may have changed how the safe window works to
> support that "SCL during vactive" stuff. I think a bit more poking
> might be needed to get to the bottom of this...
>
> [1] https://github.com/vsyrjala/intel-gpu-tools.git dsb_status_poller

I have tried with same eDP panel with PTL and LNL.
I tried my changes where SCL was programmed to 68 in above setup.
On PTL it does take the safe window as undelayed vblank -SCL.

I also tried without my changes, but just wrote TRANS_SCL_CONTEXT as 
0x44 (68) and got the same result.
Which is similar to my observation earlier.

With set context latency as 0 : we get undelayed vblank - SCL 1800 -0 = 
1800
[0] 1798 - 1799 (1799)
….
[0] 1798 - 1799 (1799)
[0] 1798 - 1799 (1799)
[0] 1798 - 1799 (1799)
dsl / pipe A / DSB0 / DSB_STATUS[26]: [0]   1798 -   1799
dsl / pipe A / DSB0 / DSB_STATUS[26]: [1]      0 - 4294967295

With set context latency set to larger value eg. 68 (0x44) and I am 
getting the safe window start as : 1731 (which is around undelayed 
vblank  - SCL i.e. 1800 -68 -1 = 1732)
[0] 1730 - 1731 (1731)
….
[0] 1730 - 1731 (1731)
[0] 1730 - 1731 (1731)
[0] 1730 - 1731 (1731)
dsl / pipe A / DSB0 / DSB_STATUS[26]: [0]   1730 -   1731
dsl / pipe A / DSB0 / DSB_STATUS[26]: [1]      0 - 4294967295


For LNL:
With set context latency as 0: we get:
[0] 1798 - 1799 (1799)
[0] 1798 - 1799 (1799)
[0] 1798 - 1799 (1799)
[0] 1798 - 1799 (1799)
[0] 1798 - 1799 (1799)
dsl / pipe A / DSB0 / DSB_STATUS[26]: [0]   1798 -   1799
dsl / pipe A / DSB0 / DSB_STATUS[26]: [1]      0 - 4294967295

But with set context latency as 68 (0x44):we get:
[0] 1798 - 1799 (1799)
[0] 1866 - 1867 (1867)
[0] 1798 - 1799 (1799)

[0] 1798 - 1799 (1799)
…
[0] 1866 - 1867 (1867)
[0] 1866 - 1867 (1867)
[0] 1866 - 1867 (1867)
[0] 1798 - 1799 (1799)
[0] 1866 - 1867 (1867)
[0] 1866 - 1867 (1867)
[0] 1866 - 1867 (1867)
[0] 1866 - 1867 (1867)
[0] 1866 - 1867 (1867)
dsl / pipe A / DSB0 / DSB_STATUS[26]: [0]   1866 -   1799
dsl / pipe A / DSB0 / DSB_STATUS[26]: [1]      0 - 4294967295

I am not sure why for LNL I am getting 1866 though.

To sum up there is indeed a difference in safe window start based on SCL 
lines for LNL and PTL.

Regards,
Ankit


>

Re: [PATCH 11/15] drm/i915/display: Use vrr.guardband to derive vblank_start

[Ville Syrjälä]

On Tue, Sep 16, 2025 at 09:56:47PM +0300, Ville Syrjälä wrote:
> On Tue, Sep 16, 2025 at 08:08:01PM +0530, Nautiyal, Ankit K wrote:
> > 
> > On 9/16/2025 8:00 PM, Nautiyal, Ankit K wrote:
> > >
> > > On 9/15/2025 6:02 PM, Ville Syrjälä wrote:
> > >> On Sun, Sep 14, 2025 at 11:29:10AM +0530, Nautiyal, Ankit K wrote:
> > >>> On 9/11/2025 7:55 PM, Ville Syrjälä wrote:
> > >>>> On Thu, Sep 11, 2025 at 08:15:50AM +0530, Ankit Nautiyal wrote:
> > >>>>> When VRR TG is always enabled and an optimized guardband is used, 
> > >>>>> the pipe
> > >>>>> vblank start is derived from the guardband.
> > >>>>> Currently TRANS_SET_CONTEXT_LATENCY is programmed with 
> > >>>>> crtc_vblank_start -
> > >>>>> crtc_vdisplay, which is ~1 when guardband matches the vblank length.
> > >>>>> With shorter guardband this become a large window.
> > >>>>>
> > >>>>> To avoid misprogramming TRANS_SET_CONTEXT_LATENCY, clamp the scl 
> > >>>>> value to 1
> > >>>>> when using optimized guardband.
> > >>>>>
> > >>>>> Also update the VRR get config logic to set crtc_vblank_start 
> > >>>>> based on
> > >>>>> vtotal - guardband, during readback.
> > >>>>>
> > >>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > >>>>> ---
> > >>>>>    drivers/gpu/drm/i915/display/intel_display.c | 36 
> > >>>>> ++++++++++++++++----
> > >>>>>    drivers/gpu/drm/i915/display/intel_vrr.c     |  9 ++++-
> > >>>>>    2 files changed, 38 insertions(+), 7 deletions(-)
> > >>>>>
> > >>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> > >>>>> b/drivers/gpu/drm/i915/display/intel_display.c
> > >>>>> index 55bea1374dc4..73aec6d4686a 100644
> > >>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
> > >>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > >>>>> @@ -2638,6 +2638,30 @@ transcoder_has_vrr(const struct 
> > >>>>> intel_crtc_state *crtc_state)
> > >>>>>        return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
> > >>>>>    }
> > >>>>>    +static int intel_set_context_latency(const struct 
> > >>>>> intel_crtc_state *crtc_state,
> > >>>>> +                     int crtc_vblank_start,
> > >>>>> +                     int crtc_vdisplay)
> > >>>>> +{
> > >>>>> +    struct intel_display *display = to_intel_display(crtc_state);
> > >>>>> +
> > >>>>> +    /*
> > >>>>> +     * When VRR TG is always on and optimized guardband is used,
> > >>>>> +     * the pipe vblank start is based on the guardband,
> > >>>>> +     * TRANS_SET_CONTEXT_LATENCY cannot be used to configure it.
> > >>>>> +     */
> > >>>>> +    if (intel_vrr_always_use_vrr_tg(display))
> > >>>>> +        return clamp(crtc_vblank_start - crtc_vdisplay, 0, 1);
> > >>>> What are you trying to achieve with this? As in what problem are you
> > >>>> seeing with the current SCL programming?
> > >>> In VRR TG mode with optimized guardband, the guardband is shortened and
> > >>> vblank start is moved to match the delayed vblank position.
> > >>>
> > >>> The SCL value which we are currently writing as difference between
> > >>> delayed vblank and undelayed vblank becomes quite large.
> > >>>
> > >>> With this large SCL, the flipline decision boundary which is given by
> > >>> delayed vblank start and SCL lines is same as the undelayed vblank.
> > >> Everything should match the undelayed vblank.
> > >>
> > >>> It seems that intel_dsb_wait_vblank_delay() (in turn
> > >>> intel_dsb_wait_usec()) does not behave correctly within the W2 window
> > >>> (between flipdone decision boundary and delayed vblank start).
> > >>>
> > >>> It seems to return prematurely. Since the push bit hasn’t cleared yet,
> > >>> this leads to DSB poll errors.
> > >> That doesn't make any sense. That command is supposed to simply wait
> > >> for the specifid number of microseconds. It should not care at all
> > >> what is happening with the scanout. If that is not the case then we
> > >> need to write a synthetic test to reproduce it, and report the
> > >> problem to the hardware folks.
> > >
> > > You are right, on debugging further I noticed that 
> > > intel_dsb_wait_usec() and intel_dsb_wait_vblank_delay() are working 
> > > correctly.
> > >
> > > Due to large SCL, the the intel_dsb_wait_vblanks() is not waiting till 
> > > the undelayed vblank but the safe window, apparently undelayed vblank 
> > > - SCL lines.
> > >
> > > We are setting DSB_CHICKEN_REG bits 14-15 : which says: Wait for 
> > > Vblank instruction will use only safe window signal from dptunit in 
> > > DSB HW to complete the wait for vblank instruction.
> > >
> > > I am not exactly sure if its mentioned in Bspec that safe window start 
> > > = undelayed vblank start - SCL lines.
> > >
> > > Observation:
> > >
> > > For example with eDP panel VRR range 40-60 and below mode:
> > >
> > > Mode: "2880x1800": 60 347710 2880 2928 2960 3040 1800 1803 1809 1906
> > >
> > > Before optimization:
> > >
> > > guardband = vblank length = 106; Undelayed vblank start =1800; Delayed 
> > > vblank start = 1906 - 106 = 1800
> > >
> > > SCL = 1800 - 1800 = 0
> > >
> > > Flipline decision boundary is = 1800
> > >
> > > After optimization:
> > >
> > > vblank length = 106; guardband = 38; Undelayed Vblank start = 1800; 
> > > Delayed Vblank start = 1868 (1906 - 38)
> > >
> > > SCL = 1868 - 1800 = 68
> > >
> > > Flipline decision boundary = 1868 - 68 = 1800
> > >
> > > Consider lines in  intel_atomic_dsb_finish() :
> > >
> > >  intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);         /* If 
> > > flip is earlier than 1732 (1800 - 68) this waits till 1732.*/
> > >
> > >                 intel_vrr_send_push(new_crtc_state->dsb_commit, 
> > > new_crtc_state);    /* Push happens immediately*/
> > >                 intel_dsb_wait_vblank_delay(state, 
> > > new_crtc_state->dsb_commit);        /* Waits for duration (delayed 
> > > vblank start - undelayed vblank start) ie. 68 lines ie. till we reach 
> > > 1732 + 68 = 1800*/
> > > intel_vrr_check_push_sent(new_crtc_state->dsb_commit,     /* Push is 
> > > not clear yet as delayed vblank start (1868) is not reach yet, we get 
> > > DSB POLL error */
> > >                                           new_crtc_state);
> > > intel_dsb_interrupt(new_crtc_state->dsb_commit);       /* DSB 
> > > interrupt is fired earlier */
> > 
> > 
> > Sorry for the bad formatting, perhaps this will be more readable:
> > 
> > 
> >   intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
> > 
> > /* If flip is earlier than 1732 (1800 - 68) this waits till 1732.*/
> 
> That does not seem right, or at least it's not how it works on LNL.
> I just hacked some DSB_STATUS stuff into intel_display_poller [1],
> and when running that on LNL the safe window always starts at the
> undelayed vblank.
> 
> So if we look at the vmax case then I think the diagram should look
> like this:
> 
>     udelayed vblank 
>     ^               vmax decision boudnary
>     |               ^           delayed vblank
>     |               |           ^                 vmax
>     |               |           |                 ^
>     | <- stretch -> | <- scl -> | <- guardband - >|
>      _______________
> ..._/               \______________________________... safe window
> 
> ... push affects curent frame ->|<- push affects next frame ...
>                                 |
> 				v
> 				push send bit clears if set
> 
> And then for the maximum vrefresh case (defined by flipline instead
> of vnax) the "stretch" part is something between 0 and 
> delayed_vblank-undelayed_vblank, depending on how we configure SCL.
> 
> Additionally if a push is sent during the scl window just
> after the vmax decisioun bondary, said push will still affect
> the current frame (ie. such a frame will not have a full
> scl/w2 window). Only a push sent after the delayed vblank
> will in fact get deferred to the next frame. That particular
> scenatio isn't really described in the bspec timing diagrams.
> Though since we always precede the push with a "wait for safe
> window" for us the push would get deferred to the next frame
> anyway.

Hmm, now that I think about this I think we might have to go with your
"minimize SCL" approach after all. The problem being that our vblank
evasion code only evades the undelayed vblank (and a bit before it).
But with a large SCL the safe window prior to the vmax decision boundary
may have already ended long before we're even close to crashing into the
undelayed vblank. Thus we will write all the double buffered registers,
and they will latch at the vmax undelayed vblank, but the push will
get deferred into the next frame due to the "wait for safe window".

I suppose we should really have our vblank evasion code extend the
evasion scanline window backwards to also cover the SCL.

I think what we probably need to do is start tracking the scl
explicitly in the crtc state. And then we'll have to set things up
in slightly different ways depending on which hw is used:
 pre-tgl: scl=0, vblank_delay=0
 tgl: scl=0, vblank_delay configured via VBLANK_START
 adl+ legacy tg: scl=vblank_delay
 adl+ vrr tg: scl=whatever(0-vblank_delay), vblank_delay configured via guardband

Hmm, or maybe we need to also pretend that tgl has scl since after
a push we need to wait for the scl window to pass, but since tgl
doesn't have one maybe there we need to actually wait for the vblank
delay. I think I'll need to poke at a tgl a bit more here to
figure out exactly how the safe window works there...

-- 
Ville Syrjälä
Intel

RE: [PATCH 11/15] drm/i915/display: Use vrr.guardband to derive vblank_start

[Shankar, Uma]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjälä
> Sent: Wednesday, September 17, 2025 4:21 PM
> To: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH 11/15] drm/i915/display: Use vrr.guardband to derive
> vblank_start
> 
> On Tue, Sep 16, 2025 at 09:56:47PM +0300, Ville Syrjälä wrote:
> > On Tue, Sep 16, 2025 at 08:08:01PM +0530, Nautiyal, Ankit K wrote:
> > >
> > > On 9/16/2025 8:00 PM, Nautiyal, Ankit K wrote:
> > > >
> > > > On 9/15/2025 6:02 PM, Ville Syrjälä wrote:
> > > >> On Sun, Sep 14, 2025 at 11:29:10AM +0530, Nautiyal, Ankit K wrote:
> > > >>> On 9/11/2025 7:55 PM, Ville Syrjälä wrote:
> > > >>>> On Thu, Sep 11, 2025 at 08:15:50AM +0530, Ankit Nautiyal wrote:
> > > >>>>> When VRR TG is always enabled and an optimized guardband is
> > > >>>>> used, the pipe vblank start is derived from the guardband.
> > > >>>>> Currently TRANS_SET_CONTEXT_LATENCY is programmed with
> > > >>>>> crtc_vblank_start - crtc_vdisplay, which is ~1 when guardband
> > > >>>>> matches the vblank length.
> > > >>>>> With shorter guardband this become a large window.
> > > >>>>>
> > > >>>>> To avoid misprogramming TRANS_SET_CONTEXT_LATENCY, clamp
> the
> > > >>>>> scl value to 1 when using optimized guardband.
> > > >>>>>
> > > >>>>> Also update the VRR get config logic to set crtc_vblank_start
> > > >>>>> based on vtotal - guardband, during readback.
> > > >>>>>
> > > >>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > >>>>> ---
> > > >>>>>    drivers/gpu/drm/i915/display/intel_display.c | 36
> > > >>>>> ++++++++++++++++----
> > > >>>>>    drivers/gpu/drm/i915/display/intel_vrr.c     |  9 ++++-
> > > >>>>>    2 files changed, 38 insertions(+), 7 deletions(-)
> > > >>>>>
> > > >>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > >>>>> b/drivers/gpu/drm/i915/display/intel_display.c
> > > >>>>> index 55bea1374dc4..73aec6d4686a 100644
> > > >>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > >>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > >>>>> @@ -2638,6 +2638,30 @@ transcoder_has_vrr(const struct
> > > >>>>> intel_crtc_state *crtc_state)
> > > >>>>>        return HAS_VRR(display) &&
> > > >>>>> !transcoder_is_dsi(cpu_transcoder);
> > > >>>>>    }
> > > >>>>>    +static int intel_set_context_latency(const struct
> > > >>>>> intel_crtc_state *crtc_state,
> > > >>>>> +                     int crtc_vblank_start,
> > > >>>>> +                     int crtc_vdisplay) {
> > > >>>>> +    struct intel_display *display =
> > > >>>>> +to_intel_display(crtc_state);
> > > >>>>> +
> > > >>>>> +    /*
> > > >>>>> +     * When VRR TG is always on and optimized guardband is
> > > >>>>> +used,
> > > >>>>> +     * the pipe vblank start is based on the guardband,
> > > >>>>> +     * TRANS_SET_CONTEXT_LATENCY cannot be used to configure
> it.
> > > >>>>> +     */
> > > >>>>> +    if (intel_vrr_always_use_vrr_tg(display))
> > > >>>>> +        return clamp(crtc_vblank_start - crtc_vdisplay, 0,
> > > >>>>> +1);
> > > >>>> What are you trying to achieve with this? As in what problem
> > > >>>> are you seeing with the current SCL programming?
> > > >>> In VRR TG mode with optimized guardband, the guardband is
> > > >>> shortened and vblank start is moved to match the delayed vblank
> position.
> > > >>>
> > > >>> The SCL value which we are currently writing as difference
> > > >>> between delayed vblank and undelayed vblank becomes quite large.
> > > >>>
> > > >>> With this large SCL, the flipline decision boundary which is
> > > >>> given by delayed vblank start and SCL lines is same as the undelayed
> vblank.
> > > >> Everything should match the undelayed vblank.
> > > >>
> > > >>> It seems that intel_dsb_wait_vblank_delay() (in turn
> > > >>> intel_dsb_wait_usec()) does not behave correctly within the W2
> > > >>> window (between flipdone decision boundary and delayed vblank start).
> > > >>>
> > > >>> It seems to return prematurely. Since the push bit hasn’t
> > > >>> cleared yet, this leads to DSB poll errors.
> > > >> That doesn't make any sense. That command is supposed to simply
> > > >> wait for the specifid number of microseconds. It should not care
> > > >> at all what is happening with the scanout. If that is not the
> > > >> case then we need to write a synthetic test to reproduce it, and
> > > >> report the problem to the hardware folks.
> > > >
> > > > You are right, on debugging further I noticed that
> > > > intel_dsb_wait_usec() and intel_dsb_wait_vblank_delay() are
> > > > working correctly.
> > > >
> > > > Due to large SCL, the the intel_dsb_wait_vblanks() is not waiting
> > > > till the undelayed vblank but the safe window, apparently
> > > > undelayed vblank
> > > > - SCL lines.
> > > >
> > > > We are setting DSB_CHICKEN_REG bits 14-15 : which says: Wait for
> > > > Vblank instruction will use only safe window signal from dptunit
> > > > in DSB HW to complete the wait for vblank instruction.
> > > >
> > > > I am not exactly sure if its mentioned in Bspec that safe window
> > > > start = undelayed vblank start - SCL lines.
> > > >
> > > > Observation:
> > > >
> > > > For example with eDP panel VRR range 40-60 and below mode:
> > > >
> > > > Mode: "2880x1800": 60 347710 2880 2928 2960 3040 1800 1803 1809
> > > > 1906
> > > >
> > > > Before optimization:
> > > >
> > > > guardband = vblank length = 106; Undelayed vblank start =1800;
> > > > Delayed vblank start = 1906 - 106 = 1800
> > > >
> > > > SCL = 1800 - 1800 = 0
> > > >
> > > > Flipline decision boundary is = 1800
> > > >
> > > > After optimization:
> > > >
> > > > vblank length = 106; guardband = 38; Undelayed Vblank start =
> > > > 1800; Delayed Vblank start = 1868 (1906 - 38)
> > > >
> > > > SCL = 1868 - 1800 = 68
> > > >
> > > > Flipline decision boundary = 1868 - 68 = 1800
> > > >
> > > > Consider lines in  intel_atomic_dsb_finish() :
> > > >
> > > >  intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);         /*
> > > > If flip is earlier than 1732 (1800 - 68) this waits till 1732.*/
> > > >
> > > >                 intel_vrr_send_push(new_crtc_state->dsb_commit,
> > > > new_crtc_state);    /* Push happens immediately*/
> > > >                 intel_dsb_wait_vblank_delay(state,
> > > > new_crtc_state->dsb_commit);        /* Waits for duration (delayed
> > > > vblank start - undelayed vblank start) ie. 68 lines ie. till we
> > > > reach
> > > > 1732 + 68 = 1800*/
> > > > intel_vrr_check_push_sent(new_crtc_state->dsb_commit,     /* Push
> > > > is not clear yet as delayed vblank start (1868) is not reach yet,
> > > > we get DSB POLL error */
> > > >                                           new_crtc_state);
> > > > intel_dsb_interrupt(new_crtc_state->dsb_commit);       /* DSB
> > > > interrupt is fired earlier */
> > >
> > >
> > > Sorry for the bad formatting, perhaps this will be more readable:
> > >
> > >
> > >   intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
> > >
> > > /* If flip is earlier than 1732 (1800 - 68) this waits till 1732.*/
> >
> > That does not seem right, or at least it's not how it works on LNL.
> > I just hacked some DSB_STATUS stuff into intel_display_poller [1], and
> > when running that on LNL the safe window always starts at the
> > undelayed vblank.
> >
> > So if we look at the vmax case then I think the diagram should look
> > like this:
> >
> >     udelayed vblank
> >     ^               vmax decision boudnary
> >     |               ^           delayed vblank
> >     |               |           ^                 vmax
> >     |               |           |                 ^
> >     | <- stretch -> | <- scl -> | <- guardband - >|
> >      _______________
> > ..._/               \______________________________... safe window
> >
> > ... push affects curent frame ->|<- push affects next frame ...
> >                                 |
> > 				v
> > 				push send bit clears if set
> >
> > And then for the maximum vrefresh case (defined by flipline instead of
> > vnax) the "stretch" part is something between 0 and
> > delayed_vblank-undelayed_vblank, depending on how we configure SCL.
> >
> > Additionally if a push is sent during the scl window just after the
> > vmax decisioun bondary, said push will still affect the current frame
> > (ie. such a frame will not have a full
> > scl/w2 window). Only a push sent after the delayed vblank will in fact
> > get deferred to the next frame. That particular scenatio isn't really
> > described in the bspec timing diagrams.
> > Though since we always precede the push with a "wait for safe window"
> > for us the push would get deferred to the next frame anyway.
> 
> Hmm, now that I think about this I think we might have to go with your "minimize
> SCL" approach after all. The problem being that our vblank evasion code only
> evades the undelayed vblank (and a bit before it).
> But with a large SCL the safe window prior to the vmax decision boundary may
> have already ended long before we're even close to crashing into the undelayed
> vblank. Thus we will write all the double buffered registers, and they will latch at
> the vmax undelayed vblank, but the push will get deferred into the next frame due
> to the "wait for safe window".
> 
> I suppose we should really have our vblank evasion code extend the evasion
> scanline window backwards to also cover the SCL.
> 

I think we can make crtc_vblank_start = delayed_vblank (decided by guardband), 
SCL as 1 (or 0 based on platforms),  vblank_delay = SCL.
evade for crtc_vblank_start - SCL - latency
Also to decide the wait for reaching delayed_vblank, we can use the DSB scanline_in_range function.

For pre-ptl platforms, guardband=vblank_length, so above should hold for those usecases as well I think.

Regards,
Uma Shankar

> I think what we probably need to do is start tracking the scl explicitly in the crtc
> state. And then we'll have to set things up in slightly different ways depending on
> which hw is used:
>  pre-tgl: scl=0, vblank_delay=0
>  tgl: scl=0, vblank_delay configured via VBLANK_START  adl+ legacy tg:
> scl=vblank_delay  adl+ vrr tg: scl=whatever(0-vblank_delay), vblank_delay
> configured via guardband
> 
> Hmm, or maybe we need to also pretend that tgl has scl since after a push we
> need to wait for the scl window to pass, but since tgl doesn't have one maybe
> there we need to actually wait for the vblank delay. I think I'll need to poke at a tgl
> a bit more here to figure out exactly how the safe window works there...
> 
> --
> Ville Syrjälä
> Intel

Re: [PATCH 11/15] drm/i915/display: Use vrr.guardband to derive vblank_start

[Ville Syrjälä]

On Wed, Sep 17, 2025 at 04:08:39PM +0530, Nautiyal, Ankit K wrote:
> 
> On 9/17/2025 12:26 AM, Ville Syrjälä wrote:
> > On Tue, Sep 16, 2025 at 08:08:01PM +0530, Nautiyal, Ankit K wrote:
> >> On 9/16/2025 8:00 PM, Nautiyal, Ankit K wrote:
> >>> On 9/15/2025 6:02 PM, Ville Syrjälä wrote:
> >>>> On Sun, Sep 14, 2025 at 11:29:10AM +0530, Nautiyal, Ankit K wrote:
> >>>>> On 9/11/2025 7:55 PM, Ville Syrjälä wrote:
> >>>>>> On Thu, Sep 11, 2025 at 08:15:50AM +0530, Ankit Nautiyal wrote:
> >>>>>>> When VRR TG is always enabled and an optimized guardband is used,
> >>>>>>> the pipe
> >>>>>>> vblank start is derived from the guardband.
> >>>>>>> Currently TRANS_SET_CONTEXT_LATENCY is programmed with
> >>>>>>> crtc_vblank_start -
> >>>>>>> crtc_vdisplay, which is ~1 when guardband matches the vblank length.
> >>>>>>> With shorter guardband this become a large window.
> >>>>>>>
> >>>>>>> To avoid misprogramming TRANS_SET_CONTEXT_LATENCY, clamp the scl
> >>>>>>> value to 1
> >>>>>>> when using optimized guardband.
> >>>>>>>
> >>>>>>> Also update the VRR get config logic to set crtc_vblank_start
> >>>>>>> based on
> >>>>>>> vtotal - guardband, during readback.
> >>>>>>>
> >>>>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >>>>>>> ---
> >>>>>>>     drivers/gpu/drm/i915/display/intel_display.c | 36
> >>>>>>> ++++++++++++++++----
> >>>>>>>     drivers/gpu/drm/i915/display/intel_vrr.c     |  9 ++++-
> >>>>>>>     2 files changed, 38 insertions(+), 7 deletions(-)
> >>>>>>>
> >>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> >>>>>>> b/drivers/gpu/drm/i915/display/intel_display.c
> >>>>>>> index 55bea1374dc4..73aec6d4686a 100644
> >>>>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >>>>>>> @@ -2638,6 +2638,30 @@ transcoder_has_vrr(const struct
> >>>>>>> intel_crtc_state *crtc_state)
> >>>>>>>         return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
> >>>>>>>     }
> >>>>>>>     +static int intel_set_context_latency(const struct
> >>>>>>> intel_crtc_state *crtc_state,
> >>>>>>> +                     int crtc_vblank_start,
> >>>>>>> +                     int crtc_vdisplay)
> >>>>>>> +{
> >>>>>>> +    struct intel_display *display = to_intel_display(crtc_state);
> >>>>>>> +
> >>>>>>> +    /*
> >>>>>>> +     * When VRR TG is always on and optimized guardband is used,
> >>>>>>> +     * the pipe vblank start is based on the guardband,
> >>>>>>> +     * TRANS_SET_CONTEXT_LATENCY cannot be used to configure it.
> >>>>>>> +     */
> >>>>>>> +    if (intel_vrr_always_use_vrr_tg(display))
> >>>>>>> +        return clamp(crtc_vblank_start - crtc_vdisplay, 0, 1);
> >>>>>> What are you trying to achieve with this? As in what problem are you
> >>>>>> seeing with the current SCL programming?
> >>>>> In VRR TG mode with optimized guardband, the guardband is shortened and
> >>>>> vblank start is moved to match the delayed vblank position.
> >>>>>
> >>>>> The SCL value which we are currently writing as difference between
> >>>>> delayed vblank and undelayed vblank becomes quite large.
> >>>>>
> >>>>> With this large SCL, the flipline decision boundary which is given by
> >>>>> delayed vblank start and SCL lines is same as the undelayed vblank.
> >>>> Everything should match the undelayed vblank.
> >>>>
> >>>>> It seems that intel_dsb_wait_vblank_delay() (in turn
> >>>>> intel_dsb_wait_usec()) does not behave correctly within the W2 window
> >>>>> (between flipdone decision boundary and delayed vblank start).
> >>>>>
> >>>>> It seems to return prematurely. Since the push bit hasn’t cleared yet,
> >>>>> this leads to DSB poll errors.
> >>>> That doesn't make any sense. That command is supposed to simply wait
> >>>> for the specifid number of microseconds. It should not care at all
> >>>> what is happening with the scanout. If that is not the case then we
> >>>> need to write a synthetic test to reproduce it, and report the
> >>>> problem to the hardware folks.
> >>> You are right, on debugging further I noticed that
> >>> intel_dsb_wait_usec() and intel_dsb_wait_vblank_delay() are working
> >>> correctly.
> >>>
> >>> Due to large SCL, the the intel_dsb_wait_vblanks() is not waiting till
> >>> the undelayed vblank but the safe window, apparently undelayed vblank
> >>> - SCL lines.
> >>>
> >>> We are setting DSB_CHICKEN_REG bits 14-15 : which says: Wait for
> >>> Vblank instruction will use only safe window signal from dptunit in
> >>> DSB HW to complete the wait for vblank instruction.
> >>>
> >>> I am not exactly sure if its mentioned in Bspec that safe window start
> >>> = undelayed vblank start - SCL lines.
> >>>
> >>> Observation:
> >>>
> >>> For example with eDP panel VRR range 40-60 and below mode:
> >>>
> >>> Mode: "2880x1800": 60 347710 2880 2928 2960 3040 1800 1803 1809 1906
> >>>
> >>> Before optimization:
> >>>
> >>> guardband = vblank length = 106; Undelayed vblank start =1800; Delayed
> >>> vblank start = 1906 - 106 = 1800
> >>>
> >>> SCL = 1800 - 1800 = 0
> >>>
> >>> Flipline decision boundary is = 1800
> >>>
> >>> After optimization:
> >>>
> >>> vblank length = 106; guardband = 38; Undelayed Vblank start = 1800;
> >>> Delayed Vblank start = 1868 (1906 - 38)
> >>>
> >>> SCL = 1868 - 1800 = 68
> >>>
> >>> Flipline decision boundary = 1868 - 68 = 1800
> >>>
> >>> Consider lines in  intel_atomic_dsb_finish() :
> >>>
> >>>   intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);         /* If
> >>> flip is earlier than 1732 (1800 - 68) this waits till 1732.*/
> >>>
> >>>                  intel_vrr_send_push(new_crtc_state->dsb_commit,
> >>> new_crtc_state);    /* Push happens immediately*/
> >>>                  intel_dsb_wait_vblank_delay(state,
> >>> new_crtc_state->dsb_commit);        /* Waits for duration (delayed
> >>> vblank start - undelayed vblank start) ie. 68 lines ie. till we reach
> >>> 1732 + 68 = 1800*/
> >>> intel_vrr_check_push_sent(new_crtc_state->dsb_commit,     /* Push is
> >>> not clear yet as delayed vblank start (1868) is not reach yet, we get
> >>> DSB POLL error */
> >>>                                            new_crtc_state);
> >>> intel_dsb_interrupt(new_crtc_state->dsb_commit);       /* DSB
> >>> interrupt is fired earlier */
> >>
> >> Sorry for the bad formatting, perhaps this will be more readable:
> >>
> >>
> >>    intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
> >>
> >> /* If flip is earlier than 1732 (1800 - 68) this waits till 1732.*/
> > That does not seem right, or at least it's not how it works on LNL.
> > I just hacked some DSB_STATUS stuff into intel_display_poller [1],
> > and when running that on LNL the safe window always starts at the
> > undelayed vblank.
> >
> > So if we look at the vmax case then I think the diagram should look
> > like this:
> >
> >      udelayed vblank
> >      ^               vmax decision boudnary
> >      |               ^           delayed vblank
> >      |               |           ^                 vmax
> >      |               |           |                 ^
> >      | <- stretch -> | <- scl -> | <- guardband - >|
> >       _______________
> > ..._/               \______________________________... safe window
> >
> > ... push affects curent frame ->|<- push affects next frame ...
> >                                  |
> > 				v
> > 				push send bit clears if set
> >
> > And then for the maximum vrefresh case (defined by flipline instead
> > of vnax) the "stretch" part is something between 0 and
> > delayed_vblank-undelayed_vblank, depending on how we configure SCL.
> >
> > Additionally if a push is sent during the scl window just
> > after the vmax decisioun bondary, said push will still affect
> > the current frame (ie. such a frame will not have a full
> > scl/w2 window). Only a push sent after the delayed vblank
> > will in fact get deferred to the next frame. That particular
> > scenatio isn't really described in the bspec timing diagrams.
> > Though since we always precede the push with a "wait for safe
> > window" for us the push would get deferred to the next frame
> > anyway.
> >
> > Now, I suppose PTL may have changed how the safe window works to
> > support that "SCL during vactive" stuff. I think a bit more poking
> > might be needed to get to the bottom of this...
> >
> > [1] https://github.com/vsyrjala/intel-gpu-tools.git dsb_status_poller
> 
> I have tried with same eDP panel with PTL and LNL.
> I tried my changes where SCL was programmed to 68 in above setup.
> On PTL it does take the safe window as undelayed vblank -SCL.
> 
> I also tried without my changes, but just wrote TRANS_SCL_CONTEXT as 
> 0x44 (68) and got the same result.
> Which is similar to my observation earlier.
> 
> With set context latency as 0 : we get undelayed vblank - SCL 1800 -0 = 
> 1800
> [0] 1798 - 1799 (1799)
> ….
> [0] 1798 - 1799 (1799)
> [0] 1798 - 1799 (1799)
> [0] 1798 - 1799 (1799)
> dsl / pipe A / DSB0 / DSB_STATUS[26]: [0]   1798 -   1799
> dsl / pipe A / DSB0 / DSB_STATUS[26]: [1]      0 - 4294967295
> 
> With set context latency set to larger value eg. 68 (0x44) and I am 
> getting the safe window start as : 1731 (which is around undelayed 
> vblank  - SCL i.e. 1800 -68 -1 = 1732)
> [0] 1730 - 1731 (1731)
> ….
> [0] 1730 - 1731 (1731)
> [0] 1730 - 1731 (1731)
> [0] 1730 - 1731 (1731)
> dsl / pipe A / DSB0 / DSB_STATUS[26]: [0]   1730 -   1731
> dsl / pipe A / DSB0 / DSB_STATUS[26]: [1]      0 - 4294967295
> 
> 
> For LNL:
> With set context latency as 0: we get:
> [0] 1798 - 1799 (1799)
> [0] 1798 - 1799 (1799)
> [0] 1798 - 1799 (1799)
> [0] 1798 - 1799 (1799)
> [0] 1798 - 1799 (1799)
> dsl / pipe A / DSB0 / DSB_STATUS[26]: [0]   1798 -   1799
> dsl / pipe A / DSB0 / DSB_STATUS[26]: [1]      0 - 4294967295
> 
> But with set context latency as 68 (0x44):we get:
> [0] 1798 - 1799 (1799)
> [0] 1866 - 1867 (1867)
> [0] 1798 - 1799 (1799)
> 
> [0] 1798 - 1799 (1799)
> …
> [0] 1866 - 1867 (1867)
> [0] 1866 - 1867 (1867)
> [0] 1866 - 1867 (1867)
> [0] 1798 - 1799 (1799)
> [0] 1866 - 1867 (1867)
> [0] 1866 - 1867 (1867)
> [0] 1866 - 1867 (1867)
> [0] 1866 - 1867 (1867)
> [0] 1866 - 1867 (1867)
> dsl / pipe A / DSB0 / DSB_STATUS[26]: [0]   1866 -   1799
> dsl / pipe A / DSB0 / DSB_STATUS[26]: [1]      0 - 4294967295
> 
> I am not sure why for LNL I am getting 1866 though.

That does look odd. The difference is exactly that 68 lines,
but the start of the safe window should not have moved at all.
One theory might be that there is a brief pulse on the safe
window signal at end of the SCL window. But so far I've not been
able to see observe such a thing on the LNL I have here.

> To sum up there is indeed a difference in safe window start based on SCL 
> lines for LNL and PTL.

Yeah, looks like it. 

So with the SCL=vblank_delay approach we could just do a scanline
window wait just after the intel_dsb_wait_vblanks() to make sure
we're not in that SCL window just before the undelayed vblank.


                   undelayed_vblank
                   ^           delayed_vblank
                   |           ^                 vmin
                   |           |                 ^
     | <-  scl  -> | <- scl -> | <- guardband -> | 
     | <-    safe window    -> |
     | XXXXXXXXXXX |
... vactive     -> | <- vblank ...

But if we do want to minimize SCL (which I'm thinking we do) then
we'll need to do something else since we'll want to wait for the
SCL rather than the vblank delay after the push. So I suppose we'd
need a scanline window wait to make sure we're not in the 
(undelayed_vblank-SCL to delayed_vblank-SCL) range:

                   undelayed_vblank
                   ^                           delayed_vblank
                   |                           ^                 vmin
                   |                           |                 ^
     | <-  scl  -> | <- stretch -> | <- scl -> | <- guardband -> | 
     | <-       safe window     -> |
     | XXXXXXXXXXXXXXXXXXXXXXXXXXX |
... vactive     -> | <- vblank ...

Hmm. I guess that (undelayed_vblank-SCL to delayed_vblank-SCL) window
is actually correct for both cases.

-- 
Ville Syrjälä
Intel

Re: [PATCH 11/15] drm/i915/display: Use vrr.guardband to derive vblank_start

[Ville Syrjälä]

On Wed, Sep 17, 2025 at 01:51:15PM +0300, Ville Syrjälä wrote:
> On Tue, Sep 16, 2025 at 09:56:47PM +0300, Ville Syrjälä wrote:
> > On Tue, Sep 16, 2025 at 08:08:01PM +0530, Nautiyal, Ankit K wrote:
> > > 
> > > On 9/16/2025 8:00 PM, Nautiyal, Ankit K wrote:
> > > >
> > > > On 9/15/2025 6:02 PM, Ville Syrjälä wrote:
> > > >> On Sun, Sep 14, 2025 at 11:29:10AM +0530, Nautiyal, Ankit K wrote:
> > > >>> On 9/11/2025 7:55 PM, Ville Syrjälä wrote:
> > > >>>> On Thu, Sep 11, 2025 at 08:15:50AM +0530, Ankit Nautiyal wrote:
> > > >>>>> When VRR TG is always enabled and an optimized guardband is used, 
> > > >>>>> the pipe
> > > >>>>> vblank start is derived from the guardband.
> > > >>>>> Currently TRANS_SET_CONTEXT_LATENCY is programmed with 
> > > >>>>> crtc_vblank_start -
> > > >>>>> crtc_vdisplay, which is ~1 when guardband matches the vblank length.
> > > >>>>> With shorter guardband this become a large window.
> > > >>>>>
> > > >>>>> To avoid misprogramming TRANS_SET_CONTEXT_LATENCY, clamp the scl 
> > > >>>>> value to 1
> > > >>>>> when using optimized guardband.
> > > >>>>>
> > > >>>>> Also update the VRR get config logic to set crtc_vblank_start 
> > > >>>>> based on
> > > >>>>> vtotal - guardband, during readback.
> > > >>>>>
> > > >>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > >>>>> ---
> > > >>>>>    drivers/gpu/drm/i915/display/intel_display.c | 36 
> > > >>>>> ++++++++++++++++----
> > > >>>>>    drivers/gpu/drm/i915/display/intel_vrr.c     |  9 ++++-
> > > >>>>>    2 files changed, 38 insertions(+), 7 deletions(-)
> > > >>>>>
> > > >>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> > > >>>>> b/drivers/gpu/drm/i915/display/intel_display.c
> > > >>>>> index 55bea1374dc4..73aec6d4686a 100644
> > > >>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > >>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > >>>>> @@ -2638,6 +2638,30 @@ transcoder_has_vrr(const struct 
> > > >>>>> intel_crtc_state *crtc_state)
> > > >>>>>        return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
> > > >>>>>    }
> > > >>>>>    +static int intel_set_context_latency(const struct 
> > > >>>>> intel_crtc_state *crtc_state,
> > > >>>>> +                     int crtc_vblank_start,
> > > >>>>> +                     int crtc_vdisplay)
> > > >>>>> +{
> > > >>>>> +    struct intel_display *display = to_intel_display(crtc_state);
> > > >>>>> +
> > > >>>>> +    /*
> > > >>>>> +     * When VRR TG is always on and optimized guardband is used,
> > > >>>>> +     * the pipe vblank start is based on the guardband,
> > > >>>>> +     * TRANS_SET_CONTEXT_LATENCY cannot be used to configure it.
> > > >>>>> +     */
> > > >>>>> +    if (intel_vrr_always_use_vrr_tg(display))
> > > >>>>> +        return clamp(crtc_vblank_start - crtc_vdisplay, 0, 1);
> > > >>>> What are you trying to achieve with this? As in what problem are you
> > > >>>> seeing with the current SCL programming?
> > > >>> In VRR TG mode with optimized guardband, the guardband is shortened and
> > > >>> vblank start is moved to match the delayed vblank position.
> > > >>>
> > > >>> The SCL value which we are currently writing as difference between
> > > >>> delayed vblank and undelayed vblank becomes quite large.
> > > >>>
> > > >>> With this large SCL, the flipline decision boundary which is given by
> > > >>> delayed vblank start and SCL lines is same as the undelayed vblank.
> > > >> Everything should match the undelayed vblank.
> > > >>
> > > >>> It seems that intel_dsb_wait_vblank_delay() (in turn
> > > >>> intel_dsb_wait_usec()) does not behave correctly within the W2 window
> > > >>> (between flipdone decision boundary and delayed vblank start).
> > > >>>
> > > >>> It seems to return prematurely. Since the push bit hasn’t cleared yet,
> > > >>> this leads to DSB poll errors.
> > > >> That doesn't make any sense. That command is supposed to simply wait
> > > >> for the specifid number of microseconds. It should not care at all
> > > >> what is happening with the scanout. If that is not the case then we
> > > >> need to write a synthetic test to reproduce it, and report the
> > > >> problem to the hardware folks.
> > > >
> > > > You are right, on debugging further I noticed that 
> > > > intel_dsb_wait_usec() and intel_dsb_wait_vblank_delay() are working 
> > > > correctly.
> > > >
> > > > Due to large SCL, the the intel_dsb_wait_vblanks() is not waiting till 
> > > > the undelayed vblank but the safe window, apparently undelayed vblank 
> > > > - SCL lines.
> > > >
> > > > We are setting DSB_CHICKEN_REG bits 14-15 : which says: Wait for 
> > > > Vblank instruction will use only safe window signal from dptunit in 
> > > > DSB HW to complete the wait for vblank instruction.
> > > >
> > > > I am not exactly sure if its mentioned in Bspec that safe window start 
> > > > = undelayed vblank start - SCL lines.
> > > >
> > > > Observation:
> > > >
> > > > For example with eDP panel VRR range 40-60 and below mode:
> > > >
> > > > Mode: "2880x1800": 60 347710 2880 2928 2960 3040 1800 1803 1809 1906
> > > >
> > > > Before optimization:
> > > >
> > > > guardband = vblank length = 106; Undelayed vblank start =1800; Delayed 
> > > > vblank start = 1906 - 106 = 1800
> > > >
> > > > SCL = 1800 - 1800 = 0
> > > >
> > > > Flipline decision boundary is = 1800
> > > >
> > > > After optimization:
> > > >
> > > > vblank length = 106; guardband = 38; Undelayed Vblank start = 1800; 
> > > > Delayed Vblank start = 1868 (1906 - 38)
> > > >
> > > > SCL = 1868 - 1800 = 68
> > > >
> > > > Flipline decision boundary = 1868 - 68 = 1800
> > > >
> > > > Consider lines in  intel_atomic_dsb_finish() :
> > > >
> > > >  intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);         /* If 
> > > > flip is earlier than 1732 (1800 - 68) this waits till 1732.*/
> > > >
> > > >                 intel_vrr_send_push(new_crtc_state->dsb_commit, 
> > > > new_crtc_state);    /* Push happens immediately*/
> > > >                 intel_dsb_wait_vblank_delay(state, 
> > > > new_crtc_state->dsb_commit);        /* Waits for duration (delayed 
> > > > vblank start - undelayed vblank start) ie. 68 lines ie. till we reach 
> > > > 1732 + 68 = 1800*/
> > > > intel_vrr_check_push_sent(new_crtc_state->dsb_commit,     /* Push is 
> > > > not clear yet as delayed vblank start (1868) is not reach yet, we get 
> > > > DSB POLL error */
> > > >                                           new_crtc_state);
> > > > intel_dsb_interrupt(new_crtc_state->dsb_commit);       /* DSB 
> > > > interrupt is fired earlier */
> > > 
> > > 
> > > Sorry for the bad formatting, perhaps this will be more readable:
> > > 
> > > 
> > >   intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
> > > 
> > > /* If flip is earlier than 1732 (1800 - 68) this waits till 1732.*/
> > 
> > That does not seem right, or at least it's not how it works on LNL.
> > I just hacked some DSB_STATUS stuff into intel_display_poller [1],
> > and when running that on LNL the safe window always starts at the
> > undelayed vblank.
> > 
> > So if we look at the vmax case then I think the diagram should look
> > like this:
> > 
> >     udelayed vblank 
> >     ^               vmax decision boudnary
> >     |               ^           delayed vblank
> >     |               |           ^                 vmax
> >     |               |           |                 ^
> >     | <- stretch -> | <- scl -> | <- guardband - >|
> >      _______________
> > ..._/               \______________________________... safe window
> > 
> > ... push affects curent frame ->|<- push affects next frame ...
> >                                 |
> > 				v
> > 				push send bit clears if set
> > 
> > And then for the maximum vrefresh case (defined by flipline instead
> > of vnax) the "stretch" part is something between 0 and 
> > delayed_vblank-undelayed_vblank, depending on how we configure SCL.
> > 
> > Additionally if a push is sent during the scl window just
> > after the vmax decisioun bondary, said push will still affect
> > the current frame (ie. such a frame will not have a full
> > scl/w2 window). Only a push sent after the delayed vblank
> > will in fact get deferred to the next frame. That particular
> > scenatio isn't really described in the bspec timing diagrams.
> > Though since we always precede the push with a "wait for safe
> > window" for us the push would get deferred to the next frame
> > anyway.
> 
> Hmm, now that I think about this I think we might have to go with your
> "minimize SCL" approach after all. The problem being that our vblank
> evasion code only evades the undelayed vblank (and a bit before it).
> But with a large SCL the safe window prior to the vmax decision boundary
> may have already ended long before we're even close to crashing into the
> undelayed vblank. Thus we will write all the double buffered registers,
> and they will latch at the vmax undelayed vblank, but the push will
> get deferred into the next frame due to the "wait for safe window".
> 
> I suppose we should really have our vblank evasion code extend the
> evasion scanline window backwards to also cover the SCL.
> 
> I think what we probably need to do is start tracking the scl
> explicitly in the crtc state. And then we'll have to set things up
> in slightly different ways depending on which hw is used:
>  pre-tgl: scl=0, vblank_delay=0
>  tgl: scl=0, vblank_delay configured via VBLANK_START
>  adl+ legacy tg: scl=vblank_delay
>  adl+ vrr tg: scl=whatever(0-vblank_delay), vblank_delay configured via guardband
> 
> Hmm, or maybe we need to also pretend that tgl has scl since after
> a push we need to wait for the scl window to pass, but since tgl
> doesn't have one maybe there we need to actually wait for the vblank
> delay. I think I'll need to poke at a tgl a bit more here to
> figure out exactly how the safe window works there...

OK, done poking TGL. And the conclusion is that it looks to
be close enough to ADL+ that we can treat it almost identically.

- TRANS_SET_CONTEXT_LATENCY doesn't exist (we knew that),
  but the VBLANK_START-VACTIVE diffence plays an identical
  role here, ie. it can be used to create the SCL window ahead
  of the undelayed vblank

- pipeline_full does appear to behave the same as the guardband,
  ie. make it shorter and the undelayed vblank moves forward
  (just sent some patches to hide the differences better)

- safe window starts at undelayed vblank, and ends at
  the start of the vmax SCL window, so same as on ADL+

- vmin/vmax/flipline need to be reduced by the SCL length
  (also sent patches to hide this annoyance better)

- I suppose the only difference we can't completely hide is
  the intel_vrr_extra_vblank_delay() off-by-one issue in the
  hardware

-- 
Ville Syrjälä
Intel

Re: [PATCH 11/15] drm/i915/display: Use vrr.guardband to derive vblank_start

[Ville Syrjälä]

On Wed, Sep 17, 2025 at 11:51:35PM +0300, Ville Syrjälä wrote:
> On Wed, Sep 17, 2025 at 01:51:15PM +0300, Ville Syrjälä wrote:
> > On Tue, Sep 16, 2025 at 09:56:47PM +0300, Ville Syrjälä wrote:
> > > On Tue, Sep 16, 2025 at 08:08:01PM +0530, Nautiyal, Ankit K wrote:
> > > > 
> > > > On 9/16/2025 8:00 PM, Nautiyal, Ankit K wrote:
> > > > >
> > > > > On 9/15/2025 6:02 PM, Ville Syrjälä wrote:
> > > > >> On Sun, Sep 14, 2025 at 11:29:10AM +0530, Nautiyal, Ankit K wrote:
> > > > >>> On 9/11/2025 7:55 PM, Ville Syrjälä wrote:
> > > > >>>> On Thu, Sep 11, 2025 at 08:15:50AM +0530, Ankit Nautiyal wrote:
> > > > >>>>> When VRR TG is always enabled and an optimized guardband is used, 
> > > > >>>>> the pipe
> > > > >>>>> vblank start is derived from the guardband.
> > > > >>>>> Currently TRANS_SET_CONTEXT_LATENCY is programmed with 
> > > > >>>>> crtc_vblank_start -
> > > > >>>>> crtc_vdisplay, which is ~1 when guardband matches the vblank length.
> > > > >>>>> With shorter guardband this become a large window.
> > > > >>>>>
> > > > >>>>> To avoid misprogramming TRANS_SET_CONTEXT_LATENCY, clamp the scl 
> > > > >>>>> value to 1
> > > > >>>>> when using optimized guardband.
> > > > >>>>>
> > > > >>>>> Also update the VRR get config logic to set crtc_vblank_start 
> > > > >>>>> based on
> > > > >>>>> vtotal - guardband, during readback.
> > > > >>>>>
> > > > >>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > > >>>>> ---
> > > > >>>>>    drivers/gpu/drm/i915/display/intel_display.c | 36 
> > > > >>>>> ++++++++++++++++----
> > > > >>>>>    drivers/gpu/drm/i915/display/intel_vrr.c     |  9 ++++-
> > > > >>>>>    2 files changed, 38 insertions(+), 7 deletions(-)
> > > > >>>>>
> > > > >>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> > > > >>>>> b/drivers/gpu/drm/i915/display/intel_display.c
> > > > >>>>> index 55bea1374dc4..73aec6d4686a 100644
> > > > >>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > >>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > >>>>> @@ -2638,6 +2638,30 @@ transcoder_has_vrr(const struct 
> > > > >>>>> intel_crtc_state *crtc_state)
> > > > >>>>>        return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
> > > > >>>>>    }
> > > > >>>>>    +static int intel_set_context_latency(const struct 
> > > > >>>>> intel_crtc_state *crtc_state,
> > > > >>>>> +                     int crtc_vblank_start,
> > > > >>>>> +                     int crtc_vdisplay)
> > > > >>>>> +{
> > > > >>>>> +    struct intel_display *display = to_intel_display(crtc_state);
> > > > >>>>> +
> > > > >>>>> +    /*
> > > > >>>>> +     * When VRR TG is always on and optimized guardband is used,
> > > > >>>>> +     * the pipe vblank start is based on the guardband,
> > > > >>>>> +     * TRANS_SET_CONTEXT_LATENCY cannot be used to configure it.
> > > > >>>>> +     */
> > > > >>>>> +    if (intel_vrr_always_use_vrr_tg(display))
> > > > >>>>> +        return clamp(crtc_vblank_start - crtc_vdisplay, 0, 1);
> > > > >>>> What are you trying to achieve with this? As in what problem are you
> > > > >>>> seeing with the current SCL programming?
> > > > >>> In VRR TG mode with optimized guardband, the guardband is shortened and
> > > > >>> vblank start is moved to match the delayed vblank position.
> > > > >>>
> > > > >>> The SCL value which we are currently writing as difference between
> > > > >>> delayed vblank and undelayed vblank becomes quite large.
> > > > >>>
> > > > >>> With this large SCL, the flipline decision boundary which is given by
> > > > >>> delayed vblank start and SCL lines is same as the undelayed vblank.
> > > > >> Everything should match the undelayed vblank.
> > > > >>
> > > > >>> It seems that intel_dsb_wait_vblank_delay() (in turn
> > > > >>> intel_dsb_wait_usec()) does not behave correctly within the W2 window
> > > > >>> (between flipdone decision boundary and delayed vblank start).
> > > > >>>
> > > > >>> It seems to return prematurely. Since the push bit hasn’t cleared yet,
> > > > >>> this leads to DSB poll errors.
> > > > >> That doesn't make any sense. That command is supposed to simply wait
> > > > >> for the specifid number of microseconds. It should not care at all
> > > > >> what is happening with the scanout. If that is not the case then we
> > > > >> need to write a synthetic test to reproduce it, and report the
> > > > >> problem to the hardware folks.
> > > > >
> > > > > You are right, on debugging further I noticed that 
> > > > > intel_dsb_wait_usec() and intel_dsb_wait_vblank_delay() are working 
> > > > > correctly.
> > > > >
> > > > > Due to large SCL, the the intel_dsb_wait_vblanks() is not waiting till 
> > > > > the undelayed vblank but the safe window, apparently undelayed vblank 
> > > > > - SCL lines.
> > > > >
> > > > > We are setting DSB_CHICKEN_REG bits 14-15 : which says: Wait for 
> > > > > Vblank instruction will use only safe window signal from dptunit in 
> > > > > DSB HW to complete the wait for vblank instruction.
> > > > >
> > > > > I am not exactly sure if its mentioned in Bspec that safe window start 
> > > > > = undelayed vblank start - SCL lines.
> > > > >
> > > > > Observation:
> > > > >
> > > > > For example with eDP panel VRR range 40-60 and below mode:
> > > > >
> > > > > Mode: "2880x1800": 60 347710 2880 2928 2960 3040 1800 1803 1809 1906
> > > > >
> > > > > Before optimization:
> > > > >
> > > > > guardband = vblank length = 106; Undelayed vblank start =1800; Delayed 
> > > > > vblank start = 1906 - 106 = 1800
> > > > >
> > > > > SCL = 1800 - 1800 = 0
> > > > >
> > > > > Flipline decision boundary is = 1800
> > > > >
> > > > > After optimization:
> > > > >
> > > > > vblank length = 106; guardband = 38; Undelayed Vblank start = 1800; 
> > > > > Delayed Vblank start = 1868 (1906 - 38)
> > > > >
> > > > > SCL = 1868 - 1800 = 68
> > > > >
> > > > > Flipline decision boundary = 1868 - 68 = 1800
> > > > >
> > > > > Consider lines in  intel_atomic_dsb_finish() :
> > > > >
> > > > >  intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);         /* If 
> > > > > flip is earlier than 1732 (1800 - 68) this waits till 1732.*/
> > > > >
> > > > >                 intel_vrr_send_push(new_crtc_state->dsb_commit, 
> > > > > new_crtc_state);    /* Push happens immediately*/
> > > > >                 intel_dsb_wait_vblank_delay(state, 
> > > > > new_crtc_state->dsb_commit);        /* Waits for duration (delayed 
> > > > > vblank start - undelayed vblank start) ie. 68 lines ie. till we reach 
> > > > > 1732 + 68 = 1800*/
> > > > > intel_vrr_check_push_sent(new_crtc_state->dsb_commit,     /* Push is 
> > > > > not clear yet as delayed vblank start (1868) is not reach yet, we get 
> > > > > DSB POLL error */
> > > > >                                           new_crtc_state);
> > > > > intel_dsb_interrupt(new_crtc_state->dsb_commit);       /* DSB 
> > > > > interrupt is fired earlier */
> > > > 
> > > > 
> > > > Sorry for the bad formatting, perhaps this will be more readable:
> > > > 
> > > > 
> > > >   intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
> > > > 
> > > > /* If flip is earlier than 1732 (1800 - 68) this waits till 1732.*/
> > > 
> > > That does not seem right, or at least it's not how it works on LNL.
> > > I just hacked some DSB_STATUS stuff into intel_display_poller [1],
> > > and when running that on LNL the safe window always starts at the
> > > undelayed vblank.
> > > 
> > > So if we look at the vmax case then I think the diagram should look
> > > like this:
> > > 
> > >     udelayed vblank 
> > >     ^               vmax decision boudnary
> > >     |               ^           delayed vblank
> > >     |               |           ^                 vmax
> > >     |               |           |                 ^
> > >     | <- stretch -> | <- scl -> | <- guardband - >|
> > >      _______________
> > > ..._/               \______________________________... safe window
> > > 
> > > ... push affects curent frame ->|<- push affects next frame ...
> > >                                 |
> > > 				v
> > > 				push send bit clears if set
> > > 
> > > And then for the maximum vrefresh case (defined by flipline instead
> > > of vnax) the "stretch" part is something between 0 and 
> > > delayed_vblank-undelayed_vblank, depending on how we configure SCL.
> > > 
> > > Additionally if a push is sent during the scl window just
> > > after the vmax decisioun bondary, said push will still affect
> > > the current frame (ie. such a frame will not have a full
> > > scl/w2 window). Only a push sent after the delayed vblank
> > > will in fact get deferred to the next frame. That particular
> > > scenatio isn't really described in the bspec timing diagrams.
> > > Though since we always precede the push with a "wait for safe
> > > window" for us the push would get deferred to the next frame
> > > anyway.
> > 
> > Hmm, now that I think about this I think we might have to go with your
> > "minimize SCL" approach after all. The problem being that our vblank
> > evasion code only evades the undelayed vblank (and a bit before it).
> > But with a large SCL the safe window prior to the vmax decision boundary
> > may have already ended long before we're even close to crashing into the
> > undelayed vblank. Thus we will write all the double buffered registers,
> > and they will latch at the vmax undelayed vblank, but the push will
> > get deferred into the next frame due to the "wait for safe window".
> > 
> > I suppose we should really have our vblank evasion code extend the
> > evasion scanline window backwards to also cover the SCL.
> > 
> > I think what we probably need to do is start tracking the scl
> > explicitly in the crtc state. And then we'll have to set things up
> > in slightly different ways depending on which hw is used:
> >  pre-tgl: scl=0, vblank_delay=0
> >  tgl: scl=0, vblank_delay configured via VBLANK_START
> >  adl+ legacy tg: scl=vblank_delay
> >  adl+ vrr tg: scl=whatever(0-vblank_delay), vblank_delay configured via guardband
> > 
> > Hmm, or maybe we need to also pretend that tgl has scl since after
> > a push we need to wait for the scl window to pass, but since tgl
> > doesn't have one maybe there we need to actually wait for the vblank
> > delay. I think I'll need to poke at a tgl a bit more here to
> > figure out exactly how the safe window works there...
> 
> OK, done poking TGL. And the conclusion is that it looks to
> be close enough to ADL+ that we can treat it almost identically.
> 
> - TRANS_SET_CONTEXT_LATENCY doesn't exist (we knew that),
>   but the VBLANK_START-VACTIVE diffence plays an identical
>   role here, ie. it can be used to create the SCL window ahead
>   of the undelayed vblank
> 
> - pipeline_full does appear to behave the same as the guardband,
>   ie. make it shorter and the undelayed vblank moves forward
>   (just sent some patches to hide the differences better)
> 
> - safe window starts at undelayed vblank, and ends at
>   the start of the vmax SCL window, so same as on ADL+
> 
> - vmin/vmax/flipline need to be reduced by the SCL length
>   (also sent patches to hide this annoyance better)
> 
> - I suppose the only difference we can't completely hide is
>   the intel_vrr_extra_vblank_delay() off-by-one issue in the
>   hardware

Hmm. Actually maybe it does get hidden once we do the scanline window
wait after the wait for safe window. The extra scanline is exactly in
that range.

While thinking about this I was getting abit confused because all the
numbers I got now were making sense, except I wasn't explicitly handling
intel_vrr_extra_vblank_delay() anywhere. But I think that gets covered
now we reduce vmin by intel_vrr_flipline_offset() before computing the
guardband. So one extra scanline gets removed from the guardband and
all the numbers come out correct in the end.

So yeah, I think this annoyance can also mostly disappear.

-- 
Ville Syrjälä
Intel