Re: [PATCH v11 05/13] drm/xe/xelp: Wait for AuxCCS invalidation to complete

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Thu, Aug 21, 2025 at 03:14:47PM +0100, Tvrtko Ursulin wrote:
> On AuxCCS platforms we need to wait for AuxCCS invalidations to complete.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 6 ++++++
>  drivers/gpu/drm/xe/xe_ring_ops.c                 | 9 ++++++++-
>  drivers/gpu/drm/xe/xe_ring_ops_types.h           | 2 +-
>  3 files changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> index c47b290e0e9f..49d8ffd026d5 100644
> --- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> +++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> @@ -81,4 +81,10 @@
>  #define MI_SET_APPID_SESSION_ID_MASK	REG_GENMASK(6, 0)
>  #define MI_SET_APPID_SESSION_ID(x)	REG_FIELD_PREP(MI_SET_APPID_SESSION_ID_MASK, x)
>  
> +#define MI_SEMAPHORE_WAIT_TOKEN		(__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5)) /* XeLP+ */
> +#define   MI_SEMAPHORE_REGISTER_POLL	REG_BIT(16)
> +#define   MI_SEMAPHORE_POLL		REG_BIT(15)
> +#define   MI_SEMAPHORE_CMP_OP_MASK	REG_GENMASK(14, 12)
> +#define   MI_SEMAPHORE_SAD_EQ_SDD	REG_FIELD_PREP(MI_SEMAPHORE_CMP_OP_MASK, 4)
> +
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> index 752dea0a9234..78d8120c4a0e 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -56,7 +56,14 @@ static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg,
>  	dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | MI_LRI_MMIO_REMAP_EN;
>  	dw[i++] = reg.addr + gt->mmio.adj_offset;
>  	dw[i++] = AUX_INV;
> -	dw[i++] = MI_NOOP;
> +	dw[i++] = MI_SEMAPHORE_WAIT_TOKEN |
> +		  MI_SEMAPHORE_REGISTER_POLL |
> +		  MI_SEMAPHORE_POLL |
> +		  MI_SEMAPHORE_SAD_EQ_SDD;
> +	dw[i++] = 0;
> +	dw[i++] = reg.addr + gt->mmio.adj_offset;
> +	dw[i++] = 0;
> +	dw[i++] = 0;
>  
>  	return i;
>  }
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops_types.h b/drivers/gpu/drm/xe/xe_ring_ops_types.h
> index 477dc7defd72..1197fc0bf2af 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops_types.h
> +++ b/drivers/gpu/drm/xe/xe_ring_ops_types.h
> @@ -8,7 +8,7 @@
>  
>  struct xe_sched_job;
>  
> -#define MAX_JOB_SIZE_DW 70
> +#define MAX_JOB_SIZE_DW 74
>  #define MAX_JOB_SIZE_BYTES (MAX_JOB_SIZE_DW * 4)
>  
>  /**
> -- 
> 2.48.0
>