Re: [PATCH v5 6/7] drm/xe/lrc: Allow to add user commands mid context switch

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Tue, Sep 16, 2025 at 02:15:43PM -0700, Lucas De Marchi wrote:
> Like done for post-context-restore commands, allow to add commands from
> configfs in the middle of context restore. Since currently the indirect
> ctx hardcodes the offset to CTX_INDIRECT_CTX_OFFSET_DEFAULT, this is
> executed in the very beginning of engine context restore.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_configfs.c | 15 +++++++++++++++
>  drivers/gpu/drm/xe/xe_configfs.h |  4 ++++
>  drivers/gpu/drm/xe/xe_lrc.c      | 37 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 56 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
> index 9a30dc958c35c..90bc5a4b5da71 100644
> --- a/drivers/gpu/drm/xe/xe_configfs.c
> +++ b/drivers/gpu/drm/xe/xe_configfs.c
> @@ -897,6 +897,21 @@ bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev)
>  	return ret;
>  }
>  
> +/**
> + * xe_configfs_get_ctx_restore_mid_bb - get configfs ctx_restore_mid_bb setting
> + * @pdev: pci device
> + * @class: hw engine class
> + * @cs: pointer to the bb to use - only valid during probe
> + *
> + * Return: Number of dwords used in the mid_ctx_restore setting in configfs
> + */
> +u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev,
> +				       enum xe_engine_class class,
> +				       const u32 **cs)
> +{
> +	return 0;
> +}
> +
>  /**
>   * xe_configfs_get_ctx_restore_post_bb - get configfs ctx_restore_post_bb setting
>   * @pdev: pci device
> diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h
> index eff2645b5f593..c61e0e47ed94c 100644
> --- a/drivers/gpu/drm/xe/xe_configfs.h
> +++ b/drivers/gpu/drm/xe/xe_configfs.h
> @@ -19,6 +19,8 @@ void xe_configfs_check_device(struct pci_dev *pdev);
>  bool xe_configfs_get_survivability_mode(struct pci_dev *pdev);
>  u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev);
>  bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev);
> +u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
> +				       const u32 **cs);
>  u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev, enum xe_engine_class,
>  					const u32 **cs);
>  #else
> @@ -28,6 +30,8 @@ static inline void xe_configfs_check_device(struct pci_dev *pdev) { }
>  static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; }
>  static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) { return U64_MAX; }
>  static inline bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev) { return false; }
> +static inline u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
> +						     const u32 **cs) { return 0; }
>  static inline u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev, enum xe_engine_class,
>  						      const u32 **cs) { return 0; }
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index 0ab99c210d882..47e9df7750725 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -77,11 +77,17 @@ lrc_to_xe(struct xe_lrc *lrc)
>  static bool
>  gt_engine_needs_indirect_ctx(struct xe_gt *gt, enum xe_engine_class class)
>  {
> +	struct xe_device *xe = gt_to_xe(gt);
> +
>  	if (XE_GT_WA(gt, 16010904313) &&
>  	    (class == XE_ENGINE_CLASS_RENDER ||
>  	     class == XE_ENGINE_CLASS_COMPUTE))
>  		return true;
>  
> +	if (xe_configfs_get_ctx_restore_mid_bb(to_pci_dev(xe->drm.dev),
> +					       class, NULL))
> +		return true;
> +
>  	return false;
>  }
>  
> @@ -1133,6 +1139,35 @@ static ssize_t setup_configfs_post_ctx_restore_bb(struct xe_lrc *lrc,
>  	return cmd - batch;
>  }
>  
> +static ssize_t setup_configfs_mid_ctx_restore_bb(struct xe_lrc *lrc,
> +						 struct xe_hw_engine *hwe,
> +						 u32 *batch, size_t max_len)
> +{
> +	struct xe_device *xe = gt_to_xe(lrc->gt);
> +	const u32 *user_batch;
> +	u32 *cmd = batch;
> +	u32 count;
> +
> +	count = xe_configfs_get_ctx_restore_mid_bb(to_pci_dev(xe->drm.dev),
> +						   hwe->class, &user_batch);
> +	if (!count)
> +		return 0;
> +
> +	if (count > max_len)
> +		return -ENOSPC;
> +
> +	/*
> +	 * This should be used only for tests and validation. Taint the kernel
> +	 * as anything could be submitted directly in context switches
> +	 */
> +	add_taint(TAINT_TEST, LOCKDEP_STILL_OK);
> +
> +	memcpy(cmd, user_batch, count * sizeof(u32));
> +	cmd += count;
> +
> +	return cmd - batch;
> +}
> +
>  static ssize_t setup_invalidate_state_cache_wa(struct xe_lrc *lrc,
>  					       struct xe_hw_engine *hwe,
>  					       u32 *batch, size_t max_len)
> @@ -1283,8 +1318,10 @@ setup_indirect_ctx(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
>  {
>  	static const struct bo_setup rcs_funcs[] = {
>  		{ .setup = setup_timestamp_wa },
> +		{ .setup = setup_configfs_mid_ctx_restore_bb },
>  	};
>  	static const struct bo_setup xcs_funcs[] = {
> +		{ .setup = setup_configfs_mid_ctx_restore_bb },
>  	};
>  	struct bo_setup_state state = {
>  		.lrc = lrc,
> 
> -- 
> 2.50.1
>