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d="scan'208";a="174877525" Received: from pgcooper-mobl3.ger.corp.intel.com (HELO localhost) ([10.245.244.255]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2025 10:32:15 -0700 Date: Thu, 18 Sep 2025 20:32:11 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: Re: [PATCH 3/5] drm/i915/irq: rename irq_mask to gen2_imr_mask Message-ID: References: <2c193663cd3ae524d8159b4216e45462017042fa.1758198300.git.jani.nikula@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <2c193663cd3ae524d8159b4216e45462017042fa.1758198300.git.jani.nikula@intel.com> X-Patchwork-Hint: comment Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Thu, Sep 18, 2025 at 03:25:46PM +0300, Jani Nikula wrote: > Rename the struct drm_i915_private irq_mask member to gen2_imr_mask to > reflect its usage more accurately. > > Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 8 ++++---- > drivers/gpu/drm/i915/i915_drv.h | 4 ++-- > drivers/gpu/drm/i915/i915_irq.c | 16 ++++++++-------- > 3 files changed, 14 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > index 8116fd5987e2..8c01fb6d4e7b 100644 > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > @@ -292,15 +292,15 @@ int gen4_emit_bb_start(struct i915_request *rq, > > void gen2_irq_enable(struct intel_engine_cs *engine) > { > - engine->i915->irq_mask &= ~engine->irq_enable_mask; > - intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); > + engine->i915->gen2_imr_mask &= ~engine->irq_enable_mask; > + intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->gen2_imr_mask); > intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR); > } > > void gen2_irq_disable(struct intel_engine_cs *engine) > { > - engine->i915->irq_mask |= engine->irq_enable_mask; > - intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); > + engine->i915->gen2_imr_mask |= engine->irq_enable_mask; > + intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->gen2_imr_mask); > } > > void gen5_irq_enable(struct intel_engine_cs *engine) > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 37970d8db255..03e497d2081e 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -234,8 +234,8 @@ struct drm_i915_private { > /* Sideband mailbox protection */ > struct mutex sb_lock; > > - /** Cached value of IMR to avoid reads in updating the bitfield */ > - u32 irq_mask; > + /* Cached value of gen 2-4 IMR to avoid reads in updating the bitfield */ > + u32 gen2_imr_mask; > > bool preserve_bios_swizzle; > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index e5fdfd51b549..ab65402bc6bf 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -897,7 +897,7 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv) > > gen2_error_reset(uncore, GEN2_ERROR_REGS); > gen2_irq_reset(uncore, GEN2_IRQ_REGS); > - dev_priv->irq_mask = ~0u; > + dev_priv->gen2_imr_mask = ~0u; > } > > static void i915_irq_postinstall(struct drm_i915_private *dev_priv) > @@ -908,7 +908,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv) > > gen2_error_init(uncore, GEN2_ERROR_REGS, ~i9xx_error_mask(dev_priv)); > > - dev_priv->irq_mask = > + dev_priv->gen2_imr_mask = > ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | > I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | > I915_MASTER_ERROR_INTERRUPT); > @@ -920,16 +920,16 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv) > I915_USER_INTERRUPT; > > if (DISPLAY_VER(display) >= 3) { > - dev_priv->irq_mask &= ~I915_ASLE_INTERRUPT; > + dev_priv->gen2_imr_mask &= ~I915_ASLE_INTERRUPT; > enable_mask |= I915_ASLE_INTERRUPT; > } > > if (HAS_HOTPLUG(display)) { > - dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; > + dev_priv->gen2_imr_mask &= ~I915_DISPLAY_PORT_INTERRUPT; > enable_mask |= I915_DISPLAY_PORT_INTERRUPT; > } > > - gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask); > + gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask); > > i915_display_irq_postinstall(display); > } > @@ -999,7 +999,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv) > > gen2_error_reset(uncore, GEN2_ERROR_REGS); > gen2_irq_reset(uncore, GEN2_IRQ_REGS); > - dev_priv->irq_mask = ~0u; > + dev_priv->gen2_imr_mask = ~0u; > } > > static u32 i965_error_mask(struct drm_i915_private *i915) > @@ -1029,7 +1029,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv) > > gen2_error_init(uncore, GEN2_ERROR_REGS, ~i965_error_mask(dev_priv)); > > - dev_priv->irq_mask = > + dev_priv->gen2_imr_mask = > ~(I915_ASLE_INTERRUPT | > I915_DISPLAY_PORT_INTERRUPT | > I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | > @@ -1047,7 +1047,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv) > if (IS_G4X(dev_priv)) > enable_mask |= I915_BSD_USER_INTERRUPT; > > - gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask); > + gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask); > > i965_display_irq_postinstall(display); > } > -- > 2.47.3 -- Ville Syrjälä Intel