[PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic

[PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic

[Ankit Nautiyal]

This patch series refactors VRR and DSB timing logic by introducing
explicit handling of Set Context Latency (SCL) the number of lines required
before double buffering to safely program display registers, aka W2 Window.

Previously, SCL was handled implicitly via vblank delay calculations. This
was a hinderance for later work to optimize guardband length. This series
formalizes SCL as `set_context_latency` in `intel_crtc_state`, enabling
consistent tracking and timing/delay computation across platforms.

- Introduces `set_context_latency` to track SCL explicitly.
- Refactors VRR evasion and DSB wait logic to use SCL directly.
- Clamps guardband values based on hardware limits and timing constraints.
- Renames helpers for clarity and removes legacy delay logic.

Ankit Nautiyal (9):
  drm/i915/psr:
    s/intel_psr_min_vblank_delay/intel_psr_min_set_context_latency
  drm/i915/display: Add set_context_latency to crtc_state->vrr
  drm/i915/display: Use VBLANK_START to get the vblank delay for TGL
  drm/i915/vrr: Use set_context_latency instead of
    intel_vrr_real_vblank_delay()
  drm/i915/vrr: s/intel_vrr_vblank_delay/intel_vrr_scl_delay
  drm/i915/display: Use set context latency in evasion logic
  drm/i915/dsb:
    s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_scl_lines
  drm/i915/display: Wait for scl start instead of dsb_wait_vblanks
  drm/i915/vrr: Clamp guardband as per hardware and timing constraints

 drivers/gpu/drm/i915/display/intel_color.c    |  2 +-
 .../drm/i915/display/intel_crtc_state_dump.c  |  5 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 43 ++++++++++-----
 .../drm/i915/display/intel_display_types.h    |  3 ++
 drivers/gpu/drm/i915/display/intel_dsb.c      | 35 ++++++++----
 drivers/gpu/drm/i915/display/intel_dsb.h      |  6 ++-
 drivers/gpu/drm/i915/display/intel_psr.c      |  6 +--
 drivers/gpu/drm/i915/display/intel_psr.h      |  2 +-
 drivers/gpu/drm/i915/display/intel_vblank.c   |  9 +---
 drivers/gpu/drm/i915/display/intel_vblank.h   |  1 -
 drivers/gpu/drm/i915/display/intel_vrr.c      | 54 ++++++++++++-------
 drivers/gpu/drm/i915/display/intel_vrr.h      |  2 +-
 12 files changed, 109 insertions(+), 59 deletions(-)

-- 
2.45.2

[PATCH 1/9] drm/i915/psr: s/intel_psr_min_vblank_delay/intel_psr_min_set_context_latency

[Ankit Nautiyal]

Rename intel_psr_min_vblank_delay to intel_psr_min_set_context_latency
to reflect that it provides the minimum value for 'Set context
latency'(SCL or Window W2) for PSR/Panel Replay to work correctly across
different platforms.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 drivers/gpu/drm/i915/display/intel_psr.c     | 6 +++---
 drivers/gpu/drm/i915/display/intel_psr.h     | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 18b9baa96241..679c2a9baaee 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2369,7 +2369,7 @@ static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state)
 	if (!HAS_DSB(display))
 		return 0;
 
-	vblank_delay = max(vblank_delay, intel_psr_min_vblank_delay(crtc_state));
+	vblank_delay = max(vblank_delay, intel_psr_min_set_context_latency(crtc_state));
 
 	return vblank_delay;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 01bf304c705f..49ccd0864c55 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2360,12 +2360,12 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
 }
 
 /**
- * intel_psr_min_vblank_delay - Minimum vblank delay needed by PSR
+ * intel_psr_min_set_context_latency - Minimum 'set context latency' lines needed by PSR
  * @crtc_state: the crtc state
  *
- * Return minimum vblank delay needed by PSR.
+ * Return minimum SCL lines/delay needed by PSR.
  */
-int intel_psr_min_vblank_delay(const struct intel_crtc_state *crtc_state)
+int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 077751aa599f..9147996d6c9e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -77,7 +77,7 @@ void intel_psr_unlock(const struct intel_crtc_state *crtc_state);
 void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
 					  struct intel_atomic_state *state,
 					  struct intel_crtc *crtc);
-int intel_psr_min_vblank_delay(const struct intel_crtc_state *crtc_state);
+int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state);
 void intel_psr_connector_debugfs_add(struct intel_connector *connector);
 void intel_psr_debugfs_register(struct intel_display *display);
 bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);
-- 
2.45.2

Re: [PATCH 1/9] drm/i915/psr: s/intel_psr_min_vblank_delay/intel_psr_min_set_context_latency

[Ville Syrjälä]

On Sun, Sep 21, 2025 at 10:05:27AM +0530, Ankit Nautiyal wrote:
> Rename intel_psr_min_vblank_delay to intel_psr_min_set_context_latency
> to reflect that it provides the minimum value for 'Set context
> latency'(SCL or Window W2) for PSR/Panel Replay to work correctly across
> different platforms.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c     | 6 +++---
>  drivers/gpu/drm/i915/display/intel_psr.h     | 2 +-
>  3 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 18b9baa96241..679c2a9baaee 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2369,7 +2369,7 @@ static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state)
>  	if (!HAS_DSB(display))
>  		return 0;
>  
> -	vblank_delay = max(vblank_delay, intel_psr_min_vblank_delay(crtc_state));
> +	vblank_delay = max(vblank_delay, intel_psr_min_set_context_latency(crtc_state));
>  
>  	return vblank_delay;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 01bf304c705f..49ccd0864c55 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2360,12 +2360,12 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
>  }
>  
>  /**
> - * intel_psr_min_vblank_delay - Minimum vblank delay needed by PSR
> + * intel_psr_min_set_context_latency - Minimum 'set context latency' lines needed by PSR
>   * @crtc_state: the crtc state
>   *
> - * Return minimum vblank delay needed by PSR.
> + * Return minimum SCL lines/delay needed by PSR.
>   */
> -int intel_psr_min_vblank_delay(const struct intel_crtc_state *crtc_state)
> +int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 077751aa599f..9147996d6c9e 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -77,7 +77,7 @@ void intel_psr_unlock(const struct intel_crtc_state *crtc_state);
>  void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
>  					  struct intel_atomic_state *state,
>  					  struct intel_crtc *crtc);
> -int intel_psr_min_vblank_delay(const struct intel_crtc_state *crtc_state);
> +int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state);
>  void intel_psr_connector_debugfs_add(struct intel_connector *connector);
>  void intel_psr_debugfs_register(struct intel_display *display);
>  bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

[PATCH 2/9] drm/i915/display: Add set_context_latency to crtc_state->vrr

[Ankit Nautiyal]

'Set context latency' (Window W2) is defined as the number of lines before
the double buffering point, which are required to complete programming of
the registers, typically when DSB is used to program the display
registers.

Since we are not using this window for programming the registers, this
is mostly set to 0, unless there is a requirement for few cases related
to PSR/PR where the 'set context latency' should be at least 1.

Currently we are using the 'set context latency' (if required) implicitly
by moving the vblank start by the required amount and then measuring the
delay i.e. the difference between undelayed vblank start and delayed vblank
start.

Since our guardband matches the vblank length, this was not a problem as
the difference between the undelayed vblank and delayed vblank was at
the most equal to the 'set context latency' lines.

However, if we want to optimize the guardband, the difference between the
undelayed and the delayed vblank will be large and we cannot use this
difference as the 'set context latency' lines.

To make way for this optimization of guardband, we formally introduce
the 'set context latency' and track it as a new member
`set_context_latency` of the intel_crtc_state.

Eventually, all references of vblank delay where we mean to use set
context latency will be replaced by this new `set_context_latency`
member.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../drm/i915/display/intel_crtc_state_dump.c  |  5 ++--
 drivers/gpu/drm/i915/display/intel_display.c  | 29 ++++++++++++-------
 .../drm/i915/display/intel_display_types.h    |  3 ++
 3 files changed, 24 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 0c7f91046996..a14bcda4446c 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -289,10 +289,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 	drm_printf(&p, "scanline offset: %d\n",
 		   intel_crtc_scanline_offset(pipe_config));
 
-	drm_printf(&p, "vblank delay: %d, framestart delay: %d, MSA timing delay: %d\n",
+	drm_printf(&p, "vblank delay: %d, framestart delay: %d, MSA timing delay: %d set context latency: %d\n",
 		   pipe_config->hw.adjusted_mode.crtc_vblank_start -
 		   pipe_config->hw.adjusted_mode.crtc_vdisplay,
-		   pipe_config->framestart_delay, pipe_config->msa_timing_delay);
+		   pipe_config->framestart_delay, pipe_config->msa_timing_delay,
+		   pipe_config->set_context_latency);
 
 	drm_printf(&p, "vrr: %s, fixed rr: %s, vmin: %d, vmax: %d, flipline: %d, pipeline full: %d, guardband: %d vsync start: %d, vsync end: %d\n",
 		   str_yes_no(pipe_config->vrr.enable),
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 679c2a9baaee..5a7794387ea2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2361,17 +2361,18 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
-static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state)
+static int intel_crtc_set_context_latency(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	int vblank_delay = 0;
+	int set_context_latency = 0;
 
 	if (!HAS_DSB(display))
 		return 0;
 
-	vblank_delay = max(vblank_delay, intel_psr_min_set_context_latency(crtc_state));
+	set_context_latency = max(set_context_latency,
+				  intel_psr_min_set_context_latency(crtc_state));
 
-	return vblank_delay;
+	return set_context_latency;
 }
 
 static int intel_crtc_compute_vblank_delay(struct intel_atomic_state *state,
@@ -2382,9 +2383,10 @@ static int intel_crtc_compute_vblank_delay(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
-	int vblank_delay, max_vblank_delay;
+	int vblank_delay = 0, max_vblank_delay;
 
-	vblank_delay = intel_crtc_vblank_delay(crtc_state);
+	crtc_state->set_context_latency = intel_crtc_set_context_latency(crtc_state);
+	vblank_delay += crtc_state->set_context_latency;
 	max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1;
 
 	if (vblank_delay > max_vblank_delay) {
@@ -2617,7 +2619,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	if (DISPLAY_VER(display) >= 13) {
 		intel_de_write(display,
 			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
-			       crtc_vblank_start - crtc_vdisplay);
+			       crtc_state->set_context_latency);
 
 		/*
 		 * VBLANK_START not used by hw, just clear it
@@ -2707,7 +2709,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 	if (DISPLAY_VER(display) >= 13) {
 		intel_de_write(display,
 			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
-			       crtc_vblank_start - crtc_vdisplay);
+			       crtc_state->set_context_latency);
 
 		/*
 		 * VBLANK_START not used by hw, just clear it
@@ -2820,11 +2822,14 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
 		adjusted_mode->crtc_vblank_end += 1;
 	}
 
-	if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder))
-		adjusted_mode->crtc_vblank_start =
-			adjusted_mode->crtc_vdisplay +
+	if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) {
+		pipe_config->set_context_latency =
 			intel_de_read(display,
 				      TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder));
+		adjusted_mode->crtc_vblank_start =
+			adjusted_mode->crtc_vdisplay +
+			pipe_config->set_context_latency;
+	}
 
 	if (DISPLAY_VER(display) >= 30)
 		pipe_config->min_hblank = intel_de_read(display,
@@ -5387,6 +5392,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_I(vrr.guardband);
 	}
 
+	PIPE_CONF_CHECK_I(set_context_latency);
+
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
 #undef PIPE_CONF_CHECK_LLI
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 358ab922d7a7..a22fe77fcca1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1341,6 +1341,9 @@ struct intel_crtc_state {
 
 	/* LOBF flag */
 	bool has_lobf;
+
+	/* W2 window or 'set context latency' lines */
+	int set_context_latency;
 };
 
 enum intel_pipe_crc_source {
-- 
2.45.2

Re: [PATCH 2/9] drm/i915/display: Add set_context_latency to crtc_state->vrr

[Ville Syrjälä]

On Sun, Sep 21, 2025 at 10:05:28AM +0530, Ankit Nautiyal wrote:
> 'Set context latency' (Window W2) is defined as the number of lines before
> the double buffering point, which are required to complete programming of
> the registers, typically when DSB is used to program the display
> registers.
> 
> Since we are not using this window for programming the registers, this
> is mostly set to 0, unless there is a requirement for few cases related
> to PSR/PR where the 'set context latency' should be at least 1.
> 
> Currently we are using the 'set context latency' (if required) implicitly
> by moving the vblank start by the required amount and then measuring the
> delay i.e. the difference between undelayed vblank start and delayed vblank
> start.
> 
> Since our guardband matches the vblank length, this was not a problem as
> the difference between the undelayed vblank and delayed vblank was at
> the most equal to the 'set context latency' lines.
> 
> However, if we want to optimize the guardband, the difference between the
> undelayed and the delayed vblank will be large and we cannot use this
> difference as the 'set context latency' lines.
> 
> To make way for this optimization of guardband, we formally introduce
> the 'set context latency' and track it as a new member
> `set_context_latency` of the intel_crtc_state.
> 
> Eventually, all references of vblank delay where we mean to use set
> context latency will be replaced by this new `set_context_latency`
> member.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  .../drm/i915/display/intel_crtc_state_dump.c  |  5 ++--
>  drivers/gpu/drm/i915/display/intel_display.c  | 29 ++++++++++++-------
>  .../drm/i915/display/intel_display_types.h    |  3 ++
>  3 files changed, 24 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 0c7f91046996..a14bcda4446c 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -289,10 +289,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>  	drm_printf(&p, "scanline offset: %d\n",
>  		   intel_crtc_scanline_offset(pipe_config));
>  
> -	drm_printf(&p, "vblank delay: %d, framestart delay: %d, MSA timing delay: %d\n",
> +	drm_printf(&p, "vblank delay: %d, framestart delay: %d, MSA timing delay: %d set context latency: %d\n",
>  		   pipe_config->hw.adjusted_mode.crtc_vblank_start -
>  		   pipe_config->hw.adjusted_mode.crtc_vdisplay,
> -		   pipe_config->framestart_delay, pipe_config->msa_timing_delay);
> +		   pipe_config->framestart_delay, pipe_config->msa_timing_delay,
> +		   pipe_config->set_context_latency);
>  
>  	drm_printf(&p, "vrr: %s, fixed rr: %s, vmin: %d, vmax: %d, flipline: %d, pipeline full: %d, guardband: %d vsync start: %d, vsync end: %d\n",
>  		   str_yes_no(pipe_config->vrr.enable),
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 679c2a9baaee..5a7794387ea2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2361,17 +2361,18 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
>  	return 0;
>  }
>  
> -static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state)
> +static int intel_crtc_set_context_latency(struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> -	int vblank_delay = 0;
> +	int set_context_latency = 0;
>  
>  	if (!HAS_DSB(display))
>  		return 0;
>  
> -	vblank_delay = max(vblank_delay, intel_psr_min_set_context_latency(crtc_state));
> +	set_context_latency = max(set_context_latency,
> +				  intel_psr_min_set_context_latency(crtc_state));
>  
> -	return vblank_delay;
> +	return set_context_latency;
>  }
>  
>  static int intel_crtc_compute_vblank_delay(struct intel_atomic_state *state,

I think we should just do a full s/vblank_delay/set_context_latency/
pass over this function. Then it'll be clear that we are calculating
only the SCL here.

> @@ -2382,9 +2383,10 @@ static int intel_crtc_compute_vblank_delay(struct intel_atomic_state *state,
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
> -	int vblank_delay, max_vblank_delay;
> +	int vblank_delay = 0, max_vblank_delay;
>  
> -	vblank_delay = intel_crtc_vblank_delay(crtc_state);
> +	crtc_state->set_context_latency = intel_crtc_set_context_latency(crtc_state);
> +	vblank_delay += crtc_state->set_context_latency;
>  	max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1;
>  
>  	if (vblank_delay > max_vblank_delay) {
> @@ -2617,7 +2619,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  	if (DISPLAY_VER(display) >= 13) {
>  		intel_de_write(display,
>  			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
> -			       crtc_vblank_start - crtc_vdisplay);
> +			       crtc_state->set_context_latency);
>  
>  		/*
>  		 * VBLANK_START not used by hw, just clear it
> @@ -2707,7 +2709,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
>  	if (DISPLAY_VER(display) >= 13) {
>  		intel_de_write(display,
>  			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
> -			       crtc_vblank_start - crtc_vdisplay);
> +			       crtc_state->set_context_latency);
>  
>  		/*
>  		 * VBLANK_START not used by hw, just clear it
> @@ -2820,11 +2822,14 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
>  		adjusted_mode->crtc_vblank_end += 1;
>  	}
>  
> -	if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder))
> -		adjusted_mode->crtc_vblank_start =
> -			adjusted_mode->crtc_vdisplay +
> +	if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) {
> +		pipe_config->set_context_latency =
>  			intel_de_read(display,
>  				      TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder));
> +		adjusted_mode->crtc_vblank_start =
> +			adjusted_mode->crtc_vdisplay +
> +			pipe_config->set_context_latency;
> +	}
>  
>  	if (DISPLAY_VER(display) >= 30)
>  		pipe_config->min_hblank = intel_de_read(display,
> @@ -5387,6 +5392,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  		PIPE_CONF_CHECK_I(vrr.guardband);
>  	}
>  
> +	PIPE_CONF_CHECK_I(set_context_latency);
> +
>  #undef PIPE_CONF_CHECK_X
>  #undef PIPE_CONF_CHECK_I
>  #undef PIPE_CONF_CHECK_LLI
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 358ab922d7a7..a22fe77fcca1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1341,6 +1341,9 @@ struct intel_crtc_state {
>  
>  	/* LOBF flag */
>  	bool has_lobf;
> +
> +	/* W2 window or 'set context latency' lines */
> +	int set_context_latency;

This can be a u16. If there's a reasonable looking place with a
suitable hole I'd try to stick it there.

>  };
>  
>  enum intel_pipe_crc_source {
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 2/9] drm/i915/display: Add set_context_latency to crtc_state->vrr

[Nautiyal, Ankit K]

On 9/22/2025 3:30 PM, Ville Syrjälä wrote:
> On Sun, Sep 21, 2025 at 10:05:28AM +0530, Ankit Nautiyal wrote:
>> 'Set context latency' (Window W2) is defined as the number of lines before
>> the double buffering point, which are required to complete programming of
>> the registers, typically when DSB is used to program the display
>> registers.
>>
>> Since we are not using this window for programming the registers, this
>> is mostly set to 0, unless there is a requirement for few cases related
>> to PSR/PR where the 'set context latency' should be at least 1.
>>
>> Currently we are using the 'set context latency' (if required) implicitly
>> by moving the vblank start by the required amount and then measuring the
>> delay i.e. the difference between undelayed vblank start and delayed vblank
>> start.
>>
>> Since our guardband matches the vblank length, this was not a problem as
>> the difference between the undelayed vblank and delayed vblank was at
>> the most equal to the 'set context latency' lines.
>>
>> However, if we want to optimize the guardband, the difference between the
>> undelayed and the delayed vblank will be large and we cannot use this
>> difference as the 'set context latency' lines.
>>
>> To make way for this optimization of guardband, we formally introduce
>> the 'set context latency' and track it as a new member
>> `set_context_latency` of the intel_crtc_state.
>>
>> Eventually, all references of vblank delay where we mean to use set
>> context latency will be replaced by this new `set_context_latency`
>> member.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   .../drm/i915/display/intel_crtc_state_dump.c  |  5 ++--
>>   drivers/gpu/drm/i915/display/intel_display.c  | 29 ++++++++++++-------
>>   .../drm/i915/display/intel_display_types.h    |  3 ++
>>   3 files changed, 24 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>> index 0c7f91046996..a14bcda4446c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>> @@ -289,10 +289,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>>   	drm_printf(&p, "scanline offset: %d\n",
>>   		   intel_crtc_scanline_offset(pipe_config));
>>   
>> -	drm_printf(&p, "vblank delay: %d, framestart delay: %d, MSA timing delay: %d\n",
>> +	drm_printf(&p, "vblank delay: %d, framestart delay: %d, MSA timing delay: %d set context latency: %d\n",
>>   		   pipe_config->hw.adjusted_mode.crtc_vblank_start -
>>   		   pipe_config->hw.adjusted_mode.crtc_vdisplay,
>> -		   pipe_config->framestart_delay, pipe_config->msa_timing_delay);
>> +		   pipe_config->framestart_delay, pipe_config->msa_timing_delay,
>> +		   pipe_config->set_context_latency);
>>   
>>   	drm_printf(&p, "vrr: %s, fixed rr: %s, vmin: %d, vmax: %d, flipline: %d, pipeline full: %d, guardband: %d vsync start: %d, vsync end: %d\n",
>>   		   str_yes_no(pipe_config->vrr.enable),
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 679c2a9baaee..5a7794387ea2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -2361,17 +2361,18 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
>>   	return 0;
>>   }
>>   
>> -static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state)
>> +static int intel_crtc_set_context_latency(struct intel_crtc_state *crtc_state)
>>   {
>>   	struct intel_display *display = to_intel_display(crtc_state);
>> -	int vblank_delay = 0;
>> +	int set_context_latency = 0;
>>   
>>   	if (!HAS_DSB(display))
>>   		return 0;
>>   
>> -	vblank_delay = max(vblank_delay, intel_psr_min_set_context_latency(crtc_state));
>> +	set_context_latency = max(set_context_latency,
>> +				  intel_psr_min_set_context_latency(crtc_state));
>>   
>> -	return vblank_delay;
>> +	return set_context_latency;
>>   }
>>   
>>   static int intel_crtc_compute_vblank_delay(struct intel_atomic_state *state,
> I think we should just do a full s/vblank_delay/set_context_latency/
> pass over this function. Then it'll be clear that we are calculating
> only the SCL here.

Sure will change this.


>
>> @@ -2382,9 +2383,10 @@ static int intel_crtc_compute_vblank_delay(struct intel_atomic_state *state,
>>   		intel_atomic_get_new_crtc_state(state, crtc);
>>   	struct drm_display_mode *adjusted_mode =
>>   		&crtc_state->hw.adjusted_mode;
>> -	int vblank_delay, max_vblank_delay;
>> +	int vblank_delay = 0, max_vblank_delay;
>>   
>> -	vblank_delay = intel_crtc_vblank_delay(crtc_state);
>> +	crtc_state->set_context_latency = intel_crtc_set_context_latency(crtc_state);
>> +	vblank_delay += crtc_state->set_context_latency;
>>   	max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1;
>>   
>>   	if (vblank_delay > max_vblank_delay) {
>> @@ -2617,7 +2619,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>>   	if (DISPLAY_VER(display) >= 13) {
>>   		intel_de_write(display,
>>   			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
>> -			       crtc_vblank_start - crtc_vdisplay);
>> +			       crtc_state->set_context_latency);
>>   
>>   		/*
>>   		 * VBLANK_START not used by hw, just clear it
>> @@ -2707,7 +2709,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
>>   	if (DISPLAY_VER(display) >= 13) {
>>   		intel_de_write(display,
>>   			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
>> -			       crtc_vblank_start - crtc_vdisplay);
>> +			       crtc_state->set_context_latency);
>>   
>>   		/*
>>   		 * VBLANK_START not used by hw, just clear it
>> @@ -2820,11 +2822,14 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
>>   		adjusted_mode->crtc_vblank_end += 1;
>>   	}
>>   
>> -	if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder))
>> -		adjusted_mode->crtc_vblank_start =
>> -			adjusted_mode->crtc_vdisplay +
>> +	if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) {
>> +		pipe_config->set_context_latency =
>>   			intel_de_read(display,
>>   				      TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder));
>> +		adjusted_mode->crtc_vblank_start =
>> +			adjusted_mode->crtc_vdisplay +
>> +			pipe_config->set_context_latency;
>> +	}
>>   
>>   	if (DISPLAY_VER(display) >= 30)
>>   		pipe_config->min_hblank = intel_de_read(display,
>> @@ -5387,6 +5392,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>>   		PIPE_CONF_CHECK_I(vrr.guardband);
>>   	}
>>   
>> +	PIPE_CONF_CHECK_I(set_context_latency);
>> +
>>   #undef PIPE_CONF_CHECK_X
>>   #undef PIPE_CONF_CHECK_I
>>   #undef PIPE_CONF_CHECK_LLI
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 358ab922d7a7..a22fe77fcca1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1341,6 +1341,9 @@ struct intel_crtc_state {
>>   
>>   	/* LOBF flag */
>>   	bool has_lobf;
>> +
>> +	/* W2 window or 'set context latency' lines */
>> +	int set_context_latency;
> This can be a u16. If there's a reasonable looking place with a
> suitable hole I'd try to stick it there.

Alright, makes sense.


Regards,

Ankit

>
>>   };
>>   
>>   enum intel_pipe_crc_source {
>> -- 
>> 2.45.2

[PATCH 3/9] drm/i915/display: Use VBLANK_START to get the vblank delay for TGL

[Ankit Nautiyal]

For TGL the TRANS_SET_CONTEXT_LATENCY doesn't exist to account for SCL.
However, the VBLANK_START-VACTIVE diffence plays an identical role here ie.
it can be used to create the SCL window ahead of the undelayed vblank.

While readback there is no specific register to read out the SCL, so use
the same helper intel_crtc_compute_scl() and reduce the vblank_start by
this amount.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5a7794387ea2..455bbebb50a5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2822,6 +2822,16 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
 		adjusted_mode->crtc_vblank_end += 1;
 	}
 
+	if (DISPLAY_VER(display) == 12) {
+		/*
+		 * There is no specific register for SCL for TGL.
+		 * Derive the value from the helper intel_crtc_set_context_latency().
+		 * crtc_vblank_start needs to be reduced with this amount.
+		 */
+		pipe_config->set_context_latency = intel_crtc_set_context_latency(pipe_config);
+		adjusted_mode->crtc_vblank_start -= pipe_config->set_context_latency;
+	}
+
 	if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) {
 		pipe_config->set_context_latency =
 			intel_de_read(display,
-- 
2.45.2

Re: [PATCH 3/9] drm/i915/display: Use VBLANK_START to get the vblank delay for TGL

[Ville Syrjälä]

On Sun, Sep 21, 2025 at 10:05:29AM +0530, Ankit Nautiyal wrote:
> For TGL the TRANS_SET_CONTEXT_LATENCY doesn't exist to account for SCL.
> However, the VBLANK_START-VACTIVE diffence plays an identical role here ie.
> it can be used to create the SCL window ahead of the undelayed vblank.
> 
> While readback there is no specific register to read out the SCL, so use
> the same helper intel_crtc_compute_scl() and reduce the vblank_start by
> this amount.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 5a7794387ea2..455bbebb50a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2822,6 +2822,16 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
>  		adjusted_mode->crtc_vblank_end += 1;
>  	}
>  
> +	if (DISPLAY_VER(display) == 12) {
> +		/*
> +		 * There is no specific register for SCL for TGL.
> +		 * Derive the value from the helper intel_crtc_set_context_latency().
> +		 * crtc_vblank_start needs to be reduced with this amount.
> +		 */
> +		pipe_config->set_context_latency = intel_crtc_set_context_latency(pipe_config);

That thing *computes* the SCL, it doesn't teel us what the
current hw value is.

> +		adjusted_mode->crtc_vblank_start -= pipe_config->set_context_latency;
> +	}
> +
>  	if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) {
>  		pipe_config->set_context_latency =
>  			intel_de_read(display,

I think this whole thing needs to look something like this:

if (DISPLAY_VER >= 13 && !dsi) {
	set_context_latency = read(TRANS_SET_CONTEXT_LATENCY);
	crtc_vblank_start = crtc_vdisplay + set_set_context_latency;
} else if (DISPLAY_VER >= 12) {
	set_context_latency = crtc_vblank_start - crtc_vdisplay;
}

That'll also cover DSI (not that the DSI code itself is actually
ready for SCL...).

And I think you need to squash this into the set_context_latency
patch. Otherwise we'll get state checker mismatches on TGL in
between.

-- 
Ville Syrjälä
Intel

Re: [PATCH 3/9] drm/i915/display: Use VBLANK_START to get the vblank delay for TGL

[Nautiyal, Ankit K]

On 9/22/2025 3:37 PM, Ville Syrjälä wrote:
> On Sun, Sep 21, 2025 at 10:05:29AM +0530, Ankit Nautiyal wrote:
>> For TGL the TRANS_SET_CONTEXT_LATENCY doesn't exist to account for SCL.
>> However, the VBLANK_START-VACTIVE diffence plays an identical role here ie.
>> it can be used to create the SCL window ahead of the undelayed vblank.
>>
>> While readback there is no specific register to read out the SCL, so use
>> the same helper intel_crtc_compute_scl() and reduce the vblank_start by
>> this amount.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++++
>>   1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 5a7794387ea2..455bbebb50a5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -2822,6 +2822,16 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
>>   		adjusted_mode->crtc_vblank_end += 1;
>>   	}
>>   
>> +	if (DISPLAY_VER(display) == 12) {
>> +		/*
>> +		 * There is no specific register for SCL for TGL.
>> +		 * Derive the value from the helper intel_crtc_set_context_latency().
>> +		 * crtc_vblank_start needs to be reduced with this amount.
>> +		 */
>> +		pipe_config->set_context_latency = intel_crtc_set_context_latency(pipe_config);
> That thing *computes* the SCL, it doesn't teel us what the
> current hw value is.
>
>> +		adjusted_mode->crtc_vblank_start -= pipe_config->set_context_latency;
>> +	}
>> +
>>   	if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) {
>>   		pipe_config->set_context_latency =
>>   			intel_de_read(display,
> I think this whole thing needs to look something like this:
>
> if (DISPLAY_VER >= 13 && !dsi) {
> 	set_context_latency = read(TRANS_SET_CONTEXT_LATENCY);
> 	crtc_vblank_start = crtc_vdisplay + set_set_context_latency;
> } else if (DISPLAY_VER >= 12) {
> 	set_context_latency = crtc_vblank_start - crtc_vdisplay;

I was wondering if we optimize the guardband for TGL, this will be a 
problem. It will make set_context_latency huge for TGL.

Or shall we drop the guardband optimization changes for TGL?


> }
>
> That'll also cover DSI (not that the DSI code itself is actually
> ready for SCL...).
>
> And I think you need to squash this into the set_context_latency
> patch. Otherwise we'll get state checker mismatches on TGL in
> between.

Yes right, I just wanted to get comments specific to this patch :) .

This change does belong to the previous patch.


Regards,

Ankit


>

Re: [PATCH 3/9] drm/i915/display: Use VBLANK_START to get the vblank delay for TGL

[Ville Syrjälä]

On Mon, Sep 22, 2025 at 03:50:17PM +0530, Nautiyal, Ankit K wrote:
> 
> On 9/22/2025 3:37 PM, Ville Syrjälä wrote:
> > On Sun, Sep 21, 2025 at 10:05:29AM +0530, Ankit Nautiyal wrote:
> >> For TGL the TRANS_SET_CONTEXT_LATENCY doesn't exist to account for SCL.
> >> However, the VBLANK_START-VACTIVE diffence plays an identical role here ie.
> >> it can be used to create the SCL window ahead of the undelayed vblank.
> >>
> >> While readback there is no specific register to read out the SCL, so use
> >> the same helper intel_crtc_compute_scl() and reduce the vblank_start by
> >> this amount.
> >>
> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++++
> >>   1 file changed, 10 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> >> index 5a7794387ea2..455bbebb50a5 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -2822,6 +2822,16 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
> >>   		adjusted_mode->crtc_vblank_end += 1;
> >>   	}
> >>   
> >> +	if (DISPLAY_VER(display) == 12) {
> >> +		/*
> >> +		 * There is no specific register for SCL for TGL.
> >> +		 * Derive the value from the helper intel_crtc_set_context_latency().
> >> +		 * crtc_vblank_start needs to be reduced with this amount.
> >> +		 */
> >> +		pipe_config->set_context_latency = intel_crtc_set_context_latency(pipe_config);
> > That thing *computes* the SCL, it doesn't teel us what the
> > current hw value is.
> >
> >> +		adjusted_mode->crtc_vblank_start -= pipe_config->set_context_latency;
> >> +	}
> >> +
> >>   	if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) {
> >>   		pipe_config->set_context_latency =
> >>   			intel_de_read(display,
> > I think this whole thing needs to look something like this:
> >
> > if (DISPLAY_VER >= 13 && !dsi) {
> > 	set_context_latency = read(TRANS_SET_CONTEXT_LATENCY);
> > 	crtc_vblank_start = crtc_vdisplay + set_set_context_latency;
> > } else if (DISPLAY_VER >= 12) {
> > 	set_context_latency = crtc_vblank_start - crtc_vdisplay;
> 
> I was wondering if we optimize the guardband for TGL, this will be a 
> problem. It will make set_context_latency huge for TGL.
> 
> Or shall we drop the guardband optimization changes for TGL?

We'll anyway clamp the guardband to the hw/vblank max.

So the initial value we can calculate any which way we want (as long
as we don't calculate it to be too small since that will either make
the commit fail, or will burn away power needleslly).

> 
> 
> > }
> >
> > That'll also cover DSI (not that the DSI code itself is actually
> > ready for SCL...).
> >
> > And I think you need to squash this into the set_context_latency
> > patch. Otherwise we'll get state checker mismatches on TGL in
> > between.
> 
> Yes right, I just wanted to get comments specific to this patch :) .
> 
> This change does belong to the previous patch.
> 
> 
> Regards,
> 
> Ankit
> 
> 
> >

-- 
Ville Syrjälä
Intel

[PATCH 4/9] drm/i915/vrr: Use set_context_latency instead of intel_vrr_real_vblank_delay()

[Ankit Nautiyal]

The helper intel_vrr_real_vblank_delay() was added to account for the
SCL lines for TGL where we do not have the TRANS_SET_CONTEXT_LATENCY.

Now, since we already are tracking the SCL with new member
`set_context_latency` use it directly instead of the helper.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 16 +++++-----------
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 9e007aab1452..698b33b5b326 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -79,12 +79,6 @@ intel_vrr_check_modeset(struct intel_atomic_state *state)
 	}
 }
 
-static int intel_vrr_real_vblank_delay(const struct intel_crtc_state *crtc_state)
-{
-	return crtc_state->hw.adjusted_mode.crtc_vblank_start -
-		crtc_state->hw.adjusted_mode.crtc_vdisplay;
-}
-
 static int intel_vrr_extra_vblank_delay(struct intel_display *display)
 {
 	/*
@@ -102,7 +96,7 @@ int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
-	return intel_vrr_real_vblank_delay(crtc_state) +
+	return crtc_state->set_context_latency +
 		intel_vrr_extra_vblank_delay(display);
 }
 
@@ -263,7 +257,7 @@ static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
 	if (DISPLAY_VER(display) >= 13)
 		return value;
 	else
-		return value - intel_vrr_real_vblank_delay(crtc_state);
+		return value - crtc_state->set_context_latency;
 }
 
 /*
@@ -761,9 +755,9 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 
 		if (DISPLAY_VER(display) < 13) {
 			/* undo what intel_vrr_hw_value() does when writing the values */
-			crtc_state->vrr.flipline += intel_vrr_real_vblank_delay(crtc_state);
-			crtc_state->vrr.vmax += intel_vrr_real_vblank_delay(crtc_state);
-			crtc_state->vrr.vmin += intel_vrr_real_vblank_delay(crtc_state);
+			crtc_state->vrr.flipline += crtc_state->set_context_latency;
+			crtc_state->vrr.vmax += crtc_state->set_context_latency;
+			crtc_state->vrr.vmin += crtc_state->set_context_latency;
 
 			crtc_state->vrr.vmin += intel_vrr_vmin_flipline_offset(display);
 		}
-- 
2.45.2

Re: [PATCH 4/9] drm/i915/vrr: Use set_context_latency instead of intel_vrr_real_vblank_delay()

[Ville Syrjälä]

On Sun, Sep 21, 2025 at 10:05:30AM +0530, Ankit Nautiyal wrote:
> The helper intel_vrr_real_vblank_delay() was added to account for the
> SCL lines for TGL where we do not have the TRANS_SET_CONTEXT_LATENCY.
> 
> Now, since we already are tracking the SCL with new member
> `set_context_latency` use it directly instead of the helper.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I think right after this patch you could also do a patch to 
change the guardband calculation to something like:

guardband = vmin - crtc_vdisplay -
	intel_vrr_extra_vblank_delay() -
	crtc_state->set_context_latency;

That better reflects how the hardware opearates.

> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 16 +++++-----------
>  1 file changed, 5 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 9e007aab1452..698b33b5b326 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -79,12 +79,6 @@ intel_vrr_check_modeset(struct intel_atomic_state *state)
>  	}
>  }
>  
> -static int intel_vrr_real_vblank_delay(const struct intel_crtc_state *crtc_state)
> -{
> -	return crtc_state->hw.adjusted_mode.crtc_vblank_start -
> -		crtc_state->hw.adjusted_mode.crtc_vdisplay;
> -}
> -
>  static int intel_vrr_extra_vblank_delay(struct intel_display *display)
>  {
>  	/*
> @@ -102,7 +96,7 @@ int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  
> -	return intel_vrr_real_vblank_delay(crtc_state) +
> +	return crtc_state->set_context_latency +
>  		intel_vrr_extra_vblank_delay(display);
>  }
>  
> @@ -263,7 +257,7 @@ static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
>  	if (DISPLAY_VER(display) >= 13)
>  		return value;
>  	else
> -		return value - intel_vrr_real_vblank_delay(crtc_state);
> +		return value - crtc_state->set_context_latency;
>  }
>  
>  /*
> @@ -761,9 +755,9 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>  
>  		if (DISPLAY_VER(display) < 13) {
>  			/* undo what intel_vrr_hw_value() does when writing the values */
> -			crtc_state->vrr.flipline += intel_vrr_real_vblank_delay(crtc_state);
> -			crtc_state->vrr.vmax += intel_vrr_real_vblank_delay(crtc_state);
> -			crtc_state->vrr.vmin += intel_vrr_real_vblank_delay(crtc_state);
> +			crtc_state->vrr.flipline += crtc_state->set_context_latency;
> +			crtc_state->vrr.vmax += crtc_state->set_context_latency;
> +			crtc_state->vrr.vmin += crtc_state->set_context_latency;
>  
>  			crtc_state->vrr.vmin += intel_vrr_vmin_flipline_offset(display);
>  		}
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 4/9] drm/i915/vrr: Use set_context_latency instead of intel_vrr_real_vblank_delay()

[Nautiyal, Ankit K]

On 9/22/2025 3:44 PM, Ville Syrjälä wrote:
> On Sun, Sep 21, 2025 at 10:05:30AM +0530, Ankit Nautiyal wrote:
>> The helper intel_vrr_real_vblank_delay() was added to account for the
>> SCL lines for TGL where we do not have the TRANS_SET_CONTEXT_LATENCY.
>>
>> Now, since we already are tracking the SCL with new member
>> `set_context_latency` use it directly instead of the helper.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> I think right after this patch you could also do a patch to
> change the guardband calculation to something like:
>
> guardband = vmin - crtc_vdisplay -
> 	intel_vrr_extra_vblank_delay() -
> 	crtc_state->set_context_latency;
>
> That better reflects how the hardware opearates.


Sure will make a separate patch for this.


Regards,

Ankit

>
>> ---
>>   drivers/gpu/drm/i915/display/intel_vrr.c | 16 +++++-----------
>>   1 file changed, 5 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 9e007aab1452..698b33b5b326 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -79,12 +79,6 @@ intel_vrr_check_modeset(struct intel_atomic_state *state)
>>   	}
>>   }
>>   
>> -static int intel_vrr_real_vblank_delay(const struct intel_crtc_state *crtc_state)
>> -{
>> -	return crtc_state->hw.adjusted_mode.crtc_vblank_start -
>> -		crtc_state->hw.adjusted_mode.crtc_vdisplay;
>> -}
>> -
>>   static int intel_vrr_extra_vblank_delay(struct intel_display *display)
>>   {
>>   	/*
>> @@ -102,7 +96,7 @@ int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state)
>>   {
>>   	struct intel_display *display = to_intel_display(crtc_state);
>>   
>> -	return intel_vrr_real_vblank_delay(crtc_state) +
>> +	return crtc_state->set_context_latency +
>>   		intel_vrr_extra_vblank_delay(display);
>>   }
>>   
>> @@ -263,7 +257,7 @@ static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
>>   	if (DISPLAY_VER(display) >= 13)
>>   		return value;
>>   	else
>> -		return value - intel_vrr_real_vblank_delay(crtc_state);
>> +		return value - crtc_state->set_context_latency;
>>   }
>>   
>>   /*
>> @@ -761,9 +755,9 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>>   
>>   		if (DISPLAY_VER(display) < 13) {
>>   			/* undo what intel_vrr_hw_value() does when writing the values */
>> -			crtc_state->vrr.flipline += intel_vrr_real_vblank_delay(crtc_state);
>> -			crtc_state->vrr.vmax += intel_vrr_real_vblank_delay(crtc_state);
>> -			crtc_state->vrr.vmin += intel_vrr_real_vblank_delay(crtc_state);
>> +			crtc_state->vrr.flipline += crtc_state->set_context_latency;
>> +			crtc_state->vrr.vmax += crtc_state->set_context_latency;
>> +			crtc_state->vrr.vmin += crtc_state->set_context_latency;
>>   
>>   			crtc_state->vrr.vmin += intel_vrr_vmin_flipline_offset(display);
>>   		}
>> -- 
>> 2.45.2

[PATCH 5/9] drm/i915/vrr: s/intel_vrr_vblank_delay/intel_vrr_scl_delay

[Ankit Nautiyal]

The helper intel_vrr_vblank_delay() is used to account for scl lines
+ extra_vblank_delay (for ICL/TGL case) for:
- evasion logic for vrr case
- to wait for SCL+ lines after send push operation.

Rename the helper to intel_vrr_scl_delay since we are interested in the
SCL+ lines for the VRR cases.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c    | 4 ++--
 drivers/gpu/drm/i915/display/intel_vblank.c | 2 +-
 drivers/gpu/drm/i915/display/intel_vrr.c    | 2 +-
 drivers/gpu/drm/i915/display/intel_vrr.h    | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index dee44d45b668..ca31e928ecb0 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -128,7 +128,7 @@ static int dsb_vblank_delay(struct intel_atomic_state *state,
 		 * scanline until the delayed vblank occurs after
 		 * TRANS_PUSH has been written.
 		 */
-		return intel_vrr_vblank_delay(crtc_state) + 1;
+		return intel_vrr_scl_delay(crtc_state) + 1;
 	else
 		return intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
 }
@@ -723,7 +723,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
 		intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
 
 	if (pre_commit_is_vrr_active(state, crtc)) {
-		int vblank_delay = intel_vrr_vblank_delay(crtc_state);
+		int vblank_delay = intel_vrr_scl_delay(crtc_state);
 
 		end = intel_vrr_vmin_vblank_start(crtc_state);
 		start = end - vblank_delay - latency;
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index c15234c1d96e..9441b7bacd27 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -681,7 +681,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 		else
 			evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
 
-		vblank_delay = intel_vrr_vblank_delay(crtc_state);
+		vblank_delay = intel_vrr_scl_delay(crtc_state);
 	} else {
 		evade->vblank_start = intel_mode_vblank_start(adjusted_mode);
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 698b33b5b326..5fa86356a791 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -92,7 +92,7 @@ static int intel_vrr_extra_vblank_delay(struct intel_display *display)
 	return DISPLAY_VER(display) < 13 ? 1 : 0;
 }
 
-int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state)
+int intel_vrr_scl_delay(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 38bf9996b883..b72e90b4abe5 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -35,7 +35,7 @@ int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state);
-int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state);
+int intel_vrr_scl_delay(const struct intel_crtc_state *crtc_state);
 bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state);
 void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
-- 
2.45.2

[PATCH 6/9] drm/i915/display: Use set context latency in evasion logic

[Ankit Nautiyal]

Currently we use difference between vactive and vblank delay to
implicitly wait for SCL lines.

Remove the function intel_mode_vblank_delay as we can simply use
the set context latency instead.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c    | 4 ++--
 drivers/gpu/drm/i915/display/intel_vblank.c | 7 +------
 drivers/gpu/drm/i915/display/intel_vblank.h | 1 -
 3 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index ca31e928ecb0..dfe928aefdcd 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -130,7 +130,7 @@ static int dsb_vblank_delay(struct intel_atomic_state *state,
 		 */
 		return intel_vrr_scl_delay(crtc_state) + 1;
 	else
-		return intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
+		return crtc_state->set_context_latency;
 }
 
 static int dsb_vtotal(struct intel_atomic_state *state,
@@ -733,7 +733,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
 		start = end - vblank_delay - latency;
 		intel_dsb_wait_scanline_out(state, dsb, start, end);
 	} else {
-		int vblank_delay = intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
+		int vblank_delay = crtc_state->set_context_latency;
 
 		end = intel_mode_vblank_start(&crtc_state->hw.adjusted_mode);
 		start = end - vblank_delay - latency;
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 9441b7bacd27..8c4cb6913ef9 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -619,11 +619,6 @@ int intel_mode_vtotal(const struct drm_display_mode *mode)
 	return vtotal;
 }
 
-int intel_mode_vblank_delay(const struct drm_display_mode *mode)
-{
-	return intel_mode_vblank_start(mode) - intel_mode_vdisplay(mode);
-}
-
 static const struct intel_crtc_state *
 pre_commit_crtc_state(const struct intel_crtc_state *old_crtc_state,
 		      const struct intel_crtc_state *new_crtc_state)
@@ -685,7 +680,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 	} else {
 		evade->vblank_start = intel_mode_vblank_start(adjusted_mode);
 
-		vblank_delay = intel_mode_vblank_delay(adjusted_mode);
+		vblank_delay = crtc_state->set_context_latency;
 	}
 
 	/* FIXME needs to be calibrated sensibly */
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h
index 21fbb08d61d5..0fd6f7aeffd4 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.h
+++ b/drivers/gpu/drm/i915/display/intel_vblank.h
@@ -25,7 +25,6 @@ int intel_mode_vdisplay(const struct drm_display_mode *mode);
 int intel_mode_vblank_start(const struct drm_display_mode *mode);
 int intel_mode_vblank_end(const struct drm_display_mode *mode);
 int intel_mode_vtotal(const struct drm_display_mode *mode);
-int intel_mode_vblank_delay(const struct drm_display_mode *mode);
 
 void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 			     const struct intel_crtc_state *new_crtc_state,
-- 
2.45.2

Re: [PATCH 6/9] drm/i915/display: Use set context latency in evasion logic

[Ville Syrjälä]

On Sun, Sep 21, 2025 at 10:05:32AM +0530, Ankit Nautiyal wrote:
> Currently we use difference between vactive and vblank delay to
> implicitly wait for SCL lines.
> 
> Remove the function intel_mode_vblank_delay as we can simply use
> the set context latency instead.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dsb.c    | 4 ++--
>  drivers/gpu/drm/i915/display/intel_vblank.c | 7 +------
>  drivers/gpu/drm/i915/display/intel_vblank.h | 1 -
>  3 files changed, 3 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index ca31e928ecb0..dfe928aefdcd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -130,7 +130,7 @@ static int dsb_vblank_delay(struct intel_atomic_state *state,
>  		 */
>  		return intel_vrr_scl_delay(crtc_state) + 1;
>  	else
> -		return intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
> +		return crtc_state->set_context_latency;

I think we want to leave all the non-VRR cases to use
intel_mode_vblank_delay(). Otherwise when running with fixed
refresh rate we won't account for a reduced guardband.

And for the cases where the fixed refresh rate is handle by the legacy
timing generator we actually need a slightly different delay for the
legacy and VRR timing generators on TGL (due to
intel_vrr_extra_vblank_delay() only affecting the VRR timing generator).

>  }
>  
>  static int dsb_vtotal(struct intel_atomic_state *state,
> @@ -733,7 +733,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
>  		start = end - vblank_delay - latency;
>  		intel_dsb_wait_scanline_out(state, dsb, start, end);
>  	} else {
> -		int vblank_delay = intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
> +		int vblank_delay = crtc_state->set_context_latency;
>  
>  		end = intel_mode_vblank_start(&crtc_state->hw.adjusted_mode);
>  		start = end - vblank_delay - latency;
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> index 9441b7bacd27..8c4cb6913ef9 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -619,11 +619,6 @@ int intel_mode_vtotal(const struct drm_display_mode *mode)
>  	return vtotal;
>  }
>  
> -int intel_mode_vblank_delay(const struct drm_display_mode *mode)
> -{
> -	return intel_mode_vblank_start(mode) - intel_mode_vdisplay(mode);
> -}
> -
>  static const struct intel_crtc_state *
>  pre_commit_crtc_state(const struct intel_crtc_state *old_crtc_state,
>  		      const struct intel_crtc_state *new_crtc_state)
> @@ -685,7 +680,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
>  	} else {
>  		evade->vblank_start = intel_mode_vblank_start(adjusted_mode);
>  
> -		vblank_delay = intel_mode_vblank_delay(adjusted_mode);
> +		vblank_delay = crtc_state->set_context_latency;
>  	}
>  
>  	/* FIXME needs to be calibrated sensibly */
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h
> index 21fbb08d61d5..0fd6f7aeffd4 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.h
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.h
> @@ -25,7 +25,6 @@ int intel_mode_vdisplay(const struct drm_display_mode *mode);
>  int intel_mode_vblank_start(const struct drm_display_mode *mode);
>  int intel_mode_vblank_end(const struct drm_display_mode *mode);
>  int intel_mode_vtotal(const struct drm_display_mode *mode);
> -int intel_mode_vblank_delay(const struct drm_display_mode *mode);
>  
>  void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
>  			     const struct intel_crtc_state *new_crtc_state,
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 6/9] drm/i915/display: Use set context latency in evasion logic

[Ville Syrjälä]

On Mon, Sep 22, 2025 at 01:18:06PM +0300, Ville Syrjälä wrote:
> On Sun, Sep 21, 2025 at 10:05:32AM +0530, Ankit Nautiyal wrote:
> > Currently we use difference between vactive and vblank delay to
> > implicitly wait for SCL lines.
> > 
> > Remove the function intel_mode_vblank_delay as we can simply use
> > the set context latency instead.
> > 
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dsb.c    | 4 ++--
> >  drivers/gpu/drm/i915/display/intel_vblank.c | 7 +------
> >  drivers/gpu/drm/i915/display/intel_vblank.h | 1 -
> >  3 files changed, 3 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> > index ca31e928ecb0..dfe928aefdcd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> > @@ -130,7 +130,7 @@ static int dsb_vblank_delay(struct intel_atomic_state *state,
> >  		 */
> >  		return intel_vrr_scl_delay(crtc_state) + 1;
> >  	else
> > -		return intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
> > +		return crtc_state->set_context_latency;
> 
> I think we want to leave all the non-VRR cases to use
> intel_mode_vblank_delay(). Otherwise when running with fixed
> refresh rate we won't account for a reduced guardband.
> 
> And for the cases where the fixed refresh rate is handle by the legacy
> timing generator we actually need a slightly different delay for the
> legacy and VRR timing generators on TGL (due to
> intel_vrr_extra_vblank_delay() only affecting the VRR timing generator).

Just to elaborate on this, I am thinking that adjusted_mode.crtc_vblank_start
should *always* match the delayed vblank for the fixed refresh rate timings.

So I am envisioning the following rules:

always_use_vrr_tg():
	crtc_vblank_start should reflect the undelayed vblank
	for the VRR TG fixed refresh rate case (ie. fixed_rr_vtotal - guardband).
	This should in fact be the same for both the VRR timings and fixed
	RR timings because the vmin and guardband should be the same for both.

!always_use_vrr_tg()
	crtc_vblank_start should reflect the undelayed vblank
	for the legacy TG (ie. vactive + SCL). The VRR timing
	generator's vblank can be different here due to reduced
	guardband.

This is rather important when we're doing a full modeset and userspace
has already requested vrr.enable=true. The actual modeset part will be
excuted while still running with the fixed refresh rate timings (either
using VRR TG or legacy TG depending on always_use_vrr_tg()). So the
vblank evasion prior to commit_arm() will need to know the correct
position of the delayed vblank for the fixed RR timings. We will then
switch over to the VRR timings (and possibly to the other timing
generator) during the actul commit.

This also means that intel_mode_vblank_delay() will always give us
the total delay betweern the undelayed vblank and delayed vblank for
the fixed RR timings. And this is exactly what we want
for eg. intel_dsb_wait_vblank_delay() since we will have configured
DSB_CHICKEN to use the undelayed vblank (as opposed to safe window)
and thus intel_dsb_wait_vblanks()/DSB_WAIT_FOR_VBLANK will wait for
the undelayed vblank.

> 
> >  }
> >  
> >  static int dsb_vtotal(struct intel_atomic_state *state,
> > @@ -733,7 +733,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
> >  		start = end - vblank_delay - latency;
> >  		intel_dsb_wait_scanline_out(state, dsb, start, end);
> >  	} else {
> > -		int vblank_delay = intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
> > +		int vblank_delay = crtc_state->set_context_latency;
> >  
> >  		end = intel_mode_vblank_start(&crtc_state->hw.adjusted_mode);
> >  		start = end - vblank_delay - latency;
> > diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> > index 9441b7bacd27..8c4cb6913ef9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> > @@ -619,11 +619,6 @@ int intel_mode_vtotal(const struct drm_display_mode *mode)
> >  	return vtotal;
> >  }
> >  
> > -int intel_mode_vblank_delay(const struct drm_display_mode *mode)
> > -{
> > -	return intel_mode_vblank_start(mode) - intel_mode_vdisplay(mode);
> > -}
> > -
> >  static const struct intel_crtc_state *
> >  pre_commit_crtc_state(const struct intel_crtc_state *old_crtc_state,
> >  		      const struct intel_crtc_state *new_crtc_state)
> > @@ -685,7 +680,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
> >  	} else {
> >  		evade->vblank_start = intel_mode_vblank_start(adjusted_mode);
> >  
> > -		vblank_delay = intel_mode_vblank_delay(adjusted_mode);
> > +		vblank_delay = crtc_state->set_context_latency;
> >  	}
> >  
> >  	/* FIXME needs to be calibrated sensibly */
> > diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h
> > index 21fbb08d61d5..0fd6f7aeffd4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vblank.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vblank.h
> > @@ -25,7 +25,6 @@ int intel_mode_vdisplay(const struct drm_display_mode *mode);
> >  int intel_mode_vblank_start(const struct drm_display_mode *mode);
> >  int intel_mode_vblank_end(const struct drm_display_mode *mode);
> >  int intel_mode_vtotal(const struct drm_display_mode *mode);
> > -int intel_mode_vblank_delay(const struct drm_display_mode *mode);
> >  
> >  void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
> >  			     const struct intel_crtc_state *new_crtc_state,
> > -- 
> > 2.45.2
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH 6/9] drm/i915/display: Use set context latency in evasion logic

[Ville Syrjälä]

On Mon, Sep 22, 2025 at 02:19:39PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 22, 2025 at 01:18:06PM +0300, Ville Syrjälä wrote:
> > On Sun, Sep 21, 2025 at 10:05:32AM +0530, Ankit Nautiyal wrote:
> > > Currently we use difference between vactive and vblank delay to
> > > implicitly wait for SCL lines.
> > > 
> > > Remove the function intel_mode_vblank_delay as we can simply use
> > > the set context latency instead.
> > > 
> > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dsb.c    | 4 ++--
> > >  drivers/gpu/drm/i915/display/intel_vblank.c | 7 +------
> > >  drivers/gpu/drm/i915/display/intel_vblank.h | 1 -
> > >  3 files changed, 3 insertions(+), 9 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> > > index ca31e928ecb0..dfe928aefdcd 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> > > @@ -130,7 +130,7 @@ static int dsb_vblank_delay(struct intel_atomic_state *state,
> > >  		 */
> > >  		return intel_vrr_scl_delay(crtc_state) + 1;
> > >  	else
> > > -		return intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
> > > +		return crtc_state->set_context_latency;
> > 
> > I think we want to leave all the non-VRR cases to use
> > intel_mode_vblank_delay(). Otherwise when running with fixed
> > refresh rate we won't account for a reduced guardband.
> > 
> > And for the cases where the fixed refresh rate is handle by the legacy
> > timing generator we actually need a slightly different delay for the
> > legacy and VRR timing generators on TGL (due to
> > intel_vrr_extra_vblank_delay() only affecting the VRR timing generator).
> 
> Just to elaborate on this, I am thinking that adjusted_mode.crtc_vblank_start
> should *always* match the delayed vblank for the fixed refresh rate timings.
> 
> So I am envisioning the following rules:
> 
> always_use_vrr_tg():
> 	crtc_vblank_start should reflect the undelayed vblank

Ugh. *delayed vblank* of course

> 	for the VRR TG fixed refresh rate case (ie. fixed_rr_vtotal - guardband).
> 	This should in fact be the same for both the VRR timings and fixed
> 	RR timings because the vmin and guardband should be the same for both.
> 
> !always_use_vrr_tg()
> 	crtc_vblank_start should reflect the undelayed vblank

ditto

> 	for the legacy TG (ie. vactive + SCL). The VRR timing
> 	generator's vblank can be different here due to reduced
> 	guardband.
> 
> This is rather important when we're doing a full modeset and userspace
> has already requested vrr.enable=true. The actual modeset part will be
> excuted while still running with the fixed refresh rate timings (either
> using VRR TG or legacy TG depending on always_use_vrr_tg()). So the
> vblank evasion prior to commit_arm() will need to know the correct
> position of the delayed vblank for the fixed RR timings. We will then
> switch over to the VRR timings (and possibly to the other timing
> generator) during the actul commit.
> 
> This also means that intel_mode_vblank_delay() will always give us
> the total delay betweern the undelayed vblank and delayed vblank for
> the fixed RR timings. And this is exactly what we want
> for eg. intel_dsb_wait_vblank_delay() since we will have configured
> DSB_CHICKEN to use the undelayed vblank (as opposed to safe window)
> and thus intel_dsb_wait_vblanks()/DSB_WAIT_FOR_VBLANK will wait for
> the undelayed vblank.
> 
> > 
> > >  }
> > >  
> > >  static int dsb_vtotal(struct intel_atomic_state *state,
> > > @@ -733,7 +733,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
> > >  		start = end - vblank_delay - latency;
> > >  		intel_dsb_wait_scanline_out(state, dsb, start, end);
> > >  	} else {
> > > -		int vblank_delay = intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
> > > +		int vblank_delay = crtc_state->set_context_latency;
> > >  
> > >  		end = intel_mode_vblank_start(&crtc_state->hw.adjusted_mode);
> > >  		start = end - vblank_delay - latency;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> > > index 9441b7bacd27..8c4cb6913ef9 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> > > @@ -619,11 +619,6 @@ int intel_mode_vtotal(const struct drm_display_mode *mode)
> > >  	return vtotal;
> > >  }
> > >  
> > > -int intel_mode_vblank_delay(const struct drm_display_mode *mode)
> > > -{
> > > -	return intel_mode_vblank_start(mode) - intel_mode_vdisplay(mode);
> > > -}
> > > -
> > >  static const struct intel_crtc_state *
> > >  pre_commit_crtc_state(const struct intel_crtc_state *old_crtc_state,
> > >  		      const struct intel_crtc_state *new_crtc_state)
> > > @@ -685,7 +680,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
> > >  	} else {
> > >  		evade->vblank_start = intel_mode_vblank_start(adjusted_mode);
> > >  
> > > -		vblank_delay = intel_mode_vblank_delay(adjusted_mode);
> > > +		vblank_delay = crtc_state->set_context_latency;
> > >  	}
> > >  
> > >  	/* FIXME needs to be calibrated sensibly */
> > > diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h
> > > index 21fbb08d61d5..0fd6f7aeffd4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_vblank.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_vblank.h
> > > @@ -25,7 +25,6 @@ int intel_mode_vdisplay(const struct drm_display_mode *mode);
> > >  int intel_mode_vblank_start(const struct drm_display_mode *mode);
> > >  int intel_mode_vblank_end(const struct drm_display_mode *mode);
> > >  int intel_mode_vtotal(const struct drm_display_mode *mode);
> > > -int intel_mode_vblank_delay(const struct drm_display_mode *mode);
> > >  
> > >  void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
> > >  			     const struct intel_crtc_state *new_crtc_state,
> > > -- 
> > > 2.45.2
> > 
> > -- 
> > Ville Syrjälä
> > Intel
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH 6/9] drm/i915/display: Use set context latency in evasion logic

[Nautiyal, Ankit K]

On 9/22/2025 5:00 PM, Ville Syrjälä wrote:
> On Mon, Sep 22, 2025 at 02:19:39PM +0300, Ville Syrjälä wrote:
>> On Mon, Sep 22, 2025 at 01:18:06PM +0300, Ville Syrjälä wrote:
>>> On Sun, Sep 21, 2025 at 10:05:32AM +0530, Ankit Nautiyal wrote:
>>>> Currently we use difference between vactive and vblank delay to
>>>> implicitly wait for SCL lines.
>>>>
>>>> Remove the function intel_mode_vblank_delay as we can simply use
>>>> the set context latency instead.
>>>>
>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> ---
>>>>   drivers/gpu/drm/i915/display/intel_dsb.c    | 4 ++--
>>>>   drivers/gpu/drm/i915/display/intel_vblank.c | 7 +------
>>>>   drivers/gpu/drm/i915/display/intel_vblank.h | 1 -
>>>>   3 files changed, 3 insertions(+), 9 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
>>>> index ca31e928ecb0..dfe928aefdcd 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>>>> @@ -130,7 +130,7 @@ static int dsb_vblank_delay(struct intel_atomic_state *state,
>>>>   		 */
>>>>   		return intel_vrr_scl_delay(crtc_state) + 1;
>>>>   	else
>>>> -		return intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
>>>> +		return crtc_state->set_context_latency;
>>> I think we want to leave all the non-VRR cases to use
>>> intel_mode_vblank_delay(). Otherwise when running with fixed
>>> refresh rate we won't account for a reduced guardband.
>>>
>>> And for the cases where the fixed refresh rate is handle by the legacy
>>> timing generator we actually need a slightly different delay for the
>>> legacy and VRR timing generators on TGL (due to
>>> intel_vrr_extra_vblank_delay() only affecting the VRR timing generator).
>> Just to elaborate on this, I am thinking that adjusted_mode.crtc_vblank_start
>> should *always* match the delayed vblank for the fixed refresh rate timings.
>>
>> So I am envisioning the following rules:
>>
>> always_use_vrr_tg():
>> 	crtc_vblank_start should reflect the undelayed vblank
> Ugh. *delayed vblank* of course
>
>> 	for the VRR TG fixed refresh rate case (ie. fixed_rr_vtotal - guardband).
>> 	This should in fact be the same for both the VRR timings and fixed
>> 	RR timings because the vmin and guardband should be the same for both.
>>
>> !always_use_vrr_tg()
>> 	crtc_vblank_start should reflect the undelayed vblank
> ditto


Ok, will drop this patch and will take care of this in the series to use 
min guardband. Thanks!


Regards,

Ankit

>
>> 	for the legacy TG (ie. vactive + SCL). The VRR timing
>> 	generator's vblank can be different here due to reduced
>> 	guardband.
>>
>> This is rather important when we're doing a full modeset and userspace
>> has already requested vrr.enable=true. The actual modeset part will be
>> excuted while still running with the fixed refresh rate timings (either
>> using VRR TG or legacy TG depending on always_use_vrr_tg()). So the
>> vblank evasion prior to commit_arm() will need to know the correct
>> position of the delayed vblank for the fixed RR timings. We will then
>> switch over to the VRR timings (and possibly to the other timing
>> generator) during the actul commit.
>>
>> This also means that intel_mode_vblank_delay() will always give us
>> the total delay betweern the undelayed vblank and delayed vblank for
>> the fixed RR timings. And this is exactly what we want
>> for eg. intel_dsb_wait_vblank_delay() since we will have configured
>> DSB_CHICKEN to use the undelayed vblank (as opposed to safe window)
>> and thus intel_dsb_wait_vblanks()/DSB_WAIT_FOR_VBLANK will wait for
>> the undelayed vblank.
>>
>>>>   }
>>>>   
>>>>   static int dsb_vtotal(struct intel_atomic_state *state,
>>>> @@ -733,7 +733,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
>>>>   		start = end - vblank_delay - latency;
>>>>   		intel_dsb_wait_scanline_out(state, dsb, start, end);
>>>>   	} else {
>>>> -		int vblank_delay = intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
>>>> +		int vblank_delay = crtc_state->set_context_latency;
>>>>   
>>>>   		end = intel_mode_vblank_start(&crtc_state->hw.adjusted_mode);
>>>>   		start = end - vblank_delay - latency;
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
>>>> index 9441b7bacd27..8c4cb6913ef9 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
>>>> @@ -619,11 +619,6 @@ int intel_mode_vtotal(const struct drm_display_mode *mode)
>>>>   	return vtotal;
>>>>   }
>>>>   
>>>> -int intel_mode_vblank_delay(const struct drm_display_mode *mode)
>>>> -{
>>>> -	return intel_mode_vblank_start(mode) - intel_mode_vdisplay(mode);
>>>> -}
>>>> -
>>>>   static const struct intel_crtc_state *
>>>>   pre_commit_crtc_state(const struct intel_crtc_state *old_crtc_state,
>>>>   		      const struct intel_crtc_state *new_crtc_state)
>>>> @@ -685,7 +680,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
>>>>   	} else {
>>>>   		evade->vblank_start = intel_mode_vblank_start(adjusted_mode);
>>>>   
>>>> -		vblank_delay = intel_mode_vblank_delay(adjusted_mode);
>>>> +		vblank_delay = crtc_state->set_context_latency;
>>>>   	}
>>>>   
>>>>   	/* FIXME needs to be calibrated sensibly */
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h
>>>> index 21fbb08d61d5..0fd6f7aeffd4 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_vblank.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_vblank.h
>>>> @@ -25,7 +25,6 @@ int intel_mode_vdisplay(const struct drm_display_mode *mode);
>>>>   int intel_mode_vblank_start(const struct drm_display_mode *mode);
>>>>   int intel_mode_vblank_end(const struct drm_display_mode *mode);
>>>>   int intel_mode_vtotal(const struct drm_display_mode *mode);
>>>> -int intel_mode_vblank_delay(const struct drm_display_mode *mode);
>>>>   
>>>>   void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
>>>>   			     const struct intel_crtc_state *new_crtc_state,
>>>> -- 
>>>> 2.45.2
>>> -- 
>>> Ville Syrjälä
>>> Intel
>> -- 
>> Ville Syrjälä
>> Intel

[PATCH 7/9] drm/i915/dsb: s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_scl_lines

[Ankit Nautiyal]

The helper intel_dsb_wait_vblank_delay() is used in DSB to wait for SCL
lines after the send push operation. Rename it to
intel_dsb_wait_for_scl_lines() to align with the semantics.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/display/intel_dsb.c     | 11 +++++------
 drivers/gpu/drm/i915/display/intel_dsb.h     |  4 ++--
 4 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 671db6926e4c..4defd2425837 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2013,7 +2013,7 @@ void intel_color_prepare_commit(struct intel_atomic_state *state,
 
 	if (crtc_state->use_dsb && intel_color_uses_chained_dsb(crtc_state)) {
 		intel_vrr_send_push(crtc_state->dsb_color, crtc_state);
-		intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color);
+		intel_dsb_wait_for_scl_lines(state, crtc_state->dsb_color);
 		intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state);
 		intel_dsb_interrupt(crtc_state->dsb_color);
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 455bbebb50a5..bfeec3706f35 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7268,7 +7268,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
 
 		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
-		intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
+		intel_dsb_wait_for_scl_lines(state, new_crtc_state->dsb_commit);
 		intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
 					  new_crtc_state);
 		intel_dsb_interrupt(new_crtc_state->dsb_commit);
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index dfe928aefdcd..400dcc87a992 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -115,8 +115,8 @@ static bool pre_commit_is_vrr_active(struct intel_atomic_state *state,
 	return old_crtc_state->vrr.enable && !intel_crtc_vrr_disabling(state, crtc);
 }
 
-static int dsb_vblank_delay(struct intel_atomic_state *state,
-			    struct intel_crtc *crtc)
+static int dsb_scl_delay(struct intel_atomic_state *state,
+			 struct intel_crtc *crtc)
 {
 	const struct intel_crtc_state *crtc_state =
 		intel_pre_commit_crtc_state(state, crtc);
@@ -815,15 +815,14 @@ void intel_dsb_chain(struct intel_atomic_state *state,
 			 wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0);
 }
 
-void intel_dsb_wait_vblank_delay(struct intel_atomic_state *state,
-				 struct intel_dsb *dsb)
+void intel_dsb_wait_for_scl_lines(struct intel_atomic_state *state,
+				  struct intel_dsb *dsb)
 {
 	struct intel_crtc *crtc = dsb->crtc;
 	const struct intel_crtc_state *crtc_state =
 		intel_pre_commit_crtc_state(state, crtc);
 	int usecs = intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode,
-					     dsb_vblank_delay(state, crtc));
-
+					     dsb_scl_delay(state, crtc));
 	intel_dsb_wait_usec(dsb, usecs);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index c8f4499916eb..1cb5ba1a0534 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -48,8 +48,8 @@ void intel_dsb_nonpost_end(struct intel_dsb *dsb);
 void intel_dsb_interrupt(struct intel_dsb *dsb);
 void intel_dsb_wait_usec(struct intel_dsb *dsb, int count);
 void intel_dsb_wait_vblanks(struct intel_dsb *dsb, int count);
-void intel_dsb_wait_vblank_delay(struct intel_atomic_state *state,
-				 struct intel_dsb *dsb);
+void intel_dsb_wait_for_scl_lines(struct intel_atomic_state *state,
+				  struct intel_dsb *dsb);
 void intel_dsb_wait_scanline_in(struct intel_atomic_state *state,
 				struct intel_dsb *dsb,
 				int lower, int upper);
-- 
2.45.2

Re: [PATCH 7/9] drm/i915/dsb: s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_scl_lines

[Ville Syrjälä]

On Sun, Sep 21, 2025 at 10:05:33AM +0530, Ankit Nautiyal wrote:
> The helper intel_dsb_wait_vblank_delay() is used in DSB to wait for SCL
> lines after the send push operation. Rename it to
> intel_dsb_wait_for_scl_lines() to align with the semantics.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_color.c   |  2 +-
>  drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_dsb.c     | 11 +++++------
>  drivers/gpu/drm/i915/display/intel_dsb.h     |  4 ++--
>  4 files changed, 9 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 671db6926e4c..4defd2425837 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -2013,7 +2013,7 @@ void intel_color_prepare_commit(struct intel_atomic_state *state,
>  
>  	if (crtc_state->use_dsb && intel_color_uses_chained_dsb(crtc_state)) {
>  		intel_vrr_send_push(crtc_state->dsb_color, crtc_state);
> -		intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color);
> +		intel_dsb_wait_for_scl_lines(state, crtc_state->dsb_color);
>  		intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state);
>  		intel_dsb_interrupt(crtc_state->dsb_color);
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 455bbebb50a5..bfeec3706f35 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7268,7 +7268,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>  		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
>  
>  		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
> -		intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
> +		intel_dsb_wait_for_scl_lines(state, new_crtc_state->dsb_commit);
>  		intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
>  					  new_crtc_state);
>  		intel_dsb_interrupt(new_crtc_state->dsb_commit);
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index dfe928aefdcd..400dcc87a992 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -115,8 +115,8 @@ static bool pre_commit_is_vrr_active(struct intel_atomic_state *state,
>  	return old_crtc_state->vrr.enable && !intel_crtc_vrr_disabling(state, crtc);
>  }
>  
> -static int dsb_vblank_delay(struct intel_atomic_state *state,
> -			    struct intel_crtc *crtc)
> +static int dsb_scl_delay(struct intel_atomic_state *state,
> +			 struct intel_crtc *crtc)
>  {
>  	const struct intel_crtc_state *crtc_state =
>  		intel_pre_commit_crtc_state(state, crtc);
> @@ -815,15 +815,14 @@ void intel_dsb_chain(struct intel_atomic_state *state,
>  			 wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0);
>  }
>  
> -void intel_dsb_wait_vblank_delay(struct intel_atomic_state *state,
> -				 struct intel_dsb *dsb)
> +void intel_dsb_wait_for_scl_lines(struct intel_atomic_state *state,
> +				  struct intel_dsb *dsb)

I'd leave this name as is for now. Or perhaps we should call it
intel_dsb_wait_for_delayed_vblank().

The actual behaviour of this will need to be slightly different between
the different timings generators/refresh rate modes so it can't just
wait for SCL lines in all the cases.


>  {
>  	struct intel_crtc *crtc = dsb->crtc;
>  	const struct intel_crtc_state *crtc_state =
>  		intel_pre_commit_crtc_state(state, crtc);
>  	int usecs = intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode,
> -					     dsb_vblank_delay(state, crtc));
> -
> +					     dsb_scl_delay(state, crtc));
>  	intel_dsb_wait_usec(dsb, usecs);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
> index c8f4499916eb..1cb5ba1a0534 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -48,8 +48,8 @@ void intel_dsb_nonpost_end(struct intel_dsb *dsb);
>  void intel_dsb_interrupt(struct intel_dsb *dsb);
>  void intel_dsb_wait_usec(struct intel_dsb *dsb, int count);
>  void intel_dsb_wait_vblanks(struct intel_dsb *dsb, int count);
> -void intel_dsb_wait_vblank_delay(struct intel_atomic_state *state,
> -				 struct intel_dsb *dsb);
> +void intel_dsb_wait_for_scl_lines(struct intel_atomic_state *state,
> +				  struct intel_dsb *dsb);
>  void intel_dsb_wait_scanline_in(struct intel_atomic_state *state,
>  				struct intel_dsb *dsb,
>  				int lower, int upper);
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 7/9] drm/i915/dsb: s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_scl_lines

[Nautiyal, Ankit K]

On 9/22/2025 4:02 PM, Ville Syrjälä wrote:
> On Sun, Sep 21, 2025 at 10:05:33AM +0530, Ankit Nautiyal wrote:
>> The helper intel_dsb_wait_vblank_delay() is used in DSB to wait for SCL
>> lines after the send push operation. Rename it to
>> intel_dsb_wait_for_scl_lines() to align with the semantics.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_color.c   |  2 +-
>>   drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>>   drivers/gpu/drm/i915/display/intel_dsb.c     | 11 +++++------
>>   drivers/gpu/drm/i915/display/intel_dsb.h     |  4 ++--
>>   4 files changed, 9 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
>> index 671db6926e4c..4defd2425837 100644
>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>> @@ -2013,7 +2013,7 @@ void intel_color_prepare_commit(struct intel_atomic_state *state,
>>   
>>   	if (crtc_state->use_dsb && intel_color_uses_chained_dsb(crtc_state)) {
>>   		intel_vrr_send_push(crtc_state->dsb_color, crtc_state);
>> -		intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color);
>> +		intel_dsb_wait_for_scl_lines(state, crtc_state->dsb_color);
>>   		intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state);
>>   		intel_dsb_interrupt(crtc_state->dsb_color);
>>   	}
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 455bbebb50a5..bfeec3706f35 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -7268,7 +7268,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>>   		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
>>   
>>   		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
>> -		intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
>> +		intel_dsb_wait_for_scl_lines(state, new_crtc_state->dsb_commit);
>>   		intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
>>   					  new_crtc_state);
>>   		intel_dsb_interrupt(new_crtc_state->dsb_commit);
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
>> index dfe928aefdcd..400dcc87a992 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>> @@ -115,8 +115,8 @@ static bool pre_commit_is_vrr_active(struct intel_atomic_state *state,
>>   	return old_crtc_state->vrr.enable && !intel_crtc_vrr_disabling(state, crtc);
>>   }
>>   
>> -static int dsb_vblank_delay(struct intel_atomic_state *state,
>> -			    struct intel_crtc *crtc)
>> +static int dsb_scl_delay(struct intel_atomic_state *state,
>> +			 struct intel_crtc *crtc)
>>   {
>>   	const struct intel_crtc_state *crtc_state =
>>   		intel_pre_commit_crtc_state(state, crtc);
>> @@ -815,15 +815,14 @@ void intel_dsb_chain(struct intel_atomic_state *state,
>>   			 wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0);
>>   }
>>   
>> -void intel_dsb_wait_vblank_delay(struct intel_atomic_state *state,
>> -				 struct intel_dsb *dsb)
>> +void intel_dsb_wait_for_scl_lines(struct intel_atomic_state *state,
>> +				  struct intel_dsb *dsb)
> I'd leave this name as is for now. Or perhaps we should call it
> intel_dsb_wait_for_delayed_vblank().
>
> The actual behaviour of this will need to be slightly different between
> the different timings generators/refresh rate modes so it can't just
> wait for SCL lines in all the cases.


intel_dsb_wait_for_delayed_vblank does make sense in that case.

Will drop the scl semantics and just rename to 
intel_dsb_wait_for_delayed_vblank()

Regards,

Ankit

>
>
>>   {
>>   	struct intel_crtc *crtc = dsb->crtc;
>>   	const struct intel_crtc_state *crtc_state =
>>   		intel_pre_commit_crtc_state(state, crtc);
>>   	int usecs = intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode,
>> -					     dsb_vblank_delay(state, crtc));
>> -
>> +					     dsb_scl_delay(state, crtc));
>>   	intel_dsb_wait_usec(dsb, usecs);
>>   }
>>   
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
>> index c8f4499916eb..1cb5ba1a0534 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
>> @@ -48,8 +48,8 @@ void intel_dsb_nonpost_end(struct intel_dsb *dsb);
>>   void intel_dsb_interrupt(struct intel_dsb *dsb);
>>   void intel_dsb_wait_usec(struct intel_dsb *dsb, int count);
>>   void intel_dsb_wait_vblanks(struct intel_dsb *dsb, int count);
>> -void intel_dsb_wait_vblank_delay(struct intel_atomic_state *state,
>> -				 struct intel_dsb *dsb);
>> +void intel_dsb_wait_for_scl_lines(struct intel_atomic_state *state,
>> +				  struct intel_dsb *dsb);
>>   void intel_dsb_wait_scanline_in(struct intel_atomic_state *state,
>>   				struct intel_dsb *dsb,
>>   				int lower, int upper);
>> -- 
>> 2.45.2

[PATCH 8/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks

[Ankit Nautiyal]

Until LNL, intel_dsb_wait_vblanks() waits for the undelayed vblank start.
However, from PTL onwards, it waits for the start of the safe window,
defined by the number of lines programmed in TRANS_SET_CONTEXT_LATENCY.
This change was introduced to move the SCL window out of the vblank region,
supporting modes with higher refresh rates and smaller vblanks.

As a result, on PTL+ platforms, the DSB wait for vblank completes exactly
SCL lines earlier than the undelayed vblank start. Since we use
intel_dsb_wait_vblanks() to time the send push operation, this causes
issues when SCL lines are non-zero.

Instead of relying on the helper, instruct the DSB to wait from
(undelayed vblank start - SCL) to (delayed vblank start - SCL) before
sending the push. This approach works for both pre-PTL and PTL+ platforms.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/display/intel_dsb.c     | 16 ++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dsb.h     |  2 ++
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bfeec3706f35..8d78037d5a2a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7265,7 +7265,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 				new_crtc_state->dsb_color);
 
 	if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) {
-		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
+		intel_dsb_wait_for_scl_start(state, new_crtc_state->dsb_commit);
 
 		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
 		intel_dsb_wait_for_scl_lines(state, new_crtc_state->dsb_commit);
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 400dcc87a992..e94a05cc8c82 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -826,6 +826,22 @@ void intel_dsb_wait_for_scl_lines(struct intel_atomic_state *state,
 	intel_dsb_wait_usec(dsb, usecs);
 }
 
+void intel_dsb_wait_for_scl_start(struct intel_atomic_state *state,
+				  struct intel_dsb *dsb)
+{
+	struct intel_crtc *crtc = dsb->crtc;
+	const struct intel_crtc_state *crtc_state =
+		intel_pre_commit_crtc_state(state, crtc);
+	int undelayed_vblank_start = crtc_state->hw.adjusted_mode.crtc_vdisplay;
+	int delayed_vblank_start = crtc_state->hw.adjusted_mode.crtc_vblank_start;
+	int start, end;
+
+	start = undelayed_vblank_start - crtc_state->set_context_latency;
+	end = delayed_vblank_start - crtc_state->set_context_latency;
+
+	intel_dsb_wait_scanline_out(state, dsb, start, end);
+}
+
 /**
  * intel_dsb_commit() - Trigger workload execution of DSB.
  * @dsb: DSB context
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index 1cb5ba1a0534..5985d0024dae 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -73,5 +73,7 @@ void intel_dsb_wait(struct intel_dsb *dsb);
 
 void intel_dsb_irq_handler(struct intel_display *display,
 			   enum pipe pipe, enum intel_dsb_id dsb_id);
+void intel_dsb_wait_for_scl_start(struct intel_atomic_state *state,
+				  struct intel_dsb *dsb);
 
 #endif
-- 
2.45.2

Re: [PATCH 8/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks

[Ville Syrjälä]

On Sun, Sep 21, 2025 at 10:05:34AM +0530, Ankit Nautiyal wrote:
> Until LNL, intel_dsb_wait_vblanks() waits for the undelayed vblank start.
> However, from PTL onwards, it waits for the start of the safe window,
> defined by the number of lines programmed in TRANS_SET_CONTEXT_LATENCY.
> This change was introduced to move the SCL window out of the vblank region,
> supporting modes with higher refresh rates and smaller vblanks.
> 
> As a result, on PTL+ platforms, the DSB wait for vblank completes exactly
> SCL lines earlier than the undelayed vblank start. Since we use
> intel_dsb_wait_vblanks() to time the send push operation, this causes
> issues when SCL lines are non-zero.
> 
> Instead of relying on the helper, instruct the DSB to wait from
> (undelayed vblank start - SCL) to (delayed vblank start - SCL) before
> sending the push. This approach works for both pre-PTL and PTL+ platforms.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_dsb.c     | 16 ++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dsb.h     |  2 ++
>  3 files changed, 19 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index bfeec3706f35..8d78037d5a2a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7265,7 +7265,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>  				new_crtc_state->dsb_color);
>  
>  	if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) {
> -		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
> +		intel_dsb_wait_for_scl_start(state, new_crtc_state->dsb_commit);
>  
>  		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
>  		intel_dsb_wait_for_scl_lines(state, new_crtc_state->dsb_commit);
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 400dcc87a992..e94a05cc8c82 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -826,6 +826,22 @@ void intel_dsb_wait_for_scl_lines(struct intel_atomic_state *state,
>  	intel_dsb_wait_usec(dsb, usecs);
>  }
>  
> +void intel_dsb_wait_for_scl_start(struct intel_atomic_state *state,
> +				  struct intel_dsb *dsb)
> +{
> +	struct intel_crtc *crtc = dsb->crtc;
> +	const struct intel_crtc_state *crtc_state =
> +		intel_pre_commit_crtc_state(state, crtc);
> +	int undelayed_vblank_start = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> +	int delayed_vblank_start = crtc_state->hw.adjusted_mode.crtc_vblank_start;
> +	int start, end;
> +
> +	start = undelayed_vblank_start - crtc_state->set_context_latency;
> +	end = delayed_vblank_start - crtc_state->set_context_latency;

For these we perhaps want something like:

intel_vrr_safe_window_start()
{
	if (ptl+)
		return crtc_vdisplay - set_context_latency;
	else
		return crtc_vdisplay;
}

intel_vrr_vmin_safe_window_end()
{
	intel_vrr_vmin_vblank_start() - set_context_latency;
}

> +
> +	intel_dsb_wait_scanline_out(state, dsb, start, end);

And I suspect we want to do this just before the usec wait in
intel_dsb_wait_vblank_delay() (for the VRR case only). No need
to bother higher level code with this, I think.

> +}
> +
>  /**
>   * intel_dsb_commit() - Trigger workload execution of DSB.
>   * @dsb: DSB context
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
> index 1cb5ba1a0534..5985d0024dae 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -73,5 +73,7 @@ void intel_dsb_wait(struct intel_dsb *dsb);
>  
>  void intel_dsb_irq_handler(struct intel_display *display,
>  			   enum pipe pipe, enum intel_dsb_id dsb_id);
> +void intel_dsb_wait_for_scl_start(struct intel_atomic_state *state,
> +				  struct intel_dsb *dsb);
>  
>  #endif
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 8/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks

[Nautiyal, Ankit K]

On 9/22/2025 3:56 PM, Ville Syrjälä wrote:
> On Sun, Sep 21, 2025 at 10:05:34AM +0530, Ankit Nautiyal wrote:
>> Until LNL, intel_dsb_wait_vblanks() waits for the undelayed vblank start.
>> However, from PTL onwards, it waits for the start of the safe window,
>> defined by the number of lines programmed in TRANS_SET_CONTEXT_LATENCY.
>> This change was introduced to move the SCL window out of the vblank region,
>> supporting modes with higher refresh rates and smaller vblanks.
>>
>> As a result, on PTL+ platforms, the DSB wait for vblank completes exactly
>> SCL lines earlier than the undelayed vblank start. Since we use
>> intel_dsb_wait_vblanks() to time the send push operation, this causes
>> issues when SCL lines are non-zero.
>>
>> Instead of relying on the helper, instruct the DSB to wait from
>> (undelayed vblank start - SCL) to (delayed vblank start - SCL) before
>> sending the push. This approach works for both pre-PTL and PTL+ platforms.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>>   drivers/gpu/drm/i915/display/intel_dsb.c     | 16 ++++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_dsb.h     |  2 ++
>>   3 files changed, 19 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index bfeec3706f35..8d78037d5a2a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -7265,7 +7265,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>>   				new_crtc_state->dsb_color);
>>   
>>   	if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) {
>> -		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
>> +		intel_dsb_wait_for_scl_start(state, new_crtc_state->dsb_commit);
>>   
>>   		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
>>   		intel_dsb_wait_for_scl_lines(state, new_crtc_state->dsb_commit);
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
>> index 400dcc87a992..e94a05cc8c82 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>> @@ -826,6 +826,22 @@ void intel_dsb_wait_for_scl_lines(struct intel_atomic_state *state,
>>   	intel_dsb_wait_usec(dsb, usecs);
>>   }
>>   
>> +void intel_dsb_wait_for_scl_start(struct intel_atomic_state *state,
>> +				  struct intel_dsb *dsb)
>> +{
>> +	struct intel_crtc *crtc = dsb->crtc;
>> +	const struct intel_crtc_state *crtc_state =
>> +		intel_pre_commit_crtc_state(state, crtc);
>> +	int undelayed_vblank_start = crtc_state->hw.adjusted_mode.crtc_vdisplay;
>> +	int delayed_vblank_start = crtc_state->hw.adjusted_mode.crtc_vblank_start;
>> +	int start, end;
>> +
>> +	start = undelayed_vblank_start - crtc_state->set_context_latency;
>> +	end = delayed_vblank_start - crtc_state->set_context_latency;
> For these we perhaps want something like:
>
> intel_vrr_safe_window_start()
> {
> 	if (ptl+)
> 		return crtc_vdisplay - set_context_latency;
> 	else
> 		return crtc_vdisplay;
> }
>
> intel_vrr_vmin_safe_window_end()
> {
> 	intel_vrr_vmin_vblank_start() - set_context_latency;
> }
>
>> +
>> +	intel_dsb_wait_scanline_out(state, dsb, start, end);
> And I suspect we want to do this just before the usec wait in
> intel_dsb_wait_vblank_delay() (for the VRR case only). No need
> to bother higher level code with this, I think.

Ok sure. I will re-arrange this and use the suggested functions for VRR 
case.

On quick checking, it seems we need to use start -1 in :

intel_dsb_wait_scanline_out(state, dsb, start -1, end);

I tested with initializing with bigger value (like 5 instead of 1).

 From the dsb utility which you had shared, also we see that it gives 
(vactive - scl - 1) as the safe window live status change for PTL.

Regards,

Ankit

>
>> +}
>> +
>>   /**
>>    * intel_dsb_commit() - Trigger workload execution of DSB.
>>    * @dsb: DSB context
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
>> index 1cb5ba1a0534..5985d0024dae 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
>> @@ -73,5 +73,7 @@ void intel_dsb_wait(struct intel_dsb *dsb);
>>   
>>   void intel_dsb_irq_handler(struct intel_display *display,
>>   			   enum pipe pipe, enum intel_dsb_id dsb_id);
>> +void intel_dsb_wait_for_scl_start(struct intel_atomic_state *state,
>> +				  struct intel_dsb *dsb);
>>   
>>   #endif
>> -- 
>> 2.45.2

Re: [PATCH 8/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks

[Ville Syrjälä]

On Mon, Sep 22, 2025 at 07:04:49PM +0530, Nautiyal, Ankit K wrote:
> 
> On 9/22/2025 3:56 PM, Ville Syrjälä wrote:
> > On Sun, Sep 21, 2025 at 10:05:34AM +0530, Ankit Nautiyal wrote:
> >> Until LNL, intel_dsb_wait_vblanks() waits for the undelayed vblank start.
> >> However, from PTL onwards, it waits for the start of the safe window,
> >> defined by the number of lines programmed in TRANS_SET_CONTEXT_LATENCY.
> >> This change was introduced to move the SCL window out of the vblank region,
> >> supporting modes with higher refresh rates and smaller vblanks.
> >>
> >> As a result, on PTL+ platforms, the DSB wait for vblank completes exactly
> >> SCL lines earlier than the undelayed vblank start. Since we use
> >> intel_dsb_wait_vblanks() to time the send push operation, this causes
> >> issues when SCL lines are non-zero.
> >>
> >> Instead of relying on the helper, instruct the DSB to wait from
> >> (undelayed vblank start - SCL) to (delayed vblank start - SCL) before
> >> sending the push. This approach works for both pre-PTL and PTL+ platforms.
> >>
> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/display/intel_display.c |  2 +-
> >>   drivers/gpu/drm/i915/display/intel_dsb.c     | 16 ++++++++++++++++
> >>   drivers/gpu/drm/i915/display/intel_dsb.h     |  2 ++
> >>   3 files changed, 19 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> >> index bfeec3706f35..8d78037d5a2a 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -7265,7 +7265,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
> >>   				new_crtc_state->dsb_color);
> >>   
> >>   	if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) {
> >> -		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
> >> +		intel_dsb_wait_for_scl_start(state, new_crtc_state->dsb_commit);
> >>   
> >>   		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
> >>   		intel_dsb_wait_for_scl_lines(state, new_crtc_state->dsb_commit);
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> >> index 400dcc87a992..e94a05cc8c82 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> >> @@ -826,6 +826,22 @@ void intel_dsb_wait_for_scl_lines(struct intel_atomic_state *state,
> >>   	intel_dsb_wait_usec(dsb, usecs);
> >>   }
> >>   
> >> +void intel_dsb_wait_for_scl_start(struct intel_atomic_state *state,
> >> +				  struct intel_dsb *dsb)
> >> +{
> >> +	struct intel_crtc *crtc = dsb->crtc;
> >> +	const struct intel_crtc_state *crtc_state =
> >> +		intel_pre_commit_crtc_state(state, crtc);
> >> +	int undelayed_vblank_start = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> >> +	int delayed_vblank_start = crtc_state->hw.adjusted_mode.crtc_vblank_start;
> >> +	int start, end;
> >> +
> >> +	start = undelayed_vblank_start - crtc_state->set_context_latency;
> >> +	end = delayed_vblank_start - crtc_state->set_context_latency;
> > For these we perhaps want something like:
> >
> > intel_vrr_safe_window_start()
> > {
> > 	if (ptl+)
> > 		return crtc_vdisplay - set_context_latency;
> > 	else
> > 		return crtc_vdisplay;
> > }
> >
> > intel_vrr_vmin_safe_window_end()
> > {
> > 	intel_vrr_vmin_vblank_start() - set_context_latency;
> > }
> >
> >> +
> >> +	intel_dsb_wait_scanline_out(state, dsb, start, end);
> > And I suspect we want to do this just before the usec wait in
> > intel_dsb_wait_vblank_delay() (for the VRR case only). No need
> > to bother higher level code with this, I think.
> 
> Ok sure. I will re-arrange this and use the suggested functions for VRR 
> case.
> 
> On quick checking, it seems we need to use start -1 in :
> 
> intel_dsb_wait_scanline_out(state, dsb, start -1, end);
> 
> I tested with initializing with bigger value (like 5 instead of 1).
> 
>  From the dsb utility which you had shared, also we see that it gives 
> (vactive - scl - 1) as the safe window live status change for PTL.

The hardware scanline numbers are always off by one (or two) when
compared to our more sensible software numbers (see
intel_crtc_scanline_offset()). On this level we're always
thinking in terms of the sotfware numbers, and dsb_scanline_to_hw()
will then do the necessary adjustment for us.

The only slight exception is the direct low level
intel_dsb_emit_wait_dsl() call in intel_dsb_vblank_evade() for PSR,
because there we really do want to evade *hardware* scanline 0.

-- 
Ville Syrjälä
Intel

Re: [PATCH 8/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks

[Ville Syrjälä]

On Mon, Sep 22, 2025 at 04:44:19PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 22, 2025 at 07:04:49PM +0530, Nautiyal, Ankit K wrote:
> > 
> > On 9/22/2025 3:56 PM, Ville Syrjälä wrote:
> > > On Sun, Sep 21, 2025 at 10:05:34AM +0530, Ankit Nautiyal wrote:
> > >> Until LNL, intel_dsb_wait_vblanks() waits for the undelayed vblank start.
> > >> However, from PTL onwards, it waits for the start of the safe window,
> > >> defined by the number of lines programmed in TRANS_SET_CONTEXT_LATENCY.
> > >> This change was introduced to move the SCL window out of the vblank region,
> > >> supporting modes with higher refresh rates and smaller vblanks.
> > >>
> > >> As a result, on PTL+ platforms, the DSB wait for vblank completes exactly
> > >> SCL lines earlier than the undelayed vblank start. Since we use
> > >> intel_dsb_wait_vblanks() to time the send push operation, this causes
> > >> issues when SCL lines are non-zero.
> > >>
> > >> Instead of relying on the helper, instruct the DSB to wait from
> > >> (undelayed vblank start - SCL) to (delayed vblank start - SCL) before
> > >> sending the push. This approach works for both pre-PTL and PTL+ platforms.
> > >>
> > >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > >> ---
> > >>   drivers/gpu/drm/i915/display/intel_display.c |  2 +-
> > >>   drivers/gpu/drm/i915/display/intel_dsb.c     | 16 ++++++++++++++++
> > >>   drivers/gpu/drm/i915/display/intel_dsb.h     |  2 ++
> > >>   3 files changed, 19 insertions(+), 1 deletion(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > >> index bfeec3706f35..8d78037d5a2a 100644
> > >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> > >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > >> @@ -7265,7 +7265,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
> > >>   				new_crtc_state->dsb_color);
> > >>   
> > >>   	if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) {
> > >> -		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
> > >> +		intel_dsb_wait_for_scl_start(state, new_crtc_state->dsb_commit);
> > >>   
> > >>   		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
> > >>   		intel_dsb_wait_for_scl_lines(state, new_crtc_state->dsb_commit);
> > >> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> > >> index 400dcc87a992..e94a05cc8c82 100644
> > >> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> > >> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> > >> @@ -826,6 +826,22 @@ void intel_dsb_wait_for_scl_lines(struct intel_atomic_state *state,
> > >>   	intel_dsb_wait_usec(dsb, usecs);
> > >>   }
> > >>   
> > >> +void intel_dsb_wait_for_scl_start(struct intel_atomic_state *state,
> > >> +				  struct intel_dsb *dsb)
> > >> +{
> > >> +	struct intel_crtc *crtc = dsb->crtc;
> > >> +	const struct intel_crtc_state *crtc_state =
> > >> +		intel_pre_commit_crtc_state(state, crtc);
> > >> +	int undelayed_vblank_start = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> > >> +	int delayed_vblank_start = crtc_state->hw.adjusted_mode.crtc_vblank_start;
> > >> +	int start, end;
> > >> +
> > >> +	start = undelayed_vblank_start - crtc_state->set_context_latency;
> > >> +	end = delayed_vblank_start - crtc_state->set_context_latency;
> > > For these we perhaps want something like:
> > >
> > > intel_vrr_safe_window_start()
> > > {
> > > 	if (ptl+)
> > > 		return crtc_vdisplay - set_context_latency;
> > > 	else
> > > 		return crtc_vdisplay;
> > > }
> > >
> > > intel_vrr_vmin_safe_window_end()
> > > {
> > > 	intel_vrr_vmin_vblank_start() - set_context_latency;
> > > }
> > >
> > >> +
> > >> +	intel_dsb_wait_scanline_out(state, dsb, start, end);
> > > And I suspect we want to do this just before the usec wait in
> > > intel_dsb_wait_vblank_delay() (for the VRR case only). No need
> > > to bother higher level code with this, I think.
> > 
> > Ok sure. I will re-arrange this and use the suggested functions for VRR 
> > case.
> > 
> > On quick checking, it seems we need to use start -1 in :
> > 
> > intel_dsb_wait_scanline_out(state, dsb, start -1, end);
> > 
> > I tested with initializing with bigger value (like 5 instead of 1).
> > 
> >  From the dsb utility which you had shared, also we see that it gives 
> > (vactive - scl - 1) as the safe window live status change for PTL.
> 
> The hardware scanline numbers are always off by one (or two) when
> compared to our more sensible software numbers (see
> intel_crtc_scanline_offset()). On this level we're always
> thinking in terms of the sotfware numbers, and dsb_scanline_to_hw()
> will then do the necessary adjustment for us.

I suppose to make our lives easier we could make intel_display_poller
adjust the scanline numbers in a similar fashion. Though we might
want to make that optional so that we can also have it use the
raw hardware numbers as well. I'll see if I can cook up something...

-- 
Ville Syrjälä
Intel

Re: [PATCH 8/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks

[Ville Syrjälä]

On Mon, Sep 22, 2025 at 04:49:46PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 22, 2025 at 04:44:19PM +0300, Ville Syrjälä wrote:
> > On Mon, Sep 22, 2025 at 07:04:49PM +0530, Nautiyal, Ankit K wrote:
> > > 
> > > On 9/22/2025 3:56 PM, Ville Syrjälä wrote:
> > > > On Sun, Sep 21, 2025 at 10:05:34AM +0530, Ankit Nautiyal wrote:
> > > >> Until LNL, intel_dsb_wait_vblanks() waits for the undelayed vblank start.
> > > >> However, from PTL onwards, it waits for the start of the safe window,
> > > >> defined by the number of lines programmed in TRANS_SET_CONTEXT_LATENCY.
> > > >> This change was introduced to move the SCL window out of the vblank region,
> > > >> supporting modes with higher refresh rates and smaller vblanks.
> > > >>
> > > >> As a result, on PTL+ platforms, the DSB wait for vblank completes exactly
> > > >> SCL lines earlier than the undelayed vblank start. Since we use
> > > >> intel_dsb_wait_vblanks() to time the send push operation, this causes
> > > >> issues when SCL lines are non-zero.
> > > >>
> > > >> Instead of relying on the helper, instruct the DSB to wait from
> > > >> (undelayed vblank start - SCL) to (delayed vblank start - SCL) before
> > > >> sending the push. This approach works for both pre-PTL and PTL+ platforms.
> > > >>
> > > >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > >> ---
> > > >>   drivers/gpu/drm/i915/display/intel_display.c |  2 +-
> > > >>   drivers/gpu/drm/i915/display/intel_dsb.c     | 16 ++++++++++++++++
> > > >>   drivers/gpu/drm/i915/display/intel_dsb.h     |  2 ++
> > > >>   3 files changed, 19 insertions(+), 1 deletion(-)
> > > >>
> > > >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > >> index bfeec3706f35..8d78037d5a2a 100644
> > > >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > >> @@ -7265,7 +7265,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
> > > >>   				new_crtc_state->dsb_color);
> > > >>   
> > > >>   	if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) {
> > > >> -		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
> > > >> +		intel_dsb_wait_for_scl_start(state, new_crtc_state->dsb_commit);
> > > >>   
> > > >>   		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
> > > >>   		intel_dsb_wait_for_scl_lines(state, new_crtc_state->dsb_commit);
> > > >> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> > > >> index 400dcc87a992..e94a05cc8c82 100644
> > > >> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> > > >> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> > > >> @@ -826,6 +826,22 @@ void intel_dsb_wait_for_scl_lines(struct intel_atomic_state *state,
> > > >>   	intel_dsb_wait_usec(dsb, usecs);
> > > >>   }
> > > >>   
> > > >> +void intel_dsb_wait_for_scl_start(struct intel_atomic_state *state,
> > > >> +				  struct intel_dsb *dsb)
> > > >> +{
> > > >> +	struct intel_crtc *crtc = dsb->crtc;
> > > >> +	const struct intel_crtc_state *crtc_state =
> > > >> +		intel_pre_commit_crtc_state(state, crtc);
> > > >> +	int undelayed_vblank_start = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> > > >> +	int delayed_vblank_start = crtc_state->hw.adjusted_mode.crtc_vblank_start;
> > > >> +	int start, end;
> > > >> +
> > > >> +	start = undelayed_vblank_start - crtc_state->set_context_latency;
> > > >> +	end = delayed_vblank_start - crtc_state->set_context_latency;
> > > > For these we perhaps want something like:
> > > >
> > > > intel_vrr_safe_window_start()
> > > > {
> > > > 	if (ptl+)
> > > > 		return crtc_vdisplay - set_context_latency;
> > > > 	else
> > > > 		return crtc_vdisplay;
> > > > }
> > > >
> > > > intel_vrr_vmin_safe_window_end()
> > > > {
> > > > 	intel_vrr_vmin_vblank_start() - set_context_latency;
> > > > }
> > > >
> > > >> +
> > > >> +	intel_dsb_wait_scanline_out(state, dsb, start, end);
> > > > And I suspect we want to do this just before the usec wait in
> > > > intel_dsb_wait_vblank_delay() (for the VRR case only). No need
> > > > to bother higher level code with this, I think.
> > > 
> > > Ok sure. I will re-arrange this and use the suggested functions for VRR 
> > > case.
> > > 
> > > On quick checking, it seems we need to use start -1 in :
> > > 
> > > intel_dsb_wait_scanline_out(state, dsb, start -1, end);
> > > 
> > > I tested with initializing with bigger value (like 5 instead of 1).
> > > 
> > >  From the dsb utility which you had shared, also we see that it gives 
> > > (vactive - scl - 1) as the safe window live status change for PTL.
> > 
> > The hardware scanline numbers are always off by one (or two) when
> > compared to our more sensible software numbers (see
> > intel_crtc_scanline_offset()). On this level we're always
> > thinking in terms of the sotfware numbers, and dsb_scanline_to_hw()
> > will then do the necessary adjustment for us.
> 
> I suppose to make our lives easier we could make intel_display_poller
> adjust the scanline numbers in a similar fashion. Though we might
> want to make that optional so that we can also have it use the
> raw hardware numbers as well. I'll see if I can cook up something...

Hmm, this might be a bit harder than I initially though because
everything would need the %vtotal to be entirely correct. So I'd
need to do a bunch of readout first to determine the vtotal
(or vmax) correctly. And if we get that wrong then we'd
potentially report garbage results.

Hmm, I suppose I could skip the %vtotal, and just not apply the
adjusment in the 'wrap' test at all. That might be the only test
that really cares about scanlines around the vtotal->0 point. And
I guess I could keep the adjustment behind a command line option
so that you sort of have to know what you're doing when enabling
it. I'll need to think about this a bit more.

-- 
Ville Syrjälä
Intel

Re: [PATCH 8/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks

[Nautiyal, Ankit K]

On 9/22/2025 7:34 PM, Ville Syrjälä wrote:
> On Mon, Sep 22, 2025 at 04:49:46PM +0300, Ville Syrjälä wrote:
>> On Mon, Sep 22, 2025 at 04:44:19PM +0300, Ville Syrjälä wrote:
>>> On Mon, Sep 22, 2025 at 07:04:49PM +0530, Nautiyal, Ankit K wrote:
>>>> On 9/22/2025 3:56 PM, Ville Syrjälä wrote:
>>>>> On Sun, Sep 21, 2025 at 10:05:34AM +0530, Ankit Nautiyal wrote:
>>>>>> Until LNL, intel_dsb_wait_vblanks() waits for the undelayed vblank start.
>>>>>> However, from PTL onwards, it waits for the start of the safe window,
>>>>>> defined by the number of lines programmed in TRANS_SET_CONTEXT_LATENCY.
>>>>>> This change was introduced to move the SCL window out of the vblank region,
>>>>>> supporting modes with higher refresh rates and smaller vblanks.
>>>>>>
>>>>>> As a result, on PTL+ platforms, the DSB wait for vblank completes exactly
>>>>>> SCL lines earlier than the undelayed vblank start. Since we use
>>>>>> intel_dsb_wait_vblanks() to time the send push operation, this causes
>>>>>> issues when SCL lines are non-zero.
>>>>>>
>>>>>> Instead of relying on the helper, instruct the DSB to wait from
>>>>>> (undelayed vblank start - SCL) to (delayed vblank start - SCL) before
>>>>>> sending the push. This approach works for both pre-PTL and PTL+ platforms.
>>>>>>
>>>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>>>> ---
>>>>>>    drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>>>>>>    drivers/gpu/drm/i915/display/intel_dsb.c     | 16 ++++++++++++++++
>>>>>>    drivers/gpu/drm/i915/display/intel_dsb.h     |  2 ++
>>>>>>    3 files changed, 19 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>>>>> index bfeec3706f35..8d78037d5a2a 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>>>>> @@ -7265,7 +7265,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>>>>>>    				new_crtc_state->dsb_color);
>>>>>>    
>>>>>>    	if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) {
>>>>>> -		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
>>>>>> +		intel_dsb_wait_for_scl_start(state, new_crtc_state->dsb_commit);
>>>>>>    
>>>>>>    		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
>>>>>>    		intel_dsb_wait_for_scl_lines(state, new_crtc_state->dsb_commit);
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
>>>>>> index 400dcc87a992..e94a05cc8c82 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>>>>>> @@ -826,6 +826,22 @@ void intel_dsb_wait_for_scl_lines(struct intel_atomic_state *state,
>>>>>>    	intel_dsb_wait_usec(dsb, usecs);
>>>>>>    }
>>>>>>    
>>>>>> +void intel_dsb_wait_for_scl_start(struct intel_atomic_state *state,
>>>>>> +				  struct intel_dsb *dsb)
>>>>>> +{
>>>>>> +	struct intel_crtc *crtc = dsb->crtc;
>>>>>> +	const struct intel_crtc_state *crtc_state =
>>>>>> +		intel_pre_commit_crtc_state(state, crtc);
>>>>>> +	int undelayed_vblank_start = crtc_state->hw.adjusted_mode.crtc_vdisplay;
>>>>>> +	int delayed_vblank_start = crtc_state->hw.adjusted_mode.crtc_vblank_start;
>>>>>> +	int start, end;
>>>>>> +
>>>>>> +	start = undelayed_vblank_start - crtc_state->set_context_latency;
>>>>>> +	end = delayed_vblank_start - crtc_state->set_context_latency;
>>>>> For these we perhaps want something like:
>>>>>
>>>>> intel_vrr_safe_window_start()
>>>>> {
>>>>> 	if (ptl+)
>>>>> 		return crtc_vdisplay - set_context_latency;
>>>>> 	else
>>>>> 		return crtc_vdisplay;
>>>>> }
>>>>>
>>>>> intel_vrr_vmin_safe_window_end()
>>>>> {
>>>>> 	intel_vrr_vmin_vblank_start() - set_context_latency;
>>>>> }
>>>>>
>>>>>> +
>>>>>> +	intel_dsb_wait_scanline_out(state, dsb, start, end);
>>>>> And I suspect we want to do this just before the usec wait in
>>>>> intel_dsb_wait_vblank_delay() (for the VRR case only). No need
>>>>> to bother higher level code with this, I think.
>>>> Ok sure. I will re-arrange this and use the suggested functions for VRR
>>>> case.
>>>>
>>>> On quick checking, it seems we need to use start -1 in :
>>>>
>>>> intel_dsb_wait_scanline_out(state, dsb, start -1, end);
>>>>
>>>> I tested with initializing with bigger value (like 5 instead of 1).
>>>>
>>>>   From the dsb utility which you had shared, also we see that it gives
>>>> (vactive - scl - 1) as the safe window live status change for PTL.
>>> The hardware scanline numbers are always off by one (or two) when
>>> compared to our more sensible software numbers (see
>>> intel_crtc_scanline_offset()). On this level we're always
>>> thinking in terms of the sotfware numbers, and dsb_scanline_to_hw()
>>> will then do the necessary adjustment for us.
>> I suppose to make our lives easier we could make intel_display_poller
>> adjust the scanline numbers in a similar fashion. Though we might
>> want to make that optional so that we can also have it use the
>> raw hardware numbers as well. I'll see if I can cook up something...
> Hmm, this might be a bit harder than I initially though because
> everything would need the %vtotal to be entirely correct. So I'd
> need to do a bunch of readout first to determine the vtotal
> (or vmax) correctly. And if we get that wrong then we'd
> potentially report garbage results.
>
> Hmm, I suppose I could skip the %vtotal, and just not apply the
> adjusment in the 'wrap' test at all. That might be the only test
> that really cares about scanlines around the vtotal->0 point. And
> I guess I could keep the adjustment behind a command line option
> so that you sort of have to know what you're doing when enabling
> it. I'll need to think about this a bit more.

I will look into this utility and try other things out too.

This does look impressive for debug and understanding whats going on 
specifically with DSB.


As for the patch, I will use the suggested helpers for start and end 
lines and move this "wait" just before the vblank_delay usecs for VRR case.


Regards,

Ankit


>

[PATCH 9/9] drm/i915/vrr: Clamp guardband as per hardware and timing constraints

[Ankit Nautiyal]

The maximum guardband value is constrained by two factors:
- The actual vblank length minus set context latency (SCL)
- The hardware register field width:
  - 8 bits for ICL/TGL (VRR_CTL_PIPELINE_FULL_MASK -> max 255)
  - 16 bits for ADL+ (XELPD_VRR_CTL_VRR_GUARDBAND_MASK -> max 65535)

Remove the #FIXME and clamp the guardband to the maximum allowed value.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 36 ++++++++++++++++++++----
 1 file changed, 30 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5fa86356a791..9bed273f96df 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -409,6 +409,34 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	}
 }
 
+static int intel_vrr_max_hw_guardband(const struct intel_crtc_state *crtc_state)
+{
+#define VRR_GUARDBAND_MAX 65535   /* based on XELPD_VRR_CTL_VRR_GUARDBAND_MASK */
+#define VRR_PIPELINE_FULL_MAX 255 /* based on VRR_CTL_PIPELINE_FULL_MASK */
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!HAS_VRR(display))
+		return 0;
+
+	if (DISPLAY_VER(display) >= 13)
+		return VRR_GUARDBAND_MAX;
+
+	return intel_vrr_pipeline_full_to_guardband(crtc_state, VRR_PIPELINE_FULL_MAX);
+}
+
+static int clamp_guardband(struct intel_crtc_state *crtc_state, int guardband)
+{
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	int vblank_length = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay;
+	int set_context_latency = crtc_state->set_context_latency;
+	int max_hw_guardband = intel_vrr_max_hw_guardband(crtc_state);
+	int max_guardband;
+
+	max_guardband = min(max_hw_guardband, vblank_length - set_context_latency);
+
+	return min(guardband, max_guardband);
+}
+
 void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -421,16 +449,12 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
 		crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
 		intel_vrr_extra_vblank_delay(display);
 
-	if (DISPLAY_VER(display) < 13) {
-		/* FIXME handle the limit in a proper way */
-		crtc_state->vrr.guardband =
-			min(crtc_state->vrr.guardband,
-			    intel_vrr_pipeline_full_to_guardband(crtc_state, 255));
+	crtc_state->vrr.guardband = clamp_guardband(crtc_state, crtc_state->vrr.guardband);
 
+	if (DISPLAY_VER(display) < 13)
 		crtc_state->vrr.pipeline_full =
 			intel_vrr_guardband_to_pipeline_full(crtc_state,
 							     crtc_state->vrr.guardband);
-	}
 }
 
 static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
-- 
2.45.2

Re: [PATCH 9/9] drm/i915/vrr: Clamp guardband as per hardware and timing constraints

[Ville Syrjälä]

On Sun, Sep 21, 2025 at 10:05:35AM +0530, Ankit Nautiyal wrote:
> The maximum guardband value is constrained by two factors:
> - The actual vblank length minus set context latency (SCL)
> - The hardware register field width:
>   - 8 bits for ICL/TGL (VRR_CTL_PIPELINE_FULL_MASK -> max 255)
>   - 16 bits for ADL+ (XELPD_VRR_CTL_VRR_GUARDBAND_MASK -> max 65535)
> 
> Remove the #FIXME and clamp the guardband to the maximum allowed value.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 36 ++++++++++++++++++++----
>  1 file changed, 30 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 5fa86356a791..9bed273f96df 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -409,6 +409,34 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>  	}
>  }
>  
> +static int intel_vrr_max_hw_guardband(const struct intel_crtc_state *crtc_state)
> +{
> +#define VRR_GUARDBAND_MAX 65535   /* based on XELPD_VRR_CTL_VRR_GUARDBAND_MASK */
> +#define VRR_PIPELINE_FULL_MAX 255 /* based on VRR_CTL_PIPELINE_FULL_MASK */

Magic numbers aren't great.

We can get those straight from the register definitions:
 REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, XELPD_VRR_CTL_VRR_GUARDBAND_MASK)
 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, VRR_CTL_PIPELINE_FULL_MASK)

or perhaps
 REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, ~0)
 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, ~0)
to be a bit less repetitive.

Hmm, yeah I like that second form since it seems harder
to screw up the masks that way. I suppose we could even
formalize this sort of stuff into a REG_FIELD_MAX() macro...


> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	if (!HAS_VRR(display))
> +		return 0;

No one should be calling this in that case.

> +
> +	if (DISPLAY_VER(display) >= 13)
> +		return VRR_GUARDBAND_MAX;
> +
> +	return intel_vrr_pipeline_full_to_guardband(crtc_state, VRR_PIPELINE_FULL_MAX);
> +}
> +
> +static int clamp_guardband(struct intel_crtc_state *crtc_state, int guardband)
> +{
> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +	int vblank_length = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay;
> +	int set_context_latency = crtc_state->set_context_latency;
> +	int max_hw_guardband = intel_vrr_max_hw_guardband(crtc_state);
> +	int max_guardband;
> +
> +	max_guardband = min(max_hw_guardband, vblank_length - set_context_latency);
> +
> +	return min(guardband, max_guardband);

You are missing intel_vrr_extra_vblank_delay() here.

To reduce the clutter I'd pull the max guardband (in terms
of the vblank length) calculation into a separate function:

intel_vrr_max_guardband()
{
	return vmin - vdisplay - extra - scl;
}

Or maybe call it something like intel_vrr_max_vblank_guardband().

And then we could have a

intel_vrr_max_guardband()
{
	return min(intel_vrr_max_vblank_guardband(), intel_vrr_max_hw_guardband());
}

to give the final number.

> +}
> +
>  void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> @@ -421,16 +449,12 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
>  		crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
>  		intel_vrr_extra_vblank_delay(display);
>  

I think the initial guardband value here we could change to be
simply 'vmin - crtc_vdisplay' (until we start to optimize it).
That way all the hw details and whatnot will be handled by
intel_vrr_max_guardband().

So in the end this could be just
guardband = min(vmin - crtc_vdisplay,
		intel_vrr_max_guardband());


> -	if (DISPLAY_VER(display) < 13) {
> -		/* FIXME handle the limit in a proper way */
> -		crtc_state->vrr.guardband =
> -			min(crtc_state->vrr.guardband,
> -			    intel_vrr_pipeline_full_to_guardband(crtc_state, 255));
> +	crtc_state->vrr.guardband = clamp_guardband(crtc_state, crtc_state->vrr.guardband);
>  
> +	if (DISPLAY_VER(display) < 13)
>  		crtc_state->vrr.pipeline_full =
>  			intel_vrr_guardband_to_pipeline_full(crtc_state,
>  							     crtc_state->vrr.guardband);
> -	}
>  }
>  
>  static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 9/9] drm/i915/vrr: Clamp guardband as per hardware and timing constraints

[Nautiyal, Ankit K]

On 9/22/2025 4:27 PM, Ville Syrjälä wrote:
> On Sun, Sep 21, 2025 at 10:05:35AM +0530, Ankit Nautiyal wrote:
>> The maximum guardband value is constrained by two factors:
>> - The actual vblank length minus set context latency (SCL)
>> - The hardware register field width:
>>    - 8 bits for ICL/TGL (VRR_CTL_PIPELINE_FULL_MASK -> max 255)
>>    - 16 bits for ADL+ (XELPD_VRR_CTL_VRR_GUARDBAND_MASK -> max 65535)
>>
>> Remove the #FIXME and clamp the guardband to the maximum allowed value.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_vrr.c | 36 ++++++++++++++++++++----
>>   1 file changed, 30 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 5fa86356a791..9bed273f96df 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -409,6 +409,34 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>>   	}
>>   }
>>   
>> +static int intel_vrr_max_hw_guardband(const struct intel_crtc_state *crtc_state)
>> +{
>> +#define VRR_GUARDBAND_MAX 65535   /* based on XELPD_VRR_CTL_VRR_GUARDBAND_MASK */
>> +#define VRR_PIPELINE_FULL_MAX 255 /* based on VRR_CTL_PIPELINE_FULL_MASK */
> Magic numbers aren't great.
>
> We can get those straight from the register definitions:
>   REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, XELPD_VRR_CTL_VRR_GUARDBAND_MASK)
>   REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, VRR_CTL_PIPELINE_FULL_MASK)
>
> or perhaps
>   REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, ~0)
>   REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, ~0)
> to be a bit less repetitive.
>
> Hmm, yeah I like that second form since it seems harder
> to screw up the masks that way. I suppose we could even
> formalize this sort of stuff into a REG_FIELD_MAX() macro...


I was thinking to have a wrapper REG_FIELD_MAX() using FIELD_MAX defined 
bitfield.h

Or should we have  REG_FIELD_MAX(mask)    REG_FIELD_GET(max, ~0) as 
suggested?


>
>
>> +	struct intel_display *display = to_intel_display(crtc_state);
>> +
>> +	if (!HAS_VRR(display))
>> +		return 0;
> No one should be calling this in that case.
>
>> +
>> +	if (DISPLAY_VER(display) >= 13)
>> +		return VRR_GUARDBAND_MAX;
>> +
>> +	return intel_vrr_pipeline_full_to_guardband(crtc_state, VRR_PIPELINE_FULL_MAX);
>> +}
>> +
>> +static int clamp_guardband(struct intel_crtc_state *crtc_state, int guardband)
>> +{
>> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>> +	int vblank_length = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay;
>> +	int set_context_latency = crtc_state->set_context_latency;
>> +	int max_hw_guardband = intel_vrr_max_hw_guardband(crtc_state);
>> +	int max_guardband;
>> +
>> +	max_guardband = min(max_hw_guardband, vblank_length - set_context_latency);
>> +
>> +	return min(guardband, max_guardband);
> You are missing intel_vrr_extra_vblank_delay() here.
>
> To reduce the clutter I'd pull the max guardband (in terms
> of the vblank length) calculation into a separate function:
>
> intel_vrr_max_guardband()
> {
> 	return vmin - vdisplay - extra - scl;
> }
>
> Or maybe call it something like intel_vrr_max_vblank_guardband().
>
> And then we could have a
>
> intel_vrr_max_guardband()
> {
> 	return min(intel_vrr_max_vblank_guardband(), intel_vrr_max_hw_guardband());
> }
>
> to give the final number.
>
>> +}
>> +
>>   void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
>>   {
>>   	struct intel_display *display = to_intel_display(crtc_state);
>> @@ -421,16 +449,12 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
>>   		crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
>>   		intel_vrr_extra_vblank_delay(display);
>>   
> I think the initial guardband value here we could change to be
> simply 'vmin - crtc_vdisplay' (until we start to optimize it).
> That way all the hw details and whatnot will be handled by
> intel_vrr_max_guardband().
>
> So in the end this could be just
> guardband = min(vmin - crtc_vdisplay,
> 		intel_vrr_max_guardband());


Sure, will make the changes as suggested.


Regards,

Ankit

>
>
>> -	if (DISPLAY_VER(display) < 13) {
>> -		/* FIXME handle the limit in a proper way */
>> -		crtc_state->vrr.guardband =
>> -			min(crtc_state->vrr.guardband,
>> -			    intel_vrr_pipeline_full_to_guardband(crtc_state, 255));
>> +	crtc_state->vrr.guardband = clamp_guardband(crtc_state, crtc_state->vrr.guardband);
>>   
>> +	if (DISPLAY_VER(display) < 13)
>>   		crtc_state->vrr.pipeline_full =
>>   			intel_vrr_guardband_to_pipeline_full(crtc_state,
>>   							     crtc_state->vrr.guardband);
>> -	}
>>   }
>>   
>>   static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
>> -- 
>> 2.45.2

Re: [PATCH 9/9] drm/i915/vrr: Clamp guardband as per hardware and timing constraints

[Ville Syrjälä]

On Tue, Sep 23, 2025 at 04:02:44PM +0530, Nautiyal, Ankit K wrote:
> 
> On 9/22/2025 4:27 PM, Ville Syrjälä wrote:
> > On Sun, Sep 21, 2025 at 10:05:35AM +0530, Ankit Nautiyal wrote:
> >> The maximum guardband value is constrained by two factors:
> >> - The actual vblank length minus set context latency (SCL)
> >> - The hardware register field width:
> >>    - 8 bits for ICL/TGL (VRR_CTL_PIPELINE_FULL_MASK -> max 255)
> >>    - 16 bits for ADL+ (XELPD_VRR_CTL_VRR_GUARDBAND_MASK -> max 65535)
> >>
> >> Remove the #FIXME and clamp the guardband to the maximum allowed value.
> >>
> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/display/intel_vrr.c | 36 ++++++++++++++++++++----
> >>   1 file changed, 30 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> >> index 5fa86356a791..9bed273f96df 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> >> @@ -409,6 +409,34 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> >>   	}
> >>   }
> >>   
> >> +static int intel_vrr_max_hw_guardband(const struct intel_crtc_state *crtc_state)
> >> +{
> >> +#define VRR_GUARDBAND_MAX 65535   /* based on XELPD_VRR_CTL_VRR_GUARDBAND_MASK */
> >> +#define VRR_PIPELINE_FULL_MAX 255 /* based on VRR_CTL_PIPELINE_FULL_MASK */
> > Magic numbers aren't great.
> >
> > We can get those straight from the register definitions:
> >   REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, XELPD_VRR_CTL_VRR_GUARDBAND_MASK)
> >   REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, VRR_CTL_PIPELINE_FULL_MASK)
> >
> > or perhaps
> >   REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, ~0)
> >   REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, ~0)
> > to be a bit less repetitive.
> >
> > Hmm, yeah I like that second form since it seems harder
> > to screw up the masks that way. I suppose we could even
> > formalize this sort of stuff into a REG_FIELD_MAX() macro...
> 
> 
> I was thinking to have a wrapper REG_FIELD_MAX() using FIELD_MAX defined 
> bitfield.h
> 
> Or should we have  REG_FIELD_MAX(mask)    REG_FIELD_GET(max, ~0) as 
> suggested?

If FIELD_MAX() already exists and does what we need then we can
use it. I suppose we do want our own wrapper for it for consistency
with names, and I guess we also want the same (u32) cast all our
other macros have.

> 
> 
> >
> >
> >> +	struct intel_display *display = to_intel_display(crtc_state);
> >> +
> >> +	if (!HAS_VRR(display))
> >> +		return 0;
> > No one should be calling this in that case.
> >
> >> +
> >> +	if (DISPLAY_VER(display) >= 13)
> >> +		return VRR_GUARDBAND_MAX;
> >> +
> >> +	return intel_vrr_pipeline_full_to_guardband(crtc_state, VRR_PIPELINE_FULL_MAX);
> >> +}
> >> +
> >> +static int clamp_guardband(struct intel_crtc_state *crtc_state, int guardband)
> >> +{
> >> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> >> +	int vblank_length = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay;
> >> +	int set_context_latency = crtc_state->set_context_latency;
> >> +	int max_hw_guardband = intel_vrr_max_hw_guardband(crtc_state);
> >> +	int max_guardband;
> >> +
> >> +	max_guardband = min(max_hw_guardband, vblank_length - set_context_latency);
> >> +
> >> +	return min(guardband, max_guardband);
> > You are missing intel_vrr_extra_vblank_delay() here.
> >
> > To reduce the clutter I'd pull the max guardband (in terms
> > of the vblank length) calculation into a separate function:
> >
> > intel_vrr_max_guardband()
> > {
> > 	return vmin - vdisplay - extra - scl;
> > }
> >
> > Or maybe call it something like intel_vrr_max_vblank_guardband().
> >
> > And then we could have a
> >
> > intel_vrr_max_guardband()
> > {
> > 	return min(intel_vrr_max_vblank_guardband(), intel_vrr_max_hw_guardband());
> > }
> >
> > to give the final number.
> >
> >> +}
> >> +
> >>   void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
> >>   {
> >>   	struct intel_display *display = to_intel_display(crtc_state);
> >> @@ -421,16 +449,12 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
> >>   		crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
> >>   		intel_vrr_extra_vblank_delay(display);
> >>   
> > I think the initial guardband value here we could change to be
> > simply 'vmin - crtc_vdisplay' (until we start to optimize it).
> > That way all the hw details and whatnot will be handled by
> > intel_vrr_max_guardband().
> >
> > So in the end this could be just
> > guardband = min(vmin - crtc_vdisplay,
> > 		intel_vrr_max_guardband());
> 
> 
> Sure, will make the changes as suggested.
> 
> 
> Regards,
> 
> Ankit
> 
> >
> >
> >> -	if (DISPLAY_VER(display) < 13) {
> >> -		/* FIXME handle the limit in a proper way */
> >> -		crtc_state->vrr.guardband =
> >> -			min(crtc_state->vrr.guardband,
> >> -			    intel_vrr_pipeline_full_to_guardband(crtc_state, 255));
> >> +	crtc_state->vrr.guardband = clamp_guardband(crtc_state, crtc_state->vrr.guardband);
> >>   
> >> +	if (DISPLAY_VER(display) < 13)
> >>   		crtc_state->vrr.pipeline_full =
> >>   			intel_vrr_guardband_to_pipeline_full(crtc_state,
> >>   							     crtc_state->vrr.guardband);
> >> -	}
> >>   }
> >>   
> >>   static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
> >> -- 
> >> 2.45.2

-- 
Ville Syrjälä
Intel

✓ CI.KUnit: success for Introduce set_context_latency and refactor VRR/DSB timing logic

[Patchwork]

== Series Details ==

Series: Introduce set_context_latency and refactor VRR/DSB timing logic
URL   : https://patchwork.freedesktop.org/series/154809/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[04:57:12] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:57:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:57:45] Starting KUnit Kernel (1/1)...
[04:57:45] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:57:45] ================== guc_buf (11 subtests) ===================
[04:57:45] [PASSED] test_smallest
[04:57:45] [PASSED] test_largest
[04:57:45] [PASSED] test_granular
[04:57:45] [PASSED] test_unique
[04:57:45] [PASSED] test_overlap
[04:57:45] [PASSED] test_reusable
[04:57:45] [PASSED] test_too_big
[04:57:45] [PASSED] test_flush
[04:57:45] [PASSED] test_lookup
[04:57:45] [PASSED] test_data
[04:57:45] [PASSED] test_class
[04:57:45] ===================== [PASSED] guc_buf =====================
[04:57:45] =================== guc_dbm (7 subtests) ===================
[04:57:45] [PASSED] test_empty
[04:57:45] [PASSED] test_default
[04:57:45] ======================== test_size  ========================
[04:57:45] [PASSED] 4
[04:57:45] [PASSED] 8
[04:57:45] [PASSED] 32
[04:57:45] [PASSED] 256
[04:57:45] ==================== [PASSED] test_size ====================
[04:57:45] ======================= test_reuse  ========================
[04:57:45] [PASSED] 4
[04:57:45] [PASSED] 8
[04:57:45] [PASSED] 32
[04:57:45] [PASSED] 256
[04:57:45] =================== [PASSED] test_reuse ====================
[04:57:45] =================== test_range_overlap  ====================
[04:57:45] [PASSED] 4
[04:57:45] [PASSED] 8
[04:57:45] [PASSED] 32
[04:57:45] [PASSED] 256
[04:57:45] =============== [PASSED] test_range_overlap ================
[04:57:45] =================== test_range_compact  ====================
[04:57:45] [PASSED] 4
[04:57:45] [PASSED] 8
[04:57:45] [PASSED] 32
[04:57:45] [PASSED] 256
[04:57:45] =============== [PASSED] test_range_compact ================
[04:57:45] ==================== test_range_spare  =====================
[04:57:45] [PASSED] 4
[04:57:45] [PASSED] 8
[04:57:45] [PASSED] 32
[04:57:45] [PASSED] 256
[04:57:45] ================ [PASSED] test_range_spare =================
[04:57:45] ===================== [PASSED] guc_dbm =====================
[04:57:45] =================== guc_idm (6 subtests) ===================
[04:57:45] [PASSED] bad_init
[04:57:45] [PASSED] no_init
[04:57:45] [PASSED] init_fini
[04:57:45] [PASSED] check_used
[04:57:45] [PASSED] check_quota
[04:57:45] [PASSED] check_all
[04:57:45] ===================== [PASSED] guc_idm =====================
[04:57:45] ================== no_relay (3 subtests) ===================
[04:57:45] [PASSED] xe_drops_guc2pf_if_not_ready
[04:57:45] [PASSED] xe_drops_guc2vf_if_not_ready
[04:57:45] [PASSED] xe_rejects_send_if_not_ready
[04:57:45] ==================== [PASSED] no_relay =====================
[04:57:45] ================== pf_relay (14 subtests) ==================
[04:57:45] [PASSED] pf_rejects_guc2pf_too_short
[04:57:45] [PASSED] pf_rejects_guc2pf_too_long
[04:57:45] [PASSED] pf_rejects_guc2pf_no_payload
[04:57:45] [PASSED] pf_fails_no_payload
[04:57:45] [PASSED] pf_fails_bad_origin
[04:57:45] [PASSED] pf_fails_bad_type
[04:57:45] [PASSED] pf_txn_reports_error
[04:57:45] [PASSED] pf_txn_sends_pf2guc
[04:57:45] [PASSED] pf_sends_pf2guc
[04:57:45] [SKIPPED] pf_loopback_nop
[04:57:45] [SKIPPED] pf_loopback_echo
[04:57:45] [SKIPPED] pf_loopback_fail
[04:57:45] [SKIPPED] pf_loopback_busy
[04:57:45] [SKIPPED] pf_loopback_retry
[04:57:45] ==================== [PASSED] pf_relay =====================
[04:57:45] ================== vf_relay (3 subtests) ===================
[04:57:45] [PASSED] vf_rejects_guc2vf_too_short
[04:57:45] [PASSED] vf_rejects_guc2vf_too_long
[04:57:45] [PASSED] vf_rejects_guc2vf_no_payload
[04:57:45] ==================== [PASSED] vf_relay =====================
[04:57:45] ===================== lmtt (1 subtest) =====================
[04:57:45] ======================== test_ops  =========================
[04:57:45] [PASSED] 2-level
[04:57:45] [PASSED] multi-level
[04:57:45] ==================== [PASSED] test_ops =====================
[04:57:45] ====================== [PASSED] lmtt =======================
[04:57:45] ================= pf_service (11 subtests) =================
[04:57:45] [PASSED] pf_negotiate_any
[04:57:45] [PASSED] pf_negotiate_base_match
[04:57:45] [PASSED] pf_negotiate_base_newer
[04:57:45] [PASSED] pf_negotiate_base_next
[04:57:45] [SKIPPED] pf_negotiate_base_older
[04:57:45] [PASSED] pf_negotiate_base_prev
[04:57:45] [PASSED] pf_negotiate_latest_match
[04:57:45] [PASSED] pf_negotiate_latest_newer
[04:57:45] [PASSED] pf_negotiate_latest_next
[04:57:45] [SKIPPED] pf_negotiate_latest_older
[04:57:45] [SKIPPED] pf_negotiate_latest_prev
[04:57:45] =================== [PASSED] pf_service ====================
[04:57:45] ================= xe_guc_g2g (2 subtests) ==================
[04:57:45] ============== xe_live_guc_g2g_kunit_default  ==============
[04:57:45] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[04:57:45] ============== xe_live_guc_g2g_kunit_allmem  ===============
[04:57:45] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[04:57:45] =================== [SKIPPED] xe_guc_g2g ===================
[04:57:45] =================== xe_mocs (2 subtests) ===================
[04:57:45] ================ xe_live_mocs_kernel_kunit  ================
[04:57:45] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[04:57:45] ================ xe_live_mocs_reset_kunit  =================
[04:57:45] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[04:57:45] ==================== [SKIPPED] xe_mocs =====================
[04:57:45] ================= xe_migrate (2 subtests) ==================
[04:57:45] ================= xe_migrate_sanity_kunit  =================
[04:57:45] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[04:57:45] ================== xe_validate_ccs_kunit  ==================
[04:57:45] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[04:57:45] =================== [SKIPPED] xe_migrate ===================
[04:57:45] ================== xe_dma_buf (1 subtest) ==================
[04:57:45] ==================== xe_dma_buf_kunit  =====================
[04:57:45] ================ [SKIPPED] xe_dma_buf_kunit ================
[04:57:45] =================== [SKIPPED] xe_dma_buf ===================
[04:57:45] ================= xe_bo_shrink (1 subtest) =================
[04:57:45] =================== xe_bo_shrink_kunit  ====================
[04:57:45] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[04:57:45] ================== [SKIPPED] xe_bo_shrink ==================
[04:57:45] ==================== xe_bo (2 subtests) ====================
[04:57:45] ================== xe_ccs_migrate_kunit  ===================
[04:57:45] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[04:57:45] ==================== xe_bo_evict_kunit  ====================
[04:57:45] =============== [SKIPPED] xe_bo_evict_kunit ================
[04:57:45] ===================== [SKIPPED] xe_bo ======================
[04:57:45] ==================== args (11 subtests) ====================
[04:57:45] [PASSED] count_args_test
[04:57:45] [PASSED] call_args_example
[04:57:45] [PASSED] call_args_test
[04:57:45] [PASSED] drop_first_arg_example
[04:57:45] [PASSED] drop_first_arg_test
[04:57:45] [PASSED] first_arg_example
[04:57:45] [PASSED] first_arg_test
[04:57:45] [PASSED] last_arg_example
[04:57:45] [PASSED] last_arg_test
[04:57:45] [PASSED] pick_arg_example
[04:57:45] [PASSED] sep_comma_example
[04:57:45] ====================== [PASSED] args =======================
[04:57:45] =================== xe_pci (3 subtests) ====================
[04:57:45] ==================== check_graphics_ip  ====================
[04:57:45] [PASSED] 12.00 Xe_LP
[04:57:45] [PASSED] 12.10 Xe_LP+
[04:57:45] [PASSED] 12.55 Xe_HPG
[04:57:45] [PASSED] 12.60 Xe_HPC
[04:57:45] [PASSED] 12.70 Xe_LPG
[04:57:45] [PASSED] 12.71 Xe_LPG
[04:57:45] [PASSED] 12.74 Xe_LPG+
[04:57:45] [PASSED] 20.01 Xe2_HPG
[04:57:45] [PASSED] 20.02 Xe2_HPG
[04:57:45] [PASSED] 20.04 Xe2_LPG
[04:57:45] [PASSED] 30.00 Xe3_LPG
[04:57:45] [PASSED] 30.01 Xe3_LPG
[04:57:45] [PASSED] 30.03 Xe3_LPG
[04:57:45] ================ [PASSED] check_graphics_ip ================
[04:57:45] ===================== check_media_ip  ======================
[04:57:45] [PASSED] 12.00 Xe_M
[04:57:45] [PASSED] 12.55 Xe_HPM
[04:57:45] [PASSED] 13.00 Xe_LPM+
[04:57:45] [PASSED] 13.01 Xe2_HPM
[04:57:45] [PASSED] 20.00 Xe2_LPM
[04:57:45] [PASSED] 30.00 Xe3_LPM
[04:57:45] [PASSED] 30.02 Xe3_LPM
[04:57:45] ================= [PASSED] check_media_ip ==================
[04:57:45] ================= check_platform_gt_count  =================
[04:57:45] [PASSED] 0x9A60 (TIGERLAKE)
[04:57:45] [PASSED] 0x9A68 (TIGERLAKE)
[04:57:45] [PASSED] 0x9A70 (TIGERLAKE)
[04:57:45] [PASSED] 0x9A40 (TIGERLAKE)
[04:57:45] [PASSED] 0x9A49 (TIGERLAKE)
[04:57:45] [PASSED] 0x9A59 (TIGERLAKE)
[04:57:45] [PASSED] 0x9A78 (TIGERLAKE)
[04:57:45] [PASSED] 0x9AC0 (TIGERLAKE)
[04:57:45] [PASSED] 0x9AC9 (TIGERLAKE)
[04:57:45] [PASSED] 0x9AD9 (TIGERLAKE)
[04:57:45] [PASSED] 0x9AF8 (TIGERLAKE)
[04:57:45] [PASSED] 0x4C80 (ROCKETLAKE)
[04:57:45] [PASSED] 0x4C8A (ROCKETLAKE)
[04:57:45] [PASSED] 0x4C8B (ROCKETLAKE)
[04:57:45] [PASSED] 0x4C8C (ROCKETLAKE)
[04:57:45] [PASSED] 0x4C90 (ROCKETLAKE)
[04:57:45] [PASSED] 0x4C9A (ROCKETLAKE)
[04:57:45] [PASSED] 0x4680 (ALDERLAKE_S)
[04:57:45] [PASSED] 0x4682 (ALDERLAKE_S)
[04:57:45] [PASSED] 0x4688 (ALDERLAKE_S)
[04:57:45] [PASSED] 0x468A (ALDERLAKE_S)
[04:57:45] [PASSED] 0x468B (ALDERLAKE_S)
[04:57:45] [PASSED] 0x4690 (ALDERLAKE_S)
[04:57:45] [PASSED] 0x4692 (ALDERLAKE_S)
[04:57:45] [PASSED] 0x4693 (ALDERLAKE_S)
[04:57:45] [PASSED] 0x46A0 (ALDERLAKE_P)
[04:57:45] [PASSED] 0x46A1 (ALDERLAKE_P)
[04:57:45] [PASSED] 0x46A2 (ALDERLAKE_P)
[04:57:45] [PASSED] 0x46A3 (ALDERLAKE_P)
[04:57:45] [PASSED] 0x46A6 (ALDERLAKE_P)
[04:57:45] [PASSED] 0x46A8 (ALDERLAKE_P)
[04:57:45] [PASSED] 0x46AA (ALDERLAKE_P)
[04:57:45] [PASSED] 0x462A (ALDERLAKE_P)
[04:57:45] [PASSED] 0x4626 (ALDERLAKE_P)
[04:57:45] [PASSED] 0x4628 (ALDERLAKE_P)
[04:57:45] [PASSED] 0x46B0 (ALDERLAKE_P)
[04:57:45] [PASSED] 0x46B1 (ALDERLAKE_P)
[04:57:45] [PASSED] 0x46B2 (ALDERLAKE_P)
[04:57:45] [PASSED] 0x46B3 (ALDERLAKE_P)
[04:57:45] [PASSED] 0x46C0 (ALDERLAKE_P)
[04:57:45] [PASSED] 0x46C1 (ALDERLAKE_P)
[04:57:45] [PASSED] 0x46C2 (ALDERLAKE_P)
[04:57:45] [PASSED] 0x46C3 (ALDERLAKE_P)
[04:57:45] [PASSED] 0x46D0 (ALDERLAKE_N)
[04:57:45] [PASSED] 0x46D1 (ALDERLAKE_N)
[04:57:45] [PASSED] 0x46D2 (ALDERLAKE_N)
[04:57:45] [PASSED] 0x46D3 (ALDERLAKE_N)
[04:57:45] [PASSED] 0x46D4 (ALDERLAKE_N)
[04:57:45] [PASSED] 0xA721 (ALDERLAKE_P)
[04:57:45] [PASSED] 0xA7A1 (ALDERLAKE_P)
[04:57:45] [PASSED] 0xA7A9 (ALDERLAKE_P)
[04:57:45] [PASSED] 0xA7AC (ALDERLAKE_P)
[04:57:45] [PASSED] 0xA7AD (ALDERLAKE_P)
[04:57:45] [PASSED] 0xA720 (ALDERLAKE_P)
[04:57:45] [PASSED] 0xA7A0 (ALDERLAKE_P)
[04:57:45] [PASSED] 0xA7A8 (ALDERLAKE_P)
[04:57:45] [PASSED] 0xA7AA (ALDERLAKE_P)
[04:57:45] [PASSED] 0xA7AB (ALDERLAKE_P)
[04:57:45] [PASSED] 0xA780 (ALDERLAKE_S)
[04:57:45] [PASSED] 0xA781 (ALDERLAKE_S)
[04:57:45] [PASSED] 0xA782 (ALDERLAKE_S)
[04:57:45] [PASSED] 0xA783 (ALDERLAKE_S)
[04:57:45] [PASSED] 0xA788 (ALDERLAKE_S)
[04:57:45] [PASSED] 0xA789 (ALDERLAKE_S)
[04:57:45] [PASSED] 0xA78A (ALDERLAKE_S)
[04:57:45] [PASSED] 0xA78B (ALDERLAKE_S)
[04:57:45] [PASSED] 0x4905 (DG1)
[04:57:45] [PASSED] 0x4906 (DG1)
[04:57:45] [PASSED] 0x4907 (DG1)
[04:57:45] [PASSED] 0x4908 (DG1)
[04:57:45] [PASSED] 0x4909 (DG1)
[04:57:45] [PASSED] 0x56C0 (DG2)
[04:57:45] [PASSED] 0x56C2 (DG2)
[04:57:45] [PASSED] 0x56C1 (DG2)
[04:57:45] [PASSED] 0x7D51 (METEORLAKE)
[04:57:45] [PASSED] 0x7DD1 (METEORLAKE)
[04:57:45] [PASSED] 0x7D41 (METEORLAKE)
[04:57:45] [PASSED] 0x7D67 (METEORLAKE)
[04:57:45] [PASSED] 0xB640 (METEORLAKE)
[04:57:45] [PASSED] 0x56A0 (DG2)
[04:57:45] [PASSED] 0x56A1 (DG2)
[04:57:45] [PASSED] 0x56A2 (DG2)
[04:57:45] [PASSED] 0x56BE (DG2)
[04:57:45] [PASSED] 0x56BF (DG2)
[04:57:45] [PASSED] 0x5690 (DG2)
[04:57:45] [PASSED] 0x5691 (DG2)
[04:57:45] [PASSED] 0x5692 (DG2)
[04:57:45] [PASSED] 0x56A5 (DG2)
[04:57:45] [PASSED] 0x56A6 (DG2)
[04:57:45] [PASSED] 0x56B0 (DG2)
[04:57:45] [PASSED] 0x56B1 (DG2)
[04:57:45] [PASSED] 0x56BA (DG2)
[04:57:45] [PASSED] 0x56BB (DG2)
[04:57:45] [PASSED] 0x56BC (DG2)
[04:57:45] [PASSED] 0x56BD (DG2)
[04:57:45] [PASSED] 0x5693 (DG2)
[04:57:45] [PASSED] 0x5694 (DG2)
[04:57:45] [PASSED] 0x5695 (DG2)
[04:57:45] [PASSED] 0x56A3 (DG2)
[04:57:45] [PASSED] 0x56A4 (DG2)
[04:57:45] [PASSED] 0x56B2 (DG2)
[04:57:45] [PASSED] 0x56B3 (DG2)
[04:57:45] [PASSED] 0x5696 (DG2)
[04:57:45] [PASSED] 0x5697 (DG2)
[04:57:45] [PASSED] 0xB69 (PVC)
[04:57:45] [PASSED] 0xB6E (PVC)
[04:57:45] [PASSED] 0xBD4 (PVC)
[04:57:45] [PASSED] 0xBD5 (PVC)
[04:57:45] [PASSED] 0xBD6 (PVC)
[04:57:45] [PASSED] 0xBD7 (PVC)
[04:57:45] [PASSED] 0xBD8 (PVC)
[04:57:45] [PASSED] 0xBD9 (PVC)
[04:57:45] [PASSED] 0xBDA (PVC)
[04:57:45] [PASSED] 0xBDB (PVC)
[04:57:45] [PASSED] 0xBE0 (PVC)
[04:57:45] [PASSED] 0xBE1 (PVC)
[04:57:45] [PASSED] 0xBE5 (PVC)
[04:57:45] [PASSED] 0x7D40 (METEORLAKE)
[04:57:45] [PASSED] 0x7D45 (METEORLAKE)
[04:57:45] [PASSED] 0x7D55 (METEORLAKE)
[04:57:45] [PASSED] 0x7D60 (METEORLAKE)
[04:57:45] [PASSED] 0x7DD5 (METEORLAKE)
[04:57:45] [PASSED] 0x6420 (LUNARLAKE)
[04:57:45] [PASSED] 0x64A0 (LUNARLAKE)
[04:57:45] [PASSED] 0x64B0 (LUNARLAKE)
[04:57:45] [PASSED] 0xE202 (BATTLEMAGE)
[04:57:45] [PASSED] 0xE209 (BATTLEMAGE)
[04:57:45] [PASSED] 0xE20B (BATTLEMAGE)
[04:57:45] [PASSED] 0xE20C (BATTLEMAGE)
[04:57:45] [PASSED] 0xE20D (BATTLEMAGE)
[04:57:45] [PASSED] 0xE210 (BATTLEMAGE)
[04:57:45] [PASSED] 0xE211 (BATTLEMAGE)
[04:57:45] [PASSED] 0xE212 (BATTLEMAGE)
[04:57:45] [PASSED] 0xE216 (BATTLEMAGE)
[04:57:45] [PASSED] 0xE220 (BATTLEMAGE)
[04:57:45] [PASSED] 0xE221 (BATTLEMAGE)
[04:57:45] [PASSED] 0xE222 (BATTLEMAGE)
[04:57:45] [PASSED] 0xE223 (BATTLEMAGE)
[04:57:45] [PASSED] 0xB080 (PANTHERLAKE)
[04:57:45] [PASSED] 0xB081 (PANTHERLAKE)
[04:57:45] [PASSED] 0xB082 (PANTHERLAKE)
[04:57:45] [PASSED] 0xB083 (PANTHERLAKE)
[04:57:45] [PASSED] 0xB084 (PANTHERLAKE)
[04:57:45] [PASSED] 0xB085 (PANTHERLAKE)
[04:57:45] [PASSED] 0xB086 (PANTHERLAKE)
[04:57:45] [PASSED] 0xB087 (PANTHERLAKE)
[04:57:45] [PASSED] 0xB08F (PANTHERLAKE)
[04:57:45] [PASSED] 0xB090 (PANTHERLAKE)
[04:57:45] [PASSED] 0xB0A0 (PANTHERLAKE)
[04:57:45] [PASSED] 0xB0B0 (PANTHERLAKE)
[04:57:45] [PASSED] 0xFD80 (PANTHERLAKE)
[04:57:45] [PASSED] 0xFD81 (PANTHERLAKE)
[04:57:45] ============= [PASSED] check_platform_gt_count =============
[04:57:45] ===================== [PASSED] xe_pci ======================
[04:57:45] =================== xe_rtp (2 subtests) ====================
[04:57:45] =============== xe_rtp_process_to_sr_tests  ================
[04:57:45] [PASSED] coalesce-same-reg
[04:57:45] [PASSED] no-match-no-add
[04:57:45] [PASSED] match-or
[04:57:45] [PASSED] match-or-xfail
[04:57:45] [PASSED] no-match-no-add-multiple-rules
[04:57:45] [PASSED] two-regs-two-entries
[04:57:45] [PASSED] clr-one-set-other
[04:57:45] [PASSED] set-field
[04:57:45] [PASSED] conflict-duplicate
[04:57:45] [PASSED] conflict-not-disjoint
[04:57:45] [PASSED] conflict-reg-type
[04:57:45] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[04:57:45] ================== xe_rtp_process_tests  ===================
[04:57:45] [PASSED] active1
[04:57:45] [PASSED] active2
[04:57:45] [PASSED] active-inactive
[04:57:45] [PASSED] inactive-active
[04:57:45] [PASSED] inactive-1st_or_active-inactive
[04:57:45] [PASSED] inactive-2nd_or_active-inactive
[04:57:45] [PASSED] inactive-last_or_active-inactive
[04:57:45] [PASSED] inactive-no_or_active-inactive
[04:57:45] ============== [PASSED] xe_rtp_process_tests ===============
[04:57:45] ===================== [PASSED] xe_rtp ======================
[04:57:45] ==================== xe_wa (1 subtest) =====================
[04:57:45] ======================== xe_wa_gt  =========================
[04:57:45] [PASSED] TIGERLAKE B0
[04:57:45] [PASSED] DG1 A0
[04:57:45] [PASSED] DG1 B0
[04:57:45] [PASSED] ALDERLAKE_S A0
[04:57:45] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[04:57:45] [PASSED] ALDERLAKE_S C0
[04:57:45] [PASSED] ALDERLAKE_S D0
[04:57:45] [PASSED] ALDERLAKE_P A0
[04:57:45] [PASSED] ALDERLAKE_P B0
[04:57:45] [PASSED] ALDERLAKE_P C0
[04:57:45] [PASSED] ALDERLAKE_S RPLS D0
[04:57:45] [PASSED] ALDERLAKE_P RPLU E0
[04:57:45] [PASSED] DG2 G10 C0
[04:57:45] [PASSED] DG2 G11 B1
[04:57:45] [PASSED] DG2 G12 A1
[04:57:45] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:57:45] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:57:45] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[04:57:45] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[04:57:45] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[04:57:45] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[04:57:45] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[04:57:45] ==================== [PASSED] xe_wa_gt =====================
[04:57:45] ====================== [PASSED] xe_wa ======================
[04:57:45] ============================================================
[04:57:45] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[04:57:45] Elapsed time: 33.740s total, 4.227s configuring, 29.147s building, 0.320s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[04:57:46] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:57:47] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:58:11] Starting KUnit Kernel (1/1)...
[04:58:11] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:58:11] ============ drm_test_pick_cmdline (2 subtests) ============
[04:58:11] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[04:58:11] =============== drm_test_pick_cmdline_named  ===============
[04:58:11] [PASSED] NTSC
[04:58:11] [PASSED] NTSC-J
[04:58:11] [PASSED] PAL
[04:58:11] [PASSED] PAL-M
[04:58:11] =========== [PASSED] drm_test_pick_cmdline_named ===========
[04:58:11] ============== [PASSED] drm_test_pick_cmdline ==============
[04:58:11] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[04:58:11] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[04:58:11] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[04:58:11] =========== drm_validate_clone_mode (2 subtests) ===========
[04:58:11] ============== drm_test_check_in_clone_mode  ===============
[04:58:11] [PASSED] in_clone_mode
[04:58:11] [PASSED] not_in_clone_mode
[04:58:11] ========== [PASSED] drm_test_check_in_clone_mode ===========
[04:58:11] =============== drm_test_check_valid_clones  ===============
[04:58:11] [PASSED] not_in_clone_mode
[04:58:11] [PASSED] valid_clone
[04:58:11] [PASSED] invalid_clone
[04:58:11] =========== [PASSED] drm_test_check_valid_clones ===========
[04:58:11] ============= [PASSED] drm_validate_clone_mode =============
[04:58:11] ============= drm_validate_modeset (1 subtest) =============
[04:58:11] [PASSED] drm_test_check_connector_changed_modeset
[04:58:11] ============== [PASSED] drm_validate_modeset ===============
[04:58:11] ====== drm_test_bridge_get_current_state (2 subtests) ======
[04:58:11] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[04:58:11] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[04:58:11] ======== [PASSED] drm_test_bridge_get_current_state ========
[04:58:11] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[04:58:11] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[04:58:11] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[04:58:11] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[04:58:11] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[04:58:11] ============== drm_bridge_alloc (2 subtests) ===============
[04:58:11] [PASSED] drm_test_drm_bridge_alloc_basic
[04:58:11] [PASSED] drm_test_drm_bridge_alloc_get_put
[04:58:11] ================ [PASSED] drm_bridge_alloc =================
[04:58:11] ================== drm_buddy (7 subtests) ==================
[04:58:11] [PASSED] drm_test_buddy_alloc_limit
[04:58:11] [PASSED] drm_test_buddy_alloc_optimistic
[04:58:11] [PASSED] drm_test_buddy_alloc_pessimistic
[04:58:11] [PASSED] drm_test_buddy_alloc_pathological
[04:58:11] [PASSED] drm_test_buddy_alloc_contiguous
[04:58:11] [PASSED] drm_test_buddy_alloc_clear
[04:58:11] [PASSED] drm_test_buddy_alloc_range_bias
[04:58:11] ==================== [PASSED] drm_buddy ====================
[04:58:11] ============= drm_cmdline_parser (40 subtests) =============
[04:58:11] [PASSED] drm_test_cmdline_force_d_only
[04:58:11] [PASSED] drm_test_cmdline_force_D_only_dvi
[04:58:11] [PASSED] drm_test_cmdline_force_D_only_hdmi
[04:58:11] [PASSED] drm_test_cmdline_force_D_only_not_digital
[04:58:11] [PASSED] drm_test_cmdline_force_e_only
[04:58:11] [PASSED] drm_test_cmdline_res
[04:58:11] [PASSED] drm_test_cmdline_res_vesa
[04:58:11] [PASSED] drm_test_cmdline_res_vesa_rblank
[04:58:11] [PASSED] drm_test_cmdline_res_rblank
[04:58:11] [PASSED] drm_test_cmdline_res_bpp
[04:58:11] [PASSED] drm_test_cmdline_res_refresh
[04:58:11] [PASSED] drm_test_cmdline_res_bpp_refresh
[04:58:11] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[04:58:11] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[04:58:11] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[04:58:11] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[04:58:11] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[04:58:11] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[04:58:11] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[04:58:11] [PASSED] drm_test_cmdline_res_margins_force_on
[04:58:11] [PASSED] drm_test_cmdline_res_vesa_margins
[04:58:11] [PASSED] drm_test_cmdline_name
[04:58:11] [PASSED] drm_test_cmdline_name_bpp
[04:58:11] [PASSED] drm_test_cmdline_name_option
[04:58:11] [PASSED] drm_test_cmdline_name_bpp_option
[04:58:11] [PASSED] drm_test_cmdline_rotate_0
[04:58:11] [PASSED] drm_test_cmdline_rotate_90
[04:58:11] [PASSED] drm_test_cmdline_rotate_180
[04:58:11] [PASSED] drm_test_cmdline_rotate_270
[04:58:11] [PASSED] drm_test_cmdline_hmirror
[04:58:11] [PASSED] drm_test_cmdline_vmirror
[04:58:11] [PASSED] drm_test_cmdline_margin_options
[04:58:11] [PASSED] drm_test_cmdline_multiple_options
[04:58:11] [PASSED] drm_test_cmdline_bpp_extra_and_option
[04:58:11] [PASSED] drm_test_cmdline_extra_and_option
[04:58:11] [PASSED] drm_test_cmdline_freestanding_options
[04:58:11] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[04:58:11] [PASSED] drm_test_cmdline_panel_orientation
[04:58:11] ================ drm_test_cmdline_invalid  =================
[04:58:11] [PASSED] margin_only
[04:58:11] [PASSED] interlace_only
[04:58:11] [PASSED] res_missing_x
[04:58:11] [PASSED] res_missing_y
[04:58:11] [PASSED] res_bad_y
[04:58:11] [PASSED] res_missing_y_bpp
[04:58:11] [PASSED] res_bad_bpp
[04:58:11] [PASSED] res_bad_refresh
[04:58:11] [PASSED] res_bpp_refresh_force_on_off
[04:58:11] [PASSED] res_invalid_mode
[04:58:11] [PASSED] res_bpp_wrong_place_mode
[04:58:11] [PASSED] name_bpp_refresh
[04:58:11] [PASSED] name_refresh
[04:58:11] [PASSED] name_refresh_wrong_mode
[04:58:11] [PASSED] name_refresh_invalid_mode
[04:58:11] [PASSED] rotate_multiple
[04:58:11] [PASSED] rotate_invalid_val
[04:58:11] [PASSED] rotate_truncated
[04:58:11] [PASSED] invalid_option
[04:58:11] [PASSED] invalid_tv_option
[04:58:11] [PASSED] truncated_tv_option
[04:58:11] ============ [PASSED] drm_test_cmdline_invalid =============
[04:58:11] =============== drm_test_cmdline_tv_options  ===============
[04:58:11] [PASSED] NTSC
[04:58:11] [PASSED] NTSC_443
[04:58:11] [PASSED] NTSC_J
[04:58:11] [PASSED] PAL
[04:58:11] [PASSED] PAL_M
[04:58:11] [PASSED] PAL_N
[04:58:11] [PASSED] SECAM
[04:58:11] [PASSED] MONO_525
[04:58:11] [PASSED] MONO_625
[04:58:11] =========== [PASSED] drm_test_cmdline_tv_options ===========
[04:58:11] =============== [PASSED] drm_cmdline_parser ================
[04:58:11] ========== drmm_connector_hdmi_init (20 subtests) ==========
[04:58:11] [PASSED] drm_test_connector_hdmi_init_valid
[04:58:11] [PASSED] drm_test_connector_hdmi_init_bpc_8
[04:58:11] [PASSED] drm_test_connector_hdmi_init_bpc_10
[04:58:11] [PASSED] drm_test_connector_hdmi_init_bpc_12
[04:58:11] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[04:58:11] [PASSED] drm_test_connector_hdmi_init_bpc_null
[04:58:11] [PASSED] drm_test_connector_hdmi_init_formats_empty
[04:58:11] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[04:58:11] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[04:58:11] [PASSED] supported_formats=0x9 yuv420_allowed=1
[04:58:11] [PASSED] supported_formats=0x9 yuv420_allowed=0
[04:58:11] [PASSED] supported_formats=0x3 yuv420_allowed=1
[04:58:11] [PASSED] supported_formats=0x3 yuv420_allowed=0
[04:58:11] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[04:58:11] [PASSED] drm_test_connector_hdmi_init_null_ddc
[04:58:11] [PASSED] drm_test_connector_hdmi_init_null_product
[04:58:11] [PASSED] drm_test_connector_hdmi_init_null_vendor
[04:58:11] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[04:58:11] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[04:58:11] [PASSED] drm_test_connector_hdmi_init_product_valid
[04:58:11] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[04:58:11] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[04:58:11] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[04:58:11] ========= drm_test_connector_hdmi_init_type_valid  =========
[04:58:11] [PASSED] HDMI-A
[04:58:11] [PASSED] HDMI-B
[04:58:11] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[04:58:11] ======== drm_test_connector_hdmi_init_type_invalid  ========
[04:58:11] [PASSED] Unknown
[04:58:11] [PASSED] VGA
[04:58:11] [PASSED] DVI-I
[04:58:11] [PASSED] DVI-D
[04:58:11] [PASSED] DVI-A
[04:58:11] [PASSED] Composite
[04:58:11] [PASSED] SVIDEO
[04:58:11] [PASSED] LVDS
[04:58:11] [PASSED] Component
[04:58:11] [PASSED] DIN
[04:58:11] [PASSED] DP
[04:58:11] [PASSED] TV
[04:58:11] [PASSED] eDP
[04:58:11] [PASSED] Virtual
[04:58:11] [PASSED] DSI
[04:58:11] [PASSED] DPI
[04:58:11] [PASSED] Writeback
[04:58:11] [PASSED] SPI
[04:58:11] [PASSED] USB
[04:58:11] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[04:58:11] ============ [PASSED] drmm_connector_hdmi_init =============
[04:58:11] ============= drmm_connector_init (3 subtests) =============
[04:58:11] [PASSED] drm_test_drmm_connector_init
[04:58:11] [PASSED] drm_test_drmm_connector_init_null_ddc
[04:58:11] ========= drm_test_drmm_connector_init_type_valid  =========
[04:58:11] [PASSED] Unknown
[04:58:11] [PASSED] VGA
[04:58:11] [PASSED] DVI-I
[04:58:11] [PASSED] DVI-D
[04:58:11] [PASSED] DVI-A
[04:58:11] [PASSED] Composite
[04:58:11] [PASSED] SVIDEO
[04:58:11] [PASSED] LVDS
[04:58:11] [PASSED] Component
[04:58:11] [PASSED] DIN
[04:58:11] [PASSED] DP
[04:58:11] [PASSED] HDMI-A
[04:58:11] [PASSED] HDMI-B
[04:58:11] [PASSED] TV
[04:58:11] [PASSED] eDP
[04:58:11] [PASSED] Virtual
[04:58:11] [PASSED] DSI
[04:58:11] [PASSED] DPI
[04:58:11] [PASSED] Writeback
[04:58:11] [PASSED] SPI
[04:58:11] [PASSED] USB
[04:58:11] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[04:58:11] =============== [PASSED] drmm_connector_init ===============
[04:58:11] ========= drm_connector_dynamic_init (6 subtests) ==========
[04:58:11] [PASSED] drm_test_drm_connector_dynamic_init
[04:58:11] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[04:58:11] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[04:58:11] [PASSED] drm_test_drm_connector_dynamic_init_properties
[04:58:11] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[04:58:11] [PASSED] Unknown
[04:58:11] [PASSED] VGA
[04:58:11] [PASSED] DVI-I
[04:58:11] [PASSED] DVI-D
[04:58:11] [PASSED] DVI-A
[04:58:11] [PASSED] Composite
[04:58:11] [PASSED] SVIDEO
[04:58:11] [PASSED] LVDS
[04:58:11] [PASSED] Component
[04:58:11] [PASSED] DIN
[04:58:11] [PASSED] DP
[04:58:11] [PASSED] HDMI-A
[04:58:11] [PASSED] HDMI-B
[04:58:11] [PASSED] TV
[04:58:11] [PASSED] eDP
[04:58:11] [PASSED] Virtual
[04:58:11] [PASSED] DSI
[04:58:11] [PASSED] DPI
[04:58:11] [PASSED] Writeback
[04:58:11] [PASSED] SPI
[04:58:11] [PASSED] USB
[04:58:11] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[04:58:11] ======== drm_test_drm_connector_dynamic_init_name  =========
[04:58:11] [PASSED] Unknown
[04:58:11] [PASSED] VGA
[04:58:11] [PASSED] DVI-I
[04:58:11] [PASSED] DVI-D
[04:58:11] [PASSED] DVI-A
[04:58:11] [PASSED] Composite
[04:58:11] [PASSED] SVIDEO
[04:58:11] [PASSED] LVDS
[04:58:11] [PASSED] Component
[04:58:11] [PASSED] DIN
[04:58:11] [PASSED] DP
[04:58:11] [PASSED] HDMI-A
[04:58:11] [PASSED] HDMI-B
[04:58:11] [PASSED] TV
[04:58:11] [PASSED] eDP
[04:58:11] [PASSED] Virtual
[04:58:11] [PASSED] DSI
[04:58:11] [PASSED] DPI
[04:58:11] [PASSED] Writeback
[04:58:11] [PASSED] SPI
[04:58:11] [PASSED] USB
[04:58:11] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[04:58:11] =========== [PASSED] drm_connector_dynamic_init ============
[04:58:11] ==== drm_connector_dynamic_register_early (4 subtests) =====
[04:58:11] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[04:58:11] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[04:58:11] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[04:58:11] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[04:58:11] ====== [PASSED] drm_connector_dynamic_register_early =======
[04:58:11] ======= drm_connector_dynamic_register (7 subtests) ========
[04:58:11] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[04:58:11] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[04:58:11] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[04:58:11] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[04:58:11] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[04:58:11] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[04:58:11] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[04:58:11] ========= [PASSED] drm_connector_dynamic_register ==========
[04:58:11] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[04:58:11] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[04:58:11] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[04:58:11] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[04:58:11] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[04:58:11] ========== drm_test_get_tv_mode_from_name_valid  ===========
[04:58:11] [PASSED] NTSC
[04:58:11] [PASSED] NTSC-443
[04:58:11] [PASSED] NTSC-J
[04:58:11] [PASSED] PAL
[04:58:11] [PASSED] PAL-M
[04:58:11] [PASSED] PAL-N
[04:58:11] [PASSED] SECAM
[04:58:11] [PASSED] Mono
[04:58:11] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[04:58:11] [PASSED] drm_test_get_tv_mode_from_name_truncated
[04:58:11] ============ [PASSED] drm_get_tv_mode_from_name ============
[04:58:11] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[04:58:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[04:58:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[04:58:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[04:58:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[04:58:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[04:58:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[04:58:11] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[04:58:11] [PASSED] VIC 96
[04:58:11] [PASSED] VIC 97
[04:58:11] [PASSED] VIC 101
[04:58:11] [PASSED] VIC 102
[04:58:11] [PASSED] VIC 106
[04:58:11] [PASSED] VIC 107
[04:58:11] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[04:58:11] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[04:58:11] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[04:58:11] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[04:58:11] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[04:58:11] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[04:58:11] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[04:58:11] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[04:58:11] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[04:58:11] [PASSED] Automatic
[04:58:11] [PASSED] Full
[04:58:11] [PASSED] Limited 16:235
[04:58:11] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[04:58:11] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[04:58:11] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[04:58:11] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[04:58:11] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[04:58:11] [PASSED] RGB
[04:58:11] [PASSED] YUV 4:2:0
[04:58:11] [PASSED] YUV 4:2:2
[04:58:11] [PASSED] YUV 4:4:4
[04:58:11] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[04:58:11] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[04:58:11] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[04:58:11] ============= drm_damage_helper (21 subtests) ==============
[04:58:11] [PASSED] drm_test_damage_iter_no_damage
[04:58:11] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[04:58:11] [PASSED] drm_test_damage_iter_no_damage_src_moved
[04:58:11] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[04:58:11] [PASSED] drm_test_damage_iter_no_damage_not_visible
[04:58:11] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[04:58:11] [PASSED] drm_test_damage_iter_no_damage_no_fb
[04:58:11] [PASSED] drm_test_damage_iter_simple_damage
[04:58:11] [PASSED] drm_test_damage_iter_single_damage
[04:58:11] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[04:58:11] [PASSED] drm_test_damage_iter_single_damage_outside_src
[04:58:11] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[04:58:11] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[04:58:11] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[04:58:11] [PASSED] drm_test_damage_iter_single_damage_src_moved
[04:58:11] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[04:58:11] [PASSED] drm_test_damage_iter_damage
[04:58:11] [PASSED] drm_test_damage_iter_damage_one_intersect
[04:58:11] [PASSED] drm_test_damage_iter_damage_one_outside
[04:58:11] [PASSED] drm_test_damage_iter_damage_src_moved
[04:58:11] [PASSED] drm_test_damage_iter_damage_not_visible
[04:58:11] ================ [PASSED] drm_damage_helper ================
[04:58:11] ============== drm_dp_mst_helper (3 subtests) ==============
[04:58:11] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[04:58:11] [PASSED] Clock 154000 BPP 30 DSC disabled
[04:58:11] [PASSED] Clock 234000 BPP 30 DSC disabled
[04:58:11] [PASSED] Clock 297000 BPP 24 DSC disabled
[04:58:11] [PASSED] Clock 332880 BPP 24 DSC enabled
[04:58:11] [PASSED] Clock 324540 BPP 24 DSC enabled
[04:58:11] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[04:58:11] ============== drm_test_dp_mst_calc_pbn_div  ===============
[04:58:11] [PASSED] Link rate 2000000 lane count 4
[04:58:11] [PASSED] Link rate 2000000 lane count 2
[04:58:11] [PASSED] Link rate 2000000 lane count 1
[04:58:11] [PASSED] Link rate 1350000 lane count 4
[04:58:11] [PASSED] Link rate 1350000 lane count 2
[04:58:11] [PASSED] Link rate 1350000 lane count 1
[04:58:11] [PASSED] Link rate 1000000 lane count 4
[04:58:11] [PASSED] Link rate 1000000 lane count 2
[04:58:11] [PASSED] Link rate 1000000 lane count 1
[04:58:11] [PASSED] Link rate 810000 lane count 4
[04:58:11] [PASSED] Link rate 810000 lane count 2
[04:58:11] [PASSED] Link rate 810000 lane count 1
[04:58:11] [PASSED] Link rate 540000 lane count 4
[04:58:11] [PASSED] Link rate 540000 lane count 2
[04:58:11] [PASSED] Link rate 540000 lane count 1
[04:58:11] [PASSED] Link rate 270000 lane count 4
[04:58:11] [PASSED] Link rate 270000 lane count 2
[04:58:11] [PASSED] Link rate 270000 lane count 1
[04:58:11] [PASSED] Link rate 162000 lane count 4
[04:58:11] [PASSED] Link rate 162000 lane count 2
[04:58:11] [PASSED] Link rate 162000 lane count 1
[04:58:11] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[04:58:11] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[04:58:11] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[04:58:11] [PASSED] DP_POWER_UP_PHY with port number
[04:58:11] [PASSED] DP_POWER_DOWN_PHY with port number
[04:58:11] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[04:58:11] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[04:58:11] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[04:58:11] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[04:58:11] [PASSED] DP_QUERY_PAYLOAD with port number
[04:58:11] [PASSED] DP_QUERY_PAYLOAD with VCPI
[04:58:11] [PASSED] DP_REMOTE_DPCD_READ with port number
[04:58:11] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[04:58:11] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[04:58:11] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[04:58:11] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[04:58:11] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[04:58:11] [PASSED] DP_REMOTE_I2C_READ with port number
[04:58:11] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[04:58:11] [PASSED] DP_REMOTE_I2C_READ with transactions array
[04:58:11] [PASSED] DP_REMOTE_I2C_WRITE with port number
[04:58:11] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[04:58:11] [PASSED] DP_REMOTE_I2C_WRITE with data array
[04:58:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[04:58:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[04:58:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[04:58:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[04:58:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[04:58:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[04:58:11] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[04:58:11] ================ [PASSED] drm_dp_mst_helper ================
[04:58:11] ================== drm_exec (7 subtests) ===================
[04:58:11] [PASSED] sanitycheck
[04:58:11] [PASSED] test_lock
[04:58:11] [PASSED] test_lock_unlock
[04:58:11] [PASSED] test_duplicates
[04:58:11] [PASSED] test_prepare
[04:58:11] [PASSED] test_prepare_array
[04:58:11] [PASSED] test_multiple_loops
[04:58:11] ==================== [PASSED] drm_exec =====================
[04:58:11] =========== drm_format_helper_test (17 subtests) ===========
[04:58:11] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[04:58:11] [PASSED] single_pixel_source_buffer
[04:58:11] [PASSED] single_pixel_clip_rectangle
[04:58:11] [PASSED] well_known_colors
[04:58:11] [PASSED] destination_pitch
[04:58:11] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[04:58:11] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[04:58:11] [PASSED] single_pixel_source_buffer
[04:58:11] [PASSED] single_pixel_clip_rectangle
[04:58:11] [PASSED] well_known_colors
[04:58:11] [PASSED] destination_pitch
[04:58:11] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[04:58:11] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[04:58:11] [PASSED] single_pixel_source_buffer
[04:58:11] [PASSED] single_pixel_clip_rectangle
[04:58:11] [PASSED] well_known_colors
[04:58:11] [PASSED] destination_pitch
[04:58:11] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[04:58:11] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[04:58:11] [PASSED] single_pixel_source_buffer
[04:58:11] [PASSED] single_pixel_clip_rectangle
[04:58:11] [PASSED] well_known_colors
[04:58:11] [PASSED] destination_pitch
[04:58:11] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[04:58:11] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[04:58:11] [PASSED] single_pixel_source_buffer
[04:58:11] [PASSED] single_pixel_clip_rectangle
[04:58:11] [PASSED] well_known_colors
[04:58:11] [PASSED] destination_pitch
[04:58:11] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[04:58:11] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[04:58:11] [PASSED] single_pixel_source_buffer
[04:58:11] [PASSED] single_pixel_clip_rectangle
[04:58:11] [PASSED] well_known_colors
[04:58:11] [PASSED] destination_pitch
[04:58:11] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[04:58:11] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[04:58:11] [PASSED] single_pixel_source_buffer
[04:58:11] [PASSED] single_pixel_clip_rectangle
[04:58:11] [PASSED] well_known_colors
[04:58:11] [PASSED] destination_pitch
[04:58:11] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[04:58:11] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[04:58:11] [PASSED] single_pixel_source_buffer
[04:58:11] [PASSED] single_pixel_clip_rectangle
[04:58:11] [PASSED] well_known_colors
[04:58:11] [PASSED] destination_pitch
[04:58:11] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[04:58:11] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[04:58:11] [PASSED] single_pixel_source_buffer
[04:58:11] [PASSED] single_pixel_clip_rectangle
[04:58:11] [PASSED] well_known_colors
[04:58:11] [PASSED] destination_pitch
[04:58:11] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[04:58:11] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[04:58:11] [PASSED] single_pixel_source_buffer
[04:58:11] [PASSED] single_pixel_clip_rectangle
[04:58:11] [PASSED] well_known_colors
[04:58:11] [PASSED] destination_pitch
[04:58:11] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[04:58:11] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[04:58:11] [PASSED] single_pixel_source_buffer
[04:58:11] [PASSED] single_pixel_clip_rectangle
[04:58:11] [PASSED] well_known_colors
[04:58:11] [PASSED] destination_pitch
[04:58:11] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[04:58:11] ============== drm_test_fb_xrgb8888_to_mono  ===============
[04:58:11] [PASSED] single_pixel_source_buffer
[04:58:11] [PASSED] single_pixel_clip_rectangle
[04:58:11] [PASSED] well_known_colors
[04:58:11] [PASSED] destination_pitch
[04:58:11] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[04:58:11] ==================== drm_test_fb_swab  =====================
[04:58:11] [PASSED] single_pixel_source_buffer
[04:58:11] [PASSED] single_pixel_clip_rectangle
[04:58:11] [PASSED] well_known_colors
[04:58:11] [PASSED] destination_pitch
[04:58:11] ================ [PASSED] drm_test_fb_swab =================
[04:58:11] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[04:58:11] [PASSED] single_pixel_source_buffer
[04:58:11] [PASSED] single_pixel_clip_rectangle
[04:58:11] [PASSED] well_known_colors
[04:58:11] [PASSED] destination_pitch
[04:58:11] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[04:58:11] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[04:58:11] [PASSED] single_pixel_source_buffer
[04:58:11] [PASSED] single_pixel_clip_rectangle
[04:58:11] [PASSED] well_known_colors
[04:58:11] [PASSED] destination_pitch
[04:58:11] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[04:58:11] ================= drm_test_fb_clip_offset  =================
[04:58:11] [PASSED] pass through
[04:58:11] [PASSED] horizontal offset
[04:58:11] [PASSED] vertical offset
[04:58:11] [PASSED] horizontal and vertical offset
[04:58:11] [PASSED] horizontal offset (custom pitch)
[04:58:11] [PASSED] vertical offset (custom pitch)
[04:58:11] [PASSED] horizontal and vertical offset (custom pitch)
[04:58:11] ============= [PASSED] drm_test_fb_clip_offset =============
[04:58:11] =================== drm_test_fb_memcpy  ====================
[04:58:11] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[04:58:11] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[04:58:11] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[04:58:11] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[04:58:11] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[04:58:11] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[04:58:11] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[04:58:11] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[04:58:11] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[04:58:11] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[04:58:11] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[04:58:11] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[04:58:11] =============== [PASSED] drm_test_fb_memcpy ================
[04:58:11] ============= [PASSED] drm_format_helper_test ==============
[04:58:11] ================= drm_format (18 subtests) =================
[04:58:11] [PASSED] drm_test_format_block_width_invalid
[04:58:11] [PASSED] drm_test_format_block_width_one_plane
[04:58:11] [PASSED] drm_test_format_block_width_two_plane
[04:58:11] [PASSED] drm_test_format_block_width_three_plane
[04:58:11] [PASSED] drm_test_format_block_width_tiled
[04:58:11] [PASSED] drm_test_format_block_height_invalid
[04:58:11] [PASSED] drm_test_format_block_height_one_plane
[04:58:11] [PASSED] drm_test_format_block_height_two_plane
[04:58:11] [PASSED] drm_test_format_block_height_three_plane
[04:58:11] [PASSED] drm_test_format_block_height_tiled
[04:58:11] [PASSED] drm_test_format_min_pitch_invalid
[04:58:11] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[04:58:11] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[04:58:11] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[04:58:11] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[04:58:11] [PASSED] drm_test_format_min_pitch_two_plane
[04:58:11] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[04:58:11] [PASSED] drm_test_format_min_pitch_tiled
[04:58:11] =================== [PASSED] drm_format ====================
[04:58:11] ============== drm_framebuffer (10 subtests) ===============
[04:58:11] ========== drm_test_framebuffer_check_src_coords  ==========
[04:58:11] [PASSED] Success: source fits into fb
[04:58:11] [PASSED] Fail: overflowing fb with x-axis coordinate
[04:58:11] [PASSED] Fail: overflowing fb with y-axis coordinate
[04:58:11] [PASSED] Fail: overflowing fb with source width
[04:58:11] [PASSED] Fail: overflowing fb with source height
[04:58:11] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[04:58:11] [PASSED] drm_test_framebuffer_cleanup
[04:58:11] =============== drm_test_framebuffer_create  ===============
[04:58:11] [PASSED] ABGR8888 normal sizes
[04:58:11] [PASSED] ABGR8888 max sizes
[04:58:11] [PASSED] ABGR8888 pitch greater than min required
[04:58:11] [PASSED] ABGR8888 pitch less than min required
[04:58:11] [PASSED] ABGR8888 Invalid width
[04:58:11] [PASSED] ABGR8888 Invalid buffer handle
[04:58:11] [PASSED] No pixel format
[04:58:11] [PASSED] ABGR8888 Width 0
[04:58:11] [PASSED] ABGR8888 Height 0
[04:58:11] [PASSED] ABGR8888 Out of bound height * pitch combination
[04:58:11] [PASSED] ABGR8888 Large buffer offset
[04:58:11] [PASSED] ABGR8888 Buffer offset for inexistent plane
[04:58:11] [PASSED] ABGR8888 Invalid flag
[04:58:11] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[04:58:11] [PASSED] ABGR8888 Valid buffer modifier
[04:58:11] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[04:58:11] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[04:58:11] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[04:58:11] [PASSED] NV12 Normal sizes
[04:58:11] [PASSED] NV12 Max sizes
[04:58:11] [PASSED] NV12 Invalid pitch
[04:58:11] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[04:58:11] [PASSED] NV12 different  modifier per-plane
[04:58:11] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[04:58:11] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[04:58:11] [PASSED] NV12 Modifier for inexistent plane
[04:58:11] [PASSED] NV12 Handle for inexistent plane
[04:58:11] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[04:58:11] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[04:58:11] [PASSED] YVU420 Normal sizes
[04:58:11] [PASSED] YVU420 Max sizes
[04:58:11] [PASSED] YVU420 Invalid pitch
[04:58:11] [PASSED] YVU420 Different pitches
[04:58:11] [PASSED] YVU420 Different buffer offsets/pitches
[04:58:11] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[04:58:11] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[04:58:11] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[04:58:11] [PASSED] YVU420 Valid modifier
[04:58:11] [PASSED] YVU420 Different modifiers per plane
[04:58:11] [PASSED] YVU420 Modifier for inexistent plane
[04:58:11] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[04:58:11] [PASSED] X0L2 Normal sizes
[04:58:11] [PASSED] X0L2 Max sizes
[04:58:11] [PASSED] X0L2 Invalid pitch
[04:58:11] [PASSED] X0L2 Pitch greater than minimum required
[04:58:11] [PASSED] X0L2 Handle for inexistent plane
[04:58:11] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[04:58:11] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[04:58:11] [PASSED] X0L2 Valid modifier
[04:58:11] [PASSED] X0L2 Modifier for inexistent plane
[04:58:11] =========== [PASSED] drm_test_framebuffer_create ===========
[04:58:11] [PASSED] drm_test_framebuffer_free
[04:58:11] [PASSED] drm_test_framebuffer_init
[04:58:11] [PASSED] drm_test_framebuffer_init_bad_format
[04:58:11] [PASSED] drm_test_framebuffer_init_dev_mismatch
[04:58:11] [PASSED] drm_test_framebuffer_lookup
[04:58:11] [PASSED] drm_test_framebuffer_lookup_inexistent
[04:58:11] [PASSED] drm_test_framebuffer_modifiers_not_supported
[04:58:11] ================= [PASSED] drm_framebuffer =================
[04:58:11] ================ drm_gem_shmem (8 subtests) ================
[04:58:11] [PASSED] drm_gem_shmem_test_obj_create
[04:58:11] [PASSED] drm_gem_shmem_test_obj_create_private
[04:58:11] [PASSED] drm_gem_shmem_test_pin_pages
[04:58:11] [PASSED] drm_gem_shmem_test_vmap
[04:58:11] [PASSED] drm_gem_shmem_test_get_pages_sgt
[04:58:11] [PASSED] drm_gem_shmem_test_get_sg_table
[04:58:11] [PASSED] drm_gem_shmem_test_madvise
[04:58:11] [PASSED] drm_gem_shmem_test_purge
[04:58:11] ================== [PASSED] drm_gem_shmem ==================
[04:58:11] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[04:58:11] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[04:58:11] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[04:58:11] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[04:58:11] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[04:58:11] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[04:58:11] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[04:58:11] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[04:58:11] [PASSED] Automatic
[04:58:11] [PASSED] Full
[04:58:11] [PASSED] Limited 16:235
[04:58:11] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[04:58:11] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[04:58:11] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[04:58:11] [PASSED] drm_test_check_disable_connector
[04:58:11] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[04:58:11] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[04:58:11] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[04:58:11] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[04:58:11] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[04:58:11] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[04:58:11] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[04:58:11] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[04:58:11] [PASSED] drm_test_check_output_bpc_dvi
[04:58:11] [PASSED] drm_test_check_output_bpc_format_vic_1
[04:58:11] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[04:58:11] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[04:58:11] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[04:58:11] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[04:58:11] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[04:58:11] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[04:58:11] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[04:58:11] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[04:58:11] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[04:58:11] [PASSED] drm_test_check_broadcast_rgb_value
[04:58:11] [PASSED] drm_test_check_bpc_8_value
[04:58:11] [PASSED] drm_test_check_bpc_10_value
[04:58:11] [PASSED] drm_test_check_bpc_12_value
[04:58:11] [PASSED] drm_test_check_format_value
[04:58:11] [PASSED] drm_test_check_tmds_char_value
[04:58:11] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[04:58:11] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[04:58:11] [PASSED] drm_test_check_mode_valid
[04:58:11] [PASSED] drm_test_check_mode_valid_reject
[04:58:11] [PASSED] drm_test_check_mode_valid_reject_rate
[04:58:11] [PASSED] drm_test_check_mode_valid_reject_max_clock
[04:58:11] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[04:58:11] ================= drm_managed (2 subtests) =================
[04:58:11] [PASSED] drm_test_managed_release_action
[04:58:11] [PASSED] drm_test_managed_run_action
[04:58:11] =================== [PASSED] drm_managed ===================
[04:58:11] =================== drm_mm (6 subtests) ====================
[04:58:11] [PASSED] drm_test_mm_init
[04:58:11] [PASSED] drm_test_mm_debug
[04:58:11] [PASSED] drm_test_mm_align32
[04:58:11] [PASSED] drm_test_mm_align64
[04:58:11] [PASSED] drm_test_mm_lowest
[04:58:11] [PASSED] drm_test_mm_highest
[04:58:11] ===================== [PASSED] drm_mm ======================
[04:58:11] ============= drm_modes_analog_tv (5 subtests) =============
[04:58:11] [PASSED] drm_test_modes_analog_tv_mono_576i
[04:58:11] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[04:58:11] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[04:58:11] [PASSED] drm_test_modes_analog_tv_pal_576i
[04:58:11] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[04:58:11] =============== [PASSED] drm_modes_analog_tv ===============
[04:58:11] ============== drm_plane_helper (2 subtests) ===============
[04:58:11] =============== drm_test_check_plane_state  ================
[04:58:11] [PASSED] clipping_simple
[04:58:11] [PASSED] clipping_rotate_reflect
[04:58:11] [PASSED] positioning_simple
[04:58:11] [PASSED] upscaling
[04:58:11] [PASSED] downscaling
[04:58:11] [PASSED] rounding1
[04:58:11] [PASSED] rounding2
[04:58:11] [PASSED] rounding3
[04:58:11] [PASSED] rounding4
[04:58:11] =========== [PASSED] drm_test_check_plane_state ============
[04:58:11] =========== drm_test_check_invalid_plane_state  ============
[04:58:11] [PASSED] positioning_invalid
[04:58:11] [PASSED] upscaling_invalid
[04:58:11] [PASSED] downscaling_invalid
[04:58:11] ======= [PASSED] drm_test_check_invalid_plane_state ========
[04:58:11] ================ [PASSED] drm_plane_helper =================
[04:58:11] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[04:58:11] ====== drm_test_connector_helper_tv_get_modes_check  =======
[04:58:11] [PASSED] None
[04:58:11] [PASSED] PAL
[04:58:11] [PASSED] NTSC
[04:58:11] [PASSED] Both, NTSC Default
[04:58:11] [PASSED] Both, PAL Default
[04:58:11] [PASSED] Both, NTSC Default, with PAL on command-line
[04:58:11] [PASSED] Both, PAL Default, with NTSC on command-line
[04:58:11] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[04:58:11] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[04:58:11] ================== drm_rect (9 subtests) ===================
[04:58:11] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[04:58:11] [PASSED] drm_test_rect_clip_scaled_not_clipped
[04:58:11] [PASSED] drm_test_rect_clip_scaled_clipped
[04:58:11] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[04:58:11] ================= drm_test_rect_intersect  =================
[04:58:11] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[04:58:11] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[04:58:11] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[04:58:11] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[04:58:11] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[04:58:11] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[04:58:11] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[04:58:11] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[04:58:11] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[04:58:11] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[04:58:11] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[04:58:11] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[04:58:11] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[04:58:11] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[04:58:11] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[04:58:11] ============= [PASSED] drm_test_rect_intersect =============
[04:58:11] ================ drm_test_rect_calc_hscale  ================
[04:58:11] [PASSED] normal use
[04:58:11] [PASSED] out of max range
[04:58:11] [PASSED] out of min range
[04:58:11] [PASSED] zero dst
[04:58:11] [PASSED] negative src
[04:58:11] [PASSED] negative dst
[04:58:11] ============ [PASSED] drm_test_rect_calc_hscale ============
[04:58:11] ================ drm_test_rect_calc_vscale  ================
[04:58:11] [PASSED] normal use
[04:58:11] [PASSED] out of max range
[04:58:11] [PASSED] out of min range
[04:58:11] [PASSED] zero dst
[04:58:11] [PASSED] negative src
stty: 'standard input': Inappropriate ioctl for device
[04:58:11] [PASSED] negative dst
[04:58:11] ============ [PASSED] drm_test_rect_calc_vscale ============
[04:58:11] ================== drm_test_rect_rotate  ===================
[04:58:11] [PASSED] reflect-x
[04:58:11] [PASSED] reflect-y
[04:58:11] [PASSED] rotate-0
[04:58:11] [PASSED] rotate-90
[04:58:11] [PASSED] rotate-180
[04:58:11] [PASSED] rotate-270
[04:58:11] ============== [PASSED] drm_test_rect_rotate ===============
[04:58:11] ================ drm_test_rect_rotate_inv  =================
[04:58:11] [PASSED] reflect-x
[04:58:11] [PASSED] reflect-y
[04:58:11] [PASSED] rotate-0
[04:58:11] [PASSED] rotate-90
[04:58:11] [PASSED] rotate-180
[04:58:11] [PASSED] rotate-270
[04:58:11] ============ [PASSED] drm_test_rect_rotate_inv =============
[04:58:11] ==================== [PASSED] drm_rect =====================
[04:58:11] ============ drm_sysfb_modeset_test (1 subtest) ============
[04:58:11] ============ drm_test_sysfb_build_fourcc_list  =============
[04:58:11] [PASSED] no native formats
[04:58:11] [PASSED] XRGB8888 as native format
[04:58:11] [PASSED] remove duplicates
[04:58:11] [PASSED] convert alpha formats
[04:58:11] [PASSED] random formats
[04:58:11] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[04:58:11] ============= [PASSED] drm_sysfb_modeset_test ==============
[04:58:11] ============================================================
[04:58:11] Testing complete. Ran 621 tests: passed: 621
[04:58:11] Elapsed time: 25.912s total, 1.769s configuring, 23.976s building, 0.153s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[04:58:12] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:58:13] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:58:22] Starting KUnit Kernel (1/1)...
[04:58:22] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:58:23] ================= ttm_device (5 subtests) ==================
[04:58:23] [PASSED] ttm_device_init_basic
[04:58:23] [PASSED] ttm_device_init_multiple
[04:58:23] [PASSED] ttm_device_fini_basic
[04:58:23] [PASSED] ttm_device_init_no_vma_man
[04:58:23] ================== ttm_device_init_pools  ==================
[04:58:23] [PASSED] No DMA allocations, no DMA32 required
[04:58:23] [PASSED] DMA allocations, DMA32 required
[04:58:23] [PASSED] No DMA allocations, DMA32 required
[04:58:23] [PASSED] DMA allocations, no DMA32 required
[04:58:23] ============== [PASSED] ttm_device_init_pools ==============
[04:58:23] =================== [PASSED] ttm_device ====================
[04:58:23] ================== ttm_pool (8 subtests) ===================
[04:58:23] ================== ttm_pool_alloc_basic  ===================
[04:58:23] [PASSED] One page
[04:58:23] [PASSED] More than one page
[04:58:23] [PASSED] Above the allocation limit
[04:58:23] [PASSED] One page, with coherent DMA mappings enabled
[04:58:23] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:58:23] ============== [PASSED] ttm_pool_alloc_basic ===============
[04:58:23] ============== ttm_pool_alloc_basic_dma_addr  ==============
[04:58:23] [PASSED] One page
[04:58:23] [PASSED] More than one page
[04:58:23] [PASSED] Above the allocation limit
[04:58:23] [PASSED] One page, with coherent DMA mappings enabled
[04:58:23] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:58:23] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[04:58:23] [PASSED] ttm_pool_alloc_order_caching_match
[04:58:23] [PASSED] ttm_pool_alloc_caching_mismatch
[04:58:23] [PASSED] ttm_pool_alloc_order_mismatch
[04:58:23] [PASSED] ttm_pool_free_dma_alloc
[04:58:23] [PASSED] ttm_pool_free_no_dma_alloc
[04:58:23] [PASSED] ttm_pool_fini_basic
[04:58:23] ==================== [PASSED] ttm_pool =====================
[04:58:23] ================ ttm_resource (8 subtests) =================
[04:58:23] ================= ttm_resource_init_basic  =================
[04:58:23] [PASSED] Init resource in TTM_PL_SYSTEM
[04:58:23] [PASSED] Init resource in TTM_PL_VRAM
[04:58:23] [PASSED] Init resource in a private placement
[04:58:23] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[04:58:23] ============= [PASSED] ttm_resource_init_basic =============
[04:58:23] [PASSED] ttm_resource_init_pinned
[04:58:23] [PASSED] ttm_resource_fini_basic
[04:58:23] [PASSED] ttm_resource_manager_init_basic
[04:58:23] [PASSED] ttm_resource_manager_usage_basic
[04:58:23] [PASSED] ttm_resource_manager_set_used_basic
[04:58:23] [PASSED] ttm_sys_man_alloc_basic
[04:58:23] [PASSED] ttm_sys_man_free_basic
[04:58:23] ================== [PASSED] ttm_resource ===================
[04:58:23] =================== ttm_tt (15 subtests) ===================
[04:58:23] ==================== ttm_tt_init_basic  ====================
[04:58:23] [PASSED] Page-aligned size
[04:58:23] [PASSED] Extra pages requested
[04:58:23] ================ [PASSED] ttm_tt_init_basic ================
[04:58:23] [PASSED] ttm_tt_init_misaligned
[04:58:23] [PASSED] ttm_tt_fini_basic
[04:58:23] [PASSED] ttm_tt_fini_sg
[04:58:23] [PASSED] ttm_tt_fini_shmem
[04:58:23] [PASSED] ttm_tt_create_basic
[04:58:23] [PASSED] ttm_tt_create_invalid_bo_type
[04:58:23] [PASSED] ttm_tt_create_ttm_exists
[04:58:23] [PASSED] ttm_tt_create_failed
[04:58:23] [PASSED] ttm_tt_destroy_basic
[04:58:23] [PASSED] ttm_tt_populate_null_ttm
[04:58:23] [PASSED] ttm_tt_populate_populated_ttm
[04:58:23] [PASSED] ttm_tt_unpopulate_basic
[04:58:23] [PASSED] ttm_tt_unpopulate_empty_ttm
[04:58:23] [PASSED] ttm_tt_swapin_basic
[04:58:23] ===================== [PASSED] ttm_tt ======================
[04:58:23] =================== ttm_bo (14 subtests) ===================
[04:58:23] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[04:58:23] [PASSED] Cannot be interrupted and sleeps
[04:58:23] [PASSED] Cannot be interrupted, locks straight away
[04:58:23] [PASSED] Can be interrupted, sleeps
[04:58:23] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[04:58:23] [PASSED] ttm_bo_reserve_locked_no_sleep
[04:58:23] [PASSED] ttm_bo_reserve_no_wait_ticket
[04:58:23] [PASSED] ttm_bo_reserve_double_resv
[04:58:23] [PASSED] ttm_bo_reserve_interrupted
[04:58:23] [PASSED] ttm_bo_reserve_deadlock
[04:58:23] [PASSED] ttm_bo_unreserve_basic
[04:58:23] [PASSED] ttm_bo_unreserve_pinned
[04:58:23] [PASSED] ttm_bo_unreserve_bulk
[04:58:23] [PASSED] ttm_bo_fini_basic
[04:58:23] [PASSED] ttm_bo_fini_shared_resv
[04:58:23] [PASSED] ttm_bo_pin_basic
[04:58:23] [PASSED] ttm_bo_pin_unpin_resource
[04:58:23] [PASSED] ttm_bo_multiple_pin_one_unpin
[04:58:23] ===================== [PASSED] ttm_bo ======================
[04:58:23] ============== ttm_bo_validate (21 subtests) ===============
[04:58:23] ============== ttm_bo_init_reserved_sys_man  ===============
[04:58:23] [PASSED] Buffer object for userspace
[04:58:23] [PASSED] Kernel buffer object
[04:58:23] [PASSED] Shared buffer object
[04:58:23] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[04:58:23] ============== ttm_bo_init_reserved_mock_man  ==============
[04:58:23] [PASSED] Buffer object for userspace
[04:58:23] [PASSED] Kernel buffer object
[04:58:23] [PASSED] Shared buffer object
[04:58:23] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[04:58:23] [PASSED] ttm_bo_init_reserved_resv
[04:58:23] ================== ttm_bo_validate_basic  ==================
[04:58:23] [PASSED] Buffer object for userspace
[04:58:23] [PASSED] Kernel buffer object
[04:58:23] [PASSED] Shared buffer object
[04:58:23] ============== [PASSED] ttm_bo_validate_basic ==============
[04:58:23] [PASSED] ttm_bo_validate_invalid_placement
[04:58:23] ============= ttm_bo_validate_same_placement  ==============
[04:58:23] [PASSED] System manager
[04:58:23] [PASSED] VRAM manager
[04:58:23] ========= [PASSED] ttm_bo_validate_same_placement ==========
[04:58:23] [PASSED] ttm_bo_validate_failed_alloc
[04:58:23] [PASSED] ttm_bo_validate_pinned
[04:58:23] [PASSED] ttm_bo_validate_busy_placement
[04:58:23] ================ ttm_bo_validate_multihop  =================
[04:58:23] [PASSED] Buffer object for userspace
[04:58:23] [PASSED] Kernel buffer object
[04:58:23] [PASSED] Shared buffer object
[04:58:23] ============ [PASSED] ttm_bo_validate_multihop =============
[04:58:23] ========== ttm_bo_validate_no_placement_signaled  ==========
[04:58:23] [PASSED] Buffer object in system domain, no page vector
[04:58:23] [PASSED] Buffer object in system domain with an existing page vector
[04:58:23] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[04:58:23] ======== ttm_bo_validate_no_placement_not_signaled  ========
[04:58:23] [PASSED] Buffer object for userspace
[04:58:23] [PASSED] Kernel buffer object
[04:58:23] [PASSED] Shared buffer object
[04:58:23] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[04:58:23] [PASSED] ttm_bo_validate_move_fence_signaled
[04:58:23] ========= ttm_bo_validate_move_fence_not_signaled  =========
[04:58:23] [PASSED] Waits for GPU
[04:58:23] [PASSED] Tries to lock straight away
[04:58:23] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[04:58:23] [PASSED] ttm_bo_validate_happy_evict
[04:58:23] [PASSED] ttm_bo_validate_all_pinned_evict
[04:58:23] [PASSED] ttm_bo_validate_allowed_only_evict
[04:58:23] [PASSED] ttm_bo_validate_deleted_evict
[04:58:23] [PASSED] ttm_bo_validate_busy_domain_evict
[04:58:23] [PASSED] ttm_bo_validate_evict_gutting
[04:58:23] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[04:58:23] ================= [PASSED] ttm_bo_validate =================
[04:58:23] ============================================================
[04:58:23] Testing complete. Ran 101 tests: passed: 101
[04:58:23] Elapsed time: 11.153s total, 1.680s configuring, 9.257s building, 0.184s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for Introduce set_context_latency and refactor VRR/DSB timing logic

[Patchwork]

== Series Details ==

Series: Introduce set_context_latency and refactor VRR/DSB timing logic
URL   : https://patchwork.freedesktop.org/series/154809/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast cfa128d879d8cdea4007ddd56dcc2eac73ff2142
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2039:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2039:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2039:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ Xe.CI.BAT: failure for Introduce set_context_latency and refactor VRR/DSB timing logic

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6816 bytes --]

== Series Details ==

Series: Introduce set_context_latency and refactor VRR/DSB timing logic
URL   : https://patchwork.freedesktop.org/series/154809/
State : failure

== Summary ==

CI Bug Log - changes from xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142_BAT -> xe-pw-154809v1_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-154809v1_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-154809v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 9)
------------------------------

  Missing    (2): bat-adlp-vm bat-ptl-vm 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-154809v1_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
    - bat-dg2-oem2:       [PASS][1] -> [FAIL][2] +6 other tests fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/bat-dg2-oem2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/bat-dg2-oem2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
    - bat-lnl-1:          [PASS][3] -> [FAIL][4] +7 other tests fail
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/bat-lnl-1/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/bat-lnl-1/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - bat-lnl-1:          [PASS][5] -> [DMESG-WARN][6] +7 other tests dmesg-warn
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/bat-lnl-1/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/bat-lnl-1/igt@kms_flip@basic-flip-vs-wf_vblank.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-hdmi-a3:
    - bat-bmg-1:          [PASS][7] -> [DMESG-WARN][8] +3 other tests dmesg-warn
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/bat-bmg-1/igt@kms_flip@basic-flip-vs-wf_vblank@a-hdmi-a3.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/bat-bmg-1/igt@kms_flip@basic-flip-vs-wf_vblank@a-hdmi-a3.html

  * igt@kms_flip@basic-plain-flip:
    - bat-bmg-1:          [PASS][9] -> [DMESG-FAIL][10] +1 other test dmesg-fail
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/bat-bmg-1/igt@kms_flip@basic-plain-flip.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/bat-bmg-1/igt@kms_flip@basic-plain-flip.html
    - bat-lnl-1:          [PASS][11] -> [DMESG-FAIL][12] +1 other test dmesg-fail
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/bat-lnl-1/igt@kms_flip@basic-plain-flip.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/bat-lnl-1/igt@kms_flip@basic-plain-flip.html

  * igt@kms_flip@basic-plain-flip@b-hdmi-a3:
    - bat-bmg-1:          [PASS][13] -> [FAIL][14] +8 other tests fail
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/bat-bmg-1/igt@kms_flip@basic-plain-flip@b-hdmi-a3.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/bat-bmg-1/igt@kms_flip@basic-plain-flip@b-hdmi-a3.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - {bat-ptl-2}:        [PASS][15] -> [FAIL][16] +8 other tests fail
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/bat-ptl-2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/bat-ptl-2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1:
    - {bat-ptl-2}:        [PASS][17] -> [DMESG-WARN][18] +3 other tests dmesg-warn
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/bat-ptl-2/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/bat-ptl-2/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html

  * igt@kms_flip@basic-plain-flip:
    - {bat-ptl-2}:        [PASS][19] -> [DMESG-FAIL][20] +1 other test dmesg-fail
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/bat-ptl-2/igt@kms_flip@basic-plain-flip.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/bat-ptl-2/igt@kms_flip@basic-plain-flip.html

  
Known issues
------------

  Here are the changes found in xe-pw-154809v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - bat-dg2-oem2:       [PASS][21] -> [DMESG-FAIL][22] ([Intel XE#4543]) +3 other tests dmesg-fail
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/bat-dg2-oem2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/bat-dg2-oem2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  * igt@kms_pipe_crc_basic@nonblocking-crc:
    - bat-dg2-oem2:       [PASS][23] -> [DMESG-WARN][24] ([Intel XE#4543]) +8 other tests dmesg-warn
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/bat-dg2-oem2/igt@kms_pipe_crc_basic@nonblocking-crc.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/bat-dg2-oem2/igt@kms_pipe_crc_basic@nonblocking-crc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543


Build changes
-------------

  * Linux: xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142 -> xe-pw-154809v1

  IGT_8546: 8546
  xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142: cfa128d879d8cdea4007ddd56dcc2eac73ff2142
  xe-pw-154809v1: 154809v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/index.html

[-- Attachment #2: Type: text/html, Size: 7801 bytes --]

✗ Xe.CI.Full: failure for Introduce set_context_latency and refactor VRR/DSB timing logic

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 70608 bytes --]

== Series Details ==

Series: Introduce set_context_latency and refactor VRR/DSB timing logic
URL   : https://patchwork.freedesktop.org/series/154809/
State : failure

== Summary ==

CI Bug Log - changes from xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142_FULL -> xe-pw-154809v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-154809v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-154809v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-154809v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-c-hdmi-a-3-4:
    - shard-bmg:          [PASS][1] -> [DMESG-WARN][2] +160 other tests dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-5/igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-c-hdmi-a-3-4.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-5/igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-c-hdmi-a-3-4.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-c-hdmi-a-6-4:
    - shard-dg2-set2:     [PASS][3] -> [DMESG-WARN][4] +84 other tests dmesg-warn
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-436/igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-c-hdmi-a-6-4.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-463/igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-c-hdmi-a-6-4.html

  * igt@kms_cursor_crc@cursor-offscreen-128x42:
    - shard-adlp:         [PASS][5] -> [FAIL][6] +231 other tests fail
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-2/igt@kms_cursor_crc@cursor-offscreen-128x42.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-8/igt@kms_cursor_crc@cursor-offscreen-128x42.html

  * igt@kms_flip@2x-flip-vs-panning-interruptible@ab-dp2-hdmi-a3:
    - shard-bmg:          [PASS][7] -> [DMESG-FAIL][8] +39 other tests dmesg-fail
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-1/igt@kms_flip@2x-flip-vs-panning-interruptible@ab-dp2-hdmi-a3.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-4/igt@kms_flip@2x-flip-vs-panning-interruptible@ab-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible@ad-dp2-hdmi-a3:
    - shard-bmg:          NOTRUN -> [DMESG-FAIL][9] +3 other tests dmesg-fail
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-2/igt@kms_flip@2x-flip-vs-rmfb-interruptible@ad-dp2-hdmi-a3.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@b-dp2:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][10] +17 other tests dmesg-warn
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-5/igt@kms_flip@basic-flip-vs-wf_vblank@b-dp2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp2:
    - shard-dg2-set2:     NOTRUN -> [FAIL][11] +31 other tests fail
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-432/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp2.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@d-hdmi-a3:
    - shard-bmg:          [PASS][12] -> [FAIL][13] +336 other tests fail
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-6/igt@kms_flip@plain-flip-ts-check-interruptible@d-hdmi-a3.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-4/igt@kms_flip@plain-flip-ts-check-interruptible@d-hdmi-a3.html

  * igt@kms_flip@plain-flip-ts-check@b-hdmi-a6:
    - shard-dg2-set2:     [PASS][14] -> [FAIL][15] +215 other tests fail
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-435/igt@kms_flip@plain-flip-ts-check@b-hdmi-a6.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-434/igt@kms_flip@plain-flip-ts-check@b-hdmi-a6.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling@pipe-a-valid-mode:
    - shard-dg2-set2:     [PASS][16] -> [DMESG-FAIL][17] +6 other tests dmesg-fail
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-432/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling@pipe-a-valid-mode.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-463/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling@pipe-a-valid-mode.html

  * igt@kms_plane_cursor@viewport@pipe-a-dp-2-size-64:
    - shard-bmg:          NOTRUN -> [FAIL][18] +43 other tests fail
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-4/igt@kms_plane_cursor@viewport@pipe-a-dp-2-size-64.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers@pipe-a:
    - shard-adlp:         [PASS][19] -> [DMESG-WARN][20] +8 other tests dmesg-warn
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-2/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers@pipe-a.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-2/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers@pipe-a.html

  * igt@xe_pmu@fn-engine-activity-sched-if-idle:
    - shard-bmg:          NOTRUN -> [ABORT][21]
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@xe_pmu@fn-engine-activity-sched-if-idle.html

  
#### Warnings ####

  * igt@kms_flip@2x-absolute-wf_vblank:
    - shard-bmg:          [SKIP][22] ([Intel XE#2316]) -> [DMESG-WARN][23]
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-6/igt@kms_flip@2x-absolute-wf_vblank.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-5/igt@kms_flip@2x-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-bmg:          [SKIP][24] ([Intel XE#2316]) -> [DMESG-FAIL][25] +1 other test dmesg-fail
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-6/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-2/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@flip-vs-rmfb-interruptible:
    - shard-adlp:         [DMESG-WARN][26] ([Intel XE#4543] / [Intel XE#5208]) -> [FAIL][27]
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-9/igt@kms_flip@flip-vs-rmfb-interruptible.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-8/igt@kms_flip@flip-vs-rmfb-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-adlp:         [DMESG-WARN][28] ([Intel XE#4543]) -> [FAIL][29] +24 other tests fail
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend@a-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][30] ([Intel XE#2953] / [Intel XE#4173]) -> [FAIL][31]
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-1/igt@kms_flip@flip-vs-suspend@a-hdmi-a1.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-6/igt@kms_flip@flip-vs-suspend@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][32] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543]) -> [FAIL][33]
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-1/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-6/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html

  * igt@kms_plane@pixel-format-source-clamping@pipe-b-plane-0:
    - shard-adlp:         [FAIL][34] ([Intel XE#5195]) -> [FAIL][35] +4 other tests fail
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-6/igt@kms_plane@pixel-format-source-clamping@pipe-b-plane-0.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-1/igt@kms_plane@pixel-format-source-clamping@pipe-b-plane-0.html

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [SKIP][58], [PASS][59], [PASS][60], [PASS][61]) ([Intel XE#378]) -> ([DMESG-WARN][62], [DMESG-WARN][63], [DMESG-WARN][64], [DMESG-WARN][65], [DMESG-WARN][66], [DMESG-WARN][67], [DMESG-WARN][68], [DMESG-WARN][69], [DMESG-WARN][70], [DMESG-WARN][71], [DMESG-WARN][72], [DMESG-WARN][73], [DMESG-WARN][74], [DMESG-WARN][75], [DMESG-WARN][76], [DMESG-WARN][77], [DMESG-WARN][78], [DMESG-WARN][79], [DMESG-WARN][80], [DMESG-WARN][81], [DMESG-WARN][82], [DMESG-WARN][83], [DMESG-WARN][84], [DMESG-WARN][85], [DMESG-WARN][86])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-7/igt@xe_module_load@load.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-1/igt@xe_module_load@load.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-1/igt@xe_module_load@load.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-8/igt@xe_module_load@load.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-8/igt@xe_module_load@load.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-4/igt@xe_module_load@load.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-2/igt@xe_module_load@load.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-2/igt@xe_module_load@load.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-2/igt@xe_module_load@load.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-4/igt@xe_module_load@load.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-4/igt@xe_module_load@load.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-5/igt@xe_module_load@load.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-3/igt@xe_module_load@load.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-3/igt@xe_module_load@load.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-3/igt@xe_module_load@load.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-8/igt@xe_module_load@load.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-7/igt@xe_module_load@load.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-4/igt@xe_module_load@load.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-5/igt@xe_module_load@load.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-5/igt@xe_module_load@load.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-5/igt@xe_module_load@load.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-7/igt@xe_module_load@load.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-1/igt@xe_module_load@load.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-8/igt@xe_module_load@load.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-3/igt@xe_module_load@load.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-lnl-1/igt@xe_module_load@load.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-5/igt@xe_module_load@load.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-5/igt@xe_module_load@load.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-7/igt@xe_module_load@load.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-7/igt@xe_module_load@load.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-7/igt@xe_module_load@load.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-7/igt@xe_module_load@load.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-5/igt@xe_module_load@load.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-5/igt@xe_module_load@load.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-4/igt@xe_module_load@load.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-4/igt@xe_module_load@load.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-4/igt@xe_module_load@load.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-1/igt@xe_module_load@load.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-8/igt@xe_module_load@load.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-8/igt@xe_module_load@load.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-8/igt@xe_module_load@load.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-2/igt@xe_module_load@load.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-3/igt@xe_module_load@load.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-3/igt@xe_module_load@load.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-2/igt@xe_module_load@load.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-3/igt@xe_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-2/igt@xe_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-1/igt@xe_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-3/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-1/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-lnl-1/igt@xe_module_load@load.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_async_flips@basic-modeset-with-all-modifiers-formats@pipe-a-dp-2-4-rgb565}:
    - shard-bmg:          [PASS][87] -> [DMESG-WARN][88] +1 other test dmesg-warn
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-4/igt@kms_async_flips@basic-modeset-with-all-modifiers-formats@pipe-a-dp-2-4-rgb565.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-2/igt@kms_async_flips@basic-modeset-with-all-modifiers-formats@pipe-a-dp-2-4-rgb565.html

  * {igt@xe_exec_system_allocator@process-many-malloc-prefetch-race}:
    - shard-bmg:          NOTRUN -> [FAIL][89] +1 other test fail
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@xe_exec_system_allocator@process-many-malloc-prefetch-race.html

  * {igt@xe_exec_system_allocator@twice-new-prefetch}:
    - shard-bmg:          [PASS][90] -> [CRASH][91] +6 other tests crash
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-5/igt@xe_exec_system_allocator@twice-new-prefetch.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-2/igt@xe_exec_system_allocator@twice-new-prefetch.html

  
Known issues
------------

  Here are the changes found in xe-pw-154809v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_atomic_transition@plane-all-transition-fencing:
    - shard-bmg:          [PASS][92] -> [DMESG-WARN][93] ([Intel XE#5667])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-8/igt@kms_atomic_transition@plane-all-transition-fencing.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-7/igt@kms_atomic_transition@plane-all-transition-fencing.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-dg2-set2:     [PASS][94] -> [FAIL][95] ([Intel XE#1231]) +2 other tests fail
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-435/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-434/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-adlp:         [PASS][96] -> [DMESG-WARN][97] ([Intel XE#4543]) +19 other tests dmesg-warn
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][98] ([Intel XE#1124])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
    - shard-bmg:          [PASS][99] -> [SKIP][100] ([Intel XE#2314] / [Intel XE#2894]) +1 other test skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-8/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-1-displays-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][101] ([Intel XE#367])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][102] ([Intel XE#455] / [Intel XE#787]) +11 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-432/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-2.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][103] ([Intel XE#787]) +76 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-463/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][104] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522] / [Intel XE#4543])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][105] -> [INCOMPLETE][106] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522] / [Intel XE#4543])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html

  * igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k:
    - shard-dg2-set2:     NOTRUN -> [SKIP][107] ([Intel XE#373])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-466/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html

  * igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode:
    - shard-bmg:          NOTRUN -> [SKIP][108] ([Intel XE#2252]) +1 other test skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-bmg:          NOTRUN -> [SKIP][109] ([Intel XE#2390])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@legacy@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][110] ([Intel XE#1178])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-4/igt@kms_content_protection@legacy@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-onscreen-256x256@pipe-d-dp-2:
    - shard-bmg:          NOTRUN -> [DMESG-FAIL][111] ([Intel XE#4626])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-4/igt@kms_cursor_crc@cursor-onscreen-256x256@pipe-d-dp-2.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [PASS][112] -> [FAIL][113] ([Intel XE#616]) +55 other tests fail
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-464/igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-6.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-466/igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-6.html

  * igt@kms_cursor_crc@cursor-random-128x128@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [FAIL][114] ([Intel XE#616]) +2 other tests fail
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-463/igt@kms_cursor_crc@cursor-random-128x128@pipe-a-hdmi-a-6.html

  * igt@kms_cursor_crc@cursor-random-128x42:
    - shard-bmg:          NOTRUN -> [SKIP][115] ([Intel XE#2320])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@kms_cursor_crc@cursor-random-128x42.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][116] -> [SKIP][117] ([Intel XE#2291]) +5 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-8/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic:
    - shard-bmg:          [PASS][118] -> [FAIL][119] ([Intel XE#5394]) +3 other tests fail
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-5/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-2/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions:
    - shard-dg2-set2:     [PASS][120] -> [INCOMPLETE][121] ([Intel XE#3226])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-435/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-434/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][122] -> [INCOMPLETE][123] ([Intel XE#3226]) +4 other tests incomplete
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-dg2-set2:     [PASS][124] -> [INCOMPLETE][125] ([Intel XE#3226] / [Intel XE#4543]) +2 other tests incomplete
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-463/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-436/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-adlp:         [PASS][126] -> [FAIL][127] ([Intel XE#1475]) +4 other tests fail
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][128] -> [FAIL][129] ([Intel XE#5299])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
    - shard-bmg:          [PASS][130] -> [FAIL][131] ([Intel XE#1475]) +3 other tests fail
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [SKIP][132] ([Intel XE#5428])
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-bmg:          [PASS][133] -> [SKIP][134] ([Intel XE#1340])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-8/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_flip@2x-flip-vs-panning@bd-hdmi-a6-dp4:
    - shard-dg2-set2:     [PASS][135] -> [DMESG-FAIL][136] ([Intel XE#4543]) +115 other tests dmesg-fail
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-463/igt@kms_flip@2x-flip-vs-panning@bd-hdmi-a6-dp4.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-433/igt@kms_flip@2x-flip-vs-panning@bd-hdmi-a6-dp4.html

  * igt@kms_flip@2x-flip-vs-suspend@bc-hdmi-a2-dp2:
    - shard-dg2-set2:     NOTRUN -> [DMESG-FAIL][137] ([Intel XE#4543]) +11 other tests dmesg-fail
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-432/igt@kms_flip@2x-flip-vs-suspend@bc-hdmi-a2-dp2.html

  * igt@kms_flip@2x-nonexisting-fb@ac-hdmi-a6-dp4:
    - shard-dg2-set2:     [PASS][138] -> [DMESG-WARN][139] ([Intel XE#4543]) +415 other tests dmesg-warn
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-435/igt@kms_flip@2x-nonexisting-fb@ac-hdmi-a6-dp4.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-434/igt@kms_flip@2x-nonexisting-fb@ac-hdmi-a6-dp4.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-bmg:          [PASS][140] -> [FAIL][141] ([Intel XE#3149]) +4 other tests fail
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-1/igt@kms_flip@2x-plain-flip-fb-recreate.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-7/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-bmg:          [PASS][142] -> [SKIP][143] ([Intel XE#2316]) +3 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-3/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-hdmi-a6:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][144] ([Intel XE#4543]) +41 other tests dmesg-warn
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-466/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-hdmi-a6.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-bmg:          [PASS][145] -> [DMESG-FAIL][146] ([Intel XE#5208]) +1 other test dmesg-fail
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-2/igt@kms_flip@flip-vs-suspend.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-8/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend@d-hdmi-a1:
    - shard-adlp:         [PASS][147] -> [DMESG-FAIL][148] ([Intel XE#2953] / [Intel XE#4173]) +2 other tests dmesg-fail
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-1/igt@kms_flip@flip-vs-suspend@d-hdmi-a1.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-6/igt@kms_flip@flip-vs-suspend@d-hdmi-a1.html

  * igt@kms_flip@modeset-vs-vblank-race-interruptible:
    - shard-bmg:          [PASS][149] -> [DMESG-WARN][150] ([Intel XE#5208]) +2 other tests dmesg-warn
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-5/igt@kms_flip@modeset-vs-vblank-race-interruptible.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-1/igt@kms_flip@modeset-vs-vblank-race-interruptible.html

  * igt@kms_flip@plain-flip-fb-recreate:
    - shard-adlp:         [PASS][151] -> [FAIL][152] ([Intel XE#3149])
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-2/igt@kms_flip@plain-flip-fb-recreate.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-3/igt@kms_flip@plain-flip-fb-recreate.html

  * igt@kms_flip@plain-flip-interruptible@d-hdmi-a1:
    - shard-adlp:         [PASS][153] -> [DMESG-FAIL][154] ([Intel XE#4543]) +2 other tests dmesg-fail
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-6/igt@kms_flip@plain-flip-interruptible@d-hdmi-a1.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-1/igt@kms_flip@plain-flip-interruptible@d-hdmi-a1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible:
    - shard-dg2-set2:     [PASS][155] -> [FAIL][156] ([Intel XE#3149]) +3 other tests fail
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-463/igt@kms_flip@plain-flip-ts-check-interruptible.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-463/igt@kms_flip@plain-flip-ts-check-interruptible.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling:
    - shard-bmg:          [PASS][157] -> [FAIL][158] ([Intel XE#3106]) +1 other test fail
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-4/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][159] ([Intel XE#2293] / [Intel XE#2380])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][160] ([Intel XE#2293])
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-y-to-x:
    - shard-adlp:         [PASS][161] -> [FAIL][162] ([Intel XE#1874]) +12 other tests fail
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-y-to-x.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-y-to-x.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][163] ([Intel XE#2311]) +4 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][164] ([Intel XE#5390])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][165] ([Intel XE#2313]) +4 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@pipe-fbc-rte:
    - shard-bmg:          NOTRUN -> [SKIP][166] ([Intel XE#5672])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - shard-adlp:         [PASS][167] -> [DMESG-WARN][168] ([Intel XE#2953] / [Intel XE#4173]) +5 other tests dmesg-warn
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-2/igt@kms_pipe_crc_basic@suspend-read-crc.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-2/igt@kms_pipe_crc_basic@suspend-read-crc.html

  * igt@kms_plane_alpha_blend@alpha-7efc@pipe-d-dp-2:
    - shard-bmg:          [PASS][169] -> [DMESG-FAIL][170] ([Intel XE#4626]) +12 other tests dmesg-fail
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-7/igt@kms_plane_alpha_blend@alpha-7efc@pipe-d-dp-2.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-5/igt@kms_plane_alpha_blend@alpha-7efc@pipe-d-dp-2.html

  * igt@kms_plane_lowres@tiling-4:
    - shard-dg2-set2:     [PASS][171] -> [DMESG-WARN][172] ([Intel XE#4543] / [Intel XE#5681]) +1 other test dmesg-warn
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-463/igt@kms_plane_lowres@tiling-4.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-436/igt@kms_plane_lowres@tiling-4.html

  * igt@kms_plane_lowres@tiling-x:
    - shard-bmg:          [PASS][173] -> [DMESG-WARN][174] ([Intel XE#5681]) +1 other test dmesg-warn
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-6/igt@kms_plane_lowres@tiling-x.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-2/igt@kms_plane_lowres@tiling-x.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-bmg:          [PASS][175] -> [SKIP][176] ([Intel XE#4596])
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-8/igt@kms_plane_multiple@2x-tiling-none.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_multiple@tiling-none:
    - shard-dg2-set2:     [PASS][177] -> [DMESG-WARN][178] ([Intel XE#4543] / [Intel XE#5175]) +1 other test dmesg-warn
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-432/igt@kms_plane_multiple@tiling-none.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-463/igt@kms_plane_multiple@tiling-none.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-bmg:          NOTRUN -> [SKIP][179] ([Intel XE#870])
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][180] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr@fbc-psr-primary-blt:
    - shard-bmg:          NOTRUN -> [SKIP][181] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850])
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@kms_psr@fbc-psr-primary-blt.html

  * igt@kms_psr@fbc-psr2-no-drrs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][182] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929])
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-466/igt@kms_psr@fbc-psr2-no-drrs.html

  * igt@kms_rotation_crc@primary-x-tiled-reflect-x-0:
    - shard-dg2-set2:     [PASS][183] -> [FAIL][184] ([Intel XE#4689] / [Intel XE#616]) +1 other test fail
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-435/igt@kms_rotation_crc@primary-x-tiled-reflect-x-0.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-434/igt@kms_rotation_crc@primary-x-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-x-tiled-reflect-x-180:
    - shard-bmg:          [PASS][185] -> [FAIL][186] ([Intel XE#4689]) +1 other test fail
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-7/igt@kms_rotation_crc@primary-x-tiled-reflect-x-180.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-1/igt@kms_rotation_crc@primary-x-tiled-reflect-x-180.html
    - shard-adlp:         [PASS][187] -> [FAIL][188] ([Intel XE#4689]) +1 other test fail
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-2/igt@kms_rotation_crc@primary-x-tiled-reflect-x-180.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-2/igt@kms_rotation_crc@primary-x-tiled-reflect-x-180.html

  * igt@kms_setmode@basic:
    - shard-bmg:          [PASS][189] -> [FAIL][190] ([Intel XE#2883]) +2 other tests fail
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-8/igt@kms_setmode@basic.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-6/igt@kms_setmode@basic.html

  * igt@xe_compute_preempt@compute-preempt-many:
    - shard-dg2-set2:     NOTRUN -> [FAIL][191] ([Intel XE#5890]) +1 other test fail
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-466/igt@xe_compute_preempt@compute-preempt-many.html

  * igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-sram:
    - shard-dg2-set2:     NOTRUN -> [SKIP][192] ([Intel XE#4837])
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-466/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-sram.html

  * igt@xe_exec_basic@multigpu-once-rebind:
    - shard-dg2-set2:     [PASS][193] -> [SKIP][194] ([Intel XE#1392]) +3 other tests skip
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-436/igt@xe_exec_basic@multigpu-once-rebind.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-432/igt@xe_exec_basic@multigpu-once-rebind.html

  * igt@xe_exec_basic@twice-bindexecqueue-userptr-invalidate:
    - shard-adlp:         [PASS][195] -> [DMESG-FAIL][196] ([Intel XE#3876]) +4 other tests dmesg-fail
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-3/igt@xe_exec_basic@twice-bindexecqueue-userptr-invalidate.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-4/igt@xe_exec_basic@twice-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_basic@twice-userptr-rebind:
    - shard-bmg:          NOTRUN -> [DMESG-FAIL][197] ([Intel XE#3876]) +4 other tests dmesg-fail
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@xe_exec_basic@twice-userptr-rebind.html

  * igt@xe_exec_fault_mode@once-bindexecqueue-userptr-rebind:
    - shard-dg2-set2:     NOTRUN -> [SKIP][198] ([Intel XE#288])
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-466/igt@xe_exec_fault_mode@once-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-prefetch:
    - shard-bmg:          NOTRUN -> [FAIL][199] ([Intel XE#6050]) +2 other tests fail
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-prefetch.html

  * igt@xe_exec_reset@parallel-gt-reset:
    - shard-adlp:         [PASS][200] -> [DMESG-WARN][201] ([Intel XE#3876])
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-3/igt@xe_exec_reset@parallel-gt-reset.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-4/igt@xe_exec_reset@parallel-gt-reset.html

  * igt@xe_exec_system_allocator@many-large-mmap-shared-remap-dontunmap-eocheck:
    - shard-bmg:          NOTRUN -> [FAIL][202] ([Intel XE#4937]) +19 other tests fail
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@xe_exec_system_allocator@many-large-mmap-shared-remap-dontunmap-eocheck.html

  * igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-huge:
    - shard-bmg:          NOTRUN -> [SKIP][203] ([Intel XE#4943]) +1 other test skip
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-huge.html

  * igt@xe_exec_system_allocator@threads-many-mmap-remap-ro-eocheck:
    - shard-dg2-set2:     NOTRUN -> [SKIP][204] ([Intel XE#4915]) +20 other tests skip
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-466/igt@xe_exec_system_allocator@threads-many-mmap-remap-ro-eocheck.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-malloc-bo-unmap:
    - shard-bmg:          [PASS][205] -> [FAIL][206] ([Intel XE#4937]) +3 other tests fail
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-1/igt@xe_exec_system_allocator@threads-shared-vm-many-large-malloc-bo-unmap.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@xe_exec_system_allocator@threads-shared-vm-many-large-malloc-bo-unmap.html

  * igt@xe_pmu@engine-activity-load:
    - shard-adlp:         [PASS][207] -> [TIMEOUT][208] ([Intel XE#3876]) +3 other tests timeout
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-3/igt@xe_pmu@engine-activity-load.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-4/igt@xe_pmu@engine-activity-load.html
    - shard-bmg:          NOTRUN -> [TIMEOUT][209] ([Intel XE#3876]) +1 other test timeout
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@xe_pmu@engine-activity-load.html

  * igt@xe_query@multigpu-query-invalid-query:
    - shard-bmg:          NOTRUN -> [SKIP][210] ([Intel XE#944])
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-8/igt@xe_query@multigpu-query-invalid-query.html

  
#### Possible fixes ####

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1:
    - shard-adlp:         [DMESG-WARN][211] ([Intel XE#4543]) -> [PASS][212]
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-6/igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-1/igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [INCOMPLETE][213] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345]) -> [PASS][214]
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][215] ([Intel XE#1727] / [Intel XE#3113]) -> [PASS][216]
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
    - shard-bmg:          [SKIP][217] ([Intel XE#2291]) -> [PASS][218] +2 other tests pass
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html

  * igt@kms_cursor_legacy@forked-bo@pipe-b:
    - shard-dg2-set2:     [INCOMPLETE][219] ([Intel XE#3226]) -> [PASS][220] +1 other test pass
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-435/igt@kms_cursor_legacy@forked-bo@pipe-b.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-466/igt@kms_cursor_legacy@forked-bo@pipe-b.html

  * igt@kms_cursor_legacy@single-bo:
    - shard-bmg:          [DMESG-WARN][221] ([Intel XE#5354]) -> [PASS][222] +1 other test pass
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-8/igt@kms_cursor_legacy@single-bo.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-7/igt@kms_cursor_legacy@single-bo.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-bmg:          [SKIP][223] ([Intel XE#4302]) -> [PASS][224]
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-6/igt@kms_display_modes@extended-mode-basic.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-5/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-bmg:          [SKIP][225] ([Intel XE#4354]) -> [PASS][226]
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-sst.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-4/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_flip@2x-flip-vs-modeset:
    - shard-bmg:          [SKIP][227] ([Intel XE#2316]) -> [PASS][228] +1 other test pass
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-6/igt@kms_flip@2x-flip-vs-modeset.html
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-4/igt@kms_flip@2x-flip-vs-modeset.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-y:
    - shard-adlp:         [DMESG-FAIL][229] ([Intel XE#4543]) -> [PASS][230]
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-y.html
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-y.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y:
    - shard-adlp:         [FAIL][231] ([Intel XE#1874]) -> [PASS][232]
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html

  * igt@kms_setmode@basic@pipe-a-dp-4:
    - shard-dg2-set2:     [FAIL][233] ([Intel XE#2883]) -> [PASS][234] +2 other tests pass
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-434/igt@kms_setmode@basic@pipe-a-dp-4.html
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-464/igt@kms_setmode@basic@pipe-a-dp-4.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind:
    - shard-dg2-set2:     [SKIP][235] ([Intel XE#1392]) -> [PASS][236] +2 other tests pass
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-463/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html

  * {igt@xe_exec_system_allocator@many-large-execqueues-new-prefetch}:
    - shard-bmg:          [CRASH][237] -> [PASS][238] +6 other tests pass
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-4/igt@xe_exec_system_allocator@many-large-execqueues-new-prefetch.html
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-7/igt@xe_exec_system_allocator@many-large-execqueues-new-prefetch.html

  * igt@xe_pat@pat-index-xe2:
    - shard-bmg:          [FAIL][239] ([Intel XE#5507]) -> [PASS][240] +1 other test pass
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-8/igt@xe_pat@pat-index-xe2.html
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-7/igt@xe_pat@pat-index-xe2.html

  
#### Warnings ####

  * igt@kms_big_fb@x-tiled-8bpp-rotate-0:
    - shard-adlp:         [DMESG-FAIL][241] ([Intel XE#4543]) -> [DMESG-WARN][242] ([Intel XE#4543]) +9 other tests dmesg-warn
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-2/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-3/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-adlp:         [DMESG-FAIL][243] ([Intel XE#4543]) -> [DMESG-FAIL][244] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543])
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][245] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345]) -> [INCOMPLETE][246] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522] / [Intel XE#4543])
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][247] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [INCOMPLETE][248] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522] / [Intel XE#4543])
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2-set2:     [FAIL][249] ([Intel XE#1178]) -> [DMESG-FAIL][250] ([Intel XE#4543]) +1 other test dmesg-fail
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-434/igt@kms_content_protection@atomic-dpms.html
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-433/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@legacy:
    - shard-bmg:          [SKIP][251] ([Intel XE#2341]) -> [FAIL][252] ([Intel XE#1178])
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-6/igt@kms_content_protection@legacy.html
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-4/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@uevent:
    - shard-dg2-set2:     [FAIL][253] ([Intel XE#1188]) -> [DMESG-FAIL][254] ([Intel XE#4543]) +1 other test dmesg-fail
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-432/igt@kms_content_protection@uevent.html
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-432/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [SKIP][255] ([Intel XE#2291]) -> [INCOMPLETE][256] ([Intel XE#3226])
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-bmg:          [SKIP][257] ([Intel XE#2316]) -> [DMESG-WARN][258] ([Intel XE#5208])
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-6/igt@kms_flip@2x-modeset-vs-vblank-race.html
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-2/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@flip-vs-panning-interruptible:
    - shard-adlp:         [DMESG-WARN][259] ([Intel XE#4543] / [Intel XE#5208]) -> [DMESG-FAIL][260] ([Intel XE#4543])
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-3/igt@kms_flip@flip-vs-panning-interruptible.html
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-4/igt@kms_flip@flip-vs-panning-interruptible.html

  * igt@kms_flip@flip-vs-panning-interruptible@b-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][261] ([Intel XE#4543]) -> [DMESG-FAIL][262] ([Intel XE#4543]) +5 other tests dmesg-fail
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-3/igt@kms_flip@flip-vs-panning-interruptible@b-hdmi-a1.html
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-4/igt@kms_flip@flip-vs-panning-interruptible@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-adlp:         [DMESG-WARN][263] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543]) -> [DMESG-FAIL][264] ([Intel XE#2953] / [Intel XE#4173])
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-1/igt@kms_flip@flip-vs-suspend.html
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-6/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@plain-flip-ts-check-interruptible:
    - shard-adlp:         [DMESG-WARN][265] ([Intel XE#4543]) -> [FAIL][266] ([Intel XE#3149])
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-3/igt@kms_flip@plain-flip-ts-check-interruptible.html
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-4/igt@kms_flip@plain-flip-ts-check-interruptible.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][267] ([Intel XE#2312]) -> [SKIP][268] ([Intel XE#2311]) +14 other tests skip
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][269] ([Intel XE#2311]) -> [SKIP][270] ([Intel XE#2312]) +14 other tests skip
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][271] ([Intel XE#5390]) -> [SKIP][272] ([Intel XE#2312]) +4 other tests skip
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][273] ([Intel XE#2312]) -> [SKIP][274] ([Intel XE#5390]) +5 other tests skip
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
    - shard-bmg:          [SKIP][275] ([Intel XE#2313]) -> [SKIP][276] ([Intel XE#2312]) +11 other tests skip
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt:
    - shard-bmg:          [SKIP][277] ([Intel XE#2312]) -> [SKIP][278] ([Intel XE#2313]) +16 other tests skip
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_setmode@basic@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [FAIL][279] ([Intel XE#2883]) -> [DMESG-WARN][280] ([Intel XE#4543]) +2 other tests dmesg-warn
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-434/igt@kms_setmode@basic@pipe-a-hdmi-a-6.html
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-464/igt@kms_setmode@basic@pipe-a-hdmi-a-6.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-dg2-set2:     [ABORT][281] ([Intel XE#5466]) -> [ABORT][282] ([Intel XE#4917] / [Intel XE#5466])
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-dg2-466/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-dg2-466/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  * igt@xe_pm@d3cold-mocs:
    - shard-adlp:         [SKIP][283] ([Intel XE#2284]) -> [TIMEOUT][284] ([Intel XE#3876])
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-adlp-3/igt@xe_pm@d3cold-mocs.html
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-adlp-4/igt@xe_pm@d3cold-mocs.html
    - shard-bmg:          [ABORT][285] ([Intel XE#4760]) -> [TIMEOUT][286] ([Intel XE#3876] / [Intel XE#6162])
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142/shard-bmg-1/igt@xe_pm@d3cold-mocs.html
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/shard-bmg-3/igt@xe_pm@d3cold-mocs.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
  [Intel XE#1231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1231
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1475]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1475
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#3106]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3106
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3226]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3226
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4626
  [Intel XE#4689]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4689
  [Intel XE#4760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4760
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
  [Intel XE#4937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4937
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5175]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5175
  [Intel XE#5195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5195
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5394]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5394
  [Intel XE#5428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5428
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5507
  [Intel XE#5667]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5667
  [Intel XE#5672]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5672
  [Intel XE#5681]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5681
  [Intel XE#5786]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5786
  [Intel XE#5890]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5890
  [Intel XE#6050]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6050
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#6162]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6162
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142 -> xe-pw-154809v1

  IGT_8546: 8546
  xe-3803-cfa128d879d8cdea4007ddd56dcc2eac73ff2142: cfa128d879d8cdea4007ddd56dcc2eac73ff2142
  xe-pw-154809v1: 154809v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v1/index.html

[-- Attachment #2: Type: text/html, Size: 83583 bytes --]

[PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic

[Ankit Nautiyal]

This patch series refactors VRR and DSB timing logic by introducing
explicit handling of Set Context Latency (SCL) the number of lines required
before double buffering to safely program display registers, aka W2 Window.

Previously, SCL was handled implicitly via vblank delay calculations. This
was a hinderance for later work to optimize guardband length. This series
formalizes SCL as `set_context_latency` in `intel_crtc_state`, enabling
consistent tracking and timing/delay computation across platforms.

- Introduces `set_context_latency` to track SCL explicitly.
- Refactors VRR evasion and DSB wait logic to use SCL directly.
- Clamps guardband values based on hardware limits and timing constraints.
- Renames helpers for clarity and removes legacy delay logic.

Rev2: Address comments from Ville:
- Handle SCL for TGL better and meld patch with previous patch.
- Drop patch to use set context latency in evasion logic.
- Add patch to introduce REG_FIELD_MAX based on FIELD_MAX.
- Added new helper to wait for SCL start and end lines.
- Other minor refactoring suggested in comments.

Ankit Nautiyal (9):
  drm/i915/psr:
    s/intel_psr_min_vblank_delay/intel_psr_min_set_context_latency
  drm/i915/display: Add set_context_latency to crtc_state
  drm/i915/vrr: Use set_context_latency instead of
    intel_vrr_real_vblank_delay()
  drm/i915/vrr: Use SCL for computing guardband
  drm/i915/vrr: s/intel_vrr_vblank_delay/intel_vrr_scl_delay
  drm/i915/dsb:
    s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_delayed_vblank
  drm/i915/display: Wait for scl start instead of dsb_wait_vblanks
  drm/i915/reg_defs: Add REG_FIELD_MAX wrapper for FIELD_MAX()
  drm/i915/vrr: Clamp guardband as per hardware and timing constraints

 drivers/gpu/drm/i915/display/intel_color.c    |  2 +-
 .../drm/i915/display/intel_crtc_state_dump.c  |  5 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 55 ++++++++-----
 .../drm/i915/display/intel_display_types.h    |  3 +
 drivers/gpu/drm/i915/display/intel_dsb.c      | 26 ++++++-
 drivers/gpu/drm/i915/display/intel_dsb.h      |  4 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  6 +-
 drivers/gpu/drm/i915/display/intel_psr.h      |  2 +-
 drivers/gpu/drm/i915/display/intel_vblank.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 77 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_vrr.h      |  4 +-
 drivers/gpu/drm/i915/i915_reg_defs.h          | 10 +++
 12 files changed, 140 insertions(+), 56 deletions(-)

-- 
2.45.2

[PATCH 9/9] drm/i915/vrr: Clamp guardband as per hardware and timing constraints

[Ankit Nautiyal]

The maximum guardband value is constrained by two factors:
- The actual vblank length minus set context latency (SCL)
- The hardware register field width:
  - 8 bits for ICL/TGL (VRR_CTL_PIPELINE_FULL_MASK -> max 255)
  - 16 bits for ADL+ (XELPD_VRR_CTL_VRR_GUARDBAND_MASK -> max 65535)

Remove the #FIXME and clamp the guardband to the maximum allowed value.

v2: Address comments from Ville:
- Use REG_FIELD_MAX()
- Separate out functions for intel_vrr_max_guardband(),
intel_vrr_max_vblank_guardband().

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 44 +++++++++++++++++-------
 1 file changed, 32 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 8f851d3a3f44..f37076575bfe 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -409,6 +409,35 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	}
 }
 
+static int
+intel_vrr_max_hw_guardband(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (DISPLAY_VER(display) >= 13)
+		return REG_FIELD_MAX(XELPD_VRR_CTL_VRR_GUARDBAND_MASK);
+
+	return intel_vrr_pipeline_full_to_guardband(crtc_state,
+						    REG_FIELD_MAX(VRR_CTL_PIPELINE_FULL_MASK));
+}
+
+static int
+intel_vrr_max_vblank_guardband(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	return crtc_state->vrr.vmin -
+	       crtc_state->set_context_latency -
+	       intel_vrr_extra_vblank_delay(display);
+}
+
+static int
+intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
+{
+	return min(intel_vrr_max_hw_guardband(crtc_state),
+		   intel_vrr_max_vblank_guardband(crtc_state));
+}
+
 void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -417,22 +446,13 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
-	crtc_state->vrr.guardband =
-		crtc_state->vrr.vmin -
-		adjusted_mode->vdisplay -
-		crtc_state->set_context_latency -
-		intel_vrr_extra_vblank_delay(display);
-
-	if (DISPLAY_VER(display) < 13) {
-		/* FIXME handle the limit in a proper way */
-		crtc_state->vrr.guardband =
-			min(crtc_state->vrr.guardband,
-			    intel_vrr_pipeline_full_to_guardband(crtc_state, 255));
+	crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
+					intel_vrr_max_guardband(crtc_state));
 
+	if (DISPLAY_VER(display) < 13)
 		crtc_state->vrr.pipeline_full =
 			intel_vrr_guardband_to_pipeline_full(crtc_state,
 							     crtc_state->vrr.guardband);
-	}
 }
 
 static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
-- 
2.45.2

Re: [PATCH 9/9] drm/i915/vrr: Clamp guardband as per hardware and timing constraints

[Ville Syrjälä]

On Tue, Sep 23, 2025 at 06:40:43PM +0530, Ankit Nautiyal wrote:
> The maximum guardband value is constrained by two factors:
> - The actual vblank length minus set context latency (SCL)
> - The hardware register field width:
>   - 8 bits for ICL/TGL (VRR_CTL_PIPELINE_FULL_MASK -> max 255)
>   - 16 bits for ADL+ (XELPD_VRR_CTL_VRR_GUARDBAND_MASK -> max 65535)
> 
> Remove the #FIXME and clamp the guardband to the maximum allowed value.
> 
> v2: Address comments from Ville:
> - Use REG_FIELD_MAX()
> - Separate out functions for intel_vrr_max_guardband(),
> intel_vrr_max_vblank_guardband().
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 44 +++++++++++++++++-------
>  1 file changed, 32 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 8f851d3a3f44..f37076575bfe 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -409,6 +409,35 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>  	}
>  }
>  
> +static int
> +intel_vrr_max_hw_guardband(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	if (DISPLAY_VER(display) >= 13)
> +		return REG_FIELD_MAX(XELPD_VRR_CTL_VRR_GUARDBAND_MASK);
> +

I'd put 'else' here for consistency with other stuff.

> +	return intel_vrr_pipeline_full_to_guardband(crtc_state,
> +						    REG_FIELD_MAX(VRR_CTL_PIPELINE_FULL_MASK));
> +}
> +
> +static int
> +intel_vrr_max_vblank_guardband(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	return crtc_state->vrr.vmin -

Missing a -crtc_vdisplay here.

what those
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +	       crtc_state->set_context_latency -
> +	       intel_vrr_extra_vblank_delay(display);
> +}
> +
> +static int
> +intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
> +{
> +	return min(intel_vrr_max_hw_guardband(crtc_state),
> +		   intel_vrr_max_vblank_guardband(crtc_state));
> +}
> +
>  void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> @@ -417,22 +446,13 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
>  	if (!intel_vrr_possible(crtc_state))
>  		return;
>  
> -	crtc_state->vrr.guardband =
> -		crtc_state->vrr.vmin -
> -		adjusted_mode->vdisplay -
> -		crtc_state->set_context_latency -
> -		intel_vrr_extra_vblank_delay(display);
> -
> -	if (DISPLAY_VER(display) < 13) {
> -		/* FIXME handle the limit in a proper way */
> -		crtc_state->vrr.guardband =
> -			min(crtc_state->vrr.guardband,
> -			    intel_vrr_pipeline_full_to_guardband(crtc_state, 255));
> +	crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
> +					intel_vrr_max_guardband(crtc_state));
>  
> +	if (DISPLAY_VER(display) < 13)
>  		crtc_state->vrr.pipeline_full =
>  			intel_vrr_guardband_to_pipeline_full(crtc_state,
>  							     crtc_state->vrr.guardband);
> -	}
>  }
>  
>  static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel