Re: ✗ Xe.CI.Full: failure for series starting with [1/2] drm/xe: Fix ggtt fb alignment

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Wed, Sep 24, 2025 at 12:26:31PM +0100, Tvrtko Ursulin wrote:
> 
> 
> On 24/09/2025 12:11, Patchwork wrote:
> 
> [snip]
> 
> >         Possible regressions
> > 
> >   *
> > 
> >     igt@kms_async_flips@async-flip-with-page-flip-events-tiled-
> >     atomic@pipe-d-dp-2-4:
> > 
> >       o shard-bmg: NOTRUN -> DMESG-WARN <https://intel-gfx-ci.01.org/
> >         tree/intel-xe/xe-pw-154941v1/shard-bmg-1/
> >         igt@kms_async_flips@async-flip-with-page-flip-events-tiled-
> >         atomic@pipe-d-dp-2-4.html> +8 other tests dmesg-warn
> >   *
> > 
> >     igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-c-
> >     hdmi-a-3-4:
> > 
> >       o shard-bmg: PASS <https://intel-gfx-ci.01.org/tree/intel-xe/
> >         xe-3822-af3cdefd0a1ad2dad29fcde0854ccbce494cc28a/shard-bmg-5/
> >         igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-
> >         c-hdmi-a-3-4.html> -> DMESG-WARN <https://intel-gfx-ci.01.org/
> >         tree/intel-xe/xe-pw-154941v1/shard-bmg-8/
> >         igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-
> >         c-hdmi-a-3-4.html> +18 other tests dmesg-warn
> 
> Mysterious page faults. Looks like the BMG failures due DPT alignment / 
> 512 were real after all. Does it provide any hint to you Ville?

Sounds like the same thing that's happening on MTL.

For ADL I previously forced the DPT alignment in GGTT to 16k
in tgl_plane_min_alignment() to cure async flip faults.

I later tried the same trick on MTL, but I think I had to
bump it to 32k to completely eliminate the faults there.

And the MTL faults didn't seem to be entirely about alignment
because IIRC the other way I could eliminate them was by adding
a few dummy pages around the DPT in GGTT, even while forcing the
start of DPT to be only 4k aligned. And that's when I got pulled
into some other work and didn't have time to finish the
investigation :/

-- 
Ville Syrjälä
Intel