[PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic

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* [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic
@ 2025-09-24 10:51 Ankit Nautiyal
  2025-09-24 10:51 ` [PATCH 1/9] drm/i915/psr: s/intel_psr_min_vblank_delay/intel_psr_min_set_context_latency Ankit Nautiyal
                   ` (12 more replies)
  0 siblings, 13 replies; 21+ messages in thread
From: Ankit Nautiyal @ 2025-09-24 10:51 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

This patch series refactors VRR and DSB timing logic by introducing
explicit handling of Set Context Latency (SCL) the number of lines required
before double buffering to safely program display registers, aka W2 Window.

Previously, SCL was handled implicitly via vblank delay calculations. This
was a hinderance for later work to optimize guardband length. This series
formalizes SCL as `set_context_latency` in `intel_crtc_state`, enabling
consistent tracking and timing/delay computation across platforms.

- Introduces `set_context_latency` to track SCL explicitly.
- Refactors VRR evasion and DSB wait logic to use SCL directly.
- Clamps guardband values based on hardware limits and timing constraints.
- Renames helpers for clarity and removes legacy delay logic.

Rev2: Address comments from Ville:
- Handle SCL for TGL better and meld patch with previous patch.
- Drop patch to use set context latency in evasion logic.
- Add patch to introduce REG_FIELD_MAX based on FIELD_MAX.
- Added new helper to wait for SCL start and end lines.
- Other minor refactoring suggested in comments.

Rev3:
- Drop patch to rename vrr_vblank_delay and instead add a patch to
  replace it directly with crtc_state->set_context_latency. (Ville)
- Fix few places where adjusted_mode->crtc_vdisplay was missed. (Ville)
- Minor refactoring to make the helpers consistent with other parts.

Ankit Nautiyal (9):
  drm/i915/psr:
    s/intel_psr_min_vblank_delay/intel_psr_min_set_context_latency
  drm/i915/display: Add set_context_latency to crtc_state
  drm/i915/vrr: Use set_context_latency instead of
    intel_vrr_real_vblank_delay()
  drm/i915/vrr: Use SCL for computing guardband
  drm/i915/dsb:
    s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_delayed_vblank
  drm/i915/display: Wait for scl start instead of dsb_wait_vblanks
  drm/i915/reg_defs: Add REG_FIELD_MAX wrapper for FIELD_MAX()
  drm/i915/vrr: Clamp guardband as per hardware and timing constraints
  drm/i915/display: Drop intel_vrr_vblank_delay and use
    set_context_latency

 drivers/gpu/drm/i915/display/intel_color.c    |  2 +-
 .../drm/i915/display/intel_crtc_state_dump.c  |  5 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 58 +++++++++----
 .../drm/i915/display/intel_display_types.h    |  3 +
 drivers/gpu/drm/i915/display/intel_dsb.c      | 24 +++++-
 drivers/gpu/drm/i915/display/intel_dsb.h      |  4 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  6 +-
 drivers/gpu/drm/i915/display/intel_psr.h      |  2 +-
 drivers/gpu/drm/i915/display/intel_vblank.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 86 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_vrr.h      |  3 +-
 drivers/gpu/drm/i915/i915_reg_defs.h          | 10 +++
 12 files changed, 143 insertions(+), 62 deletions(-)

-- 
2.45.2


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [PATCH 1/9] drm/i915/psr: s/intel_psr_min_vblank_delay/intel_psr_min_set_context_latency
  2025-09-24 10:51 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
@ 2025-09-24 10:51 ` Ankit Nautiyal
  2025-09-24 10:51 ` [PATCH 2/9] drm/i915/display: Add set_context_latency to crtc_state Ankit Nautiyal
                   ` (11 subsequent siblings)
  12 siblings, 0 replies; 21+ messages in thread
From: Ankit Nautiyal @ 2025-09-24 10:51 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

Rename intel_psr_min_vblank_delay to intel_psr_min_set_context_latency
to reflect that it provides the minimum value for 'Set context
latency'(SCL or Window W2) for PSR/Panel Replay to work correctly across
different platforms.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 drivers/gpu/drm/i915/display/intel_psr.c     | 6 +++---
 drivers/gpu/drm/i915/display/intel_psr.h     | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 18b9baa96241..679c2a9baaee 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2369,7 +2369,7 @@ static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state)
 	if (!HAS_DSB(display))
 		return 0;
 
-	vblank_delay = max(vblank_delay, intel_psr_min_vblank_delay(crtc_state));
+	vblank_delay = max(vblank_delay, intel_psr_min_set_context_latency(crtc_state));
 
 	return vblank_delay;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 01bf304c705f..49ccd0864c55 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2360,12 +2360,12 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
 }
 
 /**
- * intel_psr_min_vblank_delay - Minimum vblank delay needed by PSR
+ * intel_psr_min_set_context_latency - Minimum 'set context latency' lines needed by PSR
  * @crtc_state: the crtc state
  *
- * Return minimum vblank delay needed by PSR.
+ * Return minimum SCL lines/delay needed by PSR.
  */
-int intel_psr_min_vblank_delay(const struct intel_crtc_state *crtc_state)
+int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 077751aa599f..9147996d6c9e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -77,7 +77,7 @@ void intel_psr_unlock(const struct intel_crtc_state *crtc_state);
 void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
 					  struct intel_atomic_state *state,
 					  struct intel_crtc *crtc);
-int intel_psr_min_vblank_delay(const struct intel_crtc_state *crtc_state);
+int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state);
 void intel_psr_connector_debugfs_add(struct intel_connector *connector);
 void intel_psr_debugfs_register(struct intel_display *display);
 bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH 2/9] drm/i915/display: Add set_context_latency to crtc_state
  2025-09-24 10:51 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
  2025-09-24 10:51 ` [PATCH 1/9] drm/i915/psr: s/intel_psr_min_vblank_delay/intel_psr_min_set_context_latency Ankit Nautiyal
@ 2025-09-24 10:51 ` Ankit Nautiyal
  2025-09-24 10:51 ` [PATCH 3/9] drm/i915/vrr: Use set_context_latency instead of intel_vrr_real_vblank_delay() Ankit Nautiyal
                   ` (10 subsequent siblings)
  12 siblings, 0 replies; 21+ messages in thread
From: Ankit Nautiyal @ 2025-09-24 10:51 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

'Set context latency' (SCL, Window W2) is defined as the number of lines
before the double buffering point, which are required to complete
programming of the registers, typically when DSB is used to program the
display registers.

Since we are not using this window for programming the registers, this
is mostly set to 0, unless there is a requirement for few cases related
to PSR/PR where the 'set context latency' should be at least 1.

Currently we are using the 'set context latency' (if required) implicitly
by moving the vblank start by the required amount and then measuring the
delay i.e. the difference between undelayed vblank start and delayed vblank
start.

Since our guardband matches the vblank length, this was not a problem as
the difference between the undelayed vblank and delayed vblank was at
the most equal to the 'set context latency' lines.

However, if we want to optimize the guardband, the difference between the
undelayed and the delayed vblank will be large and we cannot use this
difference as the 'set context latency' lines.

To make way for this optimization of guardband, formally introduce the
'set context latency' or SCL and track it as a new member
`set_context_latency` of the structure intel_crtc_state.

Eventually, all references of vblank delay where we mean to use set
context latency will be replaced by this new `set_context_latency`
member.

Note: for TGL the TRANS_SET_CONTEXT_LATENCY doesn't exist to account for
the SCL. However, the VBLANK_START-VACTIVE difference plays an identical
role here ie. it can be used to create the SCL window ahead of the
undelayed vblank.

While readback since there is no specific register to read out the SCL, use
the difference between vblank start and vactive to populate the new member
for TGL.

v2:
- Use u16 for set_context_latency. (Ville)
- s/vblank_delay/set_context_latency. (Ville)
- Meld the changes for TGL with this change. (Ville)

v3:
- Update comment to clarify the TGL case. (Ville)
- Fix typo in commit message.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_crtc_state_dump.c  |  5 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 56 +++++++++++++------
 .../drm/i915/display/intel_display_types.h    |  3 +
 3 files changed, 44 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 0c7f91046996..a14bcda4446c 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -289,10 +289,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 	drm_printf(&p, "scanline offset: %d\n",
 		   intel_crtc_scanline_offset(pipe_config));
 
-	drm_printf(&p, "vblank delay: %d, framestart delay: %d, MSA timing delay: %d\n",
+	drm_printf(&p, "vblank delay: %d, framestart delay: %d, MSA timing delay: %d set context latency: %d\n",
 		   pipe_config->hw.adjusted_mode.crtc_vblank_start -
 		   pipe_config->hw.adjusted_mode.crtc_vdisplay,
-		   pipe_config->framestart_delay, pipe_config->msa_timing_delay);
+		   pipe_config->framestart_delay, pipe_config->msa_timing_delay,
+		   pipe_config->set_context_latency);
 
 	drm_printf(&p, "vrr: %s, fixed rr: %s, vmin: %d, vmax: %d, flipline: %d, pipeline full: %d, guardband: %d vsync start: %d, vsync end: %d\n",
 		   str_yes_no(pipe_config->vrr.enable),
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 679c2a9baaee..050b6849dedc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2361,39 +2361,44 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
-static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state)
+static int intel_crtc_set_context_latency(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	int vblank_delay = 0;
+	int set_context_latency = 0;
 
 	if (!HAS_DSB(display))
 		return 0;
 
-	vblank_delay = max(vblank_delay, intel_psr_min_set_context_latency(crtc_state));
+	set_context_latency = max(set_context_latency,
+				  intel_psr_min_set_context_latency(crtc_state));
 
-	return vblank_delay;
+	return set_context_latency;
 }
 
-static int intel_crtc_compute_vblank_delay(struct intel_atomic_state *state,
-					   struct intel_crtc *crtc)
+static int intel_crtc_compute_set_context_latency(struct intel_atomic_state *state,
+						  struct intel_crtc *crtc)
 {
 	struct intel_display *display = to_intel_display(state);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
-	int vblank_delay, max_vblank_delay;
+	int set_context_latency, max_vblank_delay;
+
+	set_context_latency = intel_crtc_set_context_latency(crtc_state);
 
-	vblank_delay = intel_crtc_vblank_delay(crtc_state);
 	max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1;
 
-	if (vblank_delay > max_vblank_delay) {
-		drm_dbg_kms(display->drm, "[CRTC:%d:%s] vblank delay (%d) exceeds max (%d)\n",
-			    crtc->base.base.id, crtc->base.name, vblank_delay, max_vblank_delay);
+	if (set_context_latency > max_vblank_delay) {
+		drm_dbg_kms(display->drm, "[CRTC:%d:%s] set context latency (%d) exceeds max (%d)\n",
+			    crtc->base.base.id, crtc->base.name,
+			    set_context_latency,
+			    max_vblank_delay);
 		return -EINVAL;
 	}
 
-	adjusted_mode->crtc_vblank_start += vblank_delay;
+	crtc_state->set_context_latency = set_context_latency;
+	adjusted_mode->crtc_vblank_start += set_context_latency;
 
 	return 0;
 }
@@ -2405,7 +2410,7 @@ static int intel_crtc_compute_config(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	int ret;
 
-	ret = intel_crtc_compute_vblank_delay(state, crtc);
+	ret = intel_crtc_compute_set_context_latency(state, crtc);
 	if (ret)
 		return ret;
 
@@ -2617,7 +2622,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	if (DISPLAY_VER(display) >= 13) {
 		intel_de_write(display,
 			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
-			       crtc_vblank_start - crtc_vdisplay);
+			       crtc_state->set_context_latency);
 
 		/*
 		 * VBLANK_START not used by hw, just clear it
@@ -2707,7 +2712,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 	if (DISPLAY_VER(display) >= 13) {
 		intel_de_write(display,
 			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
-			       crtc_vblank_start - crtc_vdisplay);
+			       crtc_state->set_context_latency);
 
 		/*
 		 * VBLANK_START not used by hw, just clear it
@@ -2820,11 +2825,24 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
 		adjusted_mode->crtc_vblank_end += 1;
 	}
 
-	if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder))
-		adjusted_mode->crtc_vblank_start =
-			adjusted_mode->crtc_vdisplay +
+	if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) {
+		pipe_config->set_context_latency =
 			intel_de_read(display,
 				      TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder));
+		adjusted_mode->crtc_vblank_start =
+			adjusted_mode->crtc_vdisplay +
+			pipe_config->set_context_latency;
+	} else if (DISPLAY_VER(display) == 12) {
+		/*
+		 * TGL doesn't have a dedicated register for SCL.
+		 * Instead, the hardware derives SCL from the difference between
+		 * TRANS_VBLANK.vblank_start and TRANS_VTOTAL.vactive.
+		 * To reflect the HW behaviour, readout the value for SCL as
+		 * Vblank start - Vactive.
+		 */
+		pipe_config->set_context_latency =
+			adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
+	}
 
 	if (DISPLAY_VER(display) >= 30)
 		pipe_config->min_hblank = intel_de_read(display,
@@ -5387,6 +5405,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_I(vrr.guardband);
 	}
 
+	PIPE_CONF_CHECK_I(set_context_latency);
+
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
 #undef PIPE_CONF_CHECK_LLI
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 358ab922d7a7..029c47743f8b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1341,6 +1341,9 @@ struct intel_crtc_state {
 
 	/* LOBF flag */
 	bool has_lobf;
+
+	/* W2 window or 'set context latency' lines */
+	u16 set_context_latency;
 };
 
 enum intel_pipe_crc_source {
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH 3/9] drm/i915/vrr: Use set_context_latency instead of intel_vrr_real_vblank_delay()
  2025-09-24 10:51 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
  2025-09-24 10:51 ` [PATCH 1/9] drm/i915/psr: s/intel_psr_min_vblank_delay/intel_psr_min_set_context_latency Ankit Nautiyal
  2025-09-24 10:51 ` [PATCH 2/9] drm/i915/display: Add set_context_latency to crtc_state Ankit Nautiyal
@ 2025-09-24 10:51 ` Ankit Nautiyal
  2025-09-24 10:51 ` [PATCH 4/9] drm/i915/vrr: Use SCL for computing guardband Ankit Nautiyal
                   ` (9 subsequent siblings)
  12 siblings, 0 replies; 21+ messages in thread
From: Ankit Nautiyal @ 2025-09-24 10:51 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

The helper intel_vrr_real_vblank_delay() was added to account for the
SCL lines for TGL where we do not have the TRANS_SET_CONTEXT_LATENCY.

Now, since we already are tracking the SCL with new member
`set_context_latency` use it directly instead of the helper.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 16 +++++-----------
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 9e007aab1452..698b33b5b326 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -79,12 +79,6 @@ intel_vrr_check_modeset(struct intel_atomic_state *state)
 	}
 }
 
-static int intel_vrr_real_vblank_delay(const struct intel_crtc_state *crtc_state)
-{
-	return crtc_state->hw.adjusted_mode.crtc_vblank_start -
-		crtc_state->hw.adjusted_mode.crtc_vdisplay;
-}
-
 static int intel_vrr_extra_vblank_delay(struct intel_display *display)
 {
 	/*
@@ -102,7 +96,7 @@ int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
-	return intel_vrr_real_vblank_delay(crtc_state) +
+	return crtc_state->set_context_latency +
 		intel_vrr_extra_vblank_delay(display);
 }
 
@@ -263,7 +257,7 @@ static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
 	if (DISPLAY_VER(display) >= 13)
 		return value;
 	else
-		return value - intel_vrr_real_vblank_delay(crtc_state);
+		return value - crtc_state->set_context_latency;
 }
 
 /*
@@ -761,9 +755,9 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 
 		if (DISPLAY_VER(display) < 13) {
 			/* undo what intel_vrr_hw_value() does when writing the values */
-			crtc_state->vrr.flipline += intel_vrr_real_vblank_delay(crtc_state);
-			crtc_state->vrr.vmax += intel_vrr_real_vblank_delay(crtc_state);
-			crtc_state->vrr.vmin += intel_vrr_real_vblank_delay(crtc_state);
+			crtc_state->vrr.flipline += crtc_state->set_context_latency;
+			crtc_state->vrr.vmax += crtc_state->set_context_latency;
+			crtc_state->vrr.vmin += crtc_state->set_context_latency;
 
 			crtc_state->vrr.vmin += intel_vrr_vmin_flipline_offset(display);
 		}
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH 4/9] drm/i915/vrr: Use SCL for computing guardband
  2025-09-24 10:51 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
                   ` (2 preceding siblings ...)
  2025-09-24 10:51 ` [PATCH 3/9] drm/i915/vrr: Use set_context_latency instead of intel_vrr_real_vblank_delay() Ankit Nautiyal
@ 2025-09-24 10:51 ` Ankit Nautiyal
  2025-09-24 10:51 ` [PATCH 5/9] drm/i915/dsb: s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_delayed_vblank Ankit Nautiyal
                   ` (8 subsequent siblings)
  12 siblings, 0 replies; 21+ messages in thread
From: Ankit Nautiyal @ 2025-09-24 10:51 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

For now guardband is equal to the vblank length so ideally it should be
computed as difference between the vmin vtotal and vactive. However
since we are having few lines as SCL, we need to account for this while
computing the guardband.

Since the vblank start is moved by SCL lines from the vactive, the delta
between the vmin vtotal and new vblank start was used to account for this.
Now that SCL is explicitly tracked using the `set_context_latency` member,
use it directly in the guardband calculation.

In the future, when the guardband is shortened or optimized, we may need
to factor in both the change in the vblank start and SCL lines. For now,
explicitly accounting for SCL is sufficient.

v2: Fix typo: replace adjusted_mode->vdisplay with
adjusted_mode->crtc_vdisplay. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 698b33b5b326..1bb9db06f43d 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -418,7 +418,9 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
 		return;

 	crtc_state->vrr.guardband =
-		crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
+		crtc_state->vrr.vmin -
+		adjusted_mode->crtc_vdisplay -
+		crtc_state->set_context_latency -
 		intel_vrr_extra_vblank_delay(display);

 	if (DISPLAY_VER(display) < 13) {
-- 
2.45.2

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH 5/9] drm/i915/dsb: s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_delayed_vblank
  2025-09-24 10:51 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
                   ` (3 preceding siblings ...)
  2025-09-24 10:51 ` [PATCH 4/9] drm/i915/vrr: Use SCL for computing guardband Ankit Nautiyal
@ 2025-09-24 10:51 ` Ankit Nautiyal
  2025-09-24 10:51 ` [PATCH 6/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks Ankit Nautiyal
                   ` (7 subsequent siblings)
  12 siblings, 0 replies; 21+ messages in thread
From: Ankit Nautiyal @ 2025-09-24 10:51 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

The helper intel_dsb_wait_vblank_delay() is used in DSB to wait for the
delayed vblank after the send push operation. Rename it to
intel_dsb_wait_for_delayed_vblank() to align with the semantics.

v2: Rename to intel_dsb_wait_vblank_delay instead of the proposed SCL
semantics, as this will be ot only about SCL lines with different timing
generator and different refresh rate modes. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c   | 2 +-
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 drivers/gpu/drm/i915/display/intel_dsb.c     | 4 ++--
 drivers/gpu/drm/i915/display/intel_dsb.h     | 4 ++--
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 671db6926e4c..51db70d07fae 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2013,7 +2013,7 @@ void intel_color_prepare_commit(struct intel_atomic_state *state,
 
 	if (crtc_state->use_dsb && intel_color_uses_chained_dsb(crtc_state)) {
 		intel_vrr_send_push(crtc_state->dsb_color, crtc_state);
-		intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color);
+		intel_dsb_wait_for_delayed_vblank(state, crtc_state->dsb_color);
 		intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state);
 		intel_dsb_interrupt(crtc_state->dsb_color);
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 050b6849dedc..b57efd870774 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7271,7 +7271,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
 
 		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
-		intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
+		intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit);
 		intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
 					  new_crtc_state);
 		intel_dsb_interrupt(new_crtc_state->dsb_commit);
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index dee44d45b668..135d40852e4c 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -815,8 +815,8 @@ void intel_dsb_chain(struct intel_atomic_state *state,
 			 wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0);
 }
 
-void intel_dsb_wait_vblank_delay(struct intel_atomic_state *state,
-				 struct intel_dsb *dsb)
+void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
+				       struct intel_dsb *dsb)
 {
 	struct intel_crtc *crtc = dsb->crtc;
 	const struct intel_crtc_state *crtc_state =
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index c8f4499916eb..2f31f2c1d0c5 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -48,8 +48,8 @@ void intel_dsb_nonpost_end(struct intel_dsb *dsb);
 void intel_dsb_interrupt(struct intel_dsb *dsb);
 void intel_dsb_wait_usec(struct intel_dsb *dsb, int count);
 void intel_dsb_wait_vblanks(struct intel_dsb *dsb, int count);
-void intel_dsb_wait_vblank_delay(struct intel_atomic_state *state,
-				 struct intel_dsb *dsb);
+void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
+				       struct intel_dsb *dsb);
 void intel_dsb_wait_scanline_in(struct intel_atomic_state *state,
 				struct intel_dsb *dsb,
 				int lower, int upper);
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH 6/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks
  2025-09-24 10:51 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
                   ` (4 preceding siblings ...)
  2025-09-24 10:51 ` [PATCH 5/9] drm/i915/dsb: s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_delayed_vblank Ankit Nautiyal
@ 2025-09-24 10:51 ` Ankit Nautiyal
  2025-09-24 12:11   ` Ville Syrjälä
  2025-09-24 10:51 ` [PATCH 7/9] drm/i915/reg_defs: Add REG_FIELD_MAX wrapper for FIELD_MAX() Ankit Nautiyal
                   ` (6 subsequent siblings)
  12 siblings, 1 reply; 21+ messages in thread
From: Ankit Nautiyal @ 2025-09-24 10:51 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

Until LNL, intel_dsb_wait_vblanks() used to wait for the undelayed vblank
start. However, from PTL onwards, it waits for the start of the
safe-window defined by the number of lines programmed in the register
TRANS_SET_CONTEXT_LATENCY. This change was introduced to move the SCL
window out of the vblank region, supporting modes with higher refresh
rates and smaller vblanks. This change introduces a "safe window" a
scanline range from (undelayed vblank - SCL) to (delayed vblank - SCL).

As a result, on PTL+ platforms, the DSB wait for vblank completes exactly
SCL lines earlier than the undelayed vblank start (safe window start).
If the flip occurs in the active region and the push happens before the
vmin decision boundary, the DSB wait fires early, and the push is sent
inside this safe window. In such cases, the push bit is cleared at the
delayed vblank, but our wait logic does not account for the early trigger,
leading to DSB poll errors.

To fix this, we add an explicit wait for the end of the safe window i.e.,
the scanline range from (undelayed vblank - SCL) to (delayed vblank - SCL).
Once past this window, we are exactly SCL lines away from the delayed
vblank, and our existing wait logic works as intended.

This additional wait is only effective if the push occurs before the vmin
decision boundary. If the push happens after the boundary, the hardware
already guarantees we're SCL lines away from the delayed vblank, and the
extra wait becomes a no-op.

v2:
- Use helpers for safe window start/end. (Ville)
- Move the extra wait inside the helper to wait for delayed vblank. (Ville)
- Update the commit message.

v3:
- Add more documentation for explanation for the wait. (Ville)
- Rename intel_vrr_vmin_safe_window_start/end as this is vmin safe
  window. (Ville)
- Minor refactoring to align with the code. (Ville)
- Update the commit message for more clarity.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 16 ++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.c | 17 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h |  2 ++
 3 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 135d40852e4c..3cb4c9be146f 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -824,6 +824,22 @@ void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
 	int usecs = intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode,
 					     dsb_vblank_delay(state, crtc));
 
+	/*
+	 * If the push happened before the vmin decision boundary
+	 * we don't know how far we are from the undelayed vblank.
+	 * Wait until we're past the vmin safe window, at which
+	 * point we're SCL lines away from the delayed vblank.
+	 *
+	 * If the push happened after the vmin decision boundary
+	 * the hardware itself guarantees that we're SCL lines
+	 * away from the delayed vblank, and we won't be inside
+	 * the vmin safe window so this extra wait does nothing.
+	 */
+	if (pre_commit_is_vrr_active(state, crtc))
+		intel_dsb_wait_scanline_out(state, dsb,
+					    intel_vrr_vmin_safe_window_start(crtc_state),
+					    intel_vrr_vmin_safe_window_end(crtc_state));
+
 	intel_dsb_wait_usec(dsb, usecs);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 1bb9db06f43d..26c5c32a9a58 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -800,3 +800,20 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	if (crtc_state->vrr.enable)
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
+
+int intel_vrr_vmin_safe_window_start(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (DISPLAY_VER(display) >= 30)
+		return crtc_state->hw.adjusted_mode.crtc_vdisplay -
+		       crtc_state->set_context_latency;
+	else
+		return crtc_state->hw.adjusted_mode.crtc_vdisplay;
+}
+
+int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state)
+{
+	return intel_vrr_vmin_vblank_start(crtc_state) -
+	       crtc_state->set_context_latency;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 38bf9996b883..239e4f94725c 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -41,5 +41,7 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
 bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
+int intel_vrr_vmin_safe_window_start(const struct intel_crtc_state *crtc_state);
+int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_VRR_H__ */
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [PATCH 6/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks
  2025-09-24 10:51 ` [PATCH 6/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks Ankit Nautiyal
@ 2025-09-24 12:11   ` Ville Syrjälä
  2025-09-24 14:04     ` Nautiyal, Ankit K
  0 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjälä @ 2025-09-24 12:11 UTC (permalink / raw)
  To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe

On Wed, Sep 24, 2025 at 04:21:26PM +0530, Ankit Nautiyal wrote:
> Until LNL, intel_dsb_wait_vblanks() used to wait for the undelayed vblank
> start. However, from PTL onwards, it waits for the start of the
> safe-window defined by the number of lines programmed in the register
> TRANS_SET_CONTEXT_LATENCY. This change was introduced to move the SCL
> window out of the vblank region, supporting modes with higher refresh
> rates and smaller vblanks. This change introduces a "safe window" a
> scanline range from (undelayed vblank - SCL) to (delayed vblank - SCL).
> 
> As a result, on PTL+ platforms, the DSB wait for vblank completes exactly
> SCL lines earlier than the undelayed vblank start (safe window start).
> If the flip occurs in the active region and the push happens before the
> vmin decision boundary, the DSB wait fires early, and the push is sent
> inside this safe window. In such cases, the push bit is cleared at the
> delayed vblank, but our wait logic does not account for the early trigger,
> leading to DSB poll errors.
> 
> To fix this, we add an explicit wait for the end of the safe window i.e.,
> the scanline range from (undelayed vblank - SCL) to (delayed vblank - SCL).
> Once past this window, we are exactly SCL lines away from the delayed
> vblank, and our existing wait logic works as intended.
> 
> This additional wait is only effective if the push occurs before the vmin
> decision boundary. If the push happens after the boundary, the hardware
> already guarantees we're SCL lines away from the delayed vblank, and the
> extra wait becomes a no-op.
> 
> v2:
> - Use helpers for safe window start/end. (Ville)
> - Move the extra wait inside the helper to wait for delayed vblank. (Ville)
> - Update the commit message.
> 
> v3:
> - Add more documentation for explanation for the wait. (Ville)
> - Rename intel_vrr_vmin_safe_window_start/end as this is vmin safe
>   window. (Ville)
> - Minor refactoring to align with the code. (Ville)
> - Update the commit message for more clarity.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dsb.c | 16 ++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_vrr.c | 17 +++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_vrr.h |  2 ++
>  3 files changed, 35 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 135d40852e4c..3cb4c9be146f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -824,6 +824,22 @@ void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
>  	int usecs = intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode,
>  					     dsb_vblank_delay(state, crtc));
>  
> +	/*
> +	 * If the push happened before the vmin decision boundary
> +	 * we don't know how far we are from the undelayed vblank.
> +	 * Wait until we're past the vmin safe window, at which
> +	 * point we're SCL lines away from the delayed vblank.
> +	 *
> +	 * If the push happened after the vmin decision boundary
> +	 * the hardware itself guarantees that we're SCL lines
> +	 * away from the delayed vblank, and we won't be inside
> +	 * the vmin safe window so this extra wait does nothing.
> +	 */
> +	if (pre_commit_is_vrr_active(state, crtc))
> +		intel_dsb_wait_scanline_out(state, dsb,
> +					    intel_vrr_vmin_safe_window_start(crtc_state),
> +					    intel_vrr_vmin_safe_window_end(crtc_state));

Hmm, I thought we already had a 'if (vrr)' check here. But I guess that
was in dsb_vblank_delay(). Hmm, yeah I think what you did here is fine
for the moment.

I'm thinking we should follow up with inlining dsb_vblank_delay()
directly into intel_dsb_wait_for_delayed_vblank(), just to keep all
the VRR related wait magic in one place. I don't think there are any
other users of dsb_vblank_delay().

> +
>  	intel_dsb_wait_usec(dsb, usecs);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 1bb9db06f43d..26c5c32a9a58 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -800,3 +800,20 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>  	if (crtc_state->vrr.enable)
>  		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>  }
> +
> +int intel_vrr_vmin_safe_window_start(const struct intel_crtc_state *crtc_state)

I only wanted you to rename the safe_window_end(). The safe window
start doesn't change for vmin/vmax/etc. So should drop the "vmin"
again from this one.

With that
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	if (DISPLAY_VER(display) >= 30)
> +		return crtc_state->hw.adjusted_mode.crtc_vdisplay -
> +		       crtc_state->set_context_latency;
> +	else
> +		return crtc_state->hw.adjusted_mode.crtc_vdisplay;
> +}
> +
> +int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state)
> +{
> +	return intel_vrr_vmin_vblank_start(crtc_state) -
> +	       crtc_state->set_context_latency;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 38bf9996b883..239e4f94725c 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -41,5 +41,7 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
>  void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
>  void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
>  bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
> +int intel_vrr_vmin_safe_window_start(const struct intel_crtc_state *crtc_state);
> +int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);
>  
>  #endif /* __INTEL_VRR_H__ */
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH 6/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks
  2025-09-24 12:11   ` Ville Syrjälä
@ 2025-09-24 14:04     ` Nautiyal, Ankit K
  0 siblings, 0 replies; 21+ messages in thread
From: Nautiyal, Ankit K @ 2025-09-24 14:04 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx, intel-xe


On 9/24/2025 5:41 PM, Ville Syrjälä wrote:
> On Wed, Sep 24, 2025 at 04:21:26PM +0530, Ankit Nautiyal wrote:
>> Until LNL, intel_dsb_wait_vblanks() used to wait for the undelayed vblank
>> start. However, from PTL onwards, it waits for the start of the
>> safe-window defined by the number of lines programmed in the register
>> TRANS_SET_CONTEXT_LATENCY. This change was introduced to move the SCL
>> window out of the vblank region, supporting modes with higher refresh
>> rates and smaller vblanks. This change introduces a "safe window" a
>> scanline range from (undelayed vblank - SCL) to (delayed vblank - SCL).
>>
>> As a result, on PTL+ platforms, the DSB wait for vblank completes exactly
>> SCL lines earlier than the undelayed vblank start (safe window start).
>> If the flip occurs in the active region and the push happens before the
>> vmin decision boundary, the DSB wait fires early, and the push is sent
>> inside this safe window. In such cases, the push bit is cleared at the
>> delayed vblank, but our wait logic does not account for the early trigger,
>> leading to DSB poll errors.
>>
>> To fix this, we add an explicit wait for the end of the safe window i.e.,
>> the scanline range from (undelayed vblank - SCL) to (delayed vblank - SCL).
>> Once past this window, we are exactly SCL lines away from the delayed
>> vblank, and our existing wait logic works as intended.
>>
>> This additional wait is only effective if the push occurs before the vmin
>> decision boundary. If the push happens after the boundary, the hardware
>> already guarantees we're SCL lines away from the delayed vblank, and the
>> extra wait becomes a no-op.
>>
>> v2:
>> - Use helpers for safe window start/end. (Ville)
>> - Move the extra wait inside the helper to wait for delayed vblank. (Ville)
>> - Update the commit message.
>>
>> v3:
>> - Add more documentation for explanation for the wait. (Ville)
>> - Rename intel_vrr_vmin_safe_window_start/end as this is vmin safe
>>    window. (Ville)
>> - Minor refactoring to align with the code. (Ville)
>> - Update the commit message for more clarity.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dsb.c | 16 ++++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_vrr.c | 17 +++++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_vrr.h |  2 ++
>>   3 files changed, 35 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
>> index 135d40852e4c..3cb4c9be146f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>> @@ -824,6 +824,22 @@ void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
>>   	int usecs = intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode,
>>   					     dsb_vblank_delay(state, crtc));
>>   
>> +	/*
>> +	 * If the push happened before the vmin decision boundary
>> +	 * we don't know how far we are from the undelayed vblank.
>> +	 * Wait until we're past the vmin safe window, at which
>> +	 * point we're SCL lines away from the delayed vblank.
>> +	 *
>> +	 * If the push happened after the vmin decision boundary
>> +	 * the hardware itself guarantees that we're SCL lines
>> +	 * away from the delayed vblank, and we won't be inside
>> +	 * the vmin safe window so this extra wait does nothing.
>> +	 */
>> +	if (pre_commit_is_vrr_active(state, crtc))
>> +		intel_dsb_wait_scanline_out(state, dsb,
>> +					    intel_vrr_vmin_safe_window_start(crtc_state),
>> +					    intel_vrr_vmin_safe_window_end(crtc_state));
> Hmm, I thought we already had a 'if (vrr)' check here. But I guess that
> was in dsb_vblank_delay(). Hmm, yeah I think what you did here is fine
> for the moment.
>
> I'm thinking we should follow up with inlining dsb_vblank_delay()
> directly into intel_dsb_wait_for_delayed_vblank(), just to keep all
> the VRR related wait magic in one place. I don't think there are any
> other users of dsb_vblank_delay().

Yes makes sense, can add a patch at last to clean this up.


>
>> +
>>   	intel_dsb_wait_usec(dsb, usecs);
>>   }
>>   
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 1bb9db06f43d..26c5c32a9a58 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -800,3 +800,20 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>>   	if (crtc_state->vrr.enable)
>>   		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>>   }
>> +
>> +int intel_vrr_vmin_safe_window_start(const struct intel_crtc_state *crtc_state)
> I only wanted you to rename the safe_window_end(). The safe window
> start doesn't change for vmin/vmax/etc. So should drop the "vmin"
> again from this one.

Oh alright, will drop vmin here.

Regards,

Ankit

>
> With that
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>> +{
>> +	struct intel_display *display = to_intel_display(crtc_state);
>> +
>> +	if (DISPLAY_VER(display) >= 30)
>> +		return crtc_state->hw.adjusted_mode.crtc_vdisplay -
>> +		       crtc_state->set_context_latency;
>> +	else
>> +		return crtc_state->hw.adjusted_mode.crtc_vdisplay;
>> +}
>> +
>> +int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state)
>> +{
>> +	return intel_vrr_vmin_vblank_start(crtc_state) -
>> +	       crtc_state->set_context_latency;
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
>> index 38bf9996b883..239e4f94725c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
>> @@ -41,5 +41,7 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
>>   void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
>>   void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
>>   bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
>> +int intel_vrr_vmin_safe_window_start(const struct intel_crtc_state *crtc_state);
>> +int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);
>>   
>>   #endif /* __INTEL_VRR_H__ */
>> -- 
>> 2.45.2

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [PATCH 7/9] drm/i915/reg_defs: Add REG_FIELD_MAX wrapper for FIELD_MAX()
  2025-09-24 10:51 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
                   ` (5 preceding siblings ...)
  2025-09-24 10:51 ` [PATCH 6/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks Ankit Nautiyal
@ 2025-09-24 10:51 ` Ankit Nautiyal
  2025-09-24 12:24   ` Andi Shyti
  2025-09-24 10:51 ` [PATCH 8/9] drm/i915/vrr: Clamp guardband as per hardware and timing constraints Ankit Nautiyal
                   ` (5 subsequent siblings)
  12 siblings, 1 reply; 21+ messages in thread
From: Ankit Nautiyal @ 2025-09-24 10:51 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

Introduce REG_FIELD_MAX macro as local wrapper around FIELD_MAX() to return
the maximum value representable by a bit mask. The value is cast to u32
for consistency with other REG_* macros and assumes the bitfield fits
within 32 bits.

v2: Use __mask as macro argument aligning with other macros. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg_defs.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index bfe98cb9a038..e81fac8ab51b 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -174,6 +174,16 @@
  */
 #define REG_FIELD_GET8(__mask, __val)   ((u8)FIELD_GET(__mask, __val))
 
+/**
+ * REG_FIELD_MAX() - produce the maximum value representable by a field
+ * @__mask: shifted mask defining the field's length and position
+ *
+ * Local wrapper for FIELD_MAX() to return the maximum bit value that can
+ * be held in the field specified by @_mask, cast to u32 for consistency
+ * with other macros.
+ */
+#define REG_FIELD_MAX(__mask)	((u32)FIELD_MAX(__mask))
+
 typedef struct {
 	u32 reg;
 } i915_reg_t;
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [PATCH 7/9] drm/i915/reg_defs: Add REG_FIELD_MAX wrapper for FIELD_MAX()
  2025-09-24 10:51 ` [PATCH 7/9] drm/i915/reg_defs: Add REG_FIELD_MAX wrapper for FIELD_MAX() Ankit Nautiyal
@ 2025-09-24 12:24   ` Andi Shyti
  2025-09-24 14:17     ` Nautiyal, Ankit K
  0 siblings, 1 reply; 21+ messages in thread
From: Andi Shyti @ 2025-09-24 12:24 UTC (permalink / raw)
  To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe, ville.syrjala

Hi Ankit,

> +/**
> + * REG_FIELD_MAX() - produce the maximum value representable by a field
> + * @__mask: shifted mask defining the field's length and position
> + *
> + * Local wrapper for FIELD_MAX() to return the maximum bit value that can
> + * be held in the field specified by @_mask, cast to u32 for consistency
> + * with other macros.
> + */
> +#define REG_FIELD_MAX(__mask)	((u32)FIELD_MAX(__mask))

I'm not a big fan of these generic definitions inside i915. These
should all go to bitfield.h. But this is how it's done here. For
now:

Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>

Thanks,
Andi

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH 7/9] drm/i915/reg_defs: Add REG_FIELD_MAX wrapper for FIELD_MAX()
  2025-09-24 12:24   ` Andi Shyti
@ 2025-09-24 14:17     ` Nautiyal, Ankit K
  0 siblings, 0 replies; 21+ messages in thread
From: Nautiyal, Ankit K @ 2025-09-24 14:17 UTC (permalink / raw)
  To: Andi Shyti; +Cc: intel-gfx, intel-xe, ville.syrjala


On 9/24/2025 5:54 PM, Andi Shyti wrote:
> Hi Ankit,
>
>> +/**
>> + * REG_FIELD_MAX() - produce the maximum value representable by a field
>> + * @__mask: shifted mask defining the field's length and position
>> + *
>> + * Local wrapper for FIELD_MAX() to return the maximum bit value that can
>> + * be held in the field specified by @_mask, cast to u32 for consistency
>> + * with other macros.
>> + */
>> +#define REG_FIELD_MAX(__mask)	((u32)FIELD_MAX(__mask))
> I'm not a big fan of these generic definitions inside i915. These
> should all go to bitfield.h. But this is how it's done here. For
> now:
>
> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>

Thanks Andi,  I added REG_FIELD_MAX() for consistency with other 
REG_FIELD_* macros already used in i915.

Since FIELD_MAX is already in bitfield.h, but perhaps it would be worth 
considering typed variants like FIELD_MAX_U32() or FIELD_MAX_U64() for 
broader use.

Thanks again for the review.


Regards,

Ankit






>
> Thanks,
> Andi

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [PATCH 8/9] drm/i915/vrr: Clamp guardband as per hardware and timing constraints
  2025-09-24 10:51 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
                   ` (6 preceding siblings ...)
  2025-09-24 10:51 ` [PATCH 7/9] drm/i915/reg_defs: Add REG_FIELD_MAX wrapper for FIELD_MAX() Ankit Nautiyal
@ 2025-09-24 10:51 ` Ankit Nautiyal
  2025-09-24 12:04   ` Ville Syrjälä
  2025-09-24 10:51 ` [PATCH 9/9] drm/i915/display: Drop intel_vrr_vblank_delay and use set_context_latency Ankit Nautiyal
                   ` (4 subsequent siblings)
  12 siblings, 1 reply; 21+ messages in thread
From: Ankit Nautiyal @ 2025-09-24 10:51 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

The maximum guardband value is constrained by two factors:
- The actual vblank length minus set context latency (SCL)
- The hardware register field width:
  - 8 bits for ICL/TGL (VRR_CTL_PIPELINE_FULL_MASK -> max 255)
  - 16 bits for ADL+ (XELPD_VRR_CTL_VRR_GUARDBAND_MASK -> max 65535)

Remove the #FIXME and clamp the guardband to the maximum allowed value.

v2:
- Use REG_FIELD_MAX(). (Ville)
- Separate out functions for intel_vrr_max_guardband(),
  intel_vrr_max_vblank_guardband(). (Ville)

v3:
- Fix Typo: Add the missing adjusted_mode->crtc_vdisplay in guardband
  computation. (Ville)
- Refactor intel_vrr_max_hw_guardband() and use else for consistency.
  (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 49 ++++++++++++++++++------
 1 file changed, 37 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 26c5c32a9a58..e29b4050a9df 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -409,6 +409,40 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	}
 }
 
+static int
+intel_vrr_max_hw_guardband(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	int max_pipeline_full = REG_FIELD_MAX(VRR_CTL_PIPELINE_FULL_MASK);
+	int max_guardband;
+
+	if (DISPLAY_VER(display) >= 13)
+		max_guardband = REG_FIELD_MAX(XELPD_VRR_CTL_VRR_GUARDBAND_MASK);
+	else
+		max_guardband = intel_vrr_pipeline_full_to_guardband(crtc_state,
+								     max_pipeline_full);
+	return max_guardband;
+}
+
+static int
+intel_vrr_max_vblank_guardband(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+	return crtc_state->vrr.vmin -
+	       adjusted_mode->crtc_vdisplay -
+	       crtc_state->set_context_latency -
+	       intel_vrr_extra_vblank_delay(display);
+}
+
+static int
+intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
+{
+	return min(intel_vrr_max_hw_guardband(crtc_state),
+		   intel_vrr_max_vblank_guardband(crtc_state));
+}
+
 void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -417,22 +451,13 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
-	crtc_state->vrr.guardband =
-		crtc_state->vrr.vmin -
-		adjusted_mode->crtc_vdisplay -
-		crtc_state->set_context_latency -
-		intel_vrr_extra_vblank_delay(display);
-
-	if (DISPLAY_VER(display) < 13) {
-		/* FIXME handle the limit in a proper way */
-		crtc_state->vrr.guardband =
-			min(crtc_state->vrr.guardband,
-			    intel_vrr_pipeline_full_to_guardband(crtc_state, 255));
+	crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
+					intel_vrr_max_guardband(crtc_state));
 
+	if (DISPLAY_VER(display) < 13)
 		crtc_state->vrr.pipeline_full =
 			intel_vrr_guardband_to_pipeline_full(crtc_state,
 							     crtc_state->vrr.guardband);
-	}
 }
 
 static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [PATCH 8/9] drm/i915/vrr: Clamp guardband as per hardware and timing constraints
  2025-09-24 10:51 ` [PATCH 8/9] drm/i915/vrr: Clamp guardband as per hardware and timing constraints Ankit Nautiyal
@ 2025-09-24 12:04   ` Ville Syrjälä
  2025-09-24 14:19     ` Nautiyal, Ankit K
  0 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjälä @ 2025-09-24 12:04 UTC (permalink / raw)
  To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe

On Wed, Sep 24, 2025 at 04:21:28PM +0530, Ankit Nautiyal wrote:
> The maximum guardband value is constrained by two factors:
> - The actual vblank length minus set context latency (SCL)
> - The hardware register field width:
>   - 8 bits for ICL/TGL (VRR_CTL_PIPELINE_FULL_MASK -> max 255)
>   - 16 bits for ADL+ (XELPD_VRR_CTL_VRR_GUARDBAND_MASK -> max 65535)
> 
> Remove the #FIXME and clamp the guardband to the maximum allowed value.
> 
> v2:
> - Use REG_FIELD_MAX(). (Ville)
> - Separate out functions for intel_vrr_max_guardband(),
>   intel_vrr_max_vblank_guardband(). (Ville)
> 
> v3:
> - Fix Typo: Add the missing adjusted_mode->crtc_vdisplay in guardband
>   computation. (Ville)
> - Refactor intel_vrr_max_hw_guardband() and use else for consistency.
>   (Ville)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 49 ++++++++++++++++++------
>  1 file changed, 37 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 26c5c32a9a58..e29b4050a9df 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -409,6 +409,40 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>  	}
>  }
>  
> +static int
> +intel_vrr_max_hw_guardband(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	int max_pipeline_full = REG_FIELD_MAX(VRR_CTL_PIPELINE_FULL_MASK);
> +	int max_guardband;
> +
> +	if (DISPLAY_VER(display) >= 13)
> +		max_guardband = REG_FIELD_MAX(XELPD_VRR_CTL_VRR_GUARDBAND_MASK);
> +	else
> +		max_guardband = intel_vrr_pipeline_full_to_guardband(crtc_state,
> +								     max_pipeline_full);
> +	return max_guardband;

The 'max_guardband' variable looks useless here, could just return
directly from both sides of the if-else.

'max_pipeline_full' is perhaps redundant too, but I suppose the
line would get pretty long without it. So maybe it makes sense to keep
it.

> +}
> +
> +static int
> +intel_vrr_max_vblank_guardband(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +
> +	return crtc_state->vrr.vmin -
> +	       adjusted_mode->crtc_vdisplay -
> +	       crtc_state->set_context_latency -
> +	       intel_vrr_extra_vblank_delay(display);
> +}
> +
> +static int
> +intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
> +{
> +	return min(intel_vrr_max_hw_guardband(crtc_state),
> +		   intel_vrr_max_vblank_guardband(crtc_state));
> +}
> +
>  void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> @@ -417,22 +451,13 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
>  	if (!intel_vrr_possible(crtc_state))
>  		return;
>  
> -	crtc_state->vrr.guardband =
> -		crtc_state->vrr.vmin -
> -		adjusted_mode->crtc_vdisplay -
> -		crtc_state->set_context_latency -
> -		intel_vrr_extra_vblank_delay(display);
> -
> -	if (DISPLAY_VER(display) < 13) {
> -		/* FIXME handle the limit in a proper way */
> -		crtc_state->vrr.guardband =
> -			min(crtc_state->vrr.guardband,
> -			    intel_vrr_pipeline_full_to_guardband(crtc_state, 255));
> +	crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
> +					intel_vrr_max_guardband(crtc_state));
>  
> +	if (DISPLAY_VER(display) < 13)
>  		crtc_state->vrr.pipeline_full =
>  			intel_vrr_guardband_to_pipeline_full(crtc_state,
>  							     crtc_state->vrr.guardband);
> -	}
>  }
>  
>  static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH 8/9] drm/i915/vrr: Clamp guardband as per hardware and timing constraints
  2025-09-24 12:04   ` Ville Syrjälä
@ 2025-09-24 14:19     ` Nautiyal, Ankit K
  0 siblings, 0 replies; 21+ messages in thread
From: Nautiyal, Ankit K @ 2025-09-24 14:19 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx, intel-xe


On 9/24/2025 5:34 PM, Ville Syrjälä wrote:
> On Wed, Sep 24, 2025 at 04:21:28PM +0530, Ankit Nautiyal wrote:
>> The maximum guardband value is constrained by two factors:
>> - The actual vblank length minus set context latency (SCL)
>> - The hardware register field width:
>>    - 8 bits for ICL/TGL (VRR_CTL_PIPELINE_FULL_MASK -> max 255)
>>    - 16 bits for ADL+ (XELPD_VRR_CTL_VRR_GUARDBAND_MASK -> max 65535)
>>
>> Remove the #FIXME and clamp the guardband to the maximum allowed value.
>>
>> v2:
>> - Use REG_FIELD_MAX(). (Ville)
>> - Separate out functions for intel_vrr_max_guardband(),
>>    intel_vrr_max_vblank_guardband(). (Ville)
>>
>> v3:
>> - Fix Typo: Add the missing adjusted_mode->crtc_vdisplay in guardband
>>    computation. (Ville)
>> - Refactor intel_vrr_max_hw_guardband() and use else for consistency.
>>    (Ville)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_vrr.c | 49 ++++++++++++++++++------
>>   1 file changed, 37 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 26c5c32a9a58..e29b4050a9df 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -409,6 +409,40 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>>   	}
>>   }
>>   
>> +static int
>> +intel_vrr_max_hw_guardband(const struct intel_crtc_state *crtc_state)
>> +{
>> +	struct intel_display *display = to_intel_display(crtc_state);
>> +	int max_pipeline_full = REG_FIELD_MAX(VRR_CTL_PIPELINE_FULL_MASK);
>> +	int max_guardband;
>> +
>> +	if (DISPLAY_VER(display) >= 13)
>> +		max_guardband = REG_FIELD_MAX(XELPD_VRR_CTL_VRR_GUARDBAND_MASK);
>> +	else
>> +		max_guardband = intel_vrr_pipeline_full_to_guardband(crtc_state,
>> +								     max_pipeline_full);
>> +	return max_guardband;
> The 'max_guardband' variable looks useless here, could just return
> directly from both sides of the if-else.
>
> 'max_pipeline_full' is perhaps redundant too, but I suppose the
> line would get pretty long without it. So maybe it makes sense to keep
> it.


Yeah the line was getting pretty long, so added max_pipeline_full.

Can drop max_guardband though.

Regards,

Ankit

>
>> +}
>> +
>> +static int
>> +intel_vrr_max_vblank_guardband(const struct intel_crtc_state *crtc_state)
>> +{
>> +	struct intel_display *display = to_intel_display(crtc_state);
>> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>> +
>> +	return crtc_state->vrr.vmin -
>> +	       adjusted_mode->crtc_vdisplay -
>> +	       crtc_state->set_context_latency -
>> +	       intel_vrr_extra_vblank_delay(display);
>> +}
>> +
>> +static int
>> +intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
>> +{
>> +	return min(intel_vrr_max_hw_guardband(crtc_state),
>> +		   intel_vrr_max_vblank_guardband(crtc_state));
>> +}
>> +
>>   void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
>>   {
>>   	struct intel_display *display = to_intel_display(crtc_state);
>> @@ -417,22 +451,13 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
>>   	if (!intel_vrr_possible(crtc_state))
>>   		return;
>>   
>> -	crtc_state->vrr.guardband =
>> -		crtc_state->vrr.vmin -
>> -		adjusted_mode->crtc_vdisplay -
>> -		crtc_state->set_context_latency -
>> -		intel_vrr_extra_vblank_delay(display);
>> -
>> -	if (DISPLAY_VER(display) < 13) {
>> -		/* FIXME handle the limit in a proper way */
>> -		crtc_state->vrr.guardband =
>> -			min(crtc_state->vrr.guardband,
>> -			    intel_vrr_pipeline_full_to_guardband(crtc_state, 255));
>> +	crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
>> +					intel_vrr_max_guardband(crtc_state));
>>   
>> +	if (DISPLAY_VER(display) < 13)
>>   		crtc_state->vrr.pipeline_full =
>>   			intel_vrr_guardband_to_pipeline_full(crtc_state,
>>   							     crtc_state->vrr.guardband);
>> -	}
>>   }
>>   
>>   static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
>> -- 
>> 2.45.2

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [PATCH 9/9] drm/i915/display: Drop intel_vrr_vblank_delay and use set_context_latency
  2025-09-24 10:51 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
                   ` (7 preceding siblings ...)
  2025-09-24 10:51 ` [PATCH 8/9] drm/i915/vrr: Clamp guardband as per hardware and timing constraints Ankit Nautiyal
@ 2025-09-24 10:51 ` Ankit Nautiyal
  2025-09-24 12:13   ` Ville Syrjälä
  2025-09-24 11:35 ` ✓ CI.KUnit: success for Introduce set_context_latency and refactor VRR/DSB timing logic (rev3) Patchwork
                   ` (3 subsequent siblings)
  12 siblings, 1 reply; 21+ messages in thread
From: Ankit Nautiyal @ 2025-09-24 10:51 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

The helper intel_vrr_vblank_delay() was used to keep track of the SCL
lines + the extra vblank delay required for ICL/TGL.
This was used to wait for sufficient lines for:
-push send bit to clear for VRR case
-evasion to delay the commit.

For first case we are using safe window scanline wait and with that we
just need to wait for SCL lines, we do not need to wait for the extra
vblank delay required for ICL/TGL. For the second case, we actually
do not need to wait for extra lines before the undelayed vblank, if we
are already in the safe window.

To sum up, SCL lines is sufficient for both cases.

So drop the helper intel_vrr_vblank_delay and just use
crtc_state->set_context_latency instead.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c    | 4 ++--
 drivers/gpu/drm/i915/display/intel_vblank.c | 2 +-
 drivers/gpu/drm/i915/display/intel_vrr.c    | 8 --------
 drivers/gpu/drm/i915/display/intel_vrr.h    | 1 -
 4 files changed, 3 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 3cb4c9be146f..c183209d7663 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -128,7 +128,7 @@ static int dsb_vblank_delay(struct intel_atomic_state *state,
 		 * scanline until the delayed vblank occurs after
 		 * TRANS_PUSH has been written.
 		 */
-		return intel_vrr_vblank_delay(crtc_state) + 1;
+		return crtc_state->set_context_latency + 1;
 	else
 		return intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
 }
@@ -723,7 +723,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
 		intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
 
 	if (pre_commit_is_vrr_active(state, crtc)) {
-		int vblank_delay = intel_vrr_vblank_delay(crtc_state);
+		int vblank_delay = crtc_state->set_context_latency;
 
 		end = intel_vrr_vmin_vblank_start(crtc_state);
 		start = end - vblank_delay - latency;
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index c15234c1d96e..0b7fcc05e64c 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -681,7 +681,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 		else
 			evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
 
-		vblank_delay = intel_vrr_vblank_delay(crtc_state);
+		vblank_delay = crtc_state->set_context_latency;
 	} else {
 		evade->vblank_start = intel_mode_vblank_start(adjusted_mode);
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index e29b4050a9df..6d3f9e3de1f1 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -92,14 +92,6 @@ static int intel_vrr_extra_vblank_delay(struct intel_display *display)
 	return DISPLAY_VER(display) < 13 ? 1 : 0;
 }
 
-int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_display *display = to_intel_display(crtc_state);
-
-	return crtc_state->set_context_latency +
-		intel_vrr_extra_vblank_delay(display);
-}
-
 static int intel_vrr_vmin_flipline_offset(struct intel_display *display)
 {
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 239e4f94725c..cfd027118b60 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -35,7 +35,6 @@ int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state);
-int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state);
 bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state);
 void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [PATCH 9/9] drm/i915/display: Drop intel_vrr_vblank_delay and use set_context_latency
  2025-09-24 10:51 ` [PATCH 9/9] drm/i915/display: Drop intel_vrr_vblank_delay and use set_context_latency Ankit Nautiyal
@ 2025-09-24 12:13   ` Ville Syrjälä
  0 siblings, 0 replies; 21+ messages in thread
From: Ville Syrjälä @ 2025-09-24 12:13 UTC (permalink / raw)
  To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe

On Wed, Sep 24, 2025 at 04:21:29PM +0530, Ankit Nautiyal wrote:
> The helper intel_vrr_vblank_delay() was used to keep track of the SCL
> lines + the extra vblank delay required for ICL/TGL.
> This was used to wait for sufficient lines for:
> -push send bit to clear for VRR case
> -evasion to delay the commit.
> 
> For first case we are using safe window scanline wait and with that we
> just need to wait for SCL lines, we do not need to wait for the extra
> vblank delay required for ICL/TGL. For the second case, we actually
> do not need to wait for extra lines before the undelayed vblank, if we
> are already in the safe window.
> 
> To sum up, SCL lines is sufficient for both cases.
> 
> So drop the helper intel_vrr_vblank_delay and just use
> crtc_state->set_context_latency instead.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dsb.c    | 4 ++--
>  drivers/gpu/drm/i915/display/intel_vblank.c | 2 +-
>  drivers/gpu/drm/i915/display/intel_vrr.c    | 8 --------
>  drivers/gpu/drm/i915/display/intel_vrr.h    | 1 -
>  4 files changed, 3 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 3cb4c9be146f..c183209d7663 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -128,7 +128,7 @@ static int dsb_vblank_delay(struct intel_atomic_state *state,
>  		 * scanline until the delayed vblank occurs after
>  		 * TRANS_PUSH has been written.
>  		 */
> -		return intel_vrr_vblank_delay(crtc_state) + 1;
> +		return crtc_state->set_context_latency + 1;
>  	else
>  		return intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
>  }
> @@ -723,7 +723,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
>  		intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
>  
>  	if (pre_commit_is_vrr_active(state, crtc)) {
> -		int vblank_delay = intel_vrr_vblank_delay(crtc_state);
> +		int vblank_delay = crtc_state->set_context_latency;
>  
>  		end = intel_vrr_vmin_vblank_start(crtc_state);
>  		start = end - vblank_delay - latency;
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> index c15234c1d96e..0b7fcc05e64c 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -681,7 +681,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
>  		else
>  			evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
>  
> -		vblank_delay = intel_vrr_vblank_delay(crtc_state);
> +		vblank_delay = crtc_state->set_context_latency;
>  	} else {
>  		evade->vblank_start = intel_mode_vblank_start(adjusted_mode);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index e29b4050a9df..6d3f9e3de1f1 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -92,14 +92,6 @@ static int intel_vrr_extra_vblank_delay(struct intel_display *display)
>  	return DISPLAY_VER(display) < 13 ? 1 : 0;
>  }
>  
> -int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_display *display = to_intel_display(crtc_state);
> -
> -	return crtc_state->set_context_latency +
> -		intel_vrr_extra_vblank_delay(display);
> -}
> -
>  static int intel_vrr_vmin_flipline_offset(struct intel_display *display)
>  {
>  	/*
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 239e4f94725c..cfd027118b60 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -35,7 +35,6 @@ int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state);
>  int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state);
>  int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state);
>  int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state);
> -int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state);
>  bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state);
>  void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
>  void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 21+ messages in thread

* ✓ CI.KUnit: success for Introduce set_context_latency and refactor VRR/DSB timing logic (rev3)
  2025-09-24 10:51 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
                   ` (8 preceding siblings ...)
  2025-09-24 10:51 ` [PATCH 9/9] drm/i915/display: Drop intel_vrr_vblank_delay and use set_context_latency Ankit Nautiyal
@ 2025-09-24 11:35 ` Patchwork
  2025-09-24 11:50 ` ✗ CI.checksparse: warning " Patchwork
                   ` (2 subsequent siblings)
  12 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2025-09-24 11:35 UTC (permalink / raw)
  To: Nautiyal, Ankit K; +Cc: intel-xe

== Series Details ==

Series: Introduce set_context_latency and refactor VRR/DSB timing logic (rev3)
URL   : https://patchwork.freedesktop.org/series/154809/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[11:34:24] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:34:28] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:34:58] Starting KUnit Kernel (1/1)...
[11:34:58] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:34:58] ================== guc_buf (11 subtests) ===================
[11:34:58] [PASSED] test_smallest
[11:34:58] [PASSED] test_largest
[11:34:58] [PASSED] test_granular
[11:34:58] [PASSED] test_unique
[11:34:58] [PASSED] test_overlap
[11:34:58] [PASSED] test_reusable
[11:34:58] [PASSED] test_too_big
[11:34:58] [PASSED] test_flush
[11:34:58] [PASSED] test_lookup
[11:34:58] [PASSED] test_data
[11:34:58] [PASSED] test_class
[11:34:58] ===================== [PASSED] guc_buf =====================
[11:34:58] =================== guc_dbm (7 subtests) ===================
[11:34:58] [PASSED] test_empty
[11:34:58] [PASSED] test_default
[11:34:58] ======================== test_size  ========================
[11:34:58] [PASSED] 4
[11:34:58] [PASSED] 8
[11:34:58] [PASSED] 32
[11:34:58] [PASSED] 256
[11:34:58] ==================== [PASSED] test_size ====================
[11:34:58] ======================= test_reuse  ========================
[11:34:58] [PASSED] 4
[11:34:58] [PASSED] 8
[11:34:58] [PASSED] 32
[11:34:58] [PASSED] 256
[11:34:58] =================== [PASSED] test_reuse ====================
[11:34:58] =================== test_range_overlap  ====================
[11:34:58] [PASSED] 4
[11:34:58] [PASSED] 8
[11:34:58] [PASSED] 32
[11:34:58] [PASSED] 256
[11:34:58] =============== [PASSED] test_range_overlap ================
[11:34:58] =================== test_range_compact  ====================
[11:34:58] [PASSED] 4
[11:34:58] [PASSED] 8
[11:34:58] [PASSED] 32
[11:34:58] [PASSED] 256
[11:34:58] =============== [PASSED] test_range_compact ================
[11:34:58] ==================== test_range_spare  =====================
[11:34:58] [PASSED] 4
[11:34:58] [PASSED] 8
[11:34:58] [PASSED] 32
[11:34:58] [PASSED] 256
[11:34:58] ================ [PASSED] test_range_spare =================
[11:34:58] ===================== [PASSED] guc_dbm =====================
[11:34:58] =================== guc_idm (6 subtests) ===================
[11:34:58] [PASSED] bad_init
[11:34:58] [PASSED] no_init
[11:34:58] [PASSED] init_fini
[11:34:58] [PASSED] check_used
[11:34:58] [PASSED] check_quota
[11:34:58] [PASSED] check_all
[11:34:58] ===================== [PASSED] guc_idm =====================
[11:34:58] ================== no_relay (3 subtests) ===================
[11:34:58] [PASSED] xe_drops_guc2pf_if_not_ready
[11:34:58] [PASSED] xe_drops_guc2vf_if_not_ready
[11:34:58] [PASSED] xe_rejects_send_if_not_ready
[11:34:58] ==================== [PASSED] no_relay =====================
[11:34:58] ================== pf_relay (14 subtests) ==================
[11:34:58] [PASSED] pf_rejects_guc2pf_too_short
[11:34:58] [PASSED] pf_rejects_guc2pf_too_long
[11:34:58] [PASSED] pf_rejects_guc2pf_no_payload
[11:34:58] [PASSED] pf_fails_no_payload
[11:34:58] [PASSED] pf_fails_bad_origin
[11:34:58] [PASSED] pf_fails_bad_type
[11:34:58] [PASSED] pf_txn_reports_error
[11:34:58] [PASSED] pf_txn_sends_pf2guc
[11:34:58] [PASSED] pf_sends_pf2guc
[11:34:58] [SKIPPED] pf_loopback_nop
[11:34:58] [SKIPPED] pf_loopback_echo
[11:34:58] [SKIPPED] pf_loopback_fail
[11:34:58] [SKIPPED] pf_loopback_busy
[11:34:58] [SKIPPED] pf_loopback_retry
[11:34:58] ==================== [PASSED] pf_relay =====================
[11:34:58] ================== vf_relay (3 subtests) ===================
[11:34:58] [PASSED] vf_rejects_guc2vf_too_short
[11:34:58] [PASSED] vf_rejects_guc2vf_too_long
[11:34:58] [PASSED] vf_rejects_guc2vf_no_payload
[11:34:58] ==================== [PASSED] vf_relay =====================
[11:34:58] ===================== lmtt (1 subtest) =====================
[11:34:58] ======================== test_ops  =========================
[11:34:58] [PASSED] 2-level
[11:34:58] [PASSED] multi-level
[11:34:58] ==================== [PASSED] test_ops =====================
[11:34:58] ====================== [PASSED] lmtt =======================
[11:34:58] ================= pf_service (11 subtests) =================
[11:34:58] [PASSED] pf_negotiate_any
[11:34:58] [PASSED] pf_negotiate_base_match
[11:34:58] [PASSED] pf_negotiate_base_newer
[11:34:58] [PASSED] pf_negotiate_base_next
[11:34:58] [SKIPPED] pf_negotiate_base_older
[11:34:58] [PASSED] pf_negotiate_base_prev
[11:34:58] [PASSED] pf_negotiate_latest_match
[11:34:58] [PASSED] pf_negotiate_latest_newer
[11:34:58] [PASSED] pf_negotiate_latest_next
[11:34:58] [SKIPPED] pf_negotiate_latest_older
[11:34:58] [SKIPPED] pf_negotiate_latest_prev
[11:34:58] =================== [PASSED] pf_service ====================
[11:34:58] ================= xe_guc_g2g (2 subtests) ==================
[11:34:58] ============== xe_live_guc_g2g_kunit_default  ==============
[11:34:58] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[11:34:58] ============== xe_live_guc_g2g_kunit_allmem  ===============
[11:34:58] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[11:34:58] =================== [SKIPPED] xe_guc_g2g ===================
[11:34:58] =================== xe_mocs (2 subtests) ===================
[11:34:58] ================ xe_live_mocs_kernel_kunit  ================
[11:34:58] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[11:34:58] ================ xe_live_mocs_reset_kunit  =================
[11:34:58] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[11:34:58] ==================== [SKIPPED] xe_mocs =====================
[11:34:58] ================= xe_migrate (2 subtests) ==================
[11:34:58] ================= xe_migrate_sanity_kunit  =================
[11:34:58] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[11:34:58] ================== xe_validate_ccs_kunit  ==================
[11:34:58] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[11:34:58] =================== [SKIPPED] xe_migrate ===================
[11:34:58] ================== xe_dma_buf (1 subtest) ==================
[11:34:58] ==================== xe_dma_buf_kunit  =====================
[11:34:58] ================ [SKIPPED] xe_dma_buf_kunit ================
[11:34:58] =================== [SKIPPED] xe_dma_buf ===================
[11:34:58] ================= xe_bo_shrink (1 subtest) =================
[11:34:58] =================== xe_bo_shrink_kunit  ====================
[11:34:58] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[11:34:58] ================== [SKIPPED] xe_bo_shrink ==================
[11:34:58] ==================== xe_bo (2 subtests) ====================
[11:34:58] ================== xe_ccs_migrate_kunit  ===================
[11:34:58] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[11:34:58] ==================== xe_bo_evict_kunit  ====================
[11:34:58] =============== [SKIPPED] xe_bo_evict_kunit ================
[11:34:58] ===================== [SKIPPED] xe_bo ======================
[11:34:58] ==================== args (11 subtests) ====================
[11:34:58] [PASSED] count_args_test
[11:34:58] [PASSED] call_args_example
[11:34:58] [PASSED] call_args_test
[11:34:58] [PASSED] drop_first_arg_example
[11:34:58] [PASSED] drop_first_arg_test
[11:34:58] [PASSED] first_arg_example
[11:34:58] [PASSED] first_arg_test
[11:34:58] [PASSED] last_arg_example
[11:34:58] [PASSED] last_arg_test
[11:34:58] [PASSED] pick_arg_example
[11:34:58] [PASSED] sep_comma_example
[11:34:58] ====================== [PASSED] args =======================
[11:34:58] =================== xe_pci (3 subtests) ====================
[11:34:58] ==================== check_graphics_ip  ====================
[11:34:58] [PASSED] 12.00 Xe_LP
[11:34:58] [PASSED] 12.10 Xe_LP+
[11:34:58] [PASSED] 12.55 Xe_HPG
[11:34:58] [PASSED] 12.60 Xe_HPC
[11:34:58] [PASSED] 12.70 Xe_LPG
[11:34:58] [PASSED] 12.71 Xe_LPG
[11:34:58] [PASSED] 12.74 Xe_LPG+
[11:34:58] [PASSED] 20.01 Xe2_HPG
[11:34:58] [PASSED] 20.02 Xe2_HPG
[11:34:58] [PASSED] 20.04 Xe2_LPG
[11:34:58] [PASSED] 30.00 Xe3_LPG
[11:34:58] [PASSED] 30.01 Xe3_LPG
[11:34:58] [PASSED] 30.03 Xe3_LPG
[11:34:58] ================ [PASSED] check_graphics_ip ================
[11:34:58] ===================== check_media_ip  ======================
[11:34:58] [PASSED] 12.00 Xe_M
[11:34:58] [PASSED] 12.55 Xe_HPM
[11:34:58] [PASSED] 13.00 Xe_LPM+
[11:34:58] [PASSED] 13.01 Xe2_HPM
[11:34:58] [PASSED] 20.00 Xe2_LPM
[11:34:58] [PASSED] 30.00 Xe3_LPM
[11:34:58] [PASSED] 30.02 Xe3_LPM
[11:34:58] ================= [PASSED] check_media_ip ==================
[11:34:58] ================= check_platform_gt_count  =================
[11:34:58] [PASSED] 0x9A60 (TIGERLAKE)
[11:34:58] [PASSED] 0x9A68 (TIGERLAKE)
[11:34:58] [PASSED] 0x9A70 (TIGERLAKE)
[11:34:58] [PASSED] 0x9A40 (TIGERLAKE)
[11:34:58] [PASSED] 0x9A49 (TIGERLAKE)
[11:34:58] [PASSED] 0x9A59 (TIGERLAKE)
[11:34:58] [PASSED] 0x9A78 (TIGERLAKE)
[11:34:58] [PASSED] 0x9AC0 (TIGERLAKE)
[11:34:58] [PASSED] 0x9AC9 (TIGERLAKE)
[11:34:58] [PASSED] 0x9AD9 (TIGERLAKE)
[11:34:58] [PASSED] 0x9AF8 (TIGERLAKE)
[11:34:58] [PASSED] 0x4C80 (ROCKETLAKE)
[11:34:58] [PASSED] 0x4C8A (ROCKETLAKE)
[11:34:58] [PASSED] 0x4C8B (ROCKETLAKE)
[11:34:58] [PASSED] 0x4C8C (ROCKETLAKE)
[11:34:58] [PASSED] 0x4C90 (ROCKETLAKE)
[11:34:58] [PASSED] 0x4C9A (ROCKETLAKE)
[11:34:58] [PASSED] 0x4680 (ALDERLAKE_S)
[11:34:58] [PASSED] 0x4682 (ALDERLAKE_S)
[11:34:58] [PASSED] 0x4688 (ALDERLAKE_S)
[11:34:58] [PASSED] 0x468A (ALDERLAKE_S)
[11:34:58] [PASSED] 0x468B (ALDERLAKE_S)
[11:34:58] [PASSED] 0x4690 (ALDERLAKE_S)
[11:34:58] [PASSED] 0x4692 (ALDERLAKE_S)
[11:34:58] [PASSED] 0x4693 (ALDERLAKE_S)
[11:34:58] [PASSED] 0x46A0 (ALDERLAKE_P)
[11:34:58] [PASSED] 0x46A1 (ALDERLAKE_P)
[11:34:58] [PASSED] 0x46A2 (ALDERLAKE_P)
[11:34:58] [PASSED] 0x46A3 (ALDERLAKE_P)
[11:34:58] [PASSED] 0x46A6 (ALDERLAKE_P)
[11:34:58] [PASSED] 0x46A8 (ALDERLAKE_P)
[11:34:58] [PASSED] 0x46AA (ALDERLAKE_P)
[11:34:58] [PASSED] 0x462A (ALDERLAKE_P)
[11:34:58] [PASSED] 0x4626 (ALDERLAKE_P)
[11:34:58] [PASSED] 0x4628 (ALDERLAKE_P)
[11:34:58] [PASSED] 0x46B0 (ALDERLAKE_P)
[11:34:58] [PASSED] 0x46B1 (ALDERLAKE_P)
[11:34:58] [PASSED] 0x46B2 (ALDERLAKE_P)
[11:34:58] [PASSED] 0x46B3 (ALDERLAKE_P)
[11:34:58] [PASSED] 0x46C0 (ALDERLAKE_P)
[11:34:58] [PASSED] 0x46C1 (ALDERLAKE_P)
[11:34:58] [PASSED] 0x46C2 (ALDERLAKE_P)
[11:34:58] [PASSED] 0x46C3 (ALDERLAKE_P)
[11:34:58] [PASSED] 0x46D0 (ALDERLAKE_N)
[11:34:58] [PASSED] 0x46D1 (ALDERLAKE_N)
[11:34:58] [PASSED] 0x46D2 (ALDERLAKE_N)
[11:34:58] [PASSED] 0x46D3 (ALDERLAKE_N)
[11:34:58] [PASSED] 0x46D4 (ALDERLAKE_N)
[11:34:58] [PASSED] 0xA721 (ALDERLAKE_P)
[11:34:58] [PASSED] 0xA7A1 (ALDERLAKE_P)
[11:34:58] [PASSED] 0xA7A9 (ALDERLAKE_P)
[11:34:58] [PASSED] 0xA7AC (ALDERLAKE_P)
[11:34:58] [PASSED] 0xA7AD (ALDERLAKE_P)
[11:34:58] [PASSED] 0xA720 (ALDERLAKE_P)
[11:34:58] [PASSED] 0xA7A0 (ALDERLAKE_P)
[11:34:58] [PASSED] 0xA7A8 (ALDERLAKE_P)
[11:34:58] [PASSED] 0xA7AA (ALDERLAKE_P)
[11:34:58] [PASSED] 0xA7AB (ALDERLAKE_P)
[11:34:58] [PASSED] 0xA780 (ALDERLAKE_S)
[11:34:58] [PASSED] 0xA781 (ALDERLAKE_S)
[11:34:58] [PASSED] 0xA782 (ALDERLAKE_S)
[11:34:58] [PASSED] 0xA783 (ALDERLAKE_S)
[11:34:58] [PASSED] 0xA788 (ALDERLAKE_S)
[11:34:58] [PASSED] 0xA789 (ALDERLAKE_S)
[11:34:58] [PASSED] 0xA78A (ALDERLAKE_S)
[11:34:58] [PASSED] 0xA78B (ALDERLAKE_S)
[11:34:58] [PASSED] 0x4905 (DG1)
[11:34:58] [PASSED] 0x4906 (DG1)
[11:34:58] [PASSED] 0x4907 (DG1)
[11:34:58] [PASSED] 0x4908 (DG1)
[11:34:58] [PASSED] 0x4909 (DG1)
[11:34:58] [PASSED] 0x56C0 (DG2)
[11:34:58] [PASSED] 0x56C2 (DG2)
[11:34:58] [PASSED] 0x56C1 (DG2)
[11:34:58] [PASSED] 0x7D51 (METEORLAKE)
[11:34:58] [PASSED] 0x7DD1 (METEORLAKE)
[11:34:58] [PASSED] 0x7D41 (METEORLAKE)
[11:34:58] [PASSED] 0x7D67 (METEORLAKE)
[11:34:58] [PASSED] 0xB640 (METEORLAKE)
[11:34:58] [PASSED] 0x56A0 (DG2)
[11:34:58] [PASSED] 0x56A1 (DG2)
[11:34:58] [PASSED] 0x56A2 (DG2)
[11:34:58] [PASSED] 0x56BE (DG2)
[11:34:58] [PASSED] 0x56BF (DG2)
[11:34:58] [PASSED] 0x5690 (DG2)
[11:34:58] [PASSED] 0x5691 (DG2)
[11:34:58] [PASSED] 0x5692 (DG2)
[11:34:58] [PASSED] 0x56A5 (DG2)
[11:34:58] [PASSED] 0x56A6 (DG2)
[11:34:58] [PASSED] 0x56B0 (DG2)
[11:34:58] [PASSED] 0x56B1 (DG2)
[11:34:58] [PASSED] 0x56BA (DG2)
[11:34:58] [PASSED] 0x56BB (DG2)
[11:34:58] [PASSED] 0x56BC (DG2)
[11:34:58] [PASSED] 0x56BD (DG2)
[11:34:58] [PASSED] 0x5693 (DG2)
[11:34:58] [PASSED] 0x5694 (DG2)
[11:34:58] [PASSED] 0x5695 (DG2)
[11:34:58] [PASSED] 0x56A3 (DG2)
[11:34:58] [PASSED] 0x56A4 (DG2)
[11:34:58] [PASSED] 0x56B2 (DG2)
[11:34:58] [PASSED] 0x56B3 (DG2)
[11:34:58] [PASSED] 0x5696 (DG2)
[11:34:58] [PASSED] 0x5697 (DG2)
[11:34:58] [PASSED] 0xB69 (PVC)
[11:34:58] [PASSED] 0xB6E (PVC)
[11:34:58] [PASSED] 0xBD4 (PVC)
[11:34:58] [PASSED] 0xBD5 (PVC)
[11:34:58] [PASSED] 0xBD6 (PVC)
[11:34:58] [PASSED] 0xBD7 (PVC)
[11:34:58] [PASSED] 0xBD8 (PVC)
[11:34:58] [PASSED] 0xBD9 (PVC)
[11:34:58] [PASSED] 0xBDA (PVC)
[11:34:58] [PASSED] 0xBDB (PVC)
[11:34:58] [PASSED] 0xBE0 (PVC)
[11:34:58] [PASSED] 0xBE1 (PVC)
[11:34:58] [PASSED] 0xBE5 (PVC)
[11:34:58] [PASSED] 0x7D40 (METEORLAKE)
[11:34:58] [PASSED] 0x7D45 (METEORLAKE)
[11:34:58] [PASSED] 0x7D55 (METEORLAKE)
[11:34:58] [PASSED] 0x7D60 (METEORLAKE)
[11:34:58] [PASSED] 0x7DD5 (METEORLAKE)
[11:34:58] [PASSED] 0x6420 (LUNARLAKE)
[11:34:58] [PASSED] 0x64A0 (LUNARLAKE)
[11:34:58] [PASSED] 0x64B0 (LUNARLAKE)
[11:34:58] [PASSED] 0xE202 (BATTLEMAGE)
[11:34:58] [PASSED] 0xE209 (BATTLEMAGE)
[11:34:58] [PASSED] 0xE20B (BATTLEMAGE)
[11:34:58] [PASSED] 0xE20C (BATTLEMAGE)
[11:34:58] [PASSED] 0xE20D (BATTLEMAGE)
[11:34:58] [PASSED] 0xE210 (BATTLEMAGE)
[11:34:58] [PASSED] 0xE211 (BATTLEMAGE)
[11:34:58] [PASSED] 0xE212 (BATTLEMAGE)
[11:34:58] [PASSED] 0xE216 (BATTLEMAGE)
[11:34:58] [PASSED] 0xE220 (BATTLEMAGE)
[11:34:58] [PASSED] 0xE221 (BATTLEMAGE)
[11:34:58] [PASSED] 0xE222 (BATTLEMAGE)
[11:34:58] [PASSED] 0xE223 (BATTLEMAGE)
[11:34:58] [PASSED] 0xB080 (PANTHERLAKE)
[11:34:58] [PASSED] 0xB081 (PANTHERLAKE)
[11:34:58] [PASSED] 0xB082 (PANTHERLAKE)
[11:34:58] [PASSED] 0xB083 (PANTHERLAKE)
[11:34:58] [PASSED] 0xB084 (PANTHERLAKE)
[11:34:58] [PASSED] 0xB085 (PANTHERLAKE)
[11:34:58] [PASSED] 0xB086 (PANTHERLAKE)
[11:34:58] [PASSED] 0xB087 (PANTHERLAKE)
[11:34:58] [PASSED] 0xB08F (PANTHERLAKE)
[11:34:58] [PASSED] 0xB090 (PANTHERLAKE)
[11:34:58] [PASSED] 0xB0A0 (PANTHERLAKE)
[11:34:58] [PASSED] 0xB0B0 (PANTHERLAKE)
[11:34:58] [PASSED] 0xFD80 (PANTHERLAKE)
[11:34:58] [PASSED] 0xFD81 (PANTHERLAKE)
[11:34:58] ============= [PASSED] check_platform_gt_count =============
[11:34:58] ===================== [PASSED] xe_pci ======================
[11:34:58] =================== xe_rtp (2 subtests) ====================
[11:34:58] =============== xe_rtp_process_to_sr_tests  ================
[11:34:58] [PASSED] coalesce-same-reg
[11:34:58] [PASSED] no-match-no-add
[11:34:58] [PASSED] match-or
[11:34:58] [PASSED] match-or-xfail
[11:34:58] [PASSED] no-match-no-add-multiple-rules
[11:34:58] [PASSED] two-regs-two-entries
[11:34:58] [PASSED] clr-one-set-other
[11:34:58] [PASSED] set-field
[11:34:58] [PASSED] conflict-duplicate
[11:34:58] [PASSED] conflict-not-disjoint
[11:34:58] [PASSED] conflict-reg-type
[11:34:58] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[11:34:58] ================== xe_rtp_process_tests  ===================
[11:34:58] [PASSED] active1
[11:34:58] [PASSED] active2
[11:34:58] [PASSED] active-inactive
[11:34:58] [PASSED] inactive-active
[11:34:58] [PASSED] inactive-1st_or_active-inactive
[11:34:58] [PASSED] inactive-2nd_or_active-inactive
[11:34:58] [PASSED] inactive-last_or_active-inactive
[11:34:58] [PASSED] inactive-no_or_active-inactive
[11:34:58] ============== [PASSED] xe_rtp_process_tests ===============
[11:34:58] ===================== [PASSED] xe_rtp ======================
[11:34:58] ==================== xe_wa (1 subtest) =====================
[11:34:58] ======================== xe_wa_gt  =========================
[11:34:58] [PASSED] TIGERLAKE B0
[11:34:58] [PASSED] DG1 A0
[11:34:58] [PASSED] DG1 B0
[11:34:58] [PASSED] ALDERLAKE_S A0
[11:34:58] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[11:34:58] [PASSED] ALDERLAKE_S C0
[11:34:58] [PASSED] ALDERLAKE_S D0
[11:34:58] [PASSED] ALDERLAKE_P A0
[11:34:58] [PASSED] ALDERLAKE_P B0
[11:34:58] [PASSED] ALDERLAKE_P C0
[11:34:58] [PASSED] ALDERLAKE_S RPLS D0
[11:34:58] [PASSED] ALDERLAKE_P RPLU E0
[11:34:58] [PASSED] DG2 G10 C0
[11:34:58] [PASSED] DG2 G11 B1
[11:34:58] [PASSED] DG2 G12 A1
[11:34:58] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:34:58] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:34:58] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[11:34:58] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[11:34:58] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[11:34:58] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[11:34:58] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[11:34:58] ==================== [PASSED] xe_wa_gt =====================
[11:34:58] ====================== [PASSED] xe_wa ======================
[11:34:58] ============================================================
[11:34:58] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[11:34:58] Elapsed time: 33.757s total, 4.220s configuring, 29.170s building, 0.321s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[11:34:58] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:35:00] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:35:23] Starting KUnit Kernel (1/1)...
[11:35:23] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:35:23] ============ drm_test_pick_cmdline (2 subtests) ============
[11:35:23] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[11:35:23] =============== drm_test_pick_cmdline_named  ===============
[11:35:23] [PASSED] NTSC
[11:35:23] [PASSED] NTSC-J
[11:35:23] [PASSED] PAL
[11:35:23] [PASSED] PAL-M
[11:35:23] =========== [PASSED] drm_test_pick_cmdline_named ===========
[11:35:23] ============== [PASSED] drm_test_pick_cmdline ==============
[11:35:23] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[11:35:23] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[11:35:23] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[11:35:23] =========== drm_validate_clone_mode (2 subtests) ===========
[11:35:23] ============== drm_test_check_in_clone_mode  ===============
[11:35:23] [PASSED] in_clone_mode
[11:35:23] [PASSED] not_in_clone_mode
[11:35:23] ========== [PASSED] drm_test_check_in_clone_mode ===========
[11:35:23] =============== drm_test_check_valid_clones  ===============
[11:35:23] [PASSED] not_in_clone_mode
[11:35:23] [PASSED] valid_clone
[11:35:23] [PASSED] invalid_clone
[11:35:23] =========== [PASSED] drm_test_check_valid_clones ===========
[11:35:23] ============= [PASSED] drm_validate_clone_mode =============
[11:35:23] ============= drm_validate_modeset (1 subtest) =============
[11:35:23] [PASSED] drm_test_check_connector_changed_modeset
[11:35:23] ============== [PASSED] drm_validate_modeset ===============
[11:35:23] ====== drm_test_bridge_get_current_state (2 subtests) ======
[11:35:23] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[11:35:23] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[11:35:23] ======== [PASSED] drm_test_bridge_get_current_state ========
[11:35:23] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[11:35:23] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[11:35:23] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[11:35:23] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[11:35:23] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[11:35:23] ============== drm_bridge_alloc (2 subtests) ===============
[11:35:23] [PASSED] drm_test_drm_bridge_alloc_basic
[11:35:23] [PASSED] drm_test_drm_bridge_alloc_get_put
[11:35:23] ================ [PASSED] drm_bridge_alloc =================
[11:35:23] ================== drm_buddy (7 subtests) ==================
[11:35:23] [PASSED] drm_test_buddy_alloc_limit
[11:35:23] [PASSED] drm_test_buddy_alloc_optimistic
[11:35:23] [PASSED] drm_test_buddy_alloc_pessimistic
[11:35:23] [PASSED] drm_test_buddy_alloc_pathological
[11:35:23] [PASSED] drm_test_buddy_alloc_contiguous
[11:35:23] [PASSED] drm_test_buddy_alloc_clear
[11:35:23] [PASSED] drm_test_buddy_alloc_range_bias
[11:35:23] ==================== [PASSED] drm_buddy ====================
[11:35:23] ============= drm_cmdline_parser (40 subtests) =============
[11:35:23] [PASSED] drm_test_cmdline_force_d_only
[11:35:23] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:35:23] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:35:23] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:35:23] [PASSED] drm_test_cmdline_force_e_only
[11:35:23] [PASSED] drm_test_cmdline_res
[11:35:23] [PASSED] drm_test_cmdline_res_vesa
[11:35:23] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:35:23] [PASSED] drm_test_cmdline_res_rblank
[11:35:23] [PASSED] drm_test_cmdline_res_bpp
[11:35:23] [PASSED] drm_test_cmdline_res_refresh
[11:35:23] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:35:23] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:35:23] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:35:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:35:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:35:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:35:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:35:23] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:35:23] [PASSED] drm_test_cmdline_res_margins_force_on
[11:35:23] [PASSED] drm_test_cmdline_res_vesa_margins
[11:35:23] [PASSED] drm_test_cmdline_name
[11:35:23] [PASSED] drm_test_cmdline_name_bpp
[11:35:23] [PASSED] drm_test_cmdline_name_option
[11:35:23] [PASSED] drm_test_cmdline_name_bpp_option
[11:35:23] [PASSED] drm_test_cmdline_rotate_0
[11:35:23] [PASSED] drm_test_cmdline_rotate_90
[11:35:23] [PASSED] drm_test_cmdline_rotate_180
[11:35:23] [PASSED] drm_test_cmdline_rotate_270
[11:35:23] [PASSED] drm_test_cmdline_hmirror
[11:35:23] [PASSED] drm_test_cmdline_vmirror
[11:35:23] [PASSED] drm_test_cmdline_margin_options
[11:35:23] [PASSED] drm_test_cmdline_multiple_options
[11:35:23] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:35:23] [PASSED] drm_test_cmdline_extra_and_option
[11:35:23] [PASSED] drm_test_cmdline_freestanding_options
[11:35:23] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:35:23] [PASSED] drm_test_cmdline_panel_orientation
[11:35:23] ================ drm_test_cmdline_invalid  =================
[11:35:23] [PASSED] margin_only
[11:35:23] [PASSED] interlace_only
[11:35:23] [PASSED] res_missing_x
[11:35:23] [PASSED] res_missing_y
[11:35:23] [PASSED] res_bad_y
[11:35:23] [PASSED] res_missing_y_bpp
[11:35:23] [PASSED] res_bad_bpp
[11:35:23] [PASSED] res_bad_refresh
[11:35:23] [PASSED] res_bpp_refresh_force_on_off
[11:35:23] [PASSED] res_invalid_mode
[11:35:23] [PASSED] res_bpp_wrong_place_mode
[11:35:23] [PASSED] name_bpp_refresh
[11:35:23] [PASSED] name_refresh
[11:35:23] [PASSED] name_refresh_wrong_mode
[11:35:23] [PASSED] name_refresh_invalid_mode
[11:35:23] [PASSED] rotate_multiple
[11:35:23] [PASSED] rotate_invalid_val
[11:35:23] [PASSED] rotate_truncated
[11:35:23] [PASSED] invalid_option
[11:35:23] [PASSED] invalid_tv_option
[11:35:23] [PASSED] truncated_tv_option
[11:35:23] ============ [PASSED] drm_test_cmdline_invalid =============
[11:35:23] =============== drm_test_cmdline_tv_options  ===============
[11:35:23] [PASSED] NTSC
[11:35:23] [PASSED] NTSC_443
[11:35:23] [PASSED] NTSC_J
[11:35:23] [PASSED] PAL
[11:35:23] [PASSED] PAL_M
[11:35:23] [PASSED] PAL_N
[11:35:23] [PASSED] SECAM
[11:35:23] [PASSED] MONO_525
[11:35:23] [PASSED] MONO_625
[11:35:23] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:35:23] =============== [PASSED] drm_cmdline_parser ================
[11:35:23] ========== drmm_connector_hdmi_init (20 subtests) ==========
[11:35:23] [PASSED] drm_test_connector_hdmi_init_valid
[11:35:23] [PASSED] drm_test_connector_hdmi_init_bpc_8
[11:35:23] [PASSED] drm_test_connector_hdmi_init_bpc_10
[11:35:23] [PASSED] drm_test_connector_hdmi_init_bpc_12
[11:35:23] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[11:35:23] [PASSED] drm_test_connector_hdmi_init_bpc_null
[11:35:23] [PASSED] drm_test_connector_hdmi_init_formats_empty
[11:35:23] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[11:35:23] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[11:35:23] [PASSED] supported_formats=0x9 yuv420_allowed=1
[11:35:23] [PASSED] supported_formats=0x9 yuv420_allowed=0
[11:35:23] [PASSED] supported_formats=0x3 yuv420_allowed=1
[11:35:23] [PASSED] supported_formats=0x3 yuv420_allowed=0
[11:35:23] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:35:23] [PASSED] drm_test_connector_hdmi_init_null_ddc
[11:35:23] [PASSED] drm_test_connector_hdmi_init_null_product
[11:35:23] [PASSED] drm_test_connector_hdmi_init_null_vendor
[11:35:23] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[11:35:23] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[11:35:23] [PASSED] drm_test_connector_hdmi_init_product_valid
[11:35:23] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[11:35:23] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[11:35:23] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[11:35:23] ========= drm_test_connector_hdmi_init_type_valid  =========
[11:35:23] [PASSED] HDMI-A
[11:35:23] [PASSED] HDMI-B
[11:35:23] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[11:35:23] ======== drm_test_connector_hdmi_init_type_invalid  ========
[11:35:23] [PASSED] Unknown
[11:35:23] [PASSED] VGA
[11:35:23] [PASSED] DVI-I
[11:35:23] [PASSED] DVI-D
[11:35:23] [PASSED] DVI-A
[11:35:23] [PASSED] Composite
[11:35:23] [PASSED] SVIDEO
[11:35:23] [PASSED] LVDS
[11:35:23] [PASSED] Component
[11:35:23] [PASSED] DIN
[11:35:23] [PASSED] DP
[11:35:23] [PASSED] TV
[11:35:23] [PASSED] eDP
[11:35:23] [PASSED] Virtual
[11:35:23] [PASSED] DSI
[11:35:23] [PASSED] DPI
[11:35:23] [PASSED] Writeback
[11:35:23] [PASSED] SPI
[11:35:23] [PASSED] USB
[11:35:23] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[11:35:23] ============ [PASSED] drmm_connector_hdmi_init =============
[11:35:23] ============= drmm_connector_init (3 subtests) =============
[11:35:23] [PASSED] drm_test_drmm_connector_init
[11:35:23] [PASSED] drm_test_drmm_connector_init_null_ddc
[11:35:23] ========= drm_test_drmm_connector_init_type_valid  =========
[11:35:23] [PASSED] Unknown
[11:35:23] [PASSED] VGA
[11:35:23] [PASSED] DVI-I
[11:35:23] [PASSED] DVI-D
[11:35:23] [PASSED] DVI-A
[11:35:23] [PASSED] Composite
[11:35:23] [PASSED] SVIDEO
[11:35:23] [PASSED] LVDS
[11:35:23] [PASSED] Component
[11:35:23] [PASSED] DIN
[11:35:23] [PASSED] DP
[11:35:23] [PASSED] HDMI-A
[11:35:23] [PASSED] HDMI-B
[11:35:23] [PASSED] TV
[11:35:23] [PASSED] eDP
[11:35:23] [PASSED] Virtual
[11:35:23] [PASSED] DSI
[11:35:23] [PASSED] DPI
[11:35:23] [PASSED] Writeback
[11:35:23] [PASSED] SPI
[11:35:23] [PASSED] USB
[11:35:23] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[11:35:23] =============== [PASSED] drmm_connector_init ===============
[11:35:23] ========= drm_connector_dynamic_init (6 subtests) ==========
[11:35:23] [PASSED] drm_test_drm_connector_dynamic_init
[11:35:23] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[11:35:23] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[11:35:23] [PASSED] drm_test_drm_connector_dynamic_init_properties
[11:35:23] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[11:35:23] [PASSED] Unknown
[11:35:23] [PASSED] VGA
[11:35:23] [PASSED] DVI-I
[11:35:23] [PASSED] DVI-D
[11:35:23] [PASSED] DVI-A
[11:35:23] [PASSED] Composite
[11:35:23] [PASSED] SVIDEO
[11:35:23] [PASSED] LVDS
[11:35:23] [PASSED] Component
[11:35:23] [PASSED] DIN
[11:35:23] [PASSED] DP
[11:35:23] [PASSED] HDMI-A
[11:35:23] [PASSED] HDMI-B
[11:35:23] [PASSED] TV
[11:35:23] [PASSED] eDP
[11:35:23] [PASSED] Virtual
[11:35:23] [PASSED] DSI
[11:35:23] [PASSED] DPI
[11:35:23] [PASSED] Writeback
[11:35:23] [PASSED] SPI
[11:35:23] [PASSED] USB
[11:35:23] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[11:35:23] ======== drm_test_drm_connector_dynamic_init_name  =========
[11:35:23] [PASSED] Unknown
[11:35:23] [PASSED] VGA
[11:35:23] [PASSED] DVI-I
[11:35:23] [PASSED] DVI-D
[11:35:23] [PASSED] DVI-A
[11:35:23] [PASSED] Composite
[11:35:23] [PASSED] SVIDEO
[11:35:23] [PASSED] LVDS
[11:35:23] [PASSED] Component
[11:35:23] [PASSED] DIN
[11:35:23] [PASSED] DP
[11:35:23] [PASSED] HDMI-A
[11:35:23] [PASSED] HDMI-B
[11:35:23] [PASSED] TV
[11:35:23] [PASSED] eDP
[11:35:23] [PASSED] Virtual
[11:35:23] [PASSED] DSI
[11:35:23] [PASSED] DPI
[11:35:23] [PASSED] Writeback
[11:35:23] [PASSED] SPI
[11:35:23] [PASSED] USB
[11:35:23] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[11:35:23] =========== [PASSED] drm_connector_dynamic_init ============
[11:35:23] ==== drm_connector_dynamic_register_early (4 subtests) =====
[11:35:23] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[11:35:23] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[11:35:23] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[11:35:23] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[11:35:23] ====== [PASSED] drm_connector_dynamic_register_early =======
[11:35:23] ======= drm_connector_dynamic_register (7 subtests) ========
[11:35:23] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[11:35:23] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[11:35:23] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[11:35:23] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[11:35:23] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[11:35:23] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[11:35:23] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[11:35:23] ========= [PASSED] drm_connector_dynamic_register ==========
[11:35:23] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[11:35:23] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[11:35:23] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[11:35:23] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[11:35:23] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:35:23] ========== drm_test_get_tv_mode_from_name_valid  ===========
[11:35:23] [PASSED] NTSC
[11:35:23] [PASSED] NTSC-443
[11:35:23] [PASSED] NTSC-J
[11:35:23] [PASSED] PAL
[11:35:23] [PASSED] PAL-M
[11:35:23] [PASSED] PAL-N
[11:35:23] [PASSED] SECAM
[11:35:23] [PASSED] Mono
[11:35:23] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:35:23] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:35:23] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:35:23] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[11:35:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[11:35:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[11:35:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[11:35:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[11:35:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[11:35:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[11:35:23] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[11:35:23] [PASSED] VIC 96
[11:35:23] [PASSED] VIC 97
[11:35:23] [PASSED] VIC 101
[11:35:23] [PASSED] VIC 102
[11:35:23] [PASSED] VIC 106
[11:35:23] [PASSED] VIC 107
[11:35:23] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[11:35:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[11:35:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[11:35:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[11:35:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[11:35:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[11:35:23] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[11:35:23] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[11:35:23] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[11:35:23] [PASSED] Automatic
[11:35:23] [PASSED] Full
[11:35:23] [PASSED] Limited 16:235
[11:35:23] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[11:35:23] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[11:35:23] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[11:35:23] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[11:35:23] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[11:35:23] [PASSED] RGB
[11:35:23] [PASSED] YUV 4:2:0
[11:35:23] [PASSED] YUV 4:2:2
[11:35:23] [PASSED] YUV 4:4:4
[11:35:23] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[11:35:23] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[11:35:23] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[11:35:23] ============= drm_damage_helper (21 subtests) ==============
[11:35:23] [PASSED] drm_test_damage_iter_no_damage
[11:35:23] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:35:23] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:35:23] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:35:23] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:35:23] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:35:23] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:35:23] [PASSED] drm_test_damage_iter_simple_damage
[11:35:23] [PASSED] drm_test_damage_iter_single_damage
[11:35:23] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:35:23] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:35:23] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:35:23] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:35:23] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:35:23] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:35:23] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:35:23] [PASSED] drm_test_damage_iter_damage
[11:35:23] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:35:23] [PASSED] drm_test_damage_iter_damage_one_outside
[11:35:23] [PASSED] drm_test_damage_iter_damage_src_moved
[11:35:23] [PASSED] drm_test_damage_iter_damage_not_visible
[11:35:23] ================ [PASSED] drm_damage_helper ================
[11:35:23] ============== drm_dp_mst_helper (3 subtests) ==============
[11:35:23] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[11:35:23] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:35:23] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:35:23] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:35:23] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:35:23] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:35:23] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:35:23] ============== drm_test_dp_mst_calc_pbn_div  ===============
[11:35:23] [PASSED] Link rate 2000000 lane count 4
[11:35:23] [PASSED] Link rate 2000000 lane count 2
[11:35:23] [PASSED] Link rate 2000000 lane count 1
[11:35:23] [PASSED] Link rate 1350000 lane count 4
[11:35:23] [PASSED] Link rate 1350000 lane count 2
[11:35:23] [PASSED] Link rate 1350000 lane count 1
[11:35:23] [PASSED] Link rate 1000000 lane count 4
[11:35:23] [PASSED] Link rate 1000000 lane count 2
[11:35:23] [PASSED] Link rate 1000000 lane count 1
[11:35:23] [PASSED] Link rate 810000 lane count 4
[11:35:23] [PASSED] Link rate 810000 lane count 2
[11:35:23] [PASSED] Link rate 810000 lane count 1
[11:35:23] [PASSED] Link rate 540000 lane count 4
[11:35:23] [PASSED] Link rate 540000 lane count 2
[11:35:23] [PASSED] Link rate 540000 lane count 1
[11:35:23] [PASSED] Link rate 270000 lane count 4
[11:35:23] [PASSED] Link rate 270000 lane count 2
[11:35:23] [PASSED] Link rate 270000 lane count 1
[11:35:23] [PASSED] Link rate 162000 lane count 4
[11:35:23] [PASSED] Link rate 162000 lane count 2
[11:35:23] [PASSED] Link rate 162000 lane count 1
[11:35:23] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[11:35:23] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[11:35:23] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:35:23] [PASSED] DP_POWER_UP_PHY with port number
[11:35:23] [PASSED] DP_POWER_DOWN_PHY with port number
[11:35:23] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:35:23] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:35:23] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:35:23] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:35:23] [PASSED] DP_QUERY_PAYLOAD with port number
[11:35:23] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:35:23] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:35:23] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:35:23] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:35:23] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:35:23] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:35:23] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:35:23] [PASSED] DP_REMOTE_I2C_READ with port number
[11:35:23] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:35:23] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:35:23] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:35:23] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:35:23] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:35:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:35:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:35:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:35:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:35:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:35:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:35:23] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:35:23] ================ [PASSED] drm_dp_mst_helper ================
[11:35:23] ================== drm_exec (7 subtests) ===================
[11:35:23] [PASSED] sanitycheck
[11:35:23] [PASSED] test_lock
[11:35:23] [PASSED] test_lock_unlock
[11:35:23] [PASSED] test_duplicates
[11:35:23] [PASSED] test_prepare
[11:35:23] [PASSED] test_prepare_array
[11:35:23] [PASSED] test_multiple_loops
[11:35:23] ==================== [PASSED] drm_exec =====================
[11:35:23] =========== drm_format_helper_test (17 subtests) ===========
[11:35:23] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[11:35:23] [PASSED] single_pixel_source_buffer
[11:35:23] [PASSED] single_pixel_clip_rectangle
[11:35:23] [PASSED] well_known_colors
[11:35:23] [PASSED] destination_pitch
[11:35:23] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:35:23] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[11:35:23] [PASSED] single_pixel_source_buffer
[11:35:23] [PASSED] single_pixel_clip_rectangle
[11:35:23] [PASSED] well_known_colors
[11:35:23] [PASSED] destination_pitch
[11:35:23] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:35:23] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[11:35:23] [PASSED] single_pixel_source_buffer
[11:35:23] [PASSED] single_pixel_clip_rectangle
[11:35:23] [PASSED] well_known_colors
[11:35:23] [PASSED] destination_pitch
[11:35:23] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:35:23] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[11:35:23] [PASSED] single_pixel_source_buffer
[11:35:23] [PASSED] single_pixel_clip_rectangle
[11:35:23] [PASSED] well_known_colors
[11:35:23] [PASSED] destination_pitch
[11:35:23] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:35:23] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[11:35:23] [PASSED] single_pixel_source_buffer
[11:35:23] [PASSED] single_pixel_clip_rectangle
[11:35:23] [PASSED] well_known_colors
[11:35:23] [PASSED] destination_pitch
[11:35:23] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:35:23] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[11:35:23] [PASSED] single_pixel_source_buffer
[11:35:23] [PASSED] single_pixel_clip_rectangle
[11:35:23] [PASSED] well_known_colors
[11:35:23] [PASSED] destination_pitch
[11:35:23] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:35:23] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[11:35:23] [PASSED] single_pixel_source_buffer
[11:35:23] [PASSED] single_pixel_clip_rectangle
[11:35:23] [PASSED] well_known_colors
[11:35:23] [PASSED] destination_pitch
[11:35:23] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:35:23] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[11:35:23] [PASSED] single_pixel_source_buffer
[11:35:23] [PASSED] single_pixel_clip_rectangle
[11:35:23] [PASSED] well_known_colors
[11:35:23] [PASSED] destination_pitch
[11:35:23] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[11:35:23] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[11:35:23] [PASSED] single_pixel_source_buffer
[11:35:23] [PASSED] single_pixel_clip_rectangle
[11:35:23] [PASSED] well_known_colors
[11:35:23] [PASSED] destination_pitch
[11:35:23] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:35:23] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[11:35:23] [PASSED] single_pixel_source_buffer
[11:35:23] [PASSED] single_pixel_clip_rectangle
[11:35:23] [PASSED] well_known_colors
[11:35:23] [PASSED] destination_pitch
[11:35:23] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:35:23] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[11:35:23] [PASSED] single_pixel_source_buffer
[11:35:23] [PASSED] single_pixel_clip_rectangle
[11:35:23] [PASSED] well_known_colors
[11:35:23] [PASSED] destination_pitch
[11:35:23] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:35:23] ============== drm_test_fb_xrgb8888_to_mono  ===============
[11:35:23] [PASSED] single_pixel_source_buffer
[11:35:23] [PASSED] single_pixel_clip_rectangle
[11:35:23] [PASSED] well_known_colors
[11:35:23] [PASSED] destination_pitch
[11:35:23] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:35:23] ==================== drm_test_fb_swab  =====================
[11:35:23] [PASSED] single_pixel_source_buffer
[11:35:23] [PASSED] single_pixel_clip_rectangle
[11:35:23] [PASSED] well_known_colors
[11:35:23] [PASSED] destination_pitch
[11:35:23] ================ [PASSED] drm_test_fb_swab =================
[11:35:23] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[11:35:23] [PASSED] single_pixel_source_buffer
[11:35:23] [PASSED] single_pixel_clip_rectangle
[11:35:23] [PASSED] well_known_colors
[11:35:23] [PASSED] destination_pitch
[11:35:23] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[11:35:23] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[11:35:23] [PASSED] single_pixel_source_buffer
[11:35:23] [PASSED] single_pixel_clip_rectangle
[11:35:23] [PASSED] well_known_colors
[11:35:23] [PASSED] destination_pitch
[11:35:23] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[11:35:23] ================= drm_test_fb_clip_offset  =================
[11:35:23] [PASSED] pass through
[11:35:23] [PASSED] horizontal offset
[11:35:23] [PASSED] vertical offset
[11:35:23] [PASSED] horizontal and vertical offset
[11:35:23] [PASSED] horizontal offset (custom pitch)
[11:35:23] [PASSED] vertical offset (custom pitch)
[11:35:23] [PASSED] horizontal and vertical offset (custom pitch)
[11:35:23] ============= [PASSED] drm_test_fb_clip_offset =============
[11:35:23] =================== drm_test_fb_memcpy  ====================
[11:35:23] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[11:35:23] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[11:35:23] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[11:35:23] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[11:35:23] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[11:35:23] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[11:35:23] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[11:35:23] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[11:35:23] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[11:35:23] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[11:35:23] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[11:35:23] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[11:35:23] =============== [PASSED] drm_test_fb_memcpy ================
[11:35:23] ============= [PASSED] drm_format_helper_test ==============
[11:35:23] ================= drm_format (18 subtests) =================
[11:35:23] [PASSED] drm_test_format_block_width_invalid
[11:35:23] [PASSED] drm_test_format_block_width_one_plane
[11:35:23] [PASSED] drm_test_format_block_width_two_plane
[11:35:23] [PASSED] drm_test_format_block_width_three_plane
[11:35:23] [PASSED] drm_test_format_block_width_tiled
[11:35:23] [PASSED] drm_test_format_block_height_invalid
[11:35:23] [PASSED] drm_test_format_block_height_one_plane
[11:35:23] [PASSED] drm_test_format_block_height_two_plane
[11:35:23] [PASSED] drm_test_format_block_height_three_plane
[11:35:23] [PASSED] drm_test_format_block_height_tiled
[11:35:23] [PASSED] drm_test_format_min_pitch_invalid
[11:35:23] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:35:23] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:35:23] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:35:23] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:35:23] [PASSED] drm_test_format_min_pitch_two_plane
[11:35:23] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:35:23] [PASSED] drm_test_format_min_pitch_tiled
[11:35:23] =================== [PASSED] drm_format ====================
[11:35:23] ============== drm_framebuffer (10 subtests) ===============
[11:35:23] ========== drm_test_framebuffer_check_src_coords  ==========
[11:35:23] [PASSED] Success: source fits into fb
[11:35:23] [PASSED] Fail: overflowing fb with x-axis coordinate
[11:35:23] [PASSED] Fail: overflowing fb with y-axis coordinate
[11:35:23] [PASSED] Fail: overflowing fb with source width
[11:35:23] [PASSED] Fail: overflowing fb with source height
[11:35:23] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[11:35:23] [PASSED] drm_test_framebuffer_cleanup
[11:35:23] =============== drm_test_framebuffer_create  ===============
[11:35:23] [PASSED] ABGR8888 normal sizes
[11:35:23] [PASSED] ABGR8888 max sizes
[11:35:23] [PASSED] ABGR8888 pitch greater than min required
[11:35:23] [PASSED] ABGR8888 pitch less than min required
[11:35:23] [PASSED] ABGR8888 Invalid width
[11:35:23] [PASSED] ABGR8888 Invalid buffer handle
[11:35:23] [PASSED] No pixel format
[11:35:23] [PASSED] ABGR8888 Width 0
[11:35:23] [PASSED] ABGR8888 Height 0
[11:35:23] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:35:23] [PASSED] ABGR8888 Large buffer offset
[11:35:23] [PASSED] ABGR8888 Buffer offset for inexistent plane
[11:35:23] [PASSED] ABGR8888 Invalid flag
[11:35:23] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:35:23] [PASSED] ABGR8888 Valid buffer modifier
[11:35:23] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:35:23] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:35:23] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:35:23] [PASSED] NV12 Normal sizes
[11:35:23] [PASSED] NV12 Max sizes
[11:35:23] [PASSED] NV12 Invalid pitch
[11:35:23] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:35:23] [PASSED] NV12 different  modifier per-plane
[11:35:23] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:35:23] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:35:23] [PASSED] NV12 Modifier for inexistent plane
[11:35:23] [PASSED] NV12 Handle for inexistent plane
[11:35:23] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:35:23] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:35:23] [PASSED] YVU420 Normal sizes
[11:35:23] [PASSED] YVU420 Max sizes
[11:35:23] [PASSED] YVU420 Invalid pitch
[11:35:23] [PASSED] YVU420 Different pitches
[11:35:23] [PASSED] YVU420 Different buffer offsets/pitches
[11:35:23] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:35:23] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:35:23] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:35:23] [PASSED] YVU420 Valid modifier
[11:35:23] [PASSED] YVU420 Different modifiers per plane
[11:35:23] [PASSED] YVU420 Modifier for inexistent plane
[11:35:23] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[11:35:23] [PASSED] X0L2 Normal sizes
[11:35:23] [PASSED] X0L2 Max sizes
[11:35:23] [PASSED] X0L2 Invalid pitch
[11:35:23] [PASSED] X0L2 Pitch greater than minimum required
[11:35:23] [PASSED] X0L2 Handle for inexistent plane
[11:35:23] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:35:23] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:35:23] [PASSED] X0L2 Valid modifier
[11:35:23] [PASSED] X0L2 Modifier for inexistent plane
[11:35:23] =========== [PASSED] drm_test_framebuffer_create ===========
[11:35:23] [PASSED] drm_test_framebuffer_free
[11:35:23] [PASSED] drm_test_framebuffer_init
[11:35:23] [PASSED] drm_test_framebuffer_init_bad_format
[11:35:23] [PASSED] drm_test_framebuffer_init_dev_mismatch
[11:35:23] [PASSED] drm_test_framebuffer_lookup
[11:35:23] [PASSED] drm_test_framebuffer_lookup_inexistent
[11:35:23] [PASSED] drm_test_framebuffer_modifiers_not_supported
[11:35:23] ================= [PASSED] drm_framebuffer =================
[11:35:23] ================ drm_gem_shmem (8 subtests) ================
[11:35:23] [PASSED] drm_gem_shmem_test_obj_create
[11:35:23] [PASSED] drm_gem_shmem_test_obj_create_private
[11:35:23] [PASSED] drm_gem_shmem_test_pin_pages
[11:35:23] [PASSED] drm_gem_shmem_test_vmap
[11:35:23] [PASSED] drm_gem_shmem_test_get_pages_sgt
[11:35:23] [PASSED] drm_gem_shmem_test_get_sg_table
[11:35:23] [PASSED] drm_gem_shmem_test_madvise
[11:35:23] [PASSED] drm_gem_shmem_test_purge
[11:35:23] ================== [PASSED] drm_gem_shmem ==================
[11:35:23] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[11:35:23] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[11:35:23] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[11:35:23] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[11:35:23] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[11:35:23] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[11:35:23] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[11:35:23] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[11:35:23] [PASSED] Automatic
[11:35:23] [PASSED] Full
[11:35:23] [PASSED] Limited 16:235
[11:35:23] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[11:35:23] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[11:35:23] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[11:35:23] [PASSED] drm_test_check_disable_connector
[11:35:23] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[11:35:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[11:35:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[11:35:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[11:35:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[11:35:23] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[11:35:23] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[11:35:23] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[11:35:23] [PASSED] drm_test_check_output_bpc_dvi
[11:35:23] [PASSED] drm_test_check_output_bpc_format_vic_1
[11:35:23] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[11:35:23] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[11:35:23] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[11:35:23] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[11:35:23] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[11:35:23] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[11:35:23] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[11:35:23] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[11:35:23] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[11:35:23] [PASSED] drm_test_check_broadcast_rgb_value
[11:35:23] [PASSED] drm_test_check_bpc_8_value
[11:35:23] [PASSED] drm_test_check_bpc_10_value
[11:35:23] [PASSED] drm_test_check_bpc_12_value
[11:35:23] [PASSED] drm_test_check_format_value
[11:35:23] [PASSED] drm_test_check_tmds_char_value
[11:35:23] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[11:35:23] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[11:35:23] [PASSED] drm_test_check_mode_valid
[11:35:23] [PASSED] drm_test_check_mode_valid_reject
[11:35:23] [PASSED] drm_test_check_mode_valid_reject_rate
[11:35:23] [PASSED] drm_test_check_mode_valid_reject_max_clock
[11:35:23] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[11:35:23] ================= drm_managed (2 subtests) =================
[11:35:23] [PASSED] drm_test_managed_release_action
[11:35:23] [PASSED] drm_test_managed_run_action
[11:35:23] =================== [PASSED] drm_managed ===================
[11:35:23] =================== drm_mm (6 subtests) ====================
[11:35:23] [PASSED] drm_test_mm_init
[11:35:23] [PASSED] drm_test_mm_debug
[11:35:23] [PASSED] drm_test_mm_align32
[11:35:23] [PASSED] drm_test_mm_align64
[11:35:23] [PASSED] drm_test_mm_lowest
[11:35:23] [PASSED] drm_test_mm_highest
[11:35:23] ===================== [PASSED] drm_mm ======================
[11:35:23] ============= drm_modes_analog_tv (5 subtests) =============
[11:35:23] [PASSED] drm_test_modes_analog_tv_mono_576i
[11:35:23] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:35:23] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:35:23] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:35:23] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:35:23] =============== [PASSED] drm_modes_analog_tv ===============
[11:35:23] ============== drm_plane_helper (2 subtests) ===============
[11:35:23] =============== drm_test_check_plane_state  ================
[11:35:23] [PASSED] clipping_simple
[11:35:23] [PASSED] clipping_rotate_reflect
[11:35:23] [PASSED] positioning_simple
[11:35:23] [PASSED] upscaling
[11:35:23] [PASSED] downscaling
[11:35:23] [PASSED] rounding1
[11:35:23] [PASSED] rounding2
[11:35:23] [PASSED] rounding3
[11:35:23] [PASSED] rounding4
[11:35:23] =========== [PASSED] drm_test_check_plane_state ============
[11:35:23] =========== drm_test_check_invalid_plane_state  ============
[11:35:23] [PASSED] positioning_invalid
[11:35:23] [PASSED] upscaling_invalid
[11:35:23] [PASSED] downscaling_invalid
[11:35:23] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:35:23] ================ [PASSED] drm_plane_helper =================
[11:35:23] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:35:23] ====== drm_test_connector_helper_tv_get_modes_check  =======
[11:35:23] [PASSED] None
[11:35:23] [PASSED] PAL
[11:35:23] [PASSED] NTSC
[11:35:23] [PASSED] Both, NTSC Default
[11:35:23] [PASSED] Both, PAL Default
[11:35:23] [PASSED] Both, NTSC Default, with PAL on command-line
[11:35:23] [PASSED] Both, PAL Default, with NTSC on command-line
[11:35:23] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:35:23] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:35:23] ================== drm_rect (9 subtests) ===================
[11:35:23] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:35:23] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:35:23] [PASSED] drm_test_rect_clip_scaled_clipped
[11:35:23] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:35:23] ================= drm_test_rect_intersect  =================
[11:35:23] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:35:23] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:35:23] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:35:23] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:35:23] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:35:23] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:35:23] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:35:23] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:35:23] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:35:23] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:35:23] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:35:23] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:35:23] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:35:23] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:35:23] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[11:35:23] ============= [PASSED] drm_test_rect_intersect =============
[11:35:23] ================ drm_test_rect_calc_hscale  ================
[11:35:23] [PASSED] normal use
[11:35:23] [PASSED] out of max range
[11:35:23] [PASSED] out of min range
[11:35:23] [PASSED] zero dst
[11:35:23] [PASSED] negative src
[11:35:23] [PASSED] negative dst
[11:35:23] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:35:23] ================ drm_test_rect_calc_vscale  ================
[11:35:23] [PASSED] normal use
[11:35:23] [PASSED] out of max range
[11:35:23] [PASSED] out of min range
[11:35:23] [PASSED] zero dst
[11:35:23] [PASSED] negative src
stty: 'standard input': Inappropriate ioctl for device
[11:35:23] [PASSED] negative dst
[11:35:23] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:35:23] ================== drm_test_rect_rotate  ===================
[11:35:23] [PASSED] reflect-x
[11:35:23] [PASSED] reflect-y
[11:35:23] [PASSED] rotate-0
[11:35:23] [PASSED] rotate-90
[11:35:23] [PASSED] rotate-180
[11:35:23] [PASSED] rotate-270
[11:35:23] ============== [PASSED] drm_test_rect_rotate ===============
[11:35:23] ================ drm_test_rect_rotate_inv  =================
[11:35:23] [PASSED] reflect-x
[11:35:23] [PASSED] reflect-y
[11:35:23] [PASSED] rotate-0
[11:35:23] [PASSED] rotate-90
[11:35:23] [PASSED] rotate-180
[11:35:23] [PASSED] rotate-270
[11:35:23] ============ [PASSED] drm_test_rect_rotate_inv =============
[11:35:23] ==================== [PASSED] drm_rect =====================
[11:35:23] ============ drm_sysfb_modeset_test (1 subtest) ============
[11:35:23] ============ drm_test_sysfb_build_fourcc_list  =============
[11:35:23] [PASSED] no native formats
[11:35:23] [PASSED] XRGB8888 as native format
[11:35:23] [PASSED] remove duplicates
[11:35:23] [PASSED] convert alpha formats
[11:35:23] [PASSED] random formats
[11:35:23] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[11:35:23] ============= [PASSED] drm_sysfb_modeset_test ==============
[11:35:23] ============================================================
[11:35:23] Testing complete. Ran 621 tests: passed: 621
[11:35:23] Elapsed time: 25.167s total, 1.602s configuring, 23.347s building, 0.186s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[11:35:23] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:35:25] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:35:34] Starting KUnit Kernel (1/1)...
[11:35:34] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:35:34] ================= ttm_device (5 subtests) ==================
[11:35:34] [PASSED] ttm_device_init_basic
[11:35:34] [PASSED] ttm_device_init_multiple
[11:35:34] [PASSED] ttm_device_fini_basic
[11:35:34] [PASSED] ttm_device_init_no_vma_man
[11:35:34] ================== ttm_device_init_pools  ==================
[11:35:34] [PASSED] No DMA allocations, no DMA32 required
[11:35:34] [PASSED] DMA allocations, DMA32 required
[11:35:34] [PASSED] No DMA allocations, DMA32 required
[11:35:34] [PASSED] DMA allocations, no DMA32 required
[11:35:34] ============== [PASSED] ttm_device_init_pools ==============
[11:35:34] =================== [PASSED] ttm_device ====================
[11:35:34] ================== ttm_pool (8 subtests) ===================
[11:35:34] ================== ttm_pool_alloc_basic  ===================
[11:35:34] [PASSED] One page
[11:35:34] [PASSED] More than one page
[11:35:34] [PASSED] Above the allocation limit
[11:35:34] [PASSED] One page, with coherent DMA mappings enabled
[11:35:34] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:35:34] ============== [PASSED] ttm_pool_alloc_basic ===============
[11:35:34] ============== ttm_pool_alloc_basic_dma_addr  ==============
[11:35:34] [PASSED] One page
[11:35:34] [PASSED] More than one page
[11:35:34] [PASSED] Above the allocation limit
[11:35:34] [PASSED] One page, with coherent DMA mappings enabled
[11:35:34] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:35:34] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[11:35:34] [PASSED] ttm_pool_alloc_order_caching_match
[11:35:34] [PASSED] ttm_pool_alloc_caching_mismatch
[11:35:34] [PASSED] ttm_pool_alloc_order_mismatch
[11:35:34] [PASSED] ttm_pool_free_dma_alloc
[11:35:34] [PASSED] ttm_pool_free_no_dma_alloc
[11:35:34] [PASSED] ttm_pool_fini_basic
[11:35:34] ==================== [PASSED] ttm_pool =====================
[11:35:34] ================ ttm_resource (8 subtests) =================
[11:35:34] ================= ttm_resource_init_basic  =================
[11:35:34] [PASSED] Init resource in TTM_PL_SYSTEM
[11:35:34] [PASSED] Init resource in TTM_PL_VRAM
[11:35:34] [PASSED] Init resource in a private placement
[11:35:34] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[11:35:34] ============= [PASSED] ttm_resource_init_basic =============
[11:35:34] [PASSED] ttm_resource_init_pinned
[11:35:34] [PASSED] ttm_resource_fini_basic
[11:35:34] [PASSED] ttm_resource_manager_init_basic
[11:35:34] [PASSED] ttm_resource_manager_usage_basic
[11:35:34] [PASSED] ttm_resource_manager_set_used_basic
[11:35:34] [PASSED] ttm_sys_man_alloc_basic
[11:35:34] [PASSED] ttm_sys_man_free_basic
[11:35:34] ================== [PASSED] ttm_resource ===================
[11:35:34] =================== ttm_tt (15 subtests) ===================
[11:35:34] ==================== ttm_tt_init_basic  ====================
[11:35:34] [PASSED] Page-aligned size
[11:35:34] [PASSED] Extra pages requested
[11:35:34] ================ [PASSED] ttm_tt_init_basic ================
[11:35:34] [PASSED] ttm_tt_init_misaligned
[11:35:34] [PASSED] ttm_tt_fini_basic
[11:35:34] [PASSED] ttm_tt_fini_sg
[11:35:34] [PASSED] ttm_tt_fini_shmem
[11:35:34] [PASSED] ttm_tt_create_basic
[11:35:34] [PASSED] ttm_tt_create_invalid_bo_type
[11:35:34] [PASSED] ttm_tt_create_ttm_exists
[11:35:34] [PASSED] ttm_tt_create_failed
[11:35:34] [PASSED] ttm_tt_destroy_basic
[11:35:34] [PASSED] ttm_tt_populate_null_ttm
[11:35:34] [PASSED] ttm_tt_populate_populated_ttm
[11:35:34] [PASSED] ttm_tt_unpopulate_basic
[11:35:34] [PASSED] ttm_tt_unpopulate_empty_ttm
[11:35:34] [PASSED] ttm_tt_swapin_basic
[11:35:34] ===================== [PASSED] ttm_tt ======================
[11:35:34] =================== ttm_bo (14 subtests) ===================
[11:35:34] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[11:35:34] [PASSED] Cannot be interrupted and sleeps
[11:35:34] [PASSED] Cannot be interrupted, locks straight away
[11:35:34] [PASSED] Can be interrupted, sleeps
[11:35:34] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[11:35:34] [PASSED] ttm_bo_reserve_locked_no_sleep
[11:35:34] [PASSED] ttm_bo_reserve_no_wait_ticket
[11:35:34] [PASSED] ttm_bo_reserve_double_resv
[11:35:34] [PASSED] ttm_bo_reserve_interrupted
[11:35:34] [PASSED] ttm_bo_reserve_deadlock
[11:35:34] [PASSED] ttm_bo_unreserve_basic
[11:35:34] [PASSED] ttm_bo_unreserve_pinned
[11:35:34] [PASSED] ttm_bo_unreserve_bulk
[11:35:34] [PASSED] ttm_bo_fini_basic
[11:35:34] [PASSED] ttm_bo_fini_shared_resv
[11:35:34] [PASSED] ttm_bo_pin_basic
[11:35:34] [PASSED] ttm_bo_pin_unpin_resource
[11:35:34] [PASSED] ttm_bo_multiple_pin_one_unpin
[11:35:34] ===================== [PASSED] ttm_bo ======================
[11:35:34] ============== ttm_bo_validate (21 subtests) ===============
[11:35:34] ============== ttm_bo_init_reserved_sys_man  ===============
[11:35:34] [PASSED] Buffer object for userspace
[11:35:34] [PASSED] Kernel buffer object
[11:35:34] [PASSED] Shared buffer object
[11:35:34] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[11:35:34] ============== ttm_bo_init_reserved_mock_man  ==============
[11:35:34] [PASSED] Buffer object for userspace
[11:35:34] [PASSED] Kernel buffer object
[11:35:34] [PASSED] Shared buffer object
[11:35:34] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[11:35:34] [PASSED] ttm_bo_init_reserved_resv
[11:35:34] ================== ttm_bo_validate_basic  ==================
[11:35:34] [PASSED] Buffer object for userspace
[11:35:34] [PASSED] Kernel buffer object
[11:35:34] [PASSED] Shared buffer object
[11:35:34] ============== [PASSED] ttm_bo_validate_basic ==============
[11:35:34] [PASSED] ttm_bo_validate_invalid_placement
[11:35:34] ============= ttm_bo_validate_same_placement  ==============
[11:35:34] [PASSED] System manager
[11:35:34] [PASSED] VRAM manager
[11:35:34] ========= [PASSED] ttm_bo_validate_same_placement ==========
[11:35:34] [PASSED] ttm_bo_validate_failed_alloc
[11:35:34] [PASSED] ttm_bo_validate_pinned
[11:35:34] [PASSED] ttm_bo_validate_busy_placement
[11:35:34] ================ ttm_bo_validate_multihop  =================
[11:35:34] [PASSED] Buffer object for userspace
[11:35:34] [PASSED] Kernel buffer object
[11:35:34] [PASSED] Shared buffer object
[11:35:34] ============ [PASSED] ttm_bo_validate_multihop =============
[11:35:34] ========== ttm_bo_validate_no_placement_signaled  ==========
[11:35:34] [PASSED] Buffer object in system domain, no page vector
[11:35:34] [PASSED] Buffer object in system domain with an existing page vector
[11:35:34] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[11:35:34] ======== ttm_bo_validate_no_placement_not_signaled  ========
[11:35:34] [PASSED] Buffer object for userspace
[11:35:34] [PASSED] Kernel buffer object
[11:35:34] [PASSED] Shared buffer object
[11:35:34] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[11:35:34] [PASSED] ttm_bo_validate_move_fence_signaled
[11:35:34] ========= ttm_bo_validate_move_fence_not_signaled  =========
[11:35:34] [PASSED] Waits for GPU
[11:35:34] [PASSED] Tries to lock straight away
[11:35:34] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[11:35:34] [PASSED] ttm_bo_validate_happy_evict
[11:35:34] [PASSED] ttm_bo_validate_all_pinned_evict
[11:35:34] [PASSED] ttm_bo_validate_allowed_only_evict
[11:35:34] [PASSED] ttm_bo_validate_deleted_evict
[11:35:34] [PASSED] ttm_bo_validate_busy_domain_evict
[11:35:34] [PASSED] ttm_bo_validate_evict_gutting
[11:35:34] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[11:35:34] ================= [PASSED] ttm_bo_validate =================
[11:35:34] ============================================================
[11:35:34] Testing complete. Ran 101 tests: passed: 101
[11:35:34] Elapsed time: 11.051s total, 1.664s configuring, 9.171s building, 0.184s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel



^ permalink raw reply	[flat|nested] 21+ messages in thread

* ✗ CI.checksparse: warning for Introduce set_context_latency and refactor VRR/DSB timing logic (rev3)
  2025-09-24 10:51 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
                   ` (9 preceding siblings ...)
  2025-09-24 11:35 ` ✓ CI.KUnit: success for Introduce set_context_latency and refactor VRR/DSB timing logic (rev3) Patchwork
@ 2025-09-24 11:50 ` Patchwork
  2025-09-24 12:09 ` ✓ Xe.CI.BAT: success " Patchwork
  2025-09-24 15:02 ` ✗ Xe.CI.Full: failure " Patchwork
  12 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2025-09-24 11:50 UTC (permalink / raw)
  To: Nautiyal, Ankit K; +Cc: intel-xe

== Series Details ==

Series: Introduce set_context_latency and refactor VRR/DSB timing logic (rev3)
URL   : https://patchwork.freedesktop.org/series/154809/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 7ac678a5ca459ce17bca34b51ff45d732e400261
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2026:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2039:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/gt/intel_reset.c:1569:12: warning: context imbalance in '_intel_gt_reset_lock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_sseu.c:598:17: error: too long token expansion
+drivers/gpu/drm/i915/i915_active.c:1062:16: warning: context imbalance in '__i915_active_fence_set' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_drm_client.c:92:9: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/i915/i915_drm_client.c:92:9: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/i915/i915_drm_client.c:92:9:    expected struct list_head const *list
+drivers/gpu/drm/i915/i915_drm_client.c:92:9:    got struct list_head [noderef] __rcu *pos
+drivers/gpu/drm/i915/i915_drm_client.c:92:9:    struct list_head *
+drivers/gpu/drm/i915/i915_drm_client.c:92:9:    struct list_head *
+drivers/gpu/drm/i915/i915_drm_client.c:92:9:    struct list_head [noderef] __rcu *
+drivers/gpu/drm/i915/i915_drm_client.c:92:9:    struct list_head [noderef] __rcu *
+drivers/gpu/drm/i915/i915_drm_client.c:92:9: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/i915_gpu_error.c:692:3: warning: symbol 'guc_hw_reg_state' was not declared. Should it be static?
+drivers/gpu/drm/i915/i915_irq.c:466:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:466:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:474:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:474:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:479:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:479:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:479:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:517:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:517:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:525:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:525:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:530:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:530:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:530:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:574:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:574:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:577:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:577:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:581:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:581:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:588:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:588:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:588:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:588:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/intel_uncore.c:1928:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1929:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1996:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1997:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2018:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2019:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_wakeref.c:146:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel



^ permalink raw reply	[flat|nested] 21+ messages in thread

* ✓ Xe.CI.BAT: success for Introduce set_context_latency and refactor VRR/DSB timing logic (rev3)
  2025-09-24 10:51 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
                   ` (10 preceding siblings ...)
  2025-09-24 11:50 ` ✗ CI.checksparse: warning " Patchwork
@ 2025-09-24 12:09 ` Patchwork
  2025-09-24 15:02 ` ✗ Xe.CI.Full: failure " Patchwork
  12 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2025-09-24 12:09 UTC (permalink / raw)
  To: Nautiyal, Ankit K; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 2049 bytes --]

== Series Details ==

Series: Introduce set_context_latency and refactor VRR/DSB timing logic (rev3)
URL   : https://patchwork.freedesktop.org/series/154809/
State : success

== Summary ==

CI Bug Log - changes from xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670_BAT -> xe-pw-154809v3_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 9)
------------------------------

  Missing    (2): bat-adlp-vm bat-ptl-vm 

Known issues
------------

  Here are the changes found in xe-pw-154809v3_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@kms_flip@basic-plain-flip@c-edp1:
    - bat-adlp-7:         [DMESG-WARN][1] ([Intel XE#4543]) -> [PASS][2] +1 other test pass
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/bat-adlp-7/igt@kms_flip@basic-plain-flip@c-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/bat-adlp-7/igt@kms_flip@basic-plain-flip@c-edp1.html

  * igt@xe_pat@pat-index-xe2@render:
    - bat-bmg-1:          [FAIL][3] ([Intel XE#5507]) -> [PASS][4] +1 other test pass
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/bat-bmg-1/igt@xe_pat@pat-index-xe2@render.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/bat-bmg-1/igt@xe_pat@pat-index-xe2@render.html

  
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#5507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5507


Build changes
-------------

  * Linux: xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670 -> xe-pw-154809v3

  IGT_8550: 4f8c7886ad02e116804ec08714f17bce1755c6e4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670: 53ee7e373ce454dc86b39ac27aa84d95c536b670
  xe-pw-154809v3: 154809v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/index.html

[-- Attachment #2: Type: text/html, Size: 2648 bytes --]

^ permalink raw reply	[flat|nested] 21+ messages in thread

* ✗ Xe.CI.Full: failure for Introduce set_context_latency and refactor VRR/DSB timing logic (rev3)
  2025-09-24 10:51 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
                   ` (11 preceding siblings ...)
  2025-09-24 12:09 ` ✓ Xe.CI.BAT: success " Patchwork
@ 2025-09-24 15:02 ` Patchwork
  12 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2025-09-24 15:02 UTC (permalink / raw)
  To: Ankit Nautiyal; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 56105 bytes --]

== Series Details ==

Series: Introduce set_context_latency and refactor VRR/DSB timing logic (rev3)
URL   : https://patchwork.freedesktop.org/series/154809/
State : failure

== Summary ==

CI Bug Log - changes from xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670_FULL -> xe-pw-154809v3_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-154809v3_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-154809v3_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-154809v3_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_plane_multiple@tiling-none:
    - shard-bmg:          [PASS][1] -> [TIMEOUT][2] +1 other test timeout
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-3/igt@kms_plane_multiple@tiling-none.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@kms_plane_multiple@tiling-none.html

  * igt@xe_exec_compute_mode@many-execqueues-userptr-free:
    - shard-bmg:          [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-3/igt@xe_exec_compute_mode@many-execqueues-userptr-free.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@xe_exec_compute_mode@many-execqueues-userptr-free.html

  
Known issues
------------

  Here are the changes found in xe-pw-154809v3_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-dg2-set2:     NOTRUN -> [SKIP][5] ([Intel XE#623])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][6] ([Intel XE#316]) +1 other test skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-466/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-90:
    - shard-adlp:         NOTRUN -> [SKIP][7] ([Intel XE#1124]) +2 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@linear-64bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2327])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@kms_big_fb@linear-64bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][9] ([Intel XE#4543])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][10] ([Intel XE#1124]) +11 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#2191])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-466/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#2191])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-lnl-2/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p:
    - shard-adlp:         NOTRUN -> [SKIP][13] ([Intel XE#2191])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-1-displays-1920x1080p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#367]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2887]) +3 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][16] ([Intel XE#455] / [Intel XE#787]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][17] ([Intel XE#787]) +2 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][18] ([Intel XE#787]) +202 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-432/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][19] ([Intel XE#2907]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][20] ([Intel XE#455] / [Intel XE#787]) +41 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-433/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-dp-4.html

  * igt@kms_chamelium_audio@hdmi-audio-edid:
    - shard-adlp:         NOTRUN -> [SKIP][21] ([Intel XE#373]) +2 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@kms_chamelium_audio@hdmi-audio-edid.html

  * igt@kms_chamelium_color@ctm-0-50:
    - shard-dg2-set2:     NOTRUN -> [SKIP][22] ([Intel XE#306]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@kms_chamelium_color@ctm-0-50.html

  * igt@kms_chamelium_edid@hdmi-mode-timings:
    - shard-dg2-set2:     NOTRUN -> [SKIP][23] ([Intel XE#373]) +7 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@kms_chamelium_edid@hdmi-mode-timings.html

  * igt@kms_chamelium_hpd@hdmi-hpd-after-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2252]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@kms_chamelium_hpd@hdmi-hpd-after-suspend.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][25] ([Intel XE#307]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
    - shard-dg2-set2:     NOTRUN -> [FAIL][26] ([Intel XE#1178]) +1 other test fail
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-432/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html

  * igt@kms_content_protection@uevent@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][27] ([Intel XE#1188])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-433/igt@kms_content_protection@uevent@pipe-a-dp-4.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2321])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-dg2-set2:     NOTRUN -> [SKIP][29] ([Intel XE#308]) +2 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-dg2-set2:     NOTRUN -> [SKIP][30] ([Intel XE#323])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#2286])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-dg2-set2:     NOTRUN -> [SKIP][32] ([Intel XE#4331])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
    - shard-dg2-set2:     NOTRUN -> [SKIP][33] ([Intel XE#4422])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html

  * igt@kms_fbcon_fbt@psr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][34] ([Intel XE#776])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-466/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@chamelium:
    - shard-dg2-set2:     NOTRUN -> [SKIP][35] ([Intel XE#701])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-adlp:         NOTRUN -> [SKIP][36] ([Intel XE#1137])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@2x-plain-flip:
    - shard-adlp:         NOTRUN -> [SKIP][37] ([Intel XE#310]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [PASS][38] -> [FAIL][39] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@plain-flip-interruptible@b-hdmi-a1:
    - shard-adlp:         [PASS][40] -> [DMESG-WARN][41] ([Intel XE#4543]) +8 other tests dmesg-warn
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-adlp-8/igt@kms_flip@plain-flip-interruptible@b-hdmi-a1.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@kms_flip@plain-flip-interruptible@b-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#1397] / [Intel XE#1745])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#1397])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][44] ([Intel XE#455]) +15 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y:
    - shard-adlp:         [PASS][45] -> [DMESG-FAIL][46] ([Intel XE#4543])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-x:
    - shard-adlp:         [PASS][47] -> [FAIL][48] ([Intel XE#1874]) +1 other test fail
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-x.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-x.html

  * igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#2311]) +7 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][50] ([Intel XE#651]) +26 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#5390]) +2 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-shrfb-scaledprimary:
    - shard-adlp:         NOTRUN -> [SKIP][52] ([Intel XE#651])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@kms_frontbuffer_tracking@fbcdrrs-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
    - shard-dg2-set2:     NOTRUN -> [SKIP][53] ([Intel XE#658]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#2313]) +4 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt:
    - shard-adlp:         NOTRUN -> [SKIP][55] ([Intel XE#656]) +3 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@plane-fbc-rte:
    - shard-dg2-set2:     NOTRUN -> [SKIP][56] ([Intel XE#1158])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@kms_frontbuffer_tracking@plane-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][57] ([Intel XE#653]) +28 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#656])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-lnl-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-dg2-set2:     NOTRUN -> [SKIP][59] ([Intel XE#4359])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-466/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane_lowres@tiling-x@pipe-a-hdmi-a-1:
    - shard-adlp:         [PASS][60] -> [DMESG-WARN][61] ([Intel XE#2953] / [Intel XE#4173]) +6 other tests dmesg-warn
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-adlp-4/igt@kms_plane_lowres@tiling-x@pipe-a-hdmi-a-1.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-2/igt@kms_plane_lowres@tiling-x@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c:
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#2763]) +3 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-lnl-2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#2392])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf:
    - shard-adlp:         NOTRUN -> [SKIP][64] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][65] ([Intel XE#1406] / [Intel XE#1489]) +7 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-dg2-set2:     NOTRUN -> [SKIP][67] ([Intel XE#1122] / [Intel XE#1406])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@pr-sprite-blt:
    - shard-adlp:         NOTRUN -> [SKIP][68] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@kms_psr@pr-sprite-blt.html

  * igt@kms_psr@psr-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][69] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +12 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@kms_psr@psr-dpms.html

  * igt@kms_psr@psr2-sprite-render:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@kms_psr@psr2-sprite-render.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][71] ([Intel XE#3414]) +2 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-bmg:          NOTRUN -> [SKIP][72] ([Intel XE#2330])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#3414] / [Intel XE#3904])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_scaling_modes@scaling-mode-full-aspect:
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#2413])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@kms_scaling_modes@scaling-mode-full-aspect.html

  * igt@kms_vrr@flip-suspend:
    - shard-adlp:         NOTRUN -> [SKIP][75] ([Intel XE#455]) +2 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@kms_vrr@flip-suspend.html

  * igt@kms_vrr@lobf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][76] ([Intel XE#2168])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@kms_vrr@lobf.html

  * igt@xe_compute_preempt@compute-preempt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][77] ([Intel XE#1280] / [Intel XE#455]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@xe_compute_preempt@compute-preempt.html

  * igt@xe_configfs@survivability-mode:
    - shard-dg2-set2:     NOTRUN -> [SKIP][78] ([Intel XE#6010])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@xe_configfs@survivability-mode.html

  * igt@xe_copy_basic@mem-set-linear-0xfd:
    - shard-adlp:         NOTRUN -> [SKIP][79] ([Intel XE#1126])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@xe_copy_basic@mem-set-linear-0xfd.html

  * igt@xe_copy_basic@mem-set-linear-0xfffe:
    - shard-dg2-set2:     NOTRUN -> [SKIP][80] ([Intel XE#1126])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@xe_copy_basic@mem-set-linear-0xfffe.html

  * igt@xe_eu_stall@invalid-sampling-rate:
    - shard-dg2-set2:     NOTRUN -> [SKIP][81] ([Intel XE#5626])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@xe_eu_stall@invalid-sampling-rate.html

  * igt@xe_eudebug@basic-vm-access-parameters:
    - shard-dg2-set2:     NOTRUN -> [SKIP][82] ([Intel XE#4837]) +11 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@xe_eudebug@basic-vm-access-parameters.html

  * igt@xe_eudebug_online@debugger-reopen:
    - shard-adlp:         NOTRUN -> [SKIP][83] ([Intel XE#4837] / [Intel XE#5565])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@xe_eudebug_online@debugger-reopen.html

  * igt@xe_eudebug_online@single-step:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#4837])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@xe_eudebug_online@single-step.html

  * igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-vram:
    - shard-lnl:          NOTRUN -> [SKIP][85] ([Intel XE#4837])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-lnl-2/igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-vram.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null:
    - shard-bmg:          NOTRUN -> [SKIP][86] ([Intel XE#2322])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null.html

  * igt@xe_exec_basic@multigpu-once-null:
    - shard-dg2-set2:     [PASS][87] -> [SKIP][88] ([Intel XE#1392]) +5 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-dg2-433/igt@xe_exec_basic@multigpu-once-null.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-432/igt@xe_exec_basic@multigpu-once-null.html

  * igt@xe_exec_fault_mode@many-execqueues-userptr-imm:
    - shard-bmg:          [PASS][89] -> [FAIL][90] ([Intel XE#6050])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-3/igt@xe_exec_fault_mode@many-execqueues-userptr-imm.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@xe_exec_fault_mode@many-execqueues-userptr-imm.html

  * igt@xe_exec_fault_mode@many-userptr-prefetch:
    - shard-adlp:         NOTRUN -> [SKIP][91] ([Intel XE#288] / [Intel XE#5561]) +1 other test skip
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@xe_exec_fault_mode@many-userptr-prefetch.html

  * igt@xe_exec_fault_mode@once-rebind-prefetch:
    - shard-dg2-set2:     NOTRUN -> [SKIP][92] ([Intel XE#288]) +25 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@xe_exec_fault_mode@once-rebind-prefetch.html

  * igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence:
    - shard-dg2-set2:     NOTRUN -> [SKIP][93] ([Intel XE#2360])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence.html

  * igt@xe_exec_system_allocator@process-many-execqueues-free-race:
    - shard-dg2-set2:     NOTRUN -> [SKIP][94] ([Intel XE#4915]) +237 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-466/igt@xe_exec_system_allocator@process-many-execqueues-free-race.html

  * igt@xe_exec_system_allocator@process-many-stride-mmap-new-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][95] ([Intel XE#4943]) +1 other test skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@xe_exec_system_allocator@process-many-stride-mmap-new-huge-nomemset.html

  * igt@xe_exec_system_allocator@process-many-stride-mmap-remap-dontunmap-eocheck:
    - shard-bmg:          [PASS][96] -> [ABORT][97] ([Intel XE#5790])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-3/igt@xe_exec_system_allocator@process-many-stride-mmap-remap-dontunmap-eocheck.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@xe_exec_system_allocator@process-many-stride-mmap-remap-dontunmap-eocheck.html

  * igt@xe_exec_system_allocator@threads-many-execqueues-mmap-free-huge:
    - shard-lnl:          NOTRUN -> [SKIP][98] ([Intel XE#4943]) +1 other test skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-lnl-2/igt@xe_exec_system_allocator@threads-many-execqueues-mmap-free-huge.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-malloc-race:
    - shard-adlp:         NOTRUN -> [SKIP][99] ([Intel XE#4915]) +29 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-malloc-race.html

  * igt@xe_exec_threads@threads-shared-vm-userptr-invalidate:
    - shard-bmg:          [PASS][100] -> [DMESG-FAIL][101] ([Intel XE#3876])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-3/igt@xe_exec_threads@threads-shared-vm-userptr-invalidate.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@xe_exec_threads@threads-shared-vm-userptr-invalidate.html

  * igt@xe_oa@buffer-size:
    - shard-dg2-set2:     NOTRUN -> [SKIP][102] ([Intel XE#6032])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-466/igt@xe_oa@buffer-size.html

  * igt@xe_oa@closed-fd-and-unmapped-access:
    - shard-dg2-set2:     NOTRUN -> [SKIP][103] ([Intel XE#3573]) +4 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@xe_oa@closed-fd-and-unmapped-access.html

  * igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p:
    - shard-dg2-set2:     NOTRUN -> [FAIL][104] ([Intel XE#1173])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p.html

  * igt@xe_pm@d3cold-basic-exec:
    - shard-dg2-set2:     NOTRUN -> [SKIP][105] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@xe_pm@d3cold-basic-exec.html

  * igt@xe_pm@d3cold-mocs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][106] ([Intel XE#2284])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-466/igt@xe_pm@d3cold-mocs.html

  * igt@xe_pm@d3cold-multiple-execs:
    - shard-bmg:          NOTRUN -> [SKIP][107] ([Intel XE#2284])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@xe_pm@d3cold-multiple-execs.html

  * igt@xe_pm@s2idle-vm-bind-unbind-all:
    - shard-bmg:          [PASS][108] -> [DMESG-FAIL][109] ([Intel XE#5545])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-3/igt@xe_pm@s2idle-vm-bind-unbind-all.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@xe_pm@s2idle-vm-bind-unbind-all.html

  * igt@xe_pm@vram-d3cold-threshold:
    - shard-dg2-set2:     NOTRUN -> [SKIP][110] ([Intel XE#579])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@xe_pm@vram-d3cold-threshold.html

  * igt@xe_pmu@gt-frequency:
    - shard-dg2-set2:     [PASS][111] -> [FAIL][112] ([Intel XE#4819]) +1 other test fail
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-dg2-433/igt@xe_pmu@gt-frequency.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-432/igt@xe_pmu@gt-frequency.html

  * igt@xe_pxp@display-pxp-fb:
    - shard-dg2-set2:     NOTRUN -> [SKIP][113] ([Intel XE#4733]) +2 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@xe_pxp@display-pxp-fb.html

  * igt@xe_query@multigpu-query-invalid-size:
    - shard-bmg:          NOTRUN -> [SKIP][114] ([Intel XE#944])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@xe_query@multigpu-query-invalid-size.html

  * igt@xe_query@multigpu-query-mem-usage:
    - shard-dg2-set2:     NOTRUN -> [SKIP][115] ([Intel XE#944]) +1 other test skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@xe_query@multigpu-query-mem-usage.html

  * igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][116] ([Intel XE#4130]) +2 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html

  * igt@xe_sriov_flr@flr-vfs-parallel:
    - shard-dg2-set2:     NOTRUN -> [SKIP][117] ([Intel XE#4273])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@xe_sriov_flr@flr-vfs-parallel.html

  * igt@xe_sriov_scheduling@nonpreempt-engine-resets:
    - shard-dg2-set2:     NOTRUN -> [SKIP][118] ([Intel XE#4351])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@xe_sriov_scheduling@nonpreempt-engine-resets.html

  
#### Possible fixes ####

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0:
    - shard-adlp:         [DMESG-WARN][119] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][120] +1 other test pass
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-adlp-2/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-2/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [INCOMPLETE][121] ([Intel XE#3862]) -> [PASS][122] +1 other test pass
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [INCOMPLETE][123] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][125] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) -> [PASS][126]
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [SKIP][127] ([Intel XE#2291]) -> [PASS][128] +2 other tests pass
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_dp_aux_dev:
    - shard-bmg:          [SKIP][129] ([Intel XE#3009]) -> [PASS][130]
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-6/igt@kms_dp_aux_dev.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-2/igt@kms_dp_aux_dev.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-bmg:          [SKIP][131] ([Intel XE#2316]) -> [PASS][132]
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-6/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-2/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip@blocking-wf_vblank:
    - shard-dg2-set2:     [FAIL][133] -> [PASS][134]
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-dg2-432/igt@kms_flip@blocking-wf_vblank.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-433/igt@kms_flip@blocking-wf_vblank.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][135] ([Intel XE#301]) -> [PASS][136] +1 other test pass
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-rmfb:
    - shard-adlp:         [DMESG-WARN][137] ([Intel XE#4543] / [Intel XE#5208]) -> [PASS][138]
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-adlp-6/igt@kms_flip@flip-vs-rmfb.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@kms_flip@flip-vs-rmfb.html

  * igt@kms_flip@flip-vs-suspend@d-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][139] ([Intel XE#4543]) -> [PASS][140] +7 other tests pass
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-adlp-3/igt@kms_flip@flip-vs-suspend@d-hdmi-a1.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-2/igt@kms_flip@flip-vs-suspend@d-hdmi-a1.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y:
    - shard-adlp:         [DMESG-FAIL][141] ([Intel XE#4543]) -> [PASS][142]
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y.html

  * igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap:
    - shard-dg2-set2:     [SKIP][143] ([Intel XE#1392]) -> [PASS][144] +8 other tests pass
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap.html

  * igt@xe_exec_basic@once-userptr-rebind:
    - shard-adlp:         [INCOMPLETE][145] -> [PASS][146]
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-adlp-6/igt@xe_exec_basic@once-userptr-rebind.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@xe_exec_basic@once-userptr-rebind.html

  * igt@xe_exec_compute_mode@many-execqueues-userptr-free:
    - shard-adlp:         [FAIL][147] -> [PASS][148]
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-adlp-6/igt@xe_exec_compute_mode@many-execqueues-userptr-free.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@xe_exec_compute_mode@many-execqueues-userptr-free.html

  * igt@xe_exec_reset@parallel-gt-reset:
    - shard-adlp:         [DMESG-WARN][149] ([Intel XE#3876]) -> [PASS][150]
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-adlp-6/igt@xe_exec_reset@parallel-gt-reset.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@xe_exec_reset@parallel-gt-reset.html

  * {igt@xe_exec_system_allocator@many-64k-malloc-prefetch-madvise}:
    - shard-bmg:          [CRASH][151] ([Intel XE#6192]) -> [PASS][152] +8 other tests pass
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-2/igt@xe_exec_system_allocator@many-64k-malloc-prefetch-madvise.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-1/igt@xe_exec_system_allocator@many-64k-malloc-prefetch-madvise.html

  * igt@xe_exec_system_allocator@threads-many-mmap-free:
    - shard-bmg:          [INCOMPLETE][153] ([Intel XE#2594]) -> [PASS][154]
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-4/igt@xe_exec_system_allocator@threads-many-mmap-free.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-5/igt@xe_exec_system_allocator@threads-many-mmap-free.html

  * {igt@xe_exec_system_allocator@twice-large-new-prefetch}:
    - shard-lnl:          [CRASH][155] ([Intel XE#6192]) -> [PASS][156] +5 other tests pass
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-lnl-2/igt@xe_exec_system_allocator@twice-large-new-prefetch.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-lnl-4/igt@xe_exec_system_allocator@twice-large-new-prefetch.html

  * igt@xe_exec_threads@threads-shared-vm-userptr-invalidate:
    - shard-adlp:         [DMESG-FAIL][157] ([Intel XE#3876]) -> [PASS][158]
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-adlp-6/igt@xe_exec_threads@threads-shared-vm-userptr-invalidate.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@xe_exec_threads@threads-shared-vm-userptr-invalidate.html

  * igt@xe_pm@s2idle-basic:
    - shard-adlp:         [DMESG-WARN][159] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4504]) -> [PASS][160]
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-adlp-4/igt@xe_pm@s2idle-basic.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-3/igt@xe_pm@s2idle-basic.html

  * igt@xe_pm@s2idle-vm-bind-unbind-all:
    - shard-adlp:         [DMESG-FAIL][161] ([Intel XE#5545]) -> [PASS][162]
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-adlp-6/igt@xe_pm@s2idle-vm-bind-unbind-all.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-4/igt@xe_pm@s2idle-vm-bind-unbind-all.html

  * igt@xe_pmu@gt-frequency:
    - shard-lnl:          [FAIL][163] ([Intel XE#5841]) -> [PASS][164] +1 other test pass
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-lnl-4/igt@xe_pmu@gt-frequency.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-lnl-1/igt@xe_pmu@gt-frequency.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][165] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][166] ([Intel XE#301])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-rmfb-interruptible:
    - shard-adlp:         [DMESG-WARN][167] ([Intel XE#5208]) -> [DMESG-WARN][168] ([Intel XE#4543] / [Intel XE#5208])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-adlp-3/igt@kms_flip@flip-vs-rmfb-interruptible.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-2/igt@kms_flip@flip-vs-rmfb-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][169] ([Intel XE#2312]) -> [SKIP][170] ([Intel XE#5390])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-onoff:
    - shard-bmg:          [SKIP][171] ([Intel XE#2312]) -> [SKIP][172] ([Intel XE#2311]) +3 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-onoff.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][173] ([Intel XE#2312]) -> [SKIP][174] ([Intel XE#2313]) +4 other tests skip
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-blt.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][175] ([Intel XE#2313]) -> [SKIP][176] ([Intel XE#2312])
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][177] ([Intel XE#2426]) -> [FAIL][178] ([Intel XE#1729])
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][179] ([Intel XE#2426]) -> [SKIP][180] ([Intel XE#2509])
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
    - shard-dg2-set2:     [SKIP][181] ([Intel XE#1500]) -> [SKIP][182] ([Intel XE#362])
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-dg2-432/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_exec_reset@parallel-gt-reset:
    - shard-bmg:          [DMESG-WARN][183] ([Intel XE#3876] / [Intel XE#5213]) -> [DMESG-WARN][184] ([Intel XE#3876])
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-bmg-3/igt@xe_exec_reset@parallel-gt-reset.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-bmg-3/igt@xe_exec_reset@parallel-gt-reset.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
    - shard-dg2-set2:     [DMESG-WARN][185] -> [DMESG-WARN][186] ([Intel XE#5893])
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-dg2-466/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-434/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html

  * igt@xe_peer2peer@write:
    - shard-dg2-set2:     [SKIP][187] ([Intel XE#1061]) -> [FAIL][188] ([Intel XE#1173])
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-dg2-432/igt@xe_peer2peer@write.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-dg2-436/igt@xe_peer2peer@write.html

  * igt@xe_pm_residency@gt-c6-freeze@gt0:
    - shard-adlp:         [INCOMPLETE][189] -> [INCOMPLETE][190] ([Intel XE#3088]) +1 other test incomplete
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670/shard-adlp-9/igt@xe_pm_residency@gt-c6-freeze@gt0.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/shard-adlp-3/igt@xe_pm_residency@gt-c6-freeze@gt0.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1137]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1137
  [Intel XE#1158]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1158
  [Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
  [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2594
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#3088]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3088
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4351
  [Intel XE#4359]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4359
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4819
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
  [Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
  [Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
  [Intel XE#5786]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5786
  [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
  [Intel XE#5790]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5790
  [Intel XE#5841]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5841
  [Intel XE#5893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5893
  [Intel XE#6010]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6010
  [Intel XE#6032]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6032
  [Intel XE#6050]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6050
  [Intel XE#6190]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6190
  [Intel XE#6192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6192
  [Intel XE#623]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/623
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
  [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670 -> xe-pw-154809v3

  IGT_8550: 4f8c7886ad02e116804ec08714f17bce1755c6e4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3823-53ee7e373ce454dc86b39ac27aa84d95c536b670: 53ee7e373ce454dc86b39ac27aa84d95c536b670
  xe-pw-154809v3: 154809v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154809v3/index.html

[-- Attachment #2: Type: text/html, Size: 64583 bytes --]

^ permalink raw reply	[flat|nested] 21+ messages in thread

end of thread, other threads:[~2025-09-24 15:02 UTC | newest]

Thread overview: 21+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-09-24 10:51 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
2025-09-24 10:51 ` [PATCH 1/9] drm/i915/psr: s/intel_psr_min_vblank_delay/intel_psr_min_set_context_latency Ankit Nautiyal
2025-09-24 10:51 ` [PATCH 2/9] drm/i915/display: Add set_context_latency to crtc_state Ankit Nautiyal
2025-09-24 10:51 ` [PATCH 3/9] drm/i915/vrr: Use set_context_latency instead of intel_vrr_real_vblank_delay() Ankit Nautiyal
2025-09-24 10:51 ` [PATCH 4/9] drm/i915/vrr: Use SCL for computing guardband Ankit Nautiyal
2025-09-24 10:51 ` [PATCH 5/9] drm/i915/dsb: s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_delayed_vblank Ankit Nautiyal
2025-09-24 10:51 ` [PATCH 6/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks Ankit Nautiyal
2025-09-24 12:11   ` Ville Syrjälä
2025-09-24 14:04     ` Nautiyal, Ankit K
2025-09-24 10:51 ` [PATCH 7/9] drm/i915/reg_defs: Add REG_FIELD_MAX wrapper for FIELD_MAX() Ankit Nautiyal
2025-09-24 12:24   ` Andi Shyti
2025-09-24 14:17     ` Nautiyal, Ankit K
2025-09-24 10:51 ` [PATCH 8/9] drm/i915/vrr: Clamp guardband as per hardware and timing constraints Ankit Nautiyal
2025-09-24 12:04   ` Ville Syrjälä
2025-09-24 14:19     ` Nautiyal, Ankit K
2025-09-24 10:51 ` [PATCH 9/9] drm/i915/display: Drop intel_vrr_vblank_delay and use set_context_latency Ankit Nautiyal
2025-09-24 12:13   ` Ville Syrjälä
2025-09-24 11:35 ` ✓ CI.KUnit: success for Introduce set_context_latency and refactor VRR/DSB timing logic (rev3) Patchwork
2025-09-24 11:50 ` ✗ CI.checksparse: warning " Patchwork
2025-09-24 12:09 ` ✓ Xe.CI.BAT: success " Patchwork
2025-09-24 15:02 ` ✗ Xe.CI.Full: failure " Patchwork

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