From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 10/10] drm/i915/dsb: Inline dsb_vblank_delay() into intel_dsb_wait_for_delayed_vblank()
Date: Thu, 25 Sep 2025 10:42:44 +0300 [thread overview]
Message-ID: <aNTydBiwrEr6hrGQ@intel.com> (raw)
In-Reply-To: <20250925022352.3129859-1-ankit.k.nautiyal@intel.com>
On Thu, Sep 25, 2025 at 07:53:52AM +0530, Ankit Nautiyal wrote:
> Drop the now single-use dsb_vblank_delay() helper and inline its logic
> directly into intel_dsb_wait_for_delayed_vblank().
>
> This will help to keep all VRR related wait stuff in one place.
>
> v2: Use intel_scanlines_to_usecs() in intel_dsb_wait_usec(). (Ville)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dsb.c | 59 +++++++++++-------------
> 1 file changed, 26 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index ae8574880ef2..4ad4efbf9253 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -115,24 +115,6 @@ static bool pre_commit_is_vrr_active(struct intel_atomic_state *state,
> return old_crtc_state->vrr.enable && !intel_crtc_vrr_disabling(state, crtc);
> }
>
> -static int dsb_vblank_delay(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> -{
> - const struct intel_crtc_state *crtc_state =
> - intel_pre_commit_crtc_state(state, crtc);
> -
> - if (pre_commit_is_vrr_active(state, crtc))
> - /*
> - * When the push is sent during vblank it will trigger
> - * on the next scanline, hence we have up to one extra
> - * scanline until the delayed vblank occurs after
> - * TRANS_PUSH has been written.
> - */
> - return crtc_state->set_context_latency + 1;
> - else
> - return intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
> -}
> -
> static int dsb_vtotal(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> @@ -821,26 +803,37 @@ void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
> struct intel_crtc *crtc = dsb->crtc;
> const struct intel_crtc_state *crtc_state =
> intel_pre_commit_crtc_state(state, crtc);
> - int usecs = intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode,
> - dsb_vblank_delay(state, crtc));
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> + int wait_scanlines;
>
> - /*
> - * If the push happened before the vmin decision boundary
> - * we don't know how far we are from the undelayed vblank.
> - * Wait until we're past the vmin safe window, at which
> - * point we're SCL lines away from the delayed vblank.
> - *
> - * If the push happened after the vmin decision boundary
> - * the hardware itself guarantees that we're SCL lines
> - * away from the delayed vblank, and we won't be inside
> - * the vmin safe window so this extra wait does nothing.
> - */
> - if (pre_commit_is_vrr_active(state, crtc))
> + if (pre_commit_is_vrr_active(state, crtc)) {
> + /*
> + * If the push happened before the vmin decision boundary
> + * we don't know how far we are from the undelayed vblank.
> + * Wait until we're past the vmin safe window, at which
> + * point we're SCL lines away from the delayed vblank.
> + *
> + * If the push happened after the vmin decision boundary
> + * the hardware itself guarantees that we're SCL lines
> + * away from the delayed vblank, and we won't be inside
> + * the vmin safe window so this extra wait does nothing.
> + */
> intel_dsb_wait_scanline_out(state, dsb,
> intel_vrr_safe_window_start(crtc_state),
> intel_vrr_vmin_safe_window_end(crtc_state));
> + /*
> + * When the push is sent during vblank it will trigger
> + * on the next scanline, hence we have up to one extra
> + * scanline until the delayed vblank occurs after
> + * TRANS_PUSH has been written.
> + */
> + wait_scanlines = crtc_state->set_context_latency + 1;
> + } else {
> + wait_scanlines = intel_mode_vblank_delay(adjusted_mode);
> + }
>
> - intel_dsb_wait_usec(dsb, usecs);
> + intel_dsb_wait_usec(dsb, intel_scanlines_to_usecs(adjusted_mode, wait_scanlines));
> }
>
> /**
> --
> 2.45.2
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2025-09-25 7:42 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-24 14:15 [PATCH 00/10] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 01/10] drm/i915/psr: s/intel_psr_min_vblank_delay/intel_psr_min_set_context_latency Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 02/10] drm/i915/display: Add set_context_latency to crtc_state Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 03/10] drm/i915/vrr: Use set_context_latency instead of intel_vrr_real_vblank_delay() Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 04/10] drm/i915/vrr: Use SCL for computing guardband Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 05/10] drm/i915/dsb: s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_delayed_vblank Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 06/10] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 07/10] drm/i915/reg_defs: Add REG_FIELD_MAX wrapper for FIELD_MAX() Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 08/10] drm/i915/vrr: Clamp guardband as per hardware and timing constraints Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 09/10] drm/i915/display: Drop intel_vrr_vblank_delay and use set_context_latency Ankit Nautiyal
2025-09-24 14:15 ` [PATCH 10/10] drm/i915/dsb: Inline dsb_vblank_delay() into intel_dsb_wait_for_delayed_vblank() Ankit Nautiyal
2025-09-24 15:20 ` Ville Syrjälä
2025-09-25 2:23 ` Ankit Nautiyal
2025-09-25 7:42 ` Ville Syrjälä [this message]
2025-09-24 14:37 ` ✓ CI.KUnit: success for Introduce set_context_latency and refactor VRR/DSB timing logic (rev4) Patchwork
2025-09-24 14:52 ` ✗ CI.checksparse: warning " Patchwork
2025-09-24 15:13 ` ✓ Xe.CI.BAT: success " Patchwork
2025-09-24 19:21 ` ✓ Xe.CI.Full: " Patchwork
2025-09-25 3:21 ` ✓ CI.KUnit: success for Introduce set_context_latency and refactor VRR/DSB timing logic (rev5) Patchwork
2025-09-25 3:36 ` ✗ CI.checksparse: warning " Patchwork
2025-09-25 3:55 ` ✓ Xe.CI.BAT: success " Patchwork
2025-09-25 11:31 ` ✗ Xe.CI.Full: failure " Patchwork
2025-09-25 13:36 ` [PATCH 00/10] Introduce set_context_latency and refactor VRR/DSB timing logic Nautiyal, Ankit K
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