From: Matthew Brost <matthew.brost@intel.com>
To: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Cc: <intel-xe@lists.freedesktop.org>,
Michal Wajdeczko <michal.wajdeczko@intel.com>,
Matthew Auld <matthew.auld@intel.com>
Subject: Re: [PATCH v4 2/3] drm/xe/migrate: Make emit_pte() header write atomic
Date: Mon, 6 Oct 2025 12:42:17 -0700 [thread overview]
Message-ID: <aOQbmYZzw21jRTU2@lstrano-desk.jf.intel.com> (raw)
In-Reply-To: <20251006152443.12269-7-satyanarayana.k.v.p@intel.com>
On Mon, Oct 06, 2025 at 08:54:46PM +0530, Satyanarayana K V P wrote:
> The MI_STORE_DATA_IMM instruction header is quad dword in size. If the
> vCPU halts during save/restore while this sequence is being programmed,
> partial writes may trigger page faults when saving IGPU CCS metadata.
> Update instruction header atomically.
>
> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
>
> ---
> V3 -> V4:
> - New commit added.
>
> V2 -> V3:
> - None
>
> V1 -> V2:
> - None
> ---
> drivers/gpu/drm/xe/xe_migrate.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index b960fdcecd88..4c575be45a76 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -606,9 +606,14 @@ static void emit_pte(struct xe_migrate *m,
>
> while (ptes) {
> u32 chunk = min(MAX_PTE_PER_SDI, ptes);
> + u32 dw[SZ_2], i = 0;
> +
> + dw[i++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(chunk);
> + dw[i++] = ofs;
> +
> + WRITE_ONCE(*(u64 *)&bb->cs[bb->len], READ_ONCE(*(u64 *)dw));
You don't need the READ_ONCE.
This patch should safely cover the vCPU halting case.
However, I think we still need to work out how to handle the case where
vCPUs are unhalted and modifying the buffer faster than the GPU can read
it. For example, the instruction header might be read as a NOP by the
GPU, but the CPU then programs the subsequent store values, which the
GPU interprets as invalid instructions. We can figure out how to fix
this part in a follow up as it will depend on my VF migration series
landing first.
Matt
> + bb->len += i;
>
> - bb->cs[bb->len++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(chunk);
> - bb->cs[bb->len++] = ofs;
> bb->cs[bb->len++] = 0;
>
> cur_ofs = ofs;
> --
> 2.51.0
>
next prev parent reply other threads:[~2025-10-06 19:42 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-06 15:24 [PATCH v4 0/3] drm/xe/migrate: Atomicize CCS copy command setup Satyanarayana K V P
2025-10-06 15:24 ` [PATCH v4 1/3] " Satyanarayana K V P
2025-10-06 19:58 ` Matthew Brost
2025-10-08 9:50 ` K V P, Satyanarayana
2025-10-06 15:24 ` [PATCH v4 2/3] drm/xe/migrate: Make emit_pte() header write atomic Satyanarayana K V P
2025-10-06 19:42 ` Matthew Brost [this message]
2025-10-06 15:24 ` [PATCH v4 3/3] drm/xe/vf: Clear CCS read/write buffers in atomic way Satyanarayana K V P
2025-10-06 20:12 ` Matthew Brost
2025-10-08 1:40 ` Matthew Brost
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