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Thu, 09 Oct 2025 05:58:37 -0700 (PDT) Date: Thu, 9 Oct 2025 05:58:35 -0700 In-Reply-To: Mime-Version: 1.0 References: <70b64347-2aca-4511-af78-a767d5fa8226@intel.com> <25af94f5-79e3-4005-964e-e77b1320a16e@linux.intel.com> <3bbc4e6d-9f52-483c-a25d-166dca62fb25@intel.com> <00d0f3f3-d2b4-4885-9a49-5e6f8390142b@intel.com> Message-ID: Subject: Re: REGRESSION on linux-next (next-20250919) From: Sean Christopherson To: Dapeng Mi Cc: Chaitanya Kumar Borah , "intel-gfx@lists.freedesktop.org" , "intel-xe@lists.freedesktop.org" , Suresh Kumar Kurmi , Jani Saarinen , lucas.demarchi@intel.com, linux-perf-users@vger.kernel.org, kvm@vger.kernel.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Thu, Oct 09, 2025, Dapeng Mi wrote: >=20 > On 10/7/2025 2:22 PM, Borah, Chaitanya Kumar wrote: > > Hi, > > > > On 10/6/2025 1:33 PM, Borah, Chaitanya Kumar wrote: > >> Thank you for your responses. > >> > >> Following change fixes the issue for us. > >> > >> > >> diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c > >> index 40ac4cb44ed2..487ad19a236e 100644 > >> --- a/arch/x86/kvm/pmu.c > >> +++ b/arch/x86/kvm/pmu.c > >> @@ -108,16 +108,18 @@ void kvm_init_pmu_capability(const struct=20 > >> kvm_pmu_ops *pmu_ops) > >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bool is_intel =3D boot_cpu= _data.x86_vendor =3D=3D X86_VENDOR_INTEL; > >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 int min_nr_gp_ctrs =3D pmu= _ops->MIN_NR_GP_COUNTERS; > >> > >> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 perf_get_x86_pmu_capability(&kvm= _host_pmu); > >> - > >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* > >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * Hybrid PMUs don't = play nice with virtualization without careful > >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * configuration by u= serspace, and KVM's APIs for reporting=20 > >> supported > >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * vPMU features do n= ot account for hybrid PMUs.=C2=A0 Disable vPMU=20 > >> support > >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * for hybrid PMUs un= til KVM gains a way to let userspace opt-in. > >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 */ > >> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (cpu_feature_enabled(X86_FEAT= URE_HYBRID_CPU)) > >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (cpu_feature_enabled(X86_FEAT= URE_HYBRID_CPU)) { > >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 enable_pmu =3D false; > >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 memset(&kvm_host_pmu, 0, sizeof(kvm_host_pmu)); > >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } else { > >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 perf_get_x86_pmu_capability(&kvm_host_pmu); > >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } > > Can we expect a formal patch soon? >=20 > I'd like to post a patch to fix this tomorrow if Sean has no bandwidth on > this. Thanks. Sorry, my bad, I was waiting for you to post a patch, but that wasn't at al= l clear. So yeah, go ahead and post one :-)