Re: [PATCH v3] drm/xe: Enable media sampler power gating

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Thu, Oct 09, 2025 at 11:42:35AM -0700, Vinay Belgaumkar wrote:
> Where applicable, enable media sampler power gating. Also, add
> it to the powergate_info debugfs.
> 
> v2: Remove the sampler powergate status since it is cleared quickly anyway.
> v3: Use vcs mask (Rodrigo) and fix the version check for media
> 
> Fixes: 38e8c4184ea0 ("drm/xe: Enable Coarse Power Gating")
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  1 +
>  drivers/gpu/drm/xe/xe_gt_idle.c      | 11 ++++++++++-
>  2 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 06cb6b02ec64..51f2a03847f9 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -342,6 +342,7 @@
>  #define POWERGATE_ENABLE			XE_REG(0xa210)
>  #define   RENDER_POWERGATE_ENABLE		REG_BIT(0)
>  #define   MEDIA_POWERGATE_ENABLE		REG_BIT(1)
> +#define   MEDIA_SAMPLERS_POWERGATE_ENABLE	REG_BIT(2)
>  #define   VDN_HCP_POWERGATE_ENABLE(n)		REG_BIT(3 + 2 * (n))
>  #define   VDN_MFXVDENC_POWERGATE_ENABLE(n)	REG_BIT(4 + 2 * (n))
>  
> diff --git a/drivers/gpu/drm/xe/xe_gt_idle.c b/drivers/gpu/drm/xe/xe_gt_idle.c
> index f8950a52d0a4..0a112b8943b9 100644
> --- a/drivers/gpu/drm/xe/xe_gt_idle.c
> +++ b/drivers/gpu/drm/xe/xe_gt_idle.c
> @@ -118,12 +118,16 @@ void xe_gt_idle_enable_pg(struct xe_gt *gt)
>  	vcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_VIDEO_DECODE);
>  	vecs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE);
>  
> -	if (vcs_mask || vecs_mask)
> +	if (vcs_mask || vecs_mask) {
>  		gtidle->powergate_enable = MEDIA_POWERGATE_ENABLE;
> +		if (MEDIA_VERx100(xe) >= 1100 && MEDIA_VERx100(xe) < 1270)
> +			gtidle->powergate_enable |= MEDIA_SAMPLERS_POWERGATE_ENABLE;
> +	}
>  
>  	if (xe_gt_is_main_type(gt))
>  		gtidle->powergate_enable |= RENDER_POWERGATE_ENABLE;
>  
> +
>  	if (xe->info.platform != XE_DG1) {
>  		for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {
>  			if ((gt->info.engine_mask & BIT(i)))
> @@ -245,7 +249,12 @@ int xe_gt_idle_pg_print(struct xe_gt *gt, struct drm_printer *p)
>  			if (gt->info.engine_mask & media_slices[n].engines)
>  				drm_printf(p, "Media Slice%d Power Gate Status: %s\n", n,
>  					   str_up_down(pg_status & media_slices[n].status_bit));
> +
> +		if (MEDIA_VERx100(xe) >= 1100 && MEDIA_VERx100(xe) < 1270)
> +			drm_printf(p, "Media Samplers Power Gating Enabled: %s\n",
> +				   str_yes_no(pg_enabled & MEDIA_SAMPLERS_POWERGATE_ENABLE));
>  	}
> +
>  	return 0;
>  }
>  
> -- 
> 2.38.1
>