[PATCH 0/7] drm/i915: Stop the intel_de_wait_custom() abuse

[PATCH 0/7] drm/i915: Stop the intel_de_wait_custom() abuse

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Get rid of all the custom fast vs. slow intel_de_wait_custom()
timeouts that have started to spread like a cancer recently.

The eventual aim is to get rid of the fast vs. slow timeout
stuff entirely and switch over to poll_timeout_us()...

Ville Syrjälä (7):
  drm/i915/cx0: Undo the unjustified timeout change
  drm/i915/cx0: Get rid of XELPDP_MSGBUS_TIMEOUT_FAST_US
  drm/i915/cx0: s/XELPDP_MSGBUS_TIMEOUT_SLOW/XELPDP_MSGBUS_TIMEOUT_MS/
  drm/i915/cx0:
    s/XELPDP_PORT_RESET_END_TIMEOUT/XELPDP_PORT_RESET_END_TIMEOUT_US/
  drm/i915/ltphy: Nuke bogus weird timeouts
  drm/i915/hdcp: Use the default 2 usec fast polling timeout
  drm/i915/pmdemand: Use the default 2 usec fast polling timeout

 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 19 +++++++++----------
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h |  5 ++---
 drivers/gpu/drm/i915/display/intel_hdcp.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 13 ++++++-------
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  1 -
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
 6 files changed, 19 insertions(+), 23 deletions(-)

-- 
2.49.1

[PATCH 1/7] drm/i915/cx0: Undo the unjustified timeout change

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Undo the bogus timeout change to
intel_cx0_powerdown_change_sequence(). If this was intentional
then it should have been justifie in the commit message.

This is also now abusing intel_de_wait_custom() in way that
prevents future conversion to poll_timeout_us().

Fixes: fc9be0a10ca4 ("drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index b3b506d0e040..e7fe974129fe 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2830,7 +2830,7 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
 	/* Update Timeout Value */
 	if (intel_de_wait_custom(display, buf_ctl2_reg,
 				 intel_cx0_get_powerdown_update(lane_mask), 0,
-				 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 2, NULL))
+				 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
 		drm_warn(display->drm,
 			 "PHY %c failed to bring out of Lane reset after %dus.\n",
 			 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
-- 
2.49.1

[PATCH 2/7] drm/i915/cx0: Get rid of XELPDP_MSGBUS_TIMEOUT_FAST_US

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

XELPDP_MSGBUS_TIMEOUT_FAST_US looks to be just a obfuscated version
of the default 2 microsecond fast timeout used by
intel_wait_for_register(). get rid of it to make it clear what's going
on here.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c      | 3 +--
 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 1 -
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index e7fe974129fe..6f57ad751c9e 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -168,8 +168,7 @@ int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
 				 XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
 				 XELPDP_PORT_P2M_RESPONSE_READY,
 				 XELPDP_PORT_P2M_RESPONSE_READY,
-				 XELPDP_MSGBUS_TIMEOUT_FAST_US,
-				 XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
+				 2, XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
 		drm_dbg_kms(display->drm,
 			    "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
 			    phy_name(phy), *val);
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 635b35669348..67c6f06ab9a2 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -75,7 +75,6 @@
 #define   XELPDP_PORT_P2M_ERROR_SET			REG_BIT(15)
 
 #define XELPDP_MSGBUS_TIMEOUT_SLOW			1
-#define XELPDP_MSGBUS_TIMEOUT_FAST_US			2
 #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US		3200
 #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US		20
 #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US		100
-- 
2.49.1

[PATCH 3/7] drm/i915/cx0: s/XELPDP_MSGBUS_TIMEOUT_SLOW/XELPDP_MSGBUS_TIMEOUT_MS/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The slow vs. fast timeout stuff is really just an implementation
detail. Let's not spread that terminology in random timeout defines.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c      | 12 ++++++------
 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h |  2 +-
 drivers/gpu/drm/i915/display/intel_lt_phy.c       |  2 +-
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6f57ad751c9e..55ce4f673c63 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -147,7 +147,7 @@ void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
 
 	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 				    XELPDP_PORT_M2P_TRANSACTION_RESET,
-				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+				    XELPDP_MSGBUS_TIMEOUT_MS)) {
 		drm_err_once(display->drm,
 			     "Failed to bring PHY %c to idle.\n",
 			     phy_name(phy));
@@ -168,7 +168,7 @@ int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
 				 XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
 				 XELPDP_PORT_P2M_RESPONSE_READY,
 				 XELPDP_PORT_P2M_RESPONSE_READY,
-				 2, XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
+				 2, XELPDP_MSGBUS_TIMEOUT_MS, val)) {
 		drm_dbg_kms(display->drm,
 			    "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
 			    phy_name(phy), *val);
@@ -215,7 +215,7 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
 
 	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
-				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+				    XELPDP_MSGBUS_TIMEOUT_MS)) {
 		drm_dbg_kms(display->drm,
 			    "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
 		intel_cx0_bus_reset(encoder, lane);
@@ -286,7 +286,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
 
 	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
-				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+				    XELPDP_MSGBUS_TIMEOUT_MS)) {
 		drm_dbg_kms(display->drm,
 			    "PHY %c Timeout waiting for previous transaction to complete. Resetting the bus.\n", phy_name(phy));
 		intel_cx0_bus_reset(encoder, lane);
@@ -302,7 +302,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
 
 	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
-				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+				    XELPDP_MSGBUS_TIMEOUT_MS)) {
 		drm_dbg_kms(display->drm,
 			    "PHY %c Timeout waiting for write to complete. Resetting the bus.\n", phy_name(phy));
 		intel_cx0_bus_reset(encoder, lane);
@@ -2815,7 +2815,7 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
 	for_each_cx0_lane_in_mask(lane_mask, lane)
 		if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 					    XELPDP_PORT_M2P_TRANSACTION_PENDING,
-					    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+					    XELPDP_MSGBUS_TIMEOUT_MS)) {
 			drm_dbg_kms(display->drm,
 				    "PHY %c Timeout waiting for previous transaction to complete. Reset the bus.\n",
 				    phy_name(phy));
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 67c6f06ab9a2..bd62c396c837 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -74,7 +74,7 @@
 #define   XELPDP_PORT_P2M_DATA(val)			REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
 #define   XELPDP_PORT_P2M_ERROR_SET			REG_BIT(15)
 
-#define XELPDP_MSGBUS_TIMEOUT_SLOW			1
+#define XELPDP_MSGBUS_TIMEOUT_MS			1
 #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US		3200
 #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US		20
 #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US		100
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index af48d6cde226..6fb68157b322 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1043,7 +1043,7 @@ static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder,
 
 	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 				    XELPDP_PORT_P2P_TRANSACTION_PENDING,
-				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+				    XELPDP_MSGBUS_TIMEOUT_MS)) {
 		drm_dbg_kms(display->drm,
 			    "PHY %c Timeout waiting for previous transaction to complete. Resetting bus.\n",
 			    phy_name(phy));
-- 
2.49.1

[PATCH 4/7] drm/i915/cx0: s/XELPDP_PORT_RESET_END_TIMEOUT/XELPDP_PORT_RESET_END_TIMEOUT_US/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Include the units the in the define name for XELPDP_PORT_RESET_END_TIMEOUT
to make it match all its other counterparts.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c      | 4 ++--
 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 55ce4f673c63..7c9c181aba8a 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2926,10 +2926,10 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
 
 	if (intel_de_wait_for_clear(display, XELPDP_PORT_BUF_CTL2(display, port),
 				    lane_phy_current_status,
-				    XELPDP_PORT_RESET_END_TIMEOUT))
+				    XELPDP_PORT_RESET_END_TIMEOUT_US))
 		drm_warn(display->drm,
 			 "PHY %c failed to bring out of Lane reset after %dms.\n",
-			 phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
+			 phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT_US);
 }
 
 static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_count,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index bd62c396c837..77244a5d52d4 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -80,7 +80,7 @@
 #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US		100
 #define XELPDP_PORT_RESET_START_TIMEOUT_US		5
 #define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US		100
-#define XELPDP_PORT_RESET_END_TIMEOUT			15
+#define XELPDP_PORT_RESET_END_TIMEOUT_US		15
 #define XELPDP_REFCLK_ENABLE_TIMEOUT_US			1
 
 #define _XELPDP_PORT_BUF_CTL1_LN0_A			0x64004
-- 
2.49.1

[PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The LT PHY code is abusing intel_de_wait_custom() in all kinds of weird
ways. Get rid of the weird slow timeouts. If these are actually needed
then the fast timeouts should really be specified as the default 2
microscond or something.

This will let us eventually nuke intel_de_wait_custom() and convert
over to poll_timeout_us().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c      | 11 +++++------
 drivers/gpu/drm/i915/display/intel_lt_phy_regs.h |  1 -
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 6fb68157b322..cc1d6b7a7de4 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1178,10 +1178,9 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
 	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
 				 XELPDP_LANE_PCLK_PLL_ACK(0),
 				 XELPDP_LANE_PCLK_PLL_ACK(0),
-				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
-				 XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
+				 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
 		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack not done after %dus.\n",
-			 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
+			 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
 
 	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
 		     XELPDP_FORWARD_CLOCK_UNGATE,
@@ -1192,7 +1191,7 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
 
 	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
 				 lane_phy_current_status, 0,
-				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
+				 XE3PLPD_RESET_END_LATENCY_US, 0, NULL))
 		drm_warn(display->drm,
 			 "PHY %c failed to bring out of Lane reset after %dus.\n",
 			 phy_name(phy), XE3PLPD_RESET_END_LATENCY_US);
@@ -1674,7 +1673,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 		if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
 					 XELPDP_LANE_PCLK_PLL_ACK(0),
 					 XELPDP_LANE_PCLK_PLL_ACK(0),
-					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
+					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
 			drm_warn(display->drm, "PHY %c PLL MacCLK Ack assertion Timeout after %dus.\n",
 				 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
 
@@ -1702,7 +1701,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
 		if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
 					 lane_phy_pulse_status, lane_phy_pulse_status,
-					 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
+					 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
 			drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
 				 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
 
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index 9223487d764e..36abc2bdbd9b 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -7,7 +7,6 @@
 #define __INTEL_LT_PHY_REGS_H__
 
 #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
-#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
 #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
 #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
 #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
-- 
2.49.1

[PATCH 6/7] drm/i915/hdcp: Use the default 2 usec fast polling timeout

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

For whatever unknown reason the HDCP code is using a custom
10 usec fast polling timeout instead of the normal 2 usec
value. Switch to the standard value to get rid of the special
case.

The eventual aim is to get rid of the fast vs. slow timeout
entirely and switch over to poll_timeout_us().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 7195e8cf671c..d01733b6460e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -412,7 +412,7 @@ static int intel_hdcp_load_keys(struct intel_display *display)
 	/* Wait for the keys to load (500us) */
 	ret = intel_de_wait_custom(display, HDCP_KEY_STATUS,
 				   HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE,
-				   10, 1, &val);
+				   2, 1, &val);
 	if (ret)
 		return ret;
 	else if (!(val & HDCP_KEY_LOAD_STATUS))
-- 
2.49.1

[PATCH 7/7] drm/i915/pmdemand: Use the default 2 usec fast polling timeout

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

For whatever unknown reason the pmdemand code is using a custom
50 usec fast polling timeout instead of the normal 2 usec
value. Switch to the standard value to get rid of the special
case.

The eventual aim is to get rid of the fast vs. slow timeout
entirely and switch over to poll_timeout_us().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f52abd4e2eb0..22d8f720ae7d 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -464,7 +464,7 @@ static void intel_pmdemand_poll(struct intel_display *display)
 
 	ret = intel_de_wait_custom(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
 				   XELPDP_PMDEMAND_REQ_ENABLE, 0,
-				   50, timeout_ms, &status);
+				   2, timeout_ms, &status);
 
 	if (ret == -ETIMEDOUT)
 		drm_err(display->drm,
-- 
2.49.1

Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Jani Nikula]

On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The LT PHY code is abusing intel_de_wait_custom() in all kinds of weird
> ways. Get rid of the weird slow timeouts. If these are actually needed
> then the fast timeouts should really be specified as the default 2
> microscond or something.
>
> This will let us eventually nuke intel_de_wait_custom() and convert
> over to poll_timeout_us().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Cc: Suraj, yeah, why are these intel_de_wait_custom() in the first
place?

> ---
>  drivers/gpu/drm/i915/display/intel_lt_phy.c      | 11 +++++------
>  drivers/gpu/drm/i915/display/intel_lt_phy_regs.h |  1 -
>  2 files changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 6fb68157b322..cc1d6b7a7de4 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1178,10 +1178,9 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
>  	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
>  				 XELPDP_LANE_PCLK_PLL_ACK(0),
>  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> -				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
> -				 XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
> +				 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
>  		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack not done after %dus.\n",
> -			 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
> +			 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
>  
>  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
>  		     XELPDP_FORWARD_CLOCK_UNGATE,
> @@ -1192,7 +1191,7 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
>  
>  	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
>  				 lane_phy_current_status, 0,
> -				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
> +				 XE3PLPD_RESET_END_LATENCY_US, 0, NULL))
>  		drm_warn(display->drm,
>  			 "PHY %c failed to bring out of Lane reset after %dus.\n",
>  			 phy_name(phy), XE3PLPD_RESET_END_LATENCY_US);
> @@ -1674,7 +1673,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>  		if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
>  					 XELPDP_LANE_PCLK_PLL_ACK(0),
>  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> -					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
> +					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
>  			drm_warn(display->drm, "PHY %c PLL MacCLK Ack assertion Timeout after %dus.\n",
>  				 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
>  
> @@ -1702,7 +1701,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>  		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
>  		if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
>  					 lane_phy_pulse_status, lane_phy_pulse_status,
> -					 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> +					 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
>  			drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
>  				 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> index 9223487d764e..36abc2bdbd9b 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -7,7 +7,6 @@
>  #define __INTEL_LT_PHY_REGS_H__
>  
>  #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
> -#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
>  #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
>  #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
>  #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50

-- 
Jani Nikula, Intel

✓ CI.KUnit: success for drm/i915: Stop the intel_de_wait_custom() abuse

[Patchwork]

== Series Details ==

Series: drm/i915: Stop the intel_de_wait_custom() abuse
URL   : https://patchwork.freedesktop.org/series/157098/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[22:56:18] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:56:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[22:56:52] Starting KUnit Kernel (1/1)...
[22:56:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:56:52] ================== guc_buf (11 subtests) ===================
[22:56:52] [PASSED] test_smallest
[22:56:52] [PASSED] test_largest
[22:56:52] [PASSED] test_granular
[22:56:52] [PASSED] test_unique
[22:56:52] [PASSED] test_overlap
[22:56:52] [PASSED] test_reusable
[22:56:52] [PASSED] test_too_big
[22:56:52] [PASSED] test_flush
[22:56:52] [PASSED] test_lookup
[22:56:52] [PASSED] test_data
[22:56:52] [PASSED] test_class
[22:56:52] ===================== [PASSED] guc_buf =====================
[22:56:52] =================== guc_dbm (7 subtests) ===================
[22:56:52] [PASSED] test_empty
[22:56:52] [PASSED] test_default
[22:56:52] ======================== test_size  ========================
[22:56:52] [PASSED] 4
[22:56:52] [PASSED] 8
[22:56:52] [PASSED] 32
[22:56:52] [PASSED] 256
[22:56:52] ==================== [PASSED] test_size ====================
[22:56:52] ======================= test_reuse  ========================
[22:56:52] [PASSED] 4
[22:56:52] [PASSED] 8
[22:56:52] [PASSED] 32
[22:56:52] [PASSED] 256
[22:56:52] =================== [PASSED] test_reuse ====================
[22:56:52] =================== test_range_overlap  ====================
[22:56:52] [PASSED] 4
[22:56:52] [PASSED] 8
[22:56:52] [PASSED] 32
[22:56:52] [PASSED] 256
[22:56:52] =============== [PASSED] test_range_overlap ================
[22:56:52] =================== test_range_compact  ====================
[22:56:52] [PASSED] 4
[22:56:52] [PASSED] 8
[22:56:52] [PASSED] 32
[22:56:52] [PASSED] 256
[22:56:52] =============== [PASSED] test_range_compact ================
[22:56:52] ==================== test_range_spare  =====================
[22:56:52] [PASSED] 4
[22:56:52] [PASSED] 8
[22:56:52] [PASSED] 32
[22:56:52] [PASSED] 256
[22:56:52] ================ [PASSED] test_range_spare =================
[22:56:52] ===================== [PASSED] guc_dbm =====================
[22:56:52] =================== guc_idm (6 subtests) ===================
[22:56:52] [PASSED] bad_init
[22:56:52] [PASSED] no_init
[22:56:52] [PASSED] init_fini
[22:56:52] [PASSED] check_used
[22:56:52] [PASSED] check_quota
[22:56:52] [PASSED] check_all
[22:56:52] ===================== [PASSED] guc_idm =====================
[22:56:52] ================== no_relay (3 subtests) ===================
[22:56:52] [PASSED] xe_drops_guc2pf_if_not_ready
[22:56:52] [PASSED] xe_drops_guc2vf_if_not_ready
[22:56:52] [PASSED] xe_rejects_send_if_not_ready
[22:56:52] ==================== [PASSED] no_relay =====================
[22:56:52] ================== pf_relay (14 subtests) ==================
[22:56:52] [PASSED] pf_rejects_guc2pf_too_short
[22:56:52] [PASSED] pf_rejects_guc2pf_too_long
[22:56:52] [PASSED] pf_rejects_guc2pf_no_payload
[22:56:52] [PASSED] pf_fails_no_payload
[22:56:52] [PASSED] pf_fails_bad_origin
[22:56:52] [PASSED] pf_fails_bad_type
[22:56:52] [PASSED] pf_txn_reports_error
[22:56:52] [PASSED] pf_txn_sends_pf2guc
[22:56:52] [PASSED] pf_sends_pf2guc
[22:56:52] [SKIPPED] pf_loopback_nop
[22:56:52] [SKIPPED] pf_loopback_echo
[22:56:52] [SKIPPED] pf_loopback_fail
[22:56:52] [SKIPPED] pf_loopback_busy
[22:56:52] [SKIPPED] pf_loopback_retry
[22:56:52] ==================== [PASSED] pf_relay =====================
[22:56:52] ================== vf_relay (3 subtests) ===================
[22:56:52] [PASSED] vf_rejects_guc2vf_too_short
[22:56:52] [PASSED] vf_rejects_guc2vf_too_long
[22:56:52] [PASSED] vf_rejects_guc2vf_no_payload
[22:56:52] ==================== [PASSED] vf_relay =====================
[22:56:52] ===================== lmtt (1 subtest) =====================
[22:56:52] ======================== test_ops  =========================
[22:56:52] [PASSED] 2-level
[22:56:52] [PASSED] multi-level
[22:56:52] ==================== [PASSED] test_ops =====================
[22:56:52] ====================== [PASSED] lmtt =======================
[22:56:52] ================= pf_service (11 subtests) =================
[22:56:52] [PASSED] pf_negotiate_any
[22:56:52] [PASSED] pf_negotiate_base_match
[22:56:52] [PASSED] pf_negotiate_base_newer
[22:56:52] [PASSED] pf_negotiate_base_next
[22:56:52] [SKIPPED] pf_negotiate_base_older
[22:56:52] [PASSED] pf_negotiate_base_prev
[22:56:52] [PASSED] pf_negotiate_latest_match
[22:56:52] [PASSED] pf_negotiate_latest_newer
[22:56:52] [PASSED] pf_negotiate_latest_next
[22:56:52] [SKIPPED] pf_negotiate_latest_older
[22:56:52] [SKIPPED] pf_negotiate_latest_prev
[22:56:52] =================== [PASSED] pf_service ====================
[22:56:52] ================= xe_guc_g2g (2 subtests) ==================
[22:56:52] ============== xe_live_guc_g2g_kunit_default  ==============
[22:56:52] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[22:56:52] ============== xe_live_guc_g2g_kunit_allmem  ===============
[22:56:52] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[22:56:52] =================== [SKIPPED] xe_guc_g2g ===================
[22:56:52] =================== xe_mocs (2 subtests) ===================
[22:56:52] ================ xe_live_mocs_kernel_kunit  ================
[22:56:52] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[22:56:52] ================ xe_live_mocs_reset_kunit  =================
[22:56:52] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[22:56:52] ==================== [SKIPPED] xe_mocs =====================
[22:56:52] ================= xe_migrate (2 subtests) ==================
[22:56:52] ================= xe_migrate_sanity_kunit  =================
[22:56:52] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[22:56:52] ================== xe_validate_ccs_kunit  ==================
[22:56:52] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[22:56:52] =================== [SKIPPED] xe_migrate ===================
[22:56:52] ================== xe_dma_buf (1 subtest) ==================
[22:56:52] ==================== xe_dma_buf_kunit  =====================
[22:56:52] ================ [SKIPPED] xe_dma_buf_kunit ================
[22:56:52] =================== [SKIPPED] xe_dma_buf ===================
[22:56:52] ================= xe_bo_shrink (1 subtest) =================
[22:56:52] =================== xe_bo_shrink_kunit  ====================
[22:56:52] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[22:56:52] ================== [SKIPPED] xe_bo_shrink ==================
[22:56:52] ==================== xe_bo (2 subtests) ====================
[22:56:52] ================== xe_ccs_migrate_kunit  ===================
[22:56:52] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[22:56:52] ==================== xe_bo_evict_kunit  ====================
[22:56:52] =============== [SKIPPED] xe_bo_evict_kunit ================
[22:56:52] ===================== [SKIPPED] xe_bo ======================
[22:56:52] ==================== args (11 subtests) ====================
[22:56:52] [PASSED] count_args_test
[22:56:52] [PASSED] call_args_example
[22:56:52] [PASSED] call_args_test
[22:56:52] [PASSED] drop_first_arg_example
[22:56:52] [PASSED] drop_first_arg_test
[22:56:52] [PASSED] first_arg_example
[22:56:52] [PASSED] first_arg_test
[22:56:52] [PASSED] last_arg_example
[22:56:52] [PASSED] last_arg_test
[22:56:52] [PASSED] pick_arg_example
[22:56:52] [PASSED] sep_comma_example
[22:56:52] ====================== [PASSED] args =======================
[22:56:52] =================== xe_pci (3 subtests) ====================
[22:56:52] ==================== check_graphics_ip  ====================
[22:56:52] [PASSED] 12.00 Xe_LP
[22:56:52] [PASSED] 12.10 Xe_LP+
[22:56:52] [PASSED] 12.55 Xe_HPG
[22:56:52] [PASSED] 12.60 Xe_HPC
[22:56:52] [PASSED] 12.70 Xe_LPG
[22:56:52] [PASSED] 12.71 Xe_LPG
[22:56:52] [PASSED] 12.74 Xe_LPG+
[22:56:52] [PASSED] 20.01 Xe2_HPG
[22:56:52] [PASSED] 20.02 Xe2_HPG
[22:56:52] [PASSED] 20.04 Xe2_LPG
[22:56:52] [PASSED] 30.00 Xe3_LPG
[22:56:52] [PASSED] 30.01 Xe3_LPG
[22:56:52] [PASSED] 30.03 Xe3_LPG
[22:56:52] [PASSED] 30.04 Xe3_LPG
[22:56:52] [PASSED] 30.05 Xe3_LPG
[22:56:52] [PASSED] 35.11 Xe3p_XPC
[22:56:52] ================ [PASSED] check_graphics_ip ================
[22:56:52] ===================== check_media_ip  ======================
[22:56:52] [PASSED] 12.00 Xe_M
[22:56:52] [PASSED] 12.55 Xe_HPM
[22:56:52] [PASSED] 13.00 Xe_LPM+
[22:56:52] [PASSED] 13.01 Xe2_HPM
[22:56:52] [PASSED] 20.00 Xe2_LPM
[22:56:52] [PASSED] 30.00 Xe3_LPM
[22:56:52] [PASSED] 30.02 Xe3_LPM
[22:56:52] [PASSED] 35.00 Xe3p_LPM
[22:56:52] [PASSED] 35.03 Xe3p_HPM
[22:56:52] ================= [PASSED] check_media_ip ==================
[22:56:52] =================== check_platform_desc  ===================
[22:56:52] [PASSED] 0x9A60 (TIGERLAKE)
[22:56:52] [PASSED] 0x9A68 (TIGERLAKE)
[22:56:52] [PASSED] 0x9A70 (TIGERLAKE)
[22:56:52] [PASSED] 0x9A40 (TIGERLAKE)
[22:56:52] [PASSED] 0x9A49 (TIGERLAKE)
[22:56:52] [PASSED] 0x9A59 (TIGERLAKE)
[22:56:52] [PASSED] 0x9A78 (TIGERLAKE)
[22:56:52] [PASSED] 0x9AC0 (TIGERLAKE)
[22:56:52] [PASSED] 0x9AC9 (TIGERLAKE)
[22:56:52] [PASSED] 0x9AD9 (TIGERLAKE)
[22:56:52] [PASSED] 0x9AF8 (TIGERLAKE)
[22:56:52] [PASSED] 0x4C80 (ROCKETLAKE)
[22:56:52] [PASSED] 0x4C8A (ROCKETLAKE)
[22:56:52] [PASSED] 0x4C8B (ROCKETLAKE)
[22:56:52] [PASSED] 0x4C8C (ROCKETLAKE)
[22:56:52] [PASSED] 0x4C90 (ROCKETLAKE)
[22:56:52] [PASSED] 0x4C9A (ROCKETLAKE)
[22:56:52] [PASSED] 0x4680 (ALDERLAKE_S)
[22:56:52] [PASSED] 0x4682 (ALDERLAKE_S)
[22:56:52] [PASSED] 0x4688 (ALDERLAKE_S)
[22:56:52] [PASSED] 0x468A (ALDERLAKE_S)
[22:56:52] [PASSED] 0x468B (ALDERLAKE_S)
[22:56:52] [PASSED] 0x4690 (ALDERLAKE_S)
[22:56:52] [PASSED] 0x4692 (ALDERLAKE_S)
[22:56:52] [PASSED] 0x4693 (ALDERLAKE_S)
[22:56:52] [PASSED] 0x46A0 (ALDERLAKE_P)
[22:56:52] [PASSED] 0x46A1 (ALDERLAKE_P)
[22:56:52] [PASSED] 0x46A2 (ALDERLAKE_P)
[22:56:52] [PASSED] 0x46A3 (ALDERLAKE_P)
[22:56:52] [PASSED] 0x46A6 (ALDERLAKE_P)
[22:56:52] [PASSED] 0x46A8 (ALDERLAKE_P)
[22:56:52] [PASSED] 0x46AA (ALDERLAKE_P)
[22:56:52] [PASSED] 0x462A (ALDERLAKE_P)
[22:56:52] [PASSED] 0x4626 (ALDERLAKE_P)
[22:56:52] [PASSED] 0x4628 (ALDERLAKE_P)
[22:56:52] [PASSED] 0x46B0 (ALDERLAKE_P)
[22:56:52] [PASSED] 0x46B1 (ALDERLAKE_P)
[22:56:52] [PASSED] 0x46B2 (ALDERLAKE_P)
[22:56:52] [PASSED] 0x46B3 (ALDERLAKE_P)
[22:56:52] [PASSED] 0x46C0 (ALDERLAKE_P)
[22:56:52] [PASSED] 0x46C1 (ALDERLAKE_P)
[22:56:52] [PASSED] 0x46C2 (ALDERLAKE_P)
[22:56:52] [PASSED] 0x46C3 (ALDERLAKE_P)
[22:56:52] [PASSED] 0x46D0 (ALDERLAKE_N)
[22:56:52] [PASSED] 0x46D1 (ALDERLAKE_N)
[22:56:52] [PASSED] 0x46D2 (ALDERLAKE_N)
[22:56:52] [PASSED] 0x46D3 (ALDERLAKE_N)
[22:56:52] [PASSED] 0x46D4 (ALDERLAKE_N)
[22:56:52] [PASSED] 0xA721 (ALDERLAKE_P)
[22:56:52] [PASSED] 0xA7A1 (ALDERLAKE_P)
[22:56:52] [PASSED] 0xA7A9 (ALDERLAKE_P)
[22:56:52] [PASSED] 0xA7AC (ALDERLAKE_P)
[22:56:52] [PASSED] 0xA7AD (ALDERLAKE_P)
[22:56:52] [PASSED] 0xA720 (ALDERLAKE_P)
[22:56:52] [PASSED] 0xA7A0 (ALDERLAKE_P)
[22:56:52] [PASSED] 0xA7A8 (ALDERLAKE_P)
[22:56:52] [PASSED] 0xA7AA (ALDERLAKE_P)
[22:56:52] [PASSED] 0xA7AB (ALDERLAKE_P)
[22:56:52] [PASSED] 0xA780 (ALDERLAKE_S)
[22:56:52] [PASSED] 0xA781 (ALDERLAKE_S)
[22:56:52] [PASSED] 0xA782 (ALDERLAKE_S)
[22:56:52] [PASSED] 0xA783 (ALDERLAKE_S)
[22:56:52] [PASSED] 0xA788 (ALDERLAKE_S)
[22:56:52] [PASSED] 0xA789 (ALDERLAKE_S)
[22:56:52] [PASSED] 0xA78A (ALDERLAKE_S)
[22:56:52] [PASSED] 0xA78B (ALDERLAKE_S)
[22:56:52] [PASSED] 0x4905 (DG1)
[22:56:52] [PASSED] 0x4906 (DG1)
[22:56:52] [PASSED] 0x4907 (DG1)
[22:56:52] [PASSED] 0x4908 (DG1)
[22:56:52] [PASSED] 0x4909 (DG1)
[22:56:52] [PASSED] 0x56C0 (DG2)
[22:56:52] [PASSED] 0x56C2 (DG2)
[22:56:52] [PASSED] 0x56C1 (DG2)
[22:56:52] [PASSED] 0x7D51 (METEORLAKE)
[22:56:52] [PASSED] 0x7DD1 (METEORLAKE)
[22:56:52] [PASSED] 0x7D41 (METEORLAKE)
[22:56:52] [PASSED] 0x7D67 (METEORLAKE)
[22:56:52] [PASSED] 0xB640 (METEORLAKE)
[22:56:52] [PASSED] 0x56A0 (DG2)
[22:56:52] [PASSED] 0x56A1 (DG2)
[22:56:52] [PASSED] 0x56A2 (DG2)
[22:56:52] [PASSED] 0x56BE (DG2)
[22:56:52] [PASSED] 0x56BF (DG2)
[22:56:52] [PASSED] 0x5690 (DG2)
[22:56:52] [PASSED] 0x5691 (DG2)
[22:56:52] [PASSED] 0x5692 (DG2)
[22:56:52] [PASSED] 0x56A5 (DG2)
[22:56:52] [PASSED] 0x56A6 (DG2)
[22:56:52] [PASSED] 0x56B0 (DG2)
[22:56:52] [PASSED] 0x56B1 (DG2)
[22:56:52] [PASSED] 0x56BA (DG2)
[22:56:52] [PASSED] 0x56BB (DG2)
[22:56:52] [PASSED] 0x56BC (DG2)
[22:56:52] [PASSED] 0x56BD (DG2)
[22:56:52] [PASSED] 0x5693 (DG2)
[22:56:52] [PASSED] 0x5694 (DG2)
[22:56:52] [PASSED] 0x5695 (DG2)
[22:56:52] [PASSED] 0x56A3 (DG2)
[22:56:52] [PASSED] 0x56A4 (DG2)
[22:56:52] [PASSED] 0x56B2 (DG2)
[22:56:52] [PASSED] 0x56B3 (DG2)
[22:56:52] [PASSED] 0x5696 (DG2)
[22:56:52] [PASSED] 0x5697 (DG2)
[22:56:52] [PASSED] 0xB69 (PVC)
[22:56:52] [PASSED] 0xB6E (PVC)
[22:56:52] [PASSED] 0xBD4 (PVC)
[22:56:52] [PASSED] 0xBD5 (PVC)
[22:56:52] [PASSED] 0xBD6 (PVC)
[22:56:52] [PASSED] 0xBD7 (PVC)
[22:56:52] [PASSED] 0xBD8 (PVC)
[22:56:52] [PASSED] 0xBD9 (PVC)
[22:56:52] [PASSED] 0xBDA (PVC)
[22:56:52] [PASSED] 0xBDB (PVC)
[22:56:52] [PASSED] 0xBE0 (PVC)
[22:56:52] [PASSED] 0xBE1 (PVC)
[22:56:52] [PASSED] 0xBE5 (PVC)
[22:56:52] [PASSED] 0x7D40 (METEORLAKE)
[22:56:52] [PASSED] 0x7D45 (METEORLAKE)
[22:56:52] [PASSED] 0x7D55 (METEORLAKE)
[22:56:52] [PASSED] 0x7D60 (METEORLAKE)
[22:56:52] [PASSED] 0x7DD5 (METEORLAKE)
[22:56:52] [PASSED] 0x6420 (LUNARLAKE)
[22:56:52] [PASSED] 0x64A0 (LUNARLAKE)
[22:56:52] [PASSED] 0x64B0 (LUNARLAKE)
[22:56:52] [PASSED] 0xE202 (BATTLEMAGE)
[22:56:52] [PASSED] 0xE209 (BATTLEMAGE)
[22:56:52] [PASSED] 0xE20B (BATTLEMAGE)
[22:56:52] [PASSED] 0xE20C (BATTLEMAGE)
[22:56:52] [PASSED] 0xE20D (BATTLEMAGE)
[22:56:52] [PASSED] 0xE210 (BATTLEMAGE)
[22:56:52] [PASSED] 0xE211 (BATTLEMAGE)
[22:56:52] [PASSED] 0xE212 (BATTLEMAGE)
[22:56:52] [PASSED] 0xE216 (BATTLEMAGE)
[22:56:52] [PASSED] 0xE220 (BATTLEMAGE)
[22:56:52] [PASSED] 0xE221 (BATTLEMAGE)
[22:56:52] [PASSED] 0xE222 (BATTLEMAGE)
[22:56:52] [PASSED] 0xE223 (BATTLEMAGE)
[22:56:52] [PASSED] 0xB080 (PANTHERLAKE)
[22:56:52] [PASSED] 0xB081 (PANTHERLAKE)
[22:56:52] [PASSED] 0xB082 (PANTHERLAKE)
[22:56:52] [PASSED] 0xB083 (PANTHERLAKE)
[22:56:52] [PASSED] 0xB084 (PANTHERLAKE)
[22:56:52] [PASSED] 0xB085 (PANTHERLAKE)
[22:56:52] [PASSED] 0xB086 (PANTHERLAKE)
[22:56:52] [PASSED] 0xB087 (PANTHERLAKE)
[22:56:52] [PASSED] 0xB08F (PANTHERLAKE)
[22:56:52] [PASSED] 0xB090 (PANTHERLAKE)
[22:56:52] [PASSED] 0xB0A0 (PANTHERLAKE)
[22:56:52] [PASSED] 0xB0B0 (PANTHERLAKE)
[22:56:52] [PASSED] 0xD740 (NOVALAKE_S)
[22:56:52] [PASSED] 0xD741 (NOVALAKE_S)
[22:56:52] [PASSED] 0xD742 (NOVALAKE_S)
[22:56:52] [PASSED] 0xD743 (NOVALAKE_S)
[22:56:52] [PASSED] 0xD744 (NOVALAKE_S)
[22:56:52] [PASSED] 0xD745 (NOVALAKE_S)
[22:56:52] [PASSED] 0x674C (CRESCENTISLAND)
[22:56:52] [PASSED] 0xFD80 (PANTHERLAKE)
[22:56:52] [PASSED] 0xFD81 (PANTHERLAKE)
[22:56:52] =============== [PASSED] check_platform_desc ===============
[22:56:52] ===================== [PASSED] xe_pci ======================
[22:56:52] =================== xe_rtp (2 subtests) ====================
[22:56:52] =============== xe_rtp_process_to_sr_tests  ================
[22:56:52] [PASSED] coalesce-same-reg
[22:56:52] [PASSED] no-match-no-add
[22:56:52] [PASSED] match-or
[22:56:52] [PASSED] match-or-xfail
[22:56:52] [PASSED] no-match-no-add-multiple-rules
[22:56:52] [PASSED] two-regs-two-entries
[22:56:52] [PASSED] clr-one-set-other
[22:56:52] [PASSED] set-field
[22:56:52] [PASSED] conflict-duplicate
[22:56:52] [PASSED] conflict-not-disjoint
[22:56:52] [PASSED] conflict-reg-type
[22:56:52] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[22:56:52] ================== xe_rtp_process_tests  ===================
[22:56:52] [PASSED] active1
[22:56:52] [PASSED] active2
[22:56:52] [PASSED] active-inactive
[22:56:52] [PASSED] inactive-active
[22:56:52] [PASSED] inactive-1st_or_active-inactive
[22:56:52] [PASSED] inactive-2nd_or_active-inactive
[22:56:52] [PASSED] inactive-last_or_active-inactive
stty: 'standard input': Inappropriate ioctl for device
[22:56:52] [PASSED] inactive-no_or_active-inactive
[22:56:52] ============== [PASSED] xe_rtp_process_tests ===============
[22:56:52] ===================== [PASSED] xe_rtp ======================
[22:56:52] ==================== xe_wa (1 subtest) =====================
[22:56:52] ======================== xe_wa_gt  =========================
[22:56:52] [PASSED] TIGERLAKE B0
[22:56:52] [PASSED] DG1 A0
[22:56:52] [PASSED] DG1 B0
[22:56:52] [PASSED] ALDERLAKE_S A0
[22:56:52] [PASSED] ALDERLAKE_S B0
[22:56:52] [PASSED] ALDERLAKE_S C0
[22:56:52] [PASSED] ALDERLAKE_S D0
[22:56:52] [PASSED] ALDERLAKE_P A0
[22:56:52] [PASSED] ALDERLAKE_P B0
[22:56:52] [PASSED] ALDERLAKE_P C0
[22:56:52] [PASSED] ALDERLAKE_S RPLS D0
[22:56:52] [PASSED] ALDERLAKE_P RPLU E0
[22:56:52] [PASSED] DG2 G10 C0
[22:56:52] [PASSED] DG2 G11 B1
[22:56:52] [PASSED] DG2 G12 A1
[22:56:52] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[22:56:52] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[22:56:52] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[22:56:52] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[22:56:52] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[22:56:52] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[22:56:52] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[22:56:52] ==================== [PASSED] xe_wa_gt =====================
[22:56:52] ====================== [PASSED] xe_wa ======================
[22:56:52] ============================================================
[22:56:52] Testing complete. Ran 318 tests: passed: 300, skipped: 18
[22:56:52] Elapsed time: 34.834s total, 4.235s configuring, 30.231s building, 0.331s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[22:56:53] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:56:54] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[22:57:19] Starting KUnit Kernel (1/1)...
[22:57:19] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:57:19] ============ drm_test_pick_cmdline (2 subtests) ============
[22:57:19] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[22:57:19] =============== drm_test_pick_cmdline_named  ===============
[22:57:19] [PASSED] NTSC
[22:57:19] [PASSED] NTSC-J
[22:57:19] [PASSED] PAL
[22:57:19] [PASSED] PAL-M
[22:57:19] =========== [PASSED] drm_test_pick_cmdline_named ===========
[22:57:19] ============== [PASSED] drm_test_pick_cmdline ==============
[22:57:19] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[22:57:19] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[22:57:19] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[22:57:19] =========== drm_validate_clone_mode (2 subtests) ===========
[22:57:19] ============== drm_test_check_in_clone_mode  ===============
[22:57:19] [PASSED] in_clone_mode
[22:57:19] [PASSED] not_in_clone_mode
[22:57:19] ========== [PASSED] drm_test_check_in_clone_mode ===========
[22:57:19] =============== drm_test_check_valid_clones  ===============
[22:57:19] [PASSED] not_in_clone_mode
[22:57:19] [PASSED] valid_clone
[22:57:19] [PASSED] invalid_clone
[22:57:19] =========== [PASSED] drm_test_check_valid_clones ===========
[22:57:19] ============= [PASSED] drm_validate_clone_mode =============
[22:57:19] ============= drm_validate_modeset (1 subtest) =============
[22:57:19] [PASSED] drm_test_check_connector_changed_modeset
[22:57:19] ============== [PASSED] drm_validate_modeset ===============
[22:57:19] ====== drm_test_bridge_get_current_state (2 subtests) ======
[22:57:19] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[22:57:19] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[22:57:19] ======== [PASSED] drm_test_bridge_get_current_state ========
[22:57:19] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[22:57:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[22:57:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[22:57:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[22:57:19] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[22:57:19] ============== drm_bridge_alloc (2 subtests) ===============
[22:57:19] [PASSED] drm_test_drm_bridge_alloc_basic
[22:57:19] [PASSED] drm_test_drm_bridge_alloc_get_put
[22:57:19] ================ [PASSED] drm_bridge_alloc =================
[22:57:19] ================== drm_buddy (8 subtests) ==================
[22:57:19] [PASSED] drm_test_buddy_alloc_limit
[22:57:19] [PASSED] drm_test_buddy_alloc_optimistic
[22:57:19] [PASSED] drm_test_buddy_alloc_pessimistic
[22:57:19] [PASSED] drm_test_buddy_alloc_pathological
[22:57:19] [PASSED] drm_test_buddy_alloc_contiguous
[22:57:19] [PASSED] drm_test_buddy_alloc_clear
[22:57:19] [PASSED] drm_test_buddy_alloc_range_bias
[22:57:19] [PASSED] drm_test_buddy_fragmentation_performance
[22:57:19] ==================== [PASSED] drm_buddy ====================
[22:57:19] ============= drm_cmdline_parser (40 subtests) =============
[22:57:19] [PASSED] drm_test_cmdline_force_d_only
[22:57:19] [PASSED] drm_test_cmdline_force_D_only_dvi
[22:57:19] [PASSED] drm_test_cmdline_force_D_only_hdmi
[22:57:19] [PASSED] drm_test_cmdline_force_D_only_not_digital
[22:57:19] [PASSED] drm_test_cmdline_force_e_only
[22:57:19] [PASSED] drm_test_cmdline_res
[22:57:19] [PASSED] drm_test_cmdline_res_vesa
[22:57:19] [PASSED] drm_test_cmdline_res_vesa_rblank
[22:57:19] [PASSED] drm_test_cmdline_res_rblank
[22:57:19] [PASSED] drm_test_cmdline_res_bpp
[22:57:19] [PASSED] drm_test_cmdline_res_refresh
[22:57:19] [PASSED] drm_test_cmdline_res_bpp_refresh
[22:57:19] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[22:57:19] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[22:57:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[22:57:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[22:57:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[22:57:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[22:57:19] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[22:57:19] [PASSED] drm_test_cmdline_res_margins_force_on
[22:57:19] [PASSED] drm_test_cmdline_res_vesa_margins
[22:57:19] [PASSED] drm_test_cmdline_name
[22:57:19] [PASSED] drm_test_cmdline_name_bpp
[22:57:19] [PASSED] drm_test_cmdline_name_option
[22:57:19] [PASSED] drm_test_cmdline_name_bpp_option
[22:57:19] [PASSED] drm_test_cmdline_rotate_0
[22:57:19] [PASSED] drm_test_cmdline_rotate_90
[22:57:19] [PASSED] drm_test_cmdline_rotate_180
[22:57:19] [PASSED] drm_test_cmdline_rotate_270
[22:57:19] [PASSED] drm_test_cmdline_hmirror
[22:57:19] [PASSED] drm_test_cmdline_vmirror
[22:57:19] [PASSED] drm_test_cmdline_margin_options
[22:57:19] [PASSED] drm_test_cmdline_multiple_options
[22:57:19] [PASSED] drm_test_cmdline_bpp_extra_and_option
[22:57:19] [PASSED] drm_test_cmdline_extra_and_option
[22:57:19] [PASSED] drm_test_cmdline_freestanding_options
[22:57:19] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[22:57:19] [PASSED] drm_test_cmdline_panel_orientation
[22:57:19] ================ drm_test_cmdline_invalid  =================
[22:57:19] [PASSED] margin_only
[22:57:19] [PASSED] interlace_only
[22:57:19] [PASSED] res_missing_x
[22:57:19] [PASSED] res_missing_y
[22:57:19] [PASSED] res_bad_y
[22:57:19] [PASSED] res_missing_y_bpp
[22:57:19] [PASSED] res_bad_bpp
[22:57:19] [PASSED] res_bad_refresh
[22:57:19] [PASSED] res_bpp_refresh_force_on_off
[22:57:19] [PASSED] res_invalid_mode
[22:57:19] [PASSED] res_bpp_wrong_place_mode
[22:57:19] [PASSED] name_bpp_refresh
[22:57:19] [PASSED] name_refresh
[22:57:19] [PASSED] name_refresh_wrong_mode
[22:57:19] [PASSED] name_refresh_invalid_mode
[22:57:19] [PASSED] rotate_multiple
[22:57:19] [PASSED] rotate_invalid_val
[22:57:19] [PASSED] rotate_truncated
[22:57:19] [PASSED] invalid_option
[22:57:19] [PASSED] invalid_tv_option
[22:57:19] [PASSED] truncated_tv_option
[22:57:19] ============ [PASSED] drm_test_cmdline_invalid =============
[22:57:19] =============== drm_test_cmdline_tv_options  ===============
[22:57:19] [PASSED] NTSC
[22:57:19] [PASSED] NTSC_443
[22:57:19] [PASSED] NTSC_J
[22:57:19] [PASSED] PAL
[22:57:19] [PASSED] PAL_M
[22:57:19] [PASSED] PAL_N
[22:57:19] [PASSED] SECAM
[22:57:19] [PASSED] MONO_525
[22:57:19] [PASSED] MONO_625
[22:57:19] =========== [PASSED] drm_test_cmdline_tv_options ===========
[22:57:19] =============== [PASSED] drm_cmdline_parser ================
[22:57:19] ========== drmm_connector_hdmi_init (20 subtests) ==========
[22:57:19] [PASSED] drm_test_connector_hdmi_init_valid
[22:57:19] [PASSED] drm_test_connector_hdmi_init_bpc_8
[22:57:19] [PASSED] drm_test_connector_hdmi_init_bpc_10
[22:57:19] [PASSED] drm_test_connector_hdmi_init_bpc_12
[22:57:19] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[22:57:19] [PASSED] drm_test_connector_hdmi_init_bpc_null
[22:57:19] [PASSED] drm_test_connector_hdmi_init_formats_empty
[22:57:19] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[22:57:19] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[22:57:19] [PASSED] supported_formats=0x9 yuv420_allowed=1
[22:57:19] [PASSED] supported_formats=0x9 yuv420_allowed=0
[22:57:19] [PASSED] supported_formats=0x3 yuv420_allowed=1
[22:57:19] [PASSED] supported_formats=0x3 yuv420_allowed=0
[22:57:19] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[22:57:19] [PASSED] drm_test_connector_hdmi_init_null_ddc
[22:57:19] [PASSED] drm_test_connector_hdmi_init_null_product
[22:57:19] [PASSED] drm_test_connector_hdmi_init_null_vendor
[22:57:19] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[22:57:19] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[22:57:19] [PASSED] drm_test_connector_hdmi_init_product_valid
[22:57:19] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[22:57:19] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[22:57:19] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[22:57:19] ========= drm_test_connector_hdmi_init_type_valid  =========
[22:57:19] [PASSED] HDMI-A
[22:57:19] [PASSED] HDMI-B
[22:57:19] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[22:57:19] ======== drm_test_connector_hdmi_init_type_invalid  ========
[22:57:19] [PASSED] Unknown
[22:57:19] [PASSED] VGA
[22:57:19] [PASSED] DVI-I
[22:57:19] [PASSED] DVI-D
[22:57:19] [PASSED] DVI-A
[22:57:19] [PASSED] Composite
[22:57:19] [PASSED] SVIDEO
[22:57:19] [PASSED] LVDS
[22:57:19] [PASSED] Component
[22:57:19] [PASSED] DIN
[22:57:19] [PASSED] DP
[22:57:19] [PASSED] TV
[22:57:19] [PASSED] eDP
[22:57:19] [PASSED] Virtual
[22:57:19] [PASSED] DSI
[22:57:19] [PASSED] DPI
[22:57:19] [PASSED] Writeback
[22:57:19] [PASSED] SPI
[22:57:19] [PASSED] USB
[22:57:19] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[22:57:19] ============ [PASSED] drmm_connector_hdmi_init =============
[22:57:19] ============= drmm_connector_init (3 subtests) =============
[22:57:19] [PASSED] drm_test_drmm_connector_init
[22:57:19] [PASSED] drm_test_drmm_connector_init_null_ddc
[22:57:19] ========= drm_test_drmm_connector_init_type_valid  =========
[22:57:19] [PASSED] Unknown
[22:57:19] [PASSED] VGA
[22:57:19] [PASSED] DVI-I
[22:57:19] [PASSED] DVI-D
[22:57:19] [PASSED] DVI-A
[22:57:19] [PASSED] Composite
[22:57:19] [PASSED] SVIDEO
[22:57:19] [PASSED] LVDS
[22:57:19] [PASSED] Component
[22:57:19] [PASSED] DIN
[22:57:19] [PASSED] DP
[22:57:19] [PASSED] HDMI-A
[22:57:19] [PASSED] HDMI-B
[22:57:19] [PASSED] TV
[22:57:19] [PASSED] eDP
[22:57:19] [PASSED] Virtual
[22:57:19] [PASSED] DSI
[22:57:19] [PASSED] DPI
[22:57:19] [PASSED] Writeback
[22:57:19] [PASSED] SPI
[22:57:19] [PASSED] USB
[22:57:19] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[22:57:19] =============== [PASSED] drmm_connector_init ===============
[22:57:19] ========= drm_connector_dynamic_init (6 subtests) ==========
[22:57:19] [PASSED] drm_test_drm_connector_dynamic_init
[22:57:19] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[22:57:19] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[22:57:19] [PASSED] drm_test_drm_connector_dynamic_init_properties
[22:57:19] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[22:57:19] [PASSED] Unknown
[22:57:19] [PASSED] VGA
[22:57:19] [PASSED] DVI-I
[22:57:19] [PASSED] DVI-D
[22:57:19] [PASSED] DVI-A
[22:57:19] [PASSED] Composite
[22:57:19] [PASSED] SVIDEO
[22:57:19] [PASSED] LVDS
[22:57:19] [PASSED] Component
[22:57:19] [PASSED] DIN
[22:57:19] [PASSED] DP
[22:57:19] [PASSED] HDMI-A
[22:57:19] [PASSED] HDMI-B
[22:57:19] [PASSED] TV
[22:57:19] [PASSED] eDP
[22:57:19] [PASSED] Virtual
[22:57:19] [PASSED] DSI
[22:57:19] [PASSED] DPI
[22:57:19] [PASSED] Writeback
[22:57:19] [PASSED] SPI
[22:57:19] [PASSED] USB
[22:57:19] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[22:57:20] ======== drm_test_drm_connector_dynamic_init_name  =========
[22:57:20] [PASSED] Unknown
[22:57:20] [PASSED] VGA
[22:57:20] [PASSED] DVI-I
[22:57:20] [PASSED] DVI-D
[22:57:20] [PASSED] DVI-A
[22:57:20] [PASSED] Composite
[22:57:20] [PASSED] SVIDEO
[22:57:20] [PASSED] LVDS
[22:57:20] [PASSED] Component
[22:57:20] [PASSED] DIN
[22:57:20] [PASSED] DP
[22:57:20] [PASSED] HDMI-A
[22:57:20] [PASSED] HDMI-B
[22:57:20] [PASSED] TV
[22:57:20] [PASSED] eDP
[22:57:20] [PASSED] Virtual
[22:57:20] [PASSED] DSI
[22:57:20] [PASSED] DPI
[22:57:20] [PASSED] Writeback
[22:57:20] [PASSED] SPI
[22:57:20] [PASSED] USB
[22:57:20] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[22:57:20] =========== [PASSED] drm_connector_dynamic_init ============
[22:57:20] ==== drm_connector_dynamic_register_early (4 subtests) =====
[22:57:20] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[22:57:20] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[22:57:20] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[22:57:20] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[22:57:20] ====== [PASSED] drm_connector_dynamic_register_early =======
[22:57:20] ======= drm_connector_dynamic_register (7 subtests) ========
[22:57:20] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[22:57:20] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[22:57:20] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[22:57:20] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[22:57:20] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[22:57:20] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[22:57:20] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[22:57:20] ========= [PASSED] drm_connector_dynamic_register ==========
[22:57:20] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[22:57:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[22:57:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[22:57:20] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[22:57:20] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[22:57:20] ========== drm_test_get_tv_mode_from_name_valid  ===========
[22:57:20] [PASSED] NTSC
[22:57:20] [PASSED] NTSC-443
[22:57:20] [PASSED] NTSC-J
[22:57:20] [PASSED] PAL
[22:57:20] [PASSED] PAL-M
[22:57:20] [PASSED] PAL-N
[22:57:20] [PASSED] SECAM
[22:57:20] [PASSED] Mono
[22:57:20] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[22:57:20] [PASSED] drm_test_get_tv_mode_from_name_truncated
[22:57:20] ============ [PASSED] drm_get_tv_mode_from_name ============
[22:57:20] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[22:57:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[22:57:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[22:57:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[22:57:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[22:57:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[22:57:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[22:57:20] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[22:57:20] [PASSED] VIC 96
[22:57:20] [PASSED] VIC 97
[22:57:20] [PASSED] VIC 101
[22:57:20] [PASSED] VIC 102
[22:57:20] [PASSED] VIC 106
[22:57:20] [PASSED] VIC 107
[22:57:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[22:57:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[22:57:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[22:57:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[22:57:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[22:57:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[22:57:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[22:57:20] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[22:57:20] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[22:57:20] [PASSED] Automatic
[22:57:20] [PASSED] Full
[22:57:20] [PASSED] Limited 16:235
[22:57:20] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[22:57:20] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[22:57:20] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[22:57:20] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[22:57:20] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[22:57:20] [PASSED] RGB
[22:57:20] [PASSED] YUV 4:2:0
[22:57:20] [PASSED] YUV 4:2:2
[22:57:20] [PASSED] YUV 4:4:4
[22:57:20] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[22:57:20] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[22:57:20] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[22:57:20] ============= drm_damage_helper (21 subtests) ==============
[22:57:20] [PASSED] drm_test_damage_iter_no_damage
[22:57:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[22:57:20] [PASSED] drm_test_damage_iter_no_damage_src_moved
[22:57:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[22:57:20] [PASSED] drm_test_damage_iter_no_damage_not_visible
[22:57:20] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[22:57:20] [PASSED] drm_test_damage_iter_no_damage_no_fb
[22:57:20] [PASSED] drm_test_damage_iter_simple_damage
[22:57:20] [PASSED] drm_test_damage_iter_single_damage
[22:57:20] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[22:57:20] [PASSED] drm_test_damage_iter_single_damage_outside_src
[22:57:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[22:57:20] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[22:57:20] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[22:57:20] [PASSED] drm_test_damage_iter_single_damage_src_moved
[22:57:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[22:57:20] [PASSED] drm_test_damage_iter_damage
[22:57:20] [PASSED] drm_test_damage_iter_damage_one_intersect
[22:57:20] [PASSED] drm_test_damage_iter_damage_one_outside
[22:57:20] [PASSED] drm_test_damage_iter_damage_src_moved
[22:57:20] [PASSED] drm_test_damage_iter_damage_not_visible
[22:57:20] ================ [PASSED] drm_damage_helper ================
[22:57:20] ============== drm_dp_mst_helper (3 subtests) ==============
[22:57:20] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[22:57:20] [PASSED] Clock 154000 BPP 30 DSC disabled
[22:57:20] [PASSED] Clock 234000 BPP 30 DSC disabled
[22:57:20] [PASSED] Clock 297000 BPP 24 DSC disabled
[22:57:20] [PASSED] Clock 332880 BPP 24 DSC enabled
[22:57:20] [PASSED] Clock 324540 BPP 24 DSC enabled
[22:57:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[22:57:20] ============== drm_test_dp_mst_calc_pbn_div  ===============
[22:57:20] [PASSED] Link rate 2000000 lane count 4
[22:57:20] [PASSED] Link rate 2000000 lane count 2
[22:57:20] [PASSED] Link rate 2000000 lane count 1
[22:57:20] [PASSED] Link rate 1350000 lane count 4
[22:57:20] [PASSED] Link rate 1350000 lane count 2
[22:57:20] [PASSED] Link rate 1350000 lane count 1
[22:57:20] [PASSED] Link rate 1000000 lane count 4
[22:57:20] [PASSED] Link rate 1000000 lane count 2
[22:57:20] [PASSED] Link rate 1000000 lane count 1
[22:57:20] [PASSED] Link rate 810000 lane count 4
[22:57:20] [PASSED] Link rate 810000 lane count 2
[22:57:20] [PASSED] Link rate 810000 lane count 1
[22:57:20] [PASSED] Link rate 540000 lane count 4
[22:57:20] [PASSED] Link rate 540000 lane count 2
[22:57:20] [PASSED] Link rate 540000 lane count 1
[22:57:20] [PASSED] Link rate 270000 lane count 4
[22:57:20] [PASSED] Link rate 270000 lane count 2
[22:57:20] [PASSED] Link rate 270000 lane count 1
[22:57:20] [PASSED] Link rate 162000 lane count 4
[22:57:20] [PASSED] Link rate 162000 lane count 2
[22:57:20] [PASSED] Link rate 162000 lane count 1
[22:57:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[22:57:20] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[22:57:20] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[22:57:20] [PASSED] DP_POWER_UP_PHY with port number
[22:57:20] [PASSED] DP_POWER_DOWN_PHY with port number
[22:57:20] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[22:57:20] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[22:57:20] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[22:57:20] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[22:57:20] [PASSED] DP_QUERY_PAYLOAD with port number
[22:57:20] [PASSED] DP_QUERY_PAYLOAD with VCPI
[22:57:20] [PASSED] DP_REMOTE_DPCD_READ with port number
[22:57:20] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[22:57:20] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[22:57:20] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[22:57:20] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[22:57:20] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[22:57:20] [PASSED] DP_REMOTE_I2C_READ with port number
[22:57:20] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[22:57:20] [PASSED] DP_REMOTE_I2C_READ with transactions array
[22:57:20] [PASSED] DP_REMOTE_I2C_WRITE with port number
[22:57:20] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[22:57:20] [PASSED] DP_REMOTE_I2C_WRITE with data array
[22:57:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[22:57:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[22:57:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[22:57:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[22:57:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[22:57:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[22:57:20] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[22:57:20] ================ [PASSED] drm_dp_mst_helper ================
[22:57:20] ================== drm_exec (7 subtests) ===================
[22:57:20] [PASSED] sanitycheck
[22:57:20] [PASSED] test_lock
[22:57:20] [PASSED] test_lock_unlock
[22:57:20] [PASSED] test_duplicates
[22:57:20] [PASSED] test_prepare
[22:57:20] [PASSED] test_prepare_array
[22:57:20] [PASSED] test_multiple_loops
[22:57:20] ==================== [PASSED] drm_exec =====================
[22:57:20] =========== drm_format_helper_test (17 subtests) ===========
[22:57:20] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[22:57:20] [PASSED] single_pixel_source_buffer
[22:57:20] [PASSED] single_pixel_clip_rectangle
[22:57:20] [PASSED] well_known_colors
[22:57:20] [PASSED] destination_pitch
[22:57:20] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[22:57:20] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[22:57:20] [PASSED] single_pixel_source_buffer
[22:57:20] [PASSED] single_pixel_clip_rectangle
[22:57:20] [PASSED] well_known_colors
[22:57:20] [PASSED] destination_pitch
[22:57:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[22:57:20] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[22:57:20] [PASSED] single_pixel_source_buffer
[22:57:20] [PASSED] single_pixel_clip_rectangle
[22:57:20] [PASSED] well_known_colors
[22:57:20] [PASSED] destination_pitch
[22:57:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[22:57:20] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[22:57:20] [PASSED] single_pixel_source_buffer
[22:57:20] [PASSED] single_pixel_clip_rectangle
[22:57:20] [PASSED] well_known_colors
[22:57:20] [PASSED] destination_pitch
[22:57:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[22:57:20] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[22:57:20] [PASSED] single_pixel_source_buffer
[22:57:20] [PASSED] single_pixel_clip_rectangle
[22:57:20] [PASSED] well_known_colors
[22:57:20] [PASSED] destination_pitch
[22:57:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[22:57:20] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[22:57:20] [PASSED] single_pixel_source_buffer
[22:57:20] [PASSED] single_pixel_clip_rectangle
[22:57:20] [PASSED] well_known_colors
[22:57:20] [PASSED] destination_pitch
[22:57:20] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[22:57:20] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[22:57:20] [PASSED] single_pixel_source_buffer
[22:57:20] [PASSED] single_pixel_clip_rectangle
[22:57:20] [PASSED] well_known_colors
[22:57:20] [PASSED] destination_pitch
[22:57:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[22:57:20] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[22:57:20] [PASSED] single_pixel_source_buffer
[22:57:20] [PASSED] single_pixel_clip_rectangle
[22:57:20] [PASSED] well_known_colors
[22:57:20] [PASSED] destination_pitch
[22:57:20] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[22:57:20] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[22:57:20] [PASSED] single_pixel_source_buffer
[22:57:20] [PASSED] single_pixel_clip_rectangle
[22:57:20] [PASSED] well_known_colors
[22:57:20] [PASSED] destination_pitch
[22:57:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[22:57:20] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[22:57:20] [PASSED] single_pixel_source_buffer
[22:57:20] [PASSED] single_pixel_clip_rectangle
[22:57:20] [PASSED] well_known_colors
[22:57:20] [PASSED] destination_pitch
[22:57:20] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[22:57:20] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[22:57:20] [PASSED] single_pixel_source_buffer
[22:57:20] [PASSED] single_pixel_clip_rectangle
[22:57:20] [PASSED] well_known_colors
[22:57:20] [PASSED] destination_pitch
[22:57:20] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[22:57:20] ============== drm_test_fb_xrgb8888_to_mono  ===============
[22:57:20] [PASSED] single_pixel_source_buffer
[22:57:20] [PASSED] single_pixel_clip_rectangle
[22:57:20] [PASSED] well_known_colors
[22:57:20] [PASSED] destination_pitch
[22:57:20] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[22:57:20] ==================== drm_test_fb_swab  =====================
[22:57:20] [PASSED] single_pixel_source_buffer
[22:57:20] [PASSED] single_pixel_clip_rectangle
[22:57:20] [PASSED] well_known_colors
[22:57:20] [PASSED] destination_pitch
[22:57:20] ================ [PASSED] drm_test_fb_swab =================
[22:57:20] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[22:57:20] [PASSED] single_pixel_source_buffer
[22:57:20] [PASSED] single_pixel_clip_rectangle
[22:57:20] [PASSED] well_known_colors
[22:57:20] [PASSED] destination_pitch
[22:57:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[22:57:20] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[22:57:20] [PASSED] single_pixel_source_buffer
[22:57:20] [PASSED] single_pixel_clip_rectangle
[22:57:20] [PASSED] well_known_colors
[22:57:20] [PASSED] destination_pitch
[22:57:20] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[22:57:20] ================= drm_test_fb_clip_offset  =================
[22:57:20] [PASSED] pass through
[22:57:20] [PASSED] horizontal offset
[22:57:20] [PASSED] vertical offset
[22:57:20] [PASSED] horizontal and vertical offset
[22:57:20] [PASSED] horizontal offset (custom pitch)
[22:57:20] [PASSED] vertical offset (custom pitch)
[22:57:20] [PASSED] horizontal and vertical offset (custom pitch)
[22:57:20] ============= [PASSED] drm_test_fb_clip_offset =============
[22:57:20] =================== drm_test_fb_memcpy  ====================
[22:57:20] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[22:57:20] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[22:57:20] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[22:57:20] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[22:57:20] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[22:57:20] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[22:57:20] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[22:57:20] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[22:57:20] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[22:57:20] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[22:57:20] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[22:57:20] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[22:57:20] =============== [PASSED] drm_test_fb_memcpy ================
[22:57:20] ============= [PASSED] drm_format_helper_test ==============
[22:57:20] ================= drm_format (18 subtests) =================
[22:57:20] [PASSED] drm_test_format_block_width_invalid
[22:57:20] [PASSED] drm_test_format_block_width_one_plane
[22:57:20] [PASSED] drm_test_format_block_width_two_plane
[22:57:20] [PASSED] drm_test_format_block_width_three_plane
[22:57:20] [PASSED] drm_test_format_block_width_tiled
[22:57:20] [PASSED] drm_test_format_block_height_invalid
[22:57:20] [PASSED] drm_test_format_block_height_one_plane
[22:57:20] [PASSED] drm_test_format_block_height_two_plane
[22:57:20] [PASSED] drm_test_format_block_height_three_plane
[22:57:20] [PASSED] drm_test_format_block_height_tiled
[22:57:20] [PASSED] drm_test_format_min_pitch_invalid
[22:57:20] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[22:57:20] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[22:57:20] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[22:57:20] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[22:57:20] [PASSED] drm_test_format_min_pitch_two_plane
[22:57:20] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[22:57:20] [PASSED] drm_test_format_min_pitch_tiled
[22:57:20] =================== [PASSED] drm_format ====================
[22:57:20] ============== drm_framebuffer (10 subtests) ===============
[22:57:20] ========== drm_test_framebuffer_check_src_coords  ==========
[22:57:20] [PASSED] Success: source fits into fb
[22:57:20] [PASSED] Fail: overflowing fb with x-axis coordinate
[22:57:20] [PASSED] Fail: overflowing fb with y-axis coordinate
[22:57:20] [PASSED] Fail: overflowing fb with source width
[22:57:20] [PASSED] Fail: overflowing fb with source height
[22:57:20] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[22:57:20] [PASSED] drm_test_framebuffer_cleanup
[22:57:20] =============== drm_test_framebuffer_create  ===============
[22:57:20] [PASSED] ABGR8888 normal sizes
[22:57:20] [PASSED] ABGR8888 max sizes
[22:57:20] [PASSED] ABGR8888 pitch greater than min required
[22:57:20] [PASSED] ABGR8888 pitch less than min required
[22:57:20] [PASSED] ABGR8888 Invalid width
[22:57:20] [PASSED] ABGR8888 Invalid buffer handle
[22:57:20] [PASSED] No pixel format
[22:57:20] [PASSED] ABGR8888 Width 0
[22:57:20] [PASSED] ABGR8888 Height 0
[22:57:20] [PASSED] ABGR8888 Out of bound height * pitch combination
[22:57:20] [PASSED] ABGR8888 Large buffer offset
[22:57:20] [PASSED] ABGR8888 Buffer offset for inexistent plane
[22:57:20] [PASSED] ABGR8888 Invalid flag
[22:57:20] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[22:57:20] [PASSED] ABGR8888 Valid buffer modifier
[22:57:20] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[22:57:20] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[22:57:20] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[22:57:20] [PASSED] NV12 Normal sizes
[22:57:20] [PASSED] NV12 Max sizes
[22:57:20] [PASSED] NV12 Invalid pitch
[22:57:20] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[22:57:20] [PASSED] NV12 different  modifier per-plane
[22:57:20] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[22:57:20] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[22:57:20] [PASSED] NV12 Modifier for inexistent plane
[22:57:20] [PASSED] NV12 Handle for inexistent plane
[22:57:20] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[22:57:20] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[22:57:20] [PASSED] YVU420 Normal sizes
[22:57:20] [PASSED] YVU420 Max sizes
[22:57:20] [PASSED] YVU420 Invalid pitch
[22:57:20] [PASSED] YVU420 Different pitches
[22:57:20] [PASSED] YVU420 Different buffer offsets/pitches
[22:57:20] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[22:57:20] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[22:57:20] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[22:57:20] [PASSED] YVU420 Valid modifier
[22:57:20] [PASSED] YVU420 Different modifiers per plane
[22:57:20] [PASSED] YVU420 Modifier for inexistent plane
[22:57:20] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[22:57:20] [PASSED] X0L2 Normal sizes
[22:57:20] [PASSED] X0L2 Max sizes
[22:57:20] [PASSED] X0L2 Invalid pitch
[22:57:20] [PASSED] X0L2 Pitch greater than minimum required
[22:57:20] [PASSED] X0L2 Handle for inexistent plane
[22:57:20] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[22:57:20] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[22:57:20] [PASSED] X0L2 Valid modifier
[22:57:20] [PASSED] X0L2 Modifier for inexistent plane
[22:57:20] =========== [PASSED] drm_test_framebuffer_create ===========
[22:57:20] [PASSED] drm_test_framebuffer_free
[22:57:20] [PASSED] drm_test_framebuffer_init
[22:57:20] [PASSED] drm_test_framebuffer_init_bad_format
[22:57:20] [PASSED] drm_test_framebuffer_init_dev_mismatch
[22:57:20] [PASSED] drm_test_framebuffer_lookup
[22:57:20] [PASSED] drm_test_framebuffer_lookup_inexistent
[22:57:20] [PASSED] drm_test_framebuffer_modifiers_not_supported
[22:57:20] ================= [PASSED] drm_framebuffer =================
[22:57:20] ================ drm_gem_shmem (8 subtests) ================
[22:57:20] [PASSED] drm_gem_shmem_test_obj_create
[22:57:20] [PASSED] drm_gem_shmem_test_obj_create_private
[22:57:20] [PASSED] drm_gem_shmem_test_pin_pages
[22:57:20] [PASSED] drm_gem_shmem_test_vmap
[22:57:20] [PASSED] drm_gem_shmem_test_get_pages_sgt
[22:57:20] [PASSED] drm_gem_shmem_test_get_sg_table
[22:57:20] [PASSED] drm_gem_shmem_test_madvise
[22:57:20] [PASSED] drm_gem_shmem_test_purge
[22:57:20] ================== [PASSED] drm_gem_shmem ==================
[22:57:20] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[22:57:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[22:57:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[22:57:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[22:57:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[22:57:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[22:57:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[22:57:20] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[22:57:20] [PASSED] Automatic
[22:57:20] [PASSED] Full
[22:57:20] [PASSED] Limited 16:235
[22:57:20] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[22:57:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[22:57:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[22:57:20] [PASSED] drm_test_check_disable_connector
[22:57:20] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[22:57:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[22:57:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[22:57:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[22:57:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[22:57:20] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[22:57:20] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[22:57:20] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[22:57:20] [PASSED] drm_test_check_output_bpc_dvi
[22:57:20] [PASSED] drm_test_check_output_bpc_format_vic_1
[22:57:20] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[22:57:20] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[22:57:20] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[22:57:20] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[22:57:20] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[22:57:20] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[22:57:20] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[22:57:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[22:57:20] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[22:57:20] [PASSED] drm_test_check_broadcast_rgb_value
[22:57:20] [PASSED] drm_test_check_bpc_8_value
[22:57:20] [PASSED] drm_test_check_bpc_10_value
[22:57:20] [PASSED] drm_test_check_bpc_12_value
[22:57:20] [PASSED] drm_test_check_format_value
[22:57:20] [PASSED] drm_test_check_tmds_char_value
[22:57:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[22:57:20] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[22:57:20] [PASSED] drm_test_check_mode_valid
[22:57:20] [PASSED] drm_test_check_mode_valid_reject
[22:57:20] [PASSED] drm_test_check_mode_valid_reject_rate
[22:57:20] [PASSED] drm_test_check_mode_valid_reject_max_clock
[22:57:20] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[22:57:20] ================= drm_managed (2 subtests) =================
[22:57:20] [PASSED] drm_test_managed_release_action
[22:57:20] [PASSED] drm_test_managed_run_action
[22:57:20] =================== [PASSED] drm_managed ===================
[22:57:20] =================== drm_mm (6 subtests) ====================
[22:57:20] [PASSED] drm_test_mm_init
[22:57:20] [PASSED] drm_test_mm_debug
[22:57:20] [PASSED] drm_test_mm_align32
[22:57:20] [PASSED] drm_test_mm_align64
[22:57:20] [PASSED] drm_test_mm_lowest
[22:57:20] [PASSED] drm_test_mm_highest
[22:57:20] ===================== [PASSED] drm_mm ======================
[22:57:20] ============= drm_modes_analog_tv (5 subtests) =============
[22:57:20] [PASSED] drm_test_modes_analog_tv_mono_576i
[22:57:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[22:57:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[22:57:20] [PASSED] drm_test_modes_analog_tv_pal_576i
[22:57:20] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[22:57:20] =============== [PASSED] drm_modes_analog_tv ===============
[22:57:20] ============== drm_plane_helper (2 subtests) ===============
[22:57:20] =============== drm_test_check_plane_state  ================
[22:57:20] [PASSED] clipping_simple
[22:57:20] [PASSED] clipping_rotate_reflect
[22:57:20] [PASSED] positioning_simple
[22:57:20] [PASSED] upscaling
[22:57:20] [PASSED] downscaling
[22:57:20] [PASSED] rounding1
[22:57:20] [PASSED] rounding2
[22:57:20] [PASSED] rounding3
[22:57:20] [PASSED] rounding4
[22:57:20] =========== [PASSED] drm_test_check_plane_state ============
[22:57:20] =========== drm_test_check_invalid_plane_state  ============
[22:57:20] [PASSED] positioning_invalid
[22:57:20] [PASSED] upscaling_invalid
[22:57:20] [PASSED] downscaling_invalid
[22:57:20] ======= [PASSED] drm_test_check_invalid_plane_state ========
[22:57:20] ================ [PASSED] drm_plane_helper =================
[22:57:20] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[22:57:20] ====== drm_test_connector_helper_tv_get_modes_check  =======
[22:57:20] [PASSED] None
[22:57:20] [PASSED] PAL
[22:57:20] [PASSED] NTSC
[22:57:20] [PASSED] Both, NTSC Default
[22:57:20] [PASSED] Both, PAL Default
[22:57:20] [PASSED] Both, NTSC Default, with PAL on command-line
[22:57:20] [PASSED] Both, PAL Default, with NTSC on command-line
[22:57:20] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[22:57:20] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[22:57:20] ================== drm_rect (9 subtests) ===================
[22:57:20] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[22:57:20] [PASSED] drm_test_rect_clip_scaled_not_clipped
[22:57:20] [PASSED] drm_test_rect_clip_scaled_clipped
[22:57:20] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[22:57:20] ================= drm_test_rect_intersect  =================
[22:57:20] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[22:57:20] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[22:57:20] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[22:57:20] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[22:57:20] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[22:57:20] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[22:57:20] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[22:57:20] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[22:57:20] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[22:57:20] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[22:57:20] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[22:57:20] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[22:57:20] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[22:57:20] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[22:57:20] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[22:57:20] ============= [PASSED] drm_test_rect_intersect =============
[22:57:20] ================ drm_test_rect_calc_hscale  ================
[22:57:20] [PASSED] normal use
[22:57:20] [PASSED] out of max range
[22:57:20] [PASSED] out of min range
[22:57:20] [PASSED] zero dst
[22:57:20] [PASSED] negative src
[22:57:20] [PASSED] negative dst
[22:57:20] ============ [PASSED] drm_test_rect_calc_hscale ============
[22:57:20] ================ drm_test_rect_calc_vscale  ================
[22:57:20] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[22:57:20] [PASSED] out of max range
[22:57:20] [PASSED] out of min range
[22:57:20] [PASSED] zero dst
[22:57:20] [PASSED] negative src
[22:57:20] [PASSED] negative dst
[22:57:20] ============ [PASSED] drm_test_rect_calc_vscale ============
[22:57:20] ================== drm_test_rect_rotate  ===================
[22:57:20] [PASSED] reflect-x
[22:57:20] [PASSED] reflect-y
[22:57:20] [PASSED] rotate-0
[22:57:20] [PASSED] rotate-90
[22:57:20] [PASSED] rotate-180
[22:57:20] [PASSED] rotate-270
[22:57:20] ============== [PASSED] drm_test_rect_rotate ===============
[22:57:20] ================ drm_test_rect_rotate_inv  =================
[22:57:20] [PASSED] reflect-x
[22:57:20] [PASSED] reflect-y
[22:57:20] [PASSED] rotate-0
[22:57:20] [PASSED] rotate-90
[22:57:20] [PASSED] rotate-180
[22:57:20] [PASSED] rotate-270
[22:57:20] ============ [PASSED] drm_test_rect_rotate_inv =============
[22:57:20] ==================== [PASSED] drm_rect =====================
[22:57:20] ============ drm_sysfb_modeset_test (1 subtest) ============
[22:57:20] ============ drm_test_sysfb_build_fourcc_list  =============
[22:57:20] [PASSED] no native formats
[22:57:20] [PASSED] XRGB8888 as native format
[22:57:20] [PASSED] remove duplicates
[22:57:20] [PASSED] convert alpha formats
[22:57:20] [PASSED] random formats
[22:57:20] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[22:57:20] ============= [PASSED] drm_sysfb_modeset_test ==============
[22:57:20] ============================================================
[22:57:20] Testing complete. Ran 622 tests: passed: 622
[22:57:20] Elapsed time: 27.044s total, 1.726s configuring, 24.896s building, 0.394s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[22:57:20] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:57:21] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[22:57:31] Starting KUnit Kernel (1/1)...
[22:57:31] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:57:31] ================= ttm_device (5 subtests) ==================
[22:57:31] [PASSED] ttm_device_init_basic
[22:57:31] [PASSED] ttm_device_init_multiple
[22:57:31] [PASSED] ttm_device_fini_basic
[22:57:31] [PASSED] ttm_device_init_no_vma_man
[22:57:31] ================== ttm_device_init_pools  ==================
[22:57:31] [PASSED] No DMA allocations, no DMA32 required
[22:57:31] [PASSED] DMA allocations, DMA32 required
[22:57:31] [PASSED] No DMA allocations, DMA32 required
[22:57:31] [PASSED] DMA allocations, no DMA32 required
[22:57:31] ============== [PASSED] ttm_device_init_pools ==============
[22:57:31] =================== [PASSED] ttm_device ====================
[22:57:31] ================== ttm_pool (8 subtests) ===================
[22:57:31] ================== ttm_pool_alloc_basic  ===================
[22:57:31] [PASSED] One page
[22:57:31] [PASSED] More than one page
[22:57:31] [PASSED] Above the allocation limit
[22:57:31] [PASSED] One page, with coherent DMA mappings enabled
[22:57:31] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[22:57:31] ============== [PASSED] ttm_pool_alloc_basic ===============
[22:57:31] ============== ttm_pool_alloc_basic_dma_addr  ==============
[22:57:31] [PASSED] One page
[22:57:31] [PASSED] More than one page
[22:57:31] [PASSED] Above the allocation limit
[22:57:31] [PASSED] One page, with coherent DMA mappings enabled
[22:57:31] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[22:57:31] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[22:57:31] [PASSED] ttm_pool_alloc_order_caching_match
[22:57:31] [PASSED] ttm_pool_alloc_caching_mismatch
[22:57:31] [PASSED] ttm_pool_alloc_order_mismatch
[22:57:31] [PASSED] ttm_pool_free_dma_alloc
[22:57:31] [PASSED] ttm_pool_free_no_dma_alloc
[22:57:31] [PASSED] ttm_pool_fini_basic
[22:57:31] ==================== [PASSED] ttm_pool =====================
[22:57:31] ================ ttm_resource (8 subtests) =================
[22:57:31] ================= ttm_resource_init_basic  =================
[22:57:31] [PASSED] Init resource in TTM_PL_SYSTEM
[22:57:31] [PASSED] Init resource in TTM_PL_VRAM
[22:57:31] [PASSED] Init resource in a private placement
[22:57:31] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[22:57:31] ============= [PASSED] ttm_resource_init_basic =============
[22:57:31] [PASSED] ttm_resource_init_pinned
[22:57:31] [PASSED] ttm_resource_fini_basic
[22:57:31] [PASSED] ttm_resource_manager_init_basic
[22:57:31] [PASSED] ttm_resource_manager_usage_basic
[22:57:31] [PASSED] ttm_resource_manager_set_used_basic
[22:57:31] [PASSED] ttm_sys_man_alloc_basic
[22:57:31] [PASSED] ttm_sys_man_free_basic
[22:57:31] ================== [PASSED] ttm_resource ===================
[22:57:31] =================== ttm_tt (15 subtests) ===================
[22:57:31] ==================== ttm_tt_init_basic  ====================
[22:57:31] [PASSED] Page-aligned size
[22:57:31] [PASSED] Extra pages requested
[22:57:31] ================ [PASSED] ttm_tt_init_basic ================
[22:57:31] [PASSED] ttm_tt_init_misaligned
[22:57:31] [PASSED] ttm_tt_fini_basic
[22:57:31] [PASSED] ttm_tt_fini_sg
[22:57:31] [PASSED] ttm_tt_fini_shmem
[22:57:31] [PASSED] ttm_tt_create_basic
[22:57:31] [PASSED] ttm_tt_create_invalid_bo_type
[22:57:31] [PASSED] ttm_tt_create_ttm_exists
[22:57:31] [PASSED] ttm_tt_create_failed
[22:57:31] [PASSED] ttm_tt_destroy_basic
[22:57:31] [PASSED] ttm_tt_populate_null_ttm
[22:57:31] [PASSED] ttm_tt_populate_populated_ttm
[22:57:31] [PASSED] ttm_tt_unpopulate_basic
[22:57:31] [PASSED] ttm_tt_unpopulate_empty_ttm
[22:57:31] [PASSED] ttm_tt_swapin_basic
[22:57:31] ===================== [PASSED] ttm_tt ======================
[22:57:31] =================== ttm_bo (14 subtests) ===================
[22:57:31] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[22:57:31] [PASSED] Cannot be interrupted and sleeps
[22:57:31] [PASSED] Cannot be interrupted, locks straight away
[22:57:31] [PASSED] Can be interrupted, sleeps
[22:57:31] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[22:57:31] [PASSED] ttm_bo_reserve_locked_no_sleep
[22:57:31] [PASSED] ttm_bo_reserve_no_wait_ticket
[22:57:31] [PASSED] ttm_bo_reserve_double_resv
[22:57:31] [PASSED] ttm_bo_reserve_interrupted
[22:57:31] [PASSED] ttm_bo_reserve_deadlock
[22:57:31] [PASSED] ttm_bo_unreserve_basic
[22:57:31] [PASSED] ttm_bo_unreserve_pinned
[22:57:31] [PASSED] ttm_bo_unreserve_bulk
[22:57:31] [PASSED] ttm_bo_fini_basic
[22:57:31] [PASSED] ttm_bo_fini_shared_resv
[22:57:31] [PASSED] ttm_bo_pin_basic
[22:57:31] [PASSED] ttm_bo_pin_unpin_resource
[22:57:31] [PASSED] ttm_bo_multiple_pin_one_unpin
[22:57:31] ===================== [PASSED] ttm_bo ======================
[22:57:31] ============== ttm_bo_validate (21 subtests) ===============
[22:57:31] ============== ttm_bo_init_reserved_sys_man  ===============
[22:57:31] [PASSED] Buffer object for userspace
[22:57:31] [PASSED] Kernel buffer object
[22:57:31] [PASSED] Shared buffer object
[22:57:31] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[22:57:31] ============== ttm_bo_init_reserved_mock_man  ==============
[22:57:31] [PASSED] Buffer object for userspace
[22:57:31] [PASSED] Kernel buffer object
[22:57:31] [PASSED] Shared buffer object
[22:57:31] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[22:57:31] [PASSED] ttm_bo_init_reserved_resv
[22:57:31] ================== ttm_bo_validate_basic  ==================
[22:57:31] [PASSED] Buffer object for userspace
[22:57:31] [PASSED] Kernel buffer object
[22:57:31] [PASSED] Shared buffer object
[22:57:31] ============== [PASSED] ttm_bo_validate_basic ==============
[22:57:31] [PASSED] ttm_bo_validate_invalid_placement
[22:57:31] ============= ttm_bo_validate_same_placement  ==============
[22:57:31] [PASSED] System manager
[22:57:31] [PASSED] VRAM manager
[22:57:31] ========= [PASSED] ttm_bo_validate_same_placement ==========
[22:57:31] [PASSED] ttm_bo_validate_failed_alloc
[22:57:31] [PASSED] ttm_bo_validate_pinned
[22:57:31] [PASSED] ttm_bo_validate_busy_placement
[22:57:31] ================ ttm_bo_validate_multihop  =================
[22:57:31] [PASSED] Buffer object for userspace
[22:57:31] [PASSED] Kernel buffer object
[22:57:31] [PASSED] Shared buffer object
[22:57:31] ============ [PASSED] ttm_bo_validate_multihop =============
[22:57:31] ========== ttm_bo_validate_no_placement_signaled  ==========
[22:57:31] [PASSED] Buffer object in system domain, no page vector
[22:57:31] [PASSED] Buffer object in system domain with an existing page vector
[22:57:31] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[22:57:31] ======== ttm_bo_validate_no_placement_not_signaled  ========
[22:57:31] [PASSED] Buffer object for userspace
[22:57:31] [PASSED] Kernel buffer object
[22:57:31] [PASSED] Shared buffer object
[22:57:31] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[22:57:31] [PASSED] ttm_bo_validate_move_fence_signaled
[22:57:31] ========= ttm_bo_validate_move_fence_not_signaled  =========
[22:57:31] [PASSED] Waits for GPU
[22:57:31] [PASSED] Tries to lock straight away
[22:57:31] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[22:57:31] [PASSED] ttm_bo_validate_happy_evict
[22:57:31] [PASSED] ttm_bo_validate_all_pinned_evict
[22:57:31] [PASSED] ttm_bo_validate_allowed_only_evict
[22:57:31] [PASSED] ttm_bo_validate_deleted_evict
[22:57:31] [PASSED] ttm_bo_validate_busy_domain_evict
[22:57:31] [PASSED] ttm_bo_validate_evict_gutting
[22:57:31] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[22:57:31] ================= [PASSED] ttm_bo_validate =================
[22:57:31] ============================================================
[22:57:31] Testing complete. Ran 101 tests: passed: 101
[22:57:31] Elapsed time: 11.084s total, 1.726s configuring, 9.142s building, 0.172s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for drm/i915: Stop the intel_de_wait_custom() abuse

[Patchwork]

== Series Details ==

Series: drm/i915: Stop the intel_de_wait_custom() abuse
URL   : https://patchwork.freedesktop.org/series/157098/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast b68b360d3df2b2f221a6b2395911630bc9749512
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2086:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2086:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2086:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_lt_phy.c:1604:35: warning: Using plain integer as NULL pointer

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ Xe.CI.BAT: failure for drm/i915: Stop the intel_de_wait_custom() abuse

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2313 bytes --]

== Series Details ==

Series: drm/i915: Stop the intel_de_wait_custom() abuse
URL   : https://patchwork.freedesktop.org/series/157098/
State : failure

== Summary ==

CI Bug Log - changes from xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad_BAT -> xe-pw-157098v1_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-157098v1_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-157098v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-157098v1_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_waitfence@engine:
    - bat-dg2-oem2:       [PASS][1] -> [FAIL][2] +1 other test fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/bat-dg2-oem2/igt@xe_waitfence@engine.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/bat-dg2-oem2/igt@xe_waitfence@engine.html

  
Known issues
------------

  Here are the changes found in xe-pw-157098v1_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-adlp-vm:        [INCOMPLETE][3] -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/bat-adlp-vm/igt@core_hotunplug@unbind-rebind.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/bat-adlp-vm/igt@core_hotunplug@unbind-rebind.html

  


Build changes
-------------

  * Linux: xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad -> xe-pw-157098v1

  IGT_8608: 42ea0108ec47e4a00aed97d6f98e5339847c7331 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad: 4247aae08afc576bbe58c7998b5e2f6a2ea982ad
  xe-pw-157098v1: 157098v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/index.html

[-- Attachment #2: Type: text/html, Size: 2926 bytes --]

Re: [PATCH 1/7] drm/i915/cx0: Undo the unjustified timeout change

[Jani Nikula]

On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Undo the bogus timeout change to
> intel_cx0_powerdown_change_sequence(). If this was intentional
> then it should have been justifie in the commit message.
>
> This is also now abusing intel_de_wait_custom() in way that
> prevents future conversion to poll_timeout_us().
>
> Fixes: fc9be0a10ca4 ("drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index b3b506d0e040..e7fe974129fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2830,7 +2830,7 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
>  	/* Update Timeout Value */
>  	if (intel_de_wait_custom(display, buf_ctl2_reg,
>  				 intel_cx0_get_powerdown_update(lane_mask), 0,
> -				 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 2, NULL))
> +				 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
>  		drm_warn(display->drm,
>  			 "PHY %c failed to bring out of Lane reset after %dus.\n",
>  			 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);

-- 
Jani Nikula, Intel

Re: [PATCH 2/7] drm/i915/cx0: Get rid of XELPDP_MSGBUS_TIMEOUT_FAST_US

[Jani Nikula]

On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> XELPDP_MSGBUS_TIMEOUT_FAST_US looks to be just a obfuscated version

*an

> of the default 2 microsecond fast timeout used by
> intel_wait_for_register(). get rid of it to make it clear what's going
> on here.

*Get

Moreover, I don't like timeouts being defined along with what are
supposed to be register *content* descriptions.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c      | 3 +--
>  drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 1 -
>  2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index e7fe974129fe..6f57ad751c9e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -168,8 +168,7 @@ int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
>  				 XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
>  				 XELPDP_PORT_P2M_RESPONSE_READY,
>  				 XELPDP_PORT_P2M_RESPONSE_READY,
> -				 XELPDP_MSGBUS_TIMEOUT_FAST_US,
> -				 XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
> +				 2, XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
>  		drm_dbg_kms(display->drm,
>  			    "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
>  			    phy_name(phy), *val);
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 635b35669348..67c6f06ab9a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -75,7 +75,6 @@
>  #define   XELPDP_PORT_P2M_ERROR_SET			REG_BIT(15)
>  
>  #define XELPDP_MSGBUS_TIMEOUT_SLOW			1
> -#define XELPDP_MSGBUS_TIMEOUT_FAST_US			2
>  #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US		3200
>  #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US		20
>  #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US		100

-- 
Jani Nikula, Intel

Re: [PATCH 3/7] drm/i915/cx0: s/XELPDP_MSGBUS_TIMEOUT_SLOW/XELPDP_MSGBUS_TIMEOUT_MS/

[Jani Nikula]

On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The slow vs. fast timeout stuff is really just an implementation
> detail. Let's not spread that terminology in random timeout defines.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c      | 12 ++++++------
>  drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h |  2 +-
>  drivers/gpu/drm/i915/display/intel_lt_phy.c       |  2 +-
>  3 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 6f57ad751c9e..55ce4f673c63 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -147,7 +147,7 @@ void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
>  
>  	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
>  				    XELPDP_PORT_M2P_TRANSACTION_RESET,
> -				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> +				    XELPDP_MSGBUS_TIMEOUT_MS)) {
>  		drm_err_once(display->drm,
>  			     "Failed to bring PHY %c to idle.\n",
>  			     phy_name(phy));
> @@ -168,7 +168,7 @@ int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
>  				 XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
>  				 XELPDP_PORT_P2M_RESPONSE_READY,
>  				 XELPDP_PORT_P2M_RESPONSE_READY,
> -				 2, XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
> +				 2, XELPDP_MSGBUS_TIMEOUT_MS, val)) {
>  		drm_dbg_kms(display->drm,
>  			    "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
>  			    phy_name(phy), *val);
> @@ -215,7 +215,7 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
>  
>  	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
>  				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
> -				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> +				    XELPDP_MSGBUS_TIMEOUT_MS)) {
>  		drm_dbg_kms(display->drm,
>  			    "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
>  		intel_cx0_bus_reset(encoder, lane);
> @@ -286,7 +286,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
>  
>  	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
>  				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
> -				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> +				    XELPDP_MSGBUS_TIMEOUT_MS)) {
>  		drm_dbg_kms(display->drm,
>  			    "PHY %c Timeout waiting for previous transaction to complete. Resetting the bus.\n", phy_name(phy));
>  		intel_cx0_bus_reset(encoder, lane);
> @@ -302,7 +302,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
>  
>  	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
>  				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
> -				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> +				    XELPDP_MSGBUS_TIMEOUT_MS)) {
>  		drm_dbg_kms(display->drm,
>  			    "PHY %c Timeout waiting for write to complete. Resetting the bus.\n", phy_name(phy));
>  		intel_cx0_bus_reset(encoder, lane);
> @@ -2815,7 +2815,7 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
>  	for_each_cx0_lane_in_mask(lane_mask, lane)
>  		if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
>  					    XELPDP_PORT_M2P_TRANSACTION_PENDING,
> -					    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> +					    XELPDP_MSGBUS_TIMEOUT_MS)) {
>  			drm_dbg_kms(display->drm,
>  				    "PHY %c Timeout waiting for previous transaction to complete. Reset the bus.\n",
>  				    phy_name(phy));
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 67c6f06ab9a2..bd62c396c837 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -74,7 +74,7 @@
>  #define   XELPDP_PORT_P2M_DATA(val)			REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
>  #define   XELPDP_PORT_P2M_ERROR_SET			REG_BIT(15)
>  
> -#define XELPDP_MSGBUS_TIMEOUT_SLOW			1
> +#define XELPDP_MSGBUS_TIMEOUT_MS			1
>  #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US		3200
>  #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US		20
>  #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US		100
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index af48d6cde226..6fb68157b322 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1043,7 +1043,7 @@ static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder,
>  
>  	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
>  				    XELPDP_PORT_P2P_TRANSACTION_PENDING,
> -				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> +				    XELPDP_MSGBUS_TIMEOUT_MS)) {
>  		drm_dbg_kms(display->drm,
>  			    "PHY %c Timeout waiting for previous transaction to complete. Resetting bus.\n",
>  			    phy_name(phy));

-- 
Jani Nikula, Intel

Re: [PATCH 4/7] drm/i915/cx0: s/XELPDP_PORT_RESET_END_TIMEOUT/XELPDP_PORT_RESET_END_TIMEOUT_US/

[Jani Nikula]

On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Include the units the in the define name for XELPDP_PORT_RESET_END_TIMEOUT
> to make it match all its other counterparts.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c      | 4 ++--
>  drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 55ce4f673c63..7c9c181aba8a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2926,10 +2926,10 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
>  
>  	if (intel_de_wait_for_clear(display, XELPDP_PORT_BUF_CTL2(display, port),
>  				    lane_phy_current_status,
> -				    XELPDP_PORT_RESET_END_TIMEOUT))
> +				    XELPDP_PORT_RESET_END_TIMEOUT_US))
>  		drm_warn(display->drm,
>  			 "PHY %c failed to bring out of Lane reset after %dms.\n",
> -			 phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
> +			 phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT_US);
>  }
>  
>  static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_count,
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index bd62c396c837..77244a5d52d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -80,7 +80,7 @@
>  #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US		100
>  #define XELPDP_PORT_RESET_START_TIMEOUT_US		5
>  #define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US		100
> -#define XELPDP_PORT_RESET_END_TIMEOUT			15
> +#define XELPDP_PORT_RESET_END_TIMEOUT_US		15
>  #define XELPDP_REFCLK_ENABLE_TIMEOUT_US			1
>  
>  #define _XELPDP_PORT_BUF_CTL1_LN0_A			0x64004

-- 
Jani Nikula, Intel

Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Jani Nikula]

On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The LT PHY code is abusing intel_de_wait_custom() in all kinds of weird
> ways. Get rid of the weird slow timeouts. If these are actually needed
> then the fast timeouts should really be specified as the default 2
> microscond or something.
>
> This will let us eventually nuke intel_de_wait_custom() and convert
> over to poll_timeout_us().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Suraj, any input here?

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_lt_phy.c      | 11 +++++------
>  drivers/gpu/drm/i915/display/intel_lt_phy_regs.h |  1 -
>  2 files changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 6fb68157b322..cc1d6b7a7de4 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1178,10 +1178,9 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
>  	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
>  				 XELPDP_LANE_PCLK_PLL_ACK(0),
>  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> -				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
> -				 XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
> +				 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
>  		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack not done after %dus.\n",
> -			 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
> +			 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
>  
>  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
>  		     XELPDP_FORWARD_CLOCK_UNGATE,
> @@ -1192,7 +1191,7 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
>  
>  	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
>  				 lane_phy_current_status, 0,
> -				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
> +				 XE3PLPD_RESET_END_LATENCY_US, 0, NULL))
>  		drm_warn(display->drm,
>  			 "PHY %c failed to bring out of Lane reset after %dus.\n",
>  			 phy_name(phy), XE3PLPD_RESET_END_LATENCY_US);
> @@ -1674,7 +1673,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>  		if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
>  					 XELPDP_LANE_PCLK_PLL_ACK(0),
>  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> -					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
> +					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
>  			drm_warn(display->drm, "PHY %c PLL MacCLK Ack assertion Timeout after %dus.\n",
>  				 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
>  
> @@ -1702,7 +1701,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>  		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
>  		if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
>  					 lane_phy_pulse_status, lane_phy_pulse_status,
> -					 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> +					 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
>  			drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
>  				 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> index 9223487d764e..36abc2bdbd9b 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -7,7 +7,6 @@
>  #define __INTEL_LT_PHY_REGS_H__
>  
>  #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
> -#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
>  #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
>  #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
>  #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50

-- 
Jani Nikula, Intel

Re: [PATCH 6/7] drm/i915/hdcp: Use the default 2 usec fast polling timeout

[Jani Nikula]

On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> For whatever unknown reason the HDCP code is using a custom
> 10 usec fast polling timeout instead of the normal 2 usec
> value. Switch to the standard value to get rid of the special
> case.
>
> The eventual aim is to get rid of the fast vs. slow timeout
> entirely and switch over to poll_timeout_us().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 7195e8cf671c..d01733b6460e 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -412,7 +412,7 @@ static int intel_hdcp_load_keys(struct intel_display *display)
>  	/* Wait for the keys to load (500us) */
>  	ret = intel_de_wait_custom(display, HDCP_KEY_STATUS,
>  				   HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE,
> -				   10, 1, &val);
> +				   2, 1, &val);
>  	if (ret)
>  		return ret;
>  	else if (!(val & HDCP_KEY_LOAD_STATUS))

-- 
Jani Nikula, Intel

Re: [PATCH 7/7] drm/i915/pmdemand: Use the default 2 usec fast polling timeout

[Jani Nikula]

On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> For whatever unknown reason the pmdemand code is using a custom
> 50 usec fast polling timeout instead of the normal 2 usec
> value. Switch to the standard value to get rid of the special
> case.
>
> The eventual aim is to get rid of the fast vs. slow timeout
> entirely and switch over to poll_timeout_us().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> index f52abd4e2eb0..22d8f720ae7d 100644
> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> @@ -464,7 +464,7 @@ static void intel_pmdemand_poll(struct intel_display *display)
>  
>  	ret = intel_de_wait_custom(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
>  				   XELPDP_PMDEMAND_REQ_ENABLE, 0,
> -				   50, timeout_ms, &status);
> +				   2, timeout_ms, &status);
>  
>  	if (ret == -ETIMEDOUT)
>  		drm_err(display->drm,

-- 
Jani Nikula, Intel

RE: [PATCH 1/7] drm/i915/cx0: Undo the unjustified timeout change

[Kandpal, Suraj]

> Subject: Re: [PATCH 1/7] drm/i915/cx0: Undo the unjustified timeout change
> 
> On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Undo the bogus timeout change to
> > intel_cx0_powerdown_change_sequence(). If this was intentional then it
> > should have been justifie in the commit message.
> >
> > This is also now abusing intel_de_wait_custom() in way that prevents
> > future conversion to poll_timeout_us().
> >
> > Fixes: fc9be0a10ca4 ("drm/i915/ltphy: Add a wrapper for LT Phy
> > powerdown change sequence")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index b3b506d0e040..e7fe974129fe 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -2830,7 +2830,7 @@ void
> intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
> >  	/* Update Timeout Value */
> >  	if (intel_de_wait_custom(display, buf_ctl2_reg,
> >
> intel_cx0_get_powerdown_update(lane_mask), 0,
> > -
> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 2, NULL))
> > +
> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))

According to Bspec: 74494
The powerdown change update delay can go from anywhere to 2us to
1.2ms

Regards,
Suraj Kandpal

> >  		drm_warn(display->drm,
> >  			 "PHY %c failed to bring out of Lane reset after
> %dus.\n",
> >  			 phy_name(phy),
> XELPDP_PORT_RESET_START_TIMEOUT_US);
> 
> --
> Jani Nikula, Intel

RE: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Kandpal, Suraj]

> Subject: Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts
> 
> On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The LT PHY code is abusing intel_de_wait_custom() in all kinds of
> > weird ways. Get rid of the weird slow timeouts. If these are actually
> > needed then the fast timeouts should really be specified as the
> > default 2 microscond or something.
> >
> > This will let us eventually nuke intel_de_wait_custom() and convert
> > over to poll_timeout_us().
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Suraj, any input here?
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_lt_phy.c      | 11 +++++------
> >  drivers/gpu/drm/i915/display/intel_lt_phy_regs.h |  1 -
> >  2 files changed, 5 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index 6fb68157b322..cc1d6b7a7de4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -1178,10 +1178,9 @@ intel_lt_phy_lane_reset(struct intel_encoder
> *encoder,
> >  	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
> port),
> >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> > -				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
> > -				 XE3PLPD_MACCLK_TURNON_LATENCY_MS,
> NULL))
> > +				 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0,
> NULL))
> >  		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack
> not done after %dus.\n",
> > -			 phy_name(phy),
> XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
> > +			 phy_name(phy),
> XE3PLPD_MACCLK_TURNON_LATENCY_US);

According to Bspec: 74499
Latency can be either 21us for 1ms depending on what port is connected.

 > >
> >  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> >  		     XELPDP_FORWARD_CLOCK_UNGATE,
> > @@ -1192,7 +1191,7 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > *encoder,
> >
> >  	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
> port),
> >  				 lane_phy_current_status, 0,
> > -				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
> > +				 XE3PLPD_RESET_END_LATENCY_US, 0, NULL))

Bspec : 74499
Says 200us but 2ms (1.5ms to be precise) was the actual time we found the this to work properly


> >  		drm_warn(display->drm,
> >  			 "PHY %c failed to bring out of Lane reset after
> %dus.\n",
> >  			 phy_name(phy),
> XE3PLPD_RESET_END_LATENCY_US); @@ -1674,7 +1673,7
> > @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> >  		if (intel_de_wait_custom(display,
> XELPDP_PORT_CLOCK_CTL(display, port),
> >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> > -
> XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
> > +
> XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))

Ditto here.

> >  			drm_warn(display->drm, "PHY %c PLL MacCLK Ack
> assertion Timeout after %dus.\n",
> >  				 phy_name(phy),
> XE3PLPD_MACCLK_TURNON_LATENCY_US);
> >
> > @@ -1702,7 +1701,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> *encoder,
> >  		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1
> for Owned PHY Lanes. */
> >  		if (intel_de_wait_custom(display,
> XELPDP_PORT_BUF_CTL2(display, port),
> >  					 lane_phy_pulse_status,
> lane_phy_pulse_status,
> > -
> XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> > +
> XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))

Ditto here.
I would suggest giving this a CI run on NVLS before merging this.

Regards,
Suraj Kandpal

> >  			drm_warn(display->drm, "PHY %c PLL rate not
> changed after %dus.\n",
> >  				 phy_name(phy),
> XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > index 9223487d764e..36abc2bdbd9b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > @@ -7,7 +7,6 @@
> >  #define __INTEL_LT_PHY_REGS_H__
> >
> >  #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
> > -#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
> >  #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
> >  #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
> >  #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
> 
> --
> Jani Nikula, Intel

✗ Xe.CI.Full: failure for drm/i915: Stop the intel_de_wait_custom() abuse

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 35491 bytes --]

== Series Details ==

Series: drm/i915: Stop the intel_de_wait_custom() abuse
URL   : https://patchwork.freedesktop.org/series/157098/
State : failure

== Summary ==

CI Bug Log - changes from xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad_FULL -> xe-pw-157098v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-157098v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-157098v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-157098v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_pmu@engine-activity-suspend:
    - shard-dg2-set2:     [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-dg2-436/igt@xe_pmu@engine-activity-suspend.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-466/igt@xe_pmu@engine-activity-suspend.html

  
Known issues
------------

  Here are the changes found in xe-pw-157098v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1:
    - shard-adlp:         [PASS][3] -> [DMESG-WARN][4] ([Intel XE#4543])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-adlp-1/igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-adlp-6/igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1.html

  * igt@kms_async_flips@crc-atomic@pipe-c-hdmi-a-1:
    - shard-adlp:         [PASS][5] -> [FAIL][6] ([Intel XE#3884])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-adlp-9/igt@kms_async_flips@crc-atomic@pipe-c-hdmi-a-1.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-adlp-3/igt@kms_async_flips@crc-atomic@pipe-c-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][7] ([Intel XE#316]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-433/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][8] ([Intel XE#1124]) +8 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-432/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-dg2-set2:     NOTRUN -> [SKIP][9] ([Intel XE#619])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-433/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][10] ([Intel XE#2191]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-433/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-2-displays-3840x2160p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#367])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-464/igt@kms_bw@linear-tiling-2-displays-3840x2160p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][12] ([Intel XE#2907]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-433/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][13] ([Intel XE#3442])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-432/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#455] / [Intel XE#787]) +11 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-464/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][15] ([Intel XE#787]) +41 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-a-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [PASS][16] -> [INCOMPLETE][17] ([Intel XE#2705] / [Intel XE#4212] / [Intel XE#4345])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][18] -> [INCOMPLETE][19] ([Intel XE#2705] / [Intel XE#4212])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4.html

  * igt@kms_chamelium_color@ctm-green-to-red:
    - shard-dg2-set2:     NOTRUN -> [SKIP][20] ([Intel XE#306]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-432/igt@kms_chamelium_color@ctm-green-to-red.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2252]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-5/igt@kms_chamelium_frames@dp-crc-fast.html

  * igt@kms_chamelium_hpd@vga-hpd-without-ddc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][22] ([Intel XE#373]) +2 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-433/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html

  * igt@kms_chamelium_sharpness_filter@filter-basic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][23] ([Intel XE#6507])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-464/igt@kms_chamelium_sharpness_filter@filter-basic.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-dg2-set2:     NOTRUN -> [SKIP][24] ([Intel XE#308]) +2 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-464/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
    - shard-bmg:          [PASS][25] -> [SKIP][26] ([Intel XE#2291])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-dg2-set2:     NOTRUN -> [SKIP][27] ([Intel XE#4356])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-432/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-dg2-set2:     NOTRUN -> [SKIP][28] ([Intel XE#776])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-463/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@2x-flip-vs-wf_vblank:
    - shard-bmg:          [PASS][29] -> [SKIP][30] ([Intel XE#2316])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-bmg-2/igt@kms_flip@2x-flip-vs-wf_vblank.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-6/igt@kms_flip@2x-flip-vs-wf_vblank.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [PASS][31] -> [FAIL][32] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-adlp:         [PASS][33] -> [DMESG-WARN][34] ([Intel XE#2953] / [Intel XE#4173]) +5 other tests dmesg-warn
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-adlp-3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-adlp-9/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][35] ([Intel XE#455]) +10 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-432/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-y:
    - shard-adlp:         [PASS][36] -> [DMESG-FAIL][37] ([Intel XE#4543])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-y.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-y.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y:
    - shard-adlp:         [PASS][38] -> [FAIL][39] ([Intel XE#1874])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y.html

  * igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][40] ([Intel XE#651]) +16 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][41] ([Intel XE#6312])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-slowdraw:
    - shard-dg2-set2:     NOTRUN -> [SKIP][42] ([Intel XE#653]) +14 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-slowdraw.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-bmg:          [PASS][43] -> [SKIP][44] ([Intel XE#1503])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-bmg-2/igt@kms_hdr@static-toggle-suspend.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-6/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#346])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-5/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - shard-bmg:          [PASS][46] -> [INCOMPLETE][47] ([Intel XE#2597]) +1 other test incomplete
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-bmg-8/igt@kms_pipe_crc_basic@suspend-read-crc.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-7/igt@kms_pipe_crc_basic@suspend-read-crc.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-bmg:          [PASS][48] -> [SKIP][49] ([Intel XE#4596])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-4.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-dg2-set2:     NOTRUN -> [SKIP][50] ([Intel XE#1122])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-464/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-dg2-set2:     NOTRUN -> [SKIP][51] ([Intel XE#3309])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-432/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][52] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-433/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr@fbc-pr-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][53] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +5 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-464/igt@kms_psr@fbc-pr-dpms.html

  * igt@kms_psr@fbc-psr-primary-blt:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-5/igt@kms_psr@fbc-psr-primary-blt.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][55] ([Intel XE#1127])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-433/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-dg2-set2:     NOTRUN -> [SKIP][56] ([Intel XE#330])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-432/igt@kms_tv_load_detect@load-detect.html

  * igt@xe_compute_preempt@compute-threadgroup-preempt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][57] ([Intel XE#6360])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-464/igt@xe_compute_preempt@compute-threadgroup-preempt.html

  * igt@xe_copy_basic@mem-set-linear-0x8fffe:
    - shard-dg2-set2:     NOTRUN -> [SKIP][58] ([Intel XE#5503])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-433/igt@xe_copy_basic@mem-set-linear-0x8fffe.html

  * igt@xe_eu_stall@invalid-sampling-rate:
    - shard-dg2-set2:     NOTRUN -> [SKIP][59] ([Intel XE#5626])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-463/igt@xe_eu_stall@invalid-sampling-rate.html

  * igt@xe_eudebug@basic-vm-bind-metadata-discovery:
    - shard-dg2-set2:     NOTRUN -> [SKIP][60] ([Intel XE#4837]) +6 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-432/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-bind:
    - shard-dg2-set2:     [PASS][61] -> [SKIP][62] ([Intel XE#1392])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-dg2-436/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-466/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html

  * igt@xe_exec_fault_mode@twice-userptr-rebind-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][63] ([Intel XE#288]) +14 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-464/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html

  * igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][64] ([Intel XE#6299])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-432/igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads.html

  * igt@xe_exec_system_allocator@many-64k-mmap-new-huge:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#5007])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-5/igt@xe_exec_system_allocator@many-64k-mmap-new-huge.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma:
    - shard-lnl:          [PASS][66] -> [FAIL][67] ([Intel XE#5625])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-lnl-1/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-lnl-1/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html

  * igt@xe_exec_system_allocator@threads-many-stride-new-nomemset:
    - shard-dg2-set2:     NOTRUN -> [SKIP][68] ([Intel XE#4915]) +150 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-433/igt@xe_exec_system_allocator@threads-many-stride-new-nomemset.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
    - shard-dg2-set2:     [PASS][69] -> [DMESG-WARN][70] ([Intel XE#5893])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-dg2-436/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-466/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html

  * igt@xe_oa@buffer-size:
    - shard-dg2-set2:     NOTRUN -> [SKIP][71] ([Intel XE#6032])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-433/igt@xe_oa@buffer-size.html

  * igt@xe_oa@polling-small-buf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][72] ([Intel XE#3573]) +5 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-433/igt@xe_oa@polling-small-buf.html

  * igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0:
    - shard-lnl:          [PASS][73] -> [FAIL][74] ([Intel XE#6251]) +2 other tests fail
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-lnl-7/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-lnl-7/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0.html

  * igt@xe_pmu@gt-frequency:
    - shard-dg2-set2:     NOTRUN -> [FAIL][75] ([Intel XE#4819]) +1 other test fail
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-432/igt@xe_pmu@gt-frequency.html

  * igt@xe_pxp@pxp-stale-queue-post-termination-irq:
    - shard-dg2-set2:     NOTRUN -> [SKIP][76] ([Intel XE#4733])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-432/igt@xe_pxp@pxp-stale-queue-post-termination-irq.html

  * igt@xe_query@multigpu-query-oa-units:
    - shard-dg2-set2:     NOTRUN -> [SKIP][77] ([Intel XE#944]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-432/igt@xe_query@multigpu-query-oa-units.html

  * igt@xe_render_copy@render-stress-0-copies:
    - shard-dg2-set2:     NOTRUN -> [SKIP][78] ([Intel XE#4814])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-464/igt@xe_render_copy@render-stress-0-copies.html

  * igt@xe_sriov_vram@vf-access-beyond:
    - shard-dg2-set2:     NOTRUN -> [SKIP][79] ([Intel XE#6318])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-432/igt@xe_sriov_vram@vf-access-beyond.html

  
#### Possible fixes ####

  * igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          [SKIP][80] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][81]
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-1/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][82] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [PASS][83] +1 other test pass
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][84] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522] / [Intel XE#6014]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][86] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-d-dp-4.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-d-dp-4.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-bmg:          [SKIP][88] ([Intel XE#2291]) -> [PASS][89] +2 other tests pass
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-1/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-bmg:          [SKIP][90] ([Intel XE#2316]) -> [PASS][91] +3 other tests pass
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-1/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@basic-flip-vs-modeset@b-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][92] ([Intel XE#4543]) -> [PASS][93] +1 other test pass
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-adlp-8/igt@kms_flip@basic-flip-vs-modeset@b-hdmi-a1.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-hdmi-a1.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-x:
    - shard-adlp:         [DMESG-FAIL][94] ([Intel XE#4543]) -> [PASS][95] +1 other test pass
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-x.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-x.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-y:
    - shard-adlp:         [FAIL][96] ([Intel XE#1874]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-y.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-y.html

  * igt@kms_vblank@ts-continuation-suspend:
    - shard-adlp:         [DMESG-WARN][98] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][99] +6 other tests pass
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-adlp-3/igt@kms_vblank@ts-continuation-suspend.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-adlp-9/igt@kms_vblank@ts-continuation-suspend.html

  * igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0:
    - shard-lnl:          [FAIL][100] ([Intel XE#6251]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-lnl-7/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-lnl-7/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0.html

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt:
    - shard-bmg:          [SKIP][102] ([Intel XE#2311]) -> [SKIP][103] ([Intel XE#2312]) +3 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][104] ([Intel XE#2312]) -> [SKIP][105] ([Intel XE#2311]) +6 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-mmap-wc.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][106] ([Intel XE#5390]) -> [SKIP][107] ([Intel XE#2312]) +1 other test skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          [SKIP][108] ([Intel XE#2312]) -> [SKIP][109] ([Intel XE#5390]) +1 other test skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
    - shard-bmg:          [SKIP][110] ([Intel XE#2313]) -> [SKIP][111] ([Intel XE#2312]) +3 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][112] ([Intel XE#2312]) -> [SKIP][113] ([Intel XE#2313]) +6 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][114] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][115] ([Intel XE#3544])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-bmg-4/igt@kms_hdr@brightness-with-hdr.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [FAIL][116] -> [FAIL][117] ([Intel XE#5862]) +1 other test fail
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad/shard-lnl-3/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/shard-lnl-8/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3884]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3884
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4356
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4814
  [Intel XE#4819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4819
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5503
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
  [Intel XE#5862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5862
  [Intel XE#5893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5893
  [Intel XE#6014]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6014
  [Intel XE#6032]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6032
  [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
  [Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
  [Intel XE#6299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6299
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6318]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6318
  [Intel XE#6360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6360
  [Intel XE#6507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6507
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad -> xe-pw-157098v1

  IGT_8608: 42ea0108ec47e4a00aed97d6f98e5339847c7331 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4052-4247aae08afc576bbe58c7998b5e2f6a2ea982ad: 4247aae08afc576bbe58c7998b5e2f6a2ea982ad
  xe-pw-157098v1: 157098v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157098v1/index.html

[-- Attachment #2: Type: text/html, Size: 40431 bytes --]

Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Ville Syrjälä]

On Thu, Nov 06, 2025 at 12:03:28PM +0000, Kandpal, Suraj wrote:
> > Subject: Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts
> > 
> > On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > The LT PHY code is abusing intel_de_wait_custom() in all kinds of
> > > weird ways. Get rid of the weird slow timeouts. If these are actually
> > > needed then the fast timeouts should really be specified as the
> > > default 2 microscond or something.
> > >
> > > This will let us eventually nuke intel_de_wait_custom() and convert
> > > over to poll_timeout_us().
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Suraj, any input here?
> > 
> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> > 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_lt_phy.c      | 11 +++++------
> > >  drivers/gpu/drm/i915/display/intel_lt_phy_regs.h |  1 -
> > >  2 files changed, 5 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > index 6fb68157b322..cc1d6b7a7de4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > @@ -1178,10 +1178,9 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > *encoder,
> > >  	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
> > port),
> > >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> > >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> > > -				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
> > > -				 XE3PLPD_MACCLK_TURNON_LATENCY_MS,
> > NULL))
> > > +				 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0,
> > NULL))
> > >  		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack
> > not done after %dus.\n",
> > > -			 phy_name(phy),
> > XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
> > > +			 phy_name(phy),
> > XE3PLPD_MACCLK_TURNON_LATENCY_US);
> 
> According to Bspec: 74499
> Latency can be either 21us for 1ms depending on what port is connected.
> 
>  > >
> > >  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> > >  		     XELPDP_FORWARD_CLOCK_UNGATE,
> > > @@ -1192,7 +1191,7 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > > *encoder,
> > >
> > >  	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
> > port),
> > >  				 lane_phy_current_status, 0,
> > > -				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
> > > +				 XE3PLPD_RESET_END_LATENCY_US, 0, NULL))
> 
> Bspec : 74499
> Says 200us but 2ms (1.5ms to be precise) was the actual time we found the this to work properly
> 
> 
> > >  		drm_warn(display->drm,
> > >  			 "PHY %c failed to bring out of Lane reset after
> > %dus.\n",
> > >  			 phy_name(phy),
> > XE3PLPD_RESET_END_LATENCY_US); @@ -1674,7 +1673,7
> > > @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> > >  		if (intel_de_wait_custom(display,
> > XELPDP_PORT_CLOCK_CTL(display, port),
> > >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> > >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> > > -
> > XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
> > > +
> > XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
> 
> Ditto here.
> 
> > >  			drm_warn(display->drm, "PHY %c PLL MacCLK Ack
> > assertion Timeout after %dus.\n",
> > >  				 phy_name(phy),
> > XE3PLPD_MACCLK_TURNON_LATENCY_US);
> > >
> > > @@ -1702,7 +1701,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> > *encoder,
> > >  		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1
> > for Owned PHY Lanes. */
> > >  		if (intel_de_wait_custom(display,
> > XELPDP_PORT_BUF_CTL2(display, port),
> > >  					 lane_phy_pulse_status,
> > lane_phy_pulse_status,
> > > -
> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> > > +
> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
> 
> Ditto here.
> I would suggest giving this a CI run on NVLS before merging this.

Since you have some idea why these magic numbers were chosen
please redo all of these, and make sure to:
- don't use intel_de_wait_custom() unless absolutely necessary
- if you need to use intel_de_wait_custom() then either
  use the default '2,<whatever ms>' or '<whatever us>,0' timeouts
- document all the used timeouts. This is especially important
  when they are not directly specified in bspec

> 
> Regards,
> Suraj Kandpal
> 
> > >  			drm_warn(display->drm, "PHY %c PLL rate not
> > changed after %dus.\n",
> > >  				 phy_name(phy),
> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > > b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > > index 9223487d764e..36abc2bdbd9b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > > @@ -7,7 +7,6 @@
> > >  #define __INTEL_LT_PHY_REGS_H__
> > >
> > >  #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
> > > -#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
> > >  #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
> > >  #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
> > >  #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
> > 
> > --
> > Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

RE: [PATCH 1/7] drm/i915/cx0: Undo the unjustified timeout change

[Jani Nikula]

On Thu, 06 Nov 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> Subject: Re: [PATCH 1/7] drm/i915/cx0: Undo the unjustified timeout change
>> 
>> On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > Undo the bogus timeout change to
>> > intel_cx0_powerdown_change_sequence(). If this was intentional then it
>> > should have been justifie in the commit message.
>> >
>> > This is also now abusing intel_de_wait_custom() in way that prevents
>> > future conversion to poll_timeout_us().
>> >
>> > Fixes: fc9be0a10ca4 ("drm/i915/ltphy: Add a wrapper for LT Phy
>> > powerdown change sequence")
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> 
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>> 
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
>> >  1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > index b3b506d0e040..e7fe974129fe 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > @@ -2830,7 +2830,7 @@ void
>> intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
>> >  	/* Update Timeout Value */
>> >  	if (intel_de_wait_custom(display, buf_ctl2_reg,
>> >
>> intel_cx0_get_powerdown_update(lane_mask), 0,
>> > -
>> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 2, NULL))
>> > +
>> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
>
> According to Bspec: 74494
> The powerdown change update delay can go from anywhere to 2us to
> 1.2ms

Then use intel_de_wait_for_clear() with a 2 ms timeout. There's no
reason to use intel_de_wait_custom().

BR,
Jani.


-- 
Jani Nikula, Intel

Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Ville Syrjälä]

On Thu, Nov 06, 2025 at 03:12:34PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 06, 2025 at 12:03:28PM +0000, Kandpal, Suraj wrote:
> > > Subject: Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts
> > > 
> > > On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > The LT PHY code is abusing intel_de_wait_custom() in all kinds of
> > > > weird ways. Get rid of the weird slow timeouts. If these are actually
> > > > needed then the fast timeouts should really be specified as the
> > > > default 2 microscond or something.
> > > >
> > > > This will let us eventually nuke intel_de_wait_custom() and convert
> > > > over to poll_timeout_us().
> > > >
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Suraj, any input here?
> > > 
> > > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> > > 
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_lt_phy.c      | 11 +++++------
> > > >  drivers/gpu/drm/i915/display/intel_lt_phy_regs.h |  1 -
> > > >  2 files changed, 5 insertions(+), 7 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > index 6fb68157b322..cc1d6b7a7de4 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > @@ -1178,10 +1178,9 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > > *encoder,
> > > >  	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
> > > port),
> > > >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> > > >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> > > > -				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
> > > > -				 XE3PLPD_MACCLK_TURNON_LATENCY_MS,
> > > NULL))
> > > > +				 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0,
> > > NULL))
> > > >  		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack
> > > not done after %dus.\n",
> > > > -			 phy_name(phy),
> > > XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
> > > > +			 phy_name(phy),
> > > XE3PLPD_MACCLK_TURNON_LATENCY_US);
> > 
> > According to Bspec: 74499
> > Latency can be either 21us for 1ms depending on what port is connected.
> > 
> >  > >
> > > >  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> > > >  		     XELPDP_FORWARD_CLOCK_UNGATE,
> > > > @@ -1192,7 +1191,7 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > > > *encoder,
> > > >
> > > >  	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
> > > port),
> > > >  				 lane_phy_current_status, 0,
> > > > -				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
> > > > +				 XE3PLPD_RESET_END_LATENCY_US, 0, NULL))
> > 
> > Bspec : 74499
> > Says 200us but 2ms (1.5ms to be precise) was the actual time we found the this to work properly
> > 
> > 
> > > >  		drm_warn(display->drm,
> > > >  			 "PHY %c failed to bring out of Lane reset after
> > > %dus.\n",
> > > >  			 phy_name(phy),
> > > XE3PLPD_RESET_END_LATENCY_US); @@ -1674,7 +1673,7
> > > > @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> > > >  		if (intel_de_wait_custom(display,
> > > XELPDP_PORT_CLOCK_CTL(display, port),
> > > >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> > > >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> > > > -
> > > XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
> > > > +
> > > XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
> > 
> > Ditto here.
> > 
> > > >  			drm_warn(display->drm, "PHY %c PLL MacCLK Ack
> > > assertion Timeout after %dus.\n",
> > > >  				 phy_name(phy),
> > > XE3PLPD_MACCLK_TURNON_LATENCY_US);
> > > >
> > > > @@ -1702,7 +1701,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> > > *encoder,
> > > >  		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1
> > > for Owned PHY Lanes. */
> > > >  		if (intel_de_wait_custom(display,
> > > XELPDP_PORT_BUF_CTL2(display, port),
> > > >  					 lane_phy_pulse_status,
> > > lane_phy_pulse_status,
> > > > -
> > > XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> > > > +
> > > XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
> > 
> > Ditto here.
> > I would suggest giving this a CI run on NVLS before merging this.
> 
> Since you have some idea why these magic numbers were chosen
> please redo all of these, and make sure to:
> - don't use intel_de_wait_custom() unless absolutely necessary
> - if you need to use intel_de_wait_custom() then either
>   use the default '2,<whatever ms>' or '<whatever us>,0' timeouts
> - document all the used timeouts. This is especially important
>   when they are not directly specified in bspec
> 
> > 
> > Regards,
> > Suraj Kandpal
> > 
> > > >  			drm_warn(display->drm, "PHY %c PLL rate not
> > > changed after %dus.\n",
> > > >  				 phy_name(phy),
> > > XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > > > b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > > > index 9223487d764e..36abc2bdbd9b 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > > > @@ -7,7 +7,6 @@
> > > >  #define __INTEL_LT_PHY_REGS_H__
> > > >
> > > >  #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
> > > > -#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
> > > >  #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
> > > >  #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
> > > >  #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50

Oh,and these do not belong in the regs.h file. If you feel the need
to have names for these (eg. if they are used multiple times) then
just put them in the .c file.

-- 
Ville Syrjälä
Intel

Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Jani Nikula]

On Thu, 06 Nov 2025, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Nov 06, 2025 at 12:03:28PM +0000, Kandpal, Suraj wrote:
>> > Subject: Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts
>> > 
>> > On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > >
>> > > The LT PHY code is abusing intel_de_wait_custom() in all kinds of
>> > > weird ways. Get rid of the weird slow timeouts. If these are actually
>> > > needed then the fast timeouts should really be specified as the
>> > > default 2 microscond or something.
>> > >
>> > > This will let us eventually nuke intel_de_wait_custom() and convert
>> > > over to poll_timeout_us().
>> > >
>> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > 
>> > Suraj, any input here?
>> > 
>> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>> > 
>> > > ---
>> > >  drivers/gpu/drm/i915/display/intel_lt_phy.c      | 11 +++++------
>> > >  drivers/gpu/drm/i915/display/intel_lt_phy_regs.h |  1 -
>> > >  2 files changed, 5 insertions(+), 7 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
>> > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
>> > > index 6fb68157b322..cc1d6b7a7de4 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
>> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
>> > > @@ -1178,10 +1178,9 @@ intel_lt_phy_lane_reset(struct intel_encoder
>> > *encoder,
>> > >  	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
>> > port),
>> > >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
>> > >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
>> > > -				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
>> > > -				 XE3PLPD_MACCLK_TURNON_LATENCY_MS,
>> > NULL))
>> > > +				 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0,
>> > NULL))
>> > >  		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack
>> > not done after %dus.\n",
>> > > -			 phy_name(phy),
>> > XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
>> > > +			 phy_name(phy),
>> > XE3PLPD_MACCLK_TURNON_LATENCY_US);
>> 
>> According to Bspec: 74499
>> Latency can be either 21us for 1ms depending on what port is connected.
>> 
>>  > >
>> > >  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
>> > >  		     XELPDP_FORWARD_CLOCK_UNGATE,
>> > > @@ -1192,7 +1191,7 @@ intel_lt_phy_lane_reset(struct intel_encoder
>> > > *encoder,
>> > >
>> > >  	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
>> > port),
>> > >  				 lane_phy_current_status, 0,
>> > > -				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
>> > > +				 XE3PLPD_RESET_END_LATENCY_US, 0, NULL))
>> 
>> Bspec : 74499
>> Says 200us but 2ms (1.5ms to be precise) was the actual time we found the this to work properly
>> 
>> 
>> > >  		drm_warn(display->drm,
>> > >  			 "PHY %c failed to bring out of Lane reset after
>> > %dus.\n",
>> > >  			 phy_name(phy),
>> > XE3PLPD_RESET_END_LATENCY_US); @@ -1674,7 +1673,7
>> > > @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>> > >  		if (intel_de_wait_custom(display,
>> > XELPDP_PORT_CLOCK_CTL(display, port),
>> > >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
>> > >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
>> > > -
>> > XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
>> > > +
>> > XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
>> 
>> Ditto here.
>> 
>> > >  			drm_warn(display->drm, "PHY %c PLL MacCLK Ack
>> > assertion Timeout after %dus.\n",
>> > >  				 phy_name(phy),
>> > XE3PLPD_MACCLK_TURNON_LATENCY_US);
>> > >
>> > > @@ -1702,7 +1701,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder
>> > *encoder,
>> > >  		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1
>> > for Owned PHY Lanes. */
>> > >  		if (intel_de_wait_custom(display,
>> > XELPDP_PORT_BUF_CTL2(display, port),
>> > >  					 lane_phy_pulse_status,
>> > lane_phy_pulse_status,
>> > > -
>> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
>> > > +
>> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
>> 
>> Ditto here.
>> I would suggest giving this a CI run on NVLS before merging this.
>
> Since you have some idea why these magic numbers were chosen
> please redo all of these, and make sure to:
> - don't use intel_de_wait_custom() unless absolutely necessary
> - if you need to use intel_de_wait_custom() then either
>   use the default '2,<whatever ms>' or '<whatever us>,0' timeouts
> - document all the used timeouts. This is especially important
>   when they are not directly specified in bspec

Yeah, should be intel_de_wait_for_{set,clear}() then probably.

We should probably change all of those from ms to us units to make them
more generally useful also for shorter waits.

BR,
Jni.


>
>> 
>> Regards,
>> Suraj Kandpal
>> 
>> > >  			drm_warn(display->drm, "PHY %c PLL rate not
>> > changed after %dus.\n",
>> > >  				 phy_name(phy),
>> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
>> > > b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
>> > > index 9223487d764e..36abc2bdbd9b 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
>> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
>> > > @@ -7,7 +7,6 @@
>> > >  #define __INTEL_LT_PHY_REGS_H__
>> > >
>> > >  #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
>> > > -#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
>> > >  #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
>> > >  #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
>> > >  #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
>> > 
>> > --
>> > Jani Nikula, Intel

-- 
Jani Nikula, Intel

RE: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Kandpal, Suraj]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Thursday, November 6, 2025 6:49 PM
> To: Ville Syrjälä <ville.syrjala@linux.intel.com>; Kandpal, Suraj
> <suraj.kandpal@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts
> 
> On Thu, 06 Nov 2025, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, Nov 06, 2025 at 12:03:28PM +0000, Kandpal, Suraj wrote:
> >> > Subject: Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts
> >> >
> >> > On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> >> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> > >
> >> > > The LT PHY code is abusing intel_de_wait_custom() in all kinds of
> >> > > weird ways. Get rid of the weird slow timeouts. If these are
> >> > > actually needed then the fast timeouts should really be specified
> >> > > as the default 2 microscond or something.
> >> > >
> >> > > This will let us eventually nuke intel_de_wait_custom() and
> >> > > convert over to poll_timeout_us().
> >> > >
> >> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> >
> >> > Suraj, any input here?
> >> >
> >> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> >> >
> >> > > ---
> >> > >  drivers/gpu/drm/i915/display/intel_lt_phy.c      | 11 +++++------
> >> > >  drivers/gpu/drm/i915/display/intel_lt_phy_regs.h |  1 -
> >> > >  2 files changed, 5 insertions(+), 7 deletions(-)
> >> > >
> >> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> >> > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> >> > > index 6fb68157b322..cc1d6b7a7de4 100644
> >> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> >> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> >> > > @@ -1178,10 +1178,9 @@ intel_lt_phy_lane_reset(struct
> >> > > intel_encoder
> >> > *encoder,
> >> > >  	if (intel_de_wait_custom(display,
> >> > > XELPDP_PORT_CLOCK_CTL(display,
> >> > port),
> >> > >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> >> > >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> >> > > -				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
> >> > > -				 XE3PLPD_MACCLK_TURNON_LATENCY_MS,
> >> > NULL))
> >> > > +				 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0,
> >> > NULL))
> >> > >  		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack
> >> > not done after %dus.\n",
> >> > > -			 phy_name(phy),
> >> > XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
> >> > > +			 phy_name(phy),
> >> > XE3PLPD_MACCLK_TURNON_LATENCY_US);
> >>
> >> According to Bspec: 74499
> >> Latency can be either 21us for 1ms depending on what port is connected.
> >>
> >>  > >
> >> > >  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> >> > >  		     XELPDP_FORWARD_CLOCK_UNGATE, @@ -1192,7 +1191,7
> @@
> >> > > intel_lt_phy_lane_reset(struct intel_encoder *encoder,
> >> > >
> >> > >  	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
> >> > port),
> >> > >  				 lane_phy_current_status, 0,
> >> > > -				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
> >> > > +				 XE3PLPD_RESET_END_LATENCY_US, 0, NULL))
> >>
> >> Bspec : 74499
> >> Says 200us but 2ms (1.5ms to be precise) was the actual time we found
> >> the this to work properly
> >>
> >>
> >> > >  		drm_warn(display->drm,
> >> > >  			 "PHY %c failed to bring out of Lane reset after
> >> > %dus.\n",
> >> > >  			 phy_name(phy),
> >> > XE3PLPD_RESET_END_LATENCY_US); @@ -1674,7 +1673,7
> >> > > @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> >> > >  		if (intel_de_wait_custom(display,
> >> > XELPDP_PORT_CLOCK_CTL(display, port),
> >> > >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> >> > >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> >> > > -
> >> > XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
> >> > > +
> >> > XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
> >>
> >> Ditto here.
> >>
> >> > >  			drm_warn(display->drm, "PHY %c PLL MacCLK Ack
> >> > assertion Timeout after %dus.\n",
> >> > >  				 phy_name(phy),
> >> > XE3PLPD_MACCLK_TURNON_LATENCY_US);
> >> > >
> >> > > @@ -1702,7 +1701,7 @@ void intel_lt_phy_pll_enable(struct
> >> > > intel_encoder
> >> > *encoder,
> >> > >  		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1
> >> > for Owned PHY Lanes. */
> >> > >  		if (intel_de_wait_custom(display,
> >> > XELPDP_PORT_BUF_CTL2(display, port),
> >> > >  					 lane_phy_pulse_status,
> >> > lane_phy_pulse_status,
> >> > > -
> >> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> >> > > +
> >> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
> >>
> >> Ditto here.
> >> I would suggest giving this a CI run on NVLS before merging this.
> >
> > Since you have some idea why these magic numbers were chosen please
> > redo all of these, and make sure to:
> > - don't use intel_de_wait_custom() unless absolutely necessary
> > - if you need to use intel_de_wait_custom() then either
> >   use the default '2,<whatever ms>' or '<whatever us>,0' timeouts
> > - document all the used timeouts. This is especially important
> >   when they are not directly specified in bspec
> 
> Yeah, should be intel_de_wait_for_{set,clear}() then probably.
> 
> We should probably change all of those from ms to us units to make them
> more generally useful also for shorter waits.

Sure let me take care of the lt phy and cx0 phy stuff in a separate series then

Regards,
Suraj Kandpal

> 
> BR,
> Jni.
> 
> 
> >
> >>
> >> Regards,
> >> Suraj Kandpal
> >>
> >> > >  			drm_warn(display->drm, "PHY %c PLL rate not
> >> > changed after %dus.\n",
> >> > >  				 phy_name(phy),
> >> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
> >> > >
> >> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> >> > > b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> >> > > index 9223487d764e..36abc2bdbd9b 100644
> >> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> >> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> >> > > @@ -7,7 +7,6 @@
> >> > >  #define __INTEL_LT_PHY_REGS_H__
> >> > >
> >> > >  #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
> >> > > -#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
> >> > >  #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
> >> > >  #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
> >> > >  #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
> >> >
> >> > --
> >> > Jani Nikula, Intel
> 
> --
> Jani Nikula, Intel

RE: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Jani Nikula]

On Fri, 07 Nov 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> > Since you have some idea why these magic numbers were chosen please
>> > redo all of these, and make sure to:
>> > - don't use intel_de_wait_custom() unless absolutely necessary
>> > - if you need to use intel_de_wait_custom() then either
>> >   use the default '2,<whatever ms>' or '<whatever us>,0' timeouts
>> > - document all the used timeouts. This is especially important
>> >   when they are not directly specified in bspec
>> 
>> Yeah, should be intel_de_wait_for_{set,clear}() then probably.
>> 
>> We should probably change all of those from ms to us units to make them
>> more generally useful also for shorter waits.
>
> Sure let me take care of the lt phy and cx0 phy stuff in a separate series then

This is what Ville followed up with [1].

BR,
Jani.


[1] https://lore.kernel.org/r/20251106152049.21115-1-ville.syrjala@linux.intel.com


-- 
Jani Nikula, Intel

RE: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Kandpal, Suraj]

> Subject: RE: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts
> 
> On Fri, 07 Nov 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
> >> > Since you have some idea why these magic numbers were chosen please
> >> > redo all of these, and make sure to:
> >> > - don't use intel_de_wait_custom() unless absolutely necessary
> >> > - if you need to use intel_de_wait_custom() then either
> >> >   use the default '2,<whatever ms>' or '<whatever us>,0' timeouts
> >> > - document all the used timeouts. This is especially important
> >> >   when they are not directly specified in bspec
> >>
> >> Yeah, should be intel_de_wait_for_{set,clear}() then probably.
> >>
> >> We should probably change all of those from ms to us units to make
> >> them more generally useful also for shorter waits.
> >
> > Sure let me take care of the lt phy and cx0 phy stuff in a separate
> > series then
> 
> This is what Ville followed up with [1].
> 
> BR,
> Jani.
> 
> 
> [1] https://lore.kernel.org/r/20251106152049.21115-1-
> ville.syrjala@linux.intel.com

Yes saw this,
Shouldn't cause any issue the way it is done now.

Regards,
Suraj Kandpal

> 
> 
> --
> Jani Nikula, Intel