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d="scan'208";a="199461824" Received: from rfrazer-mobl3.amr.corp.intel.com (HELO kuha) ([10.124.220.149]) by orviesa004.jf.intel.com with SMTP; 04 Dec 2025 05:25:17 -0800 Received: by kuha (sSMTP sendmail emulation); Thu, 04 Dec 2025 15:25:07 +0200 Date: Thu, 4 Dec 2025 15:25:07 +0200 From: Heikki Krogerus To: Raag Jadav Cc: intel-xe@lists.freedesktop.org, rodrigo.vivi@intel.com, andi.shyti@linux.intel.com Subject: Re: [PATCH v1] drm/xe/cri: Enable I2C controller Message-ID: References: <20251128084414.306265-1-raag.jadav@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251128084414.306265-1-raag.jadav@intel.com> X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Fri, Nov 28, 2025 at 02:14:14PM +0530, Raag Jadav kirjoitti: > Enable I2C controller for Crescent Island and while at it, rely on > has_i2c flag instead of manual platform checks. > > Signed-off-by: Raag Jadav FWIW: Reviewed-by: Heikki Krogerus > --- > drivers/gpu/drm/xe/xe_device_types.h | 2 ++ > drivers/gpu/drm/xe/xe_i2c.c | 2 +- > drivers/gpu/drm/xe/xe_pci.c | 3 +++ > drivers/gpu/drm/xe/xe_pci_types.h | 1 + > 4 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h > index 9a9a8eb84a78..e23c50273c28 100644 > --- a/drivers/gpu/drm/xe/xe_device_types.h > +++ b/drivers/gpu/drm/xe/xe_device_types.h > @@ -299,6 +299,8 @@ struct xe_device { > u8 has_heci_cscfi:1; > /** @info.has_heci_gscfi: device has heci gscfi */ > u8 has_heci_gscfi:1; > + /** @info.has_i2c: Device has I2C controller */ > + u8 has_i2c:1; > /** @info.has_late_bind: Device has firmware late binding support */ > u8 has_late_bind:1; > /** @info.has_llc: Device has a shared CPU+GPU last level cache */ > diff --git a/drivers/gpu/drm/xe/xe_i2c.c b/drivers/gpu/drm/xe/xe_i2c.c > index 0b5452be0c87..8eccbae05705 100644 > --- a/drivers/gpu/drm/xe/xe_i2c.c > +++ b/drivers/gpu/drm/xe/xe_i2c.c > @@ -319,7 +319,7 @@ int xe_i2c_probe(struct xe_device *xe) > struct xe_i2c *i2c; > int ret; > > - if (xe->info.platform != XE_BATTLEMAGE) > + if (!xe->info.has_i2c) > return 0; > > if (IS_SRIOV_VF(xe)) > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c > index 763f588521d0..2e2e9158d621 100644 > --- a/drivers/gpu/drm/xe/xe_pci.c > +++ b/drivers/gpu/drm/xe/xe_pci.c > @@ -366,6 +366,7 @@ static const struct xe_device_desc bmg_desc = { > .has_mbx_power_limits = true, > .has_gsc_nvm = 1, > .has_heci_cscfi = 1, > + .has_i2c = true, > .has_late_bind = true, > .has_sriov = true, > .has_mem_copy_instr = true, > @@ -411,6 +412,7 @@ static const struct xe_device_desc cri_desc = { > .dma_mask_size = 52, > .has_display = false, > .has_flat_ccs = false, > + .has_i2c = true, > .has_mbx_power_limits = true, > .has_mert = true, > .has_sriov = true, > @@ -676,6 +678,7 @@ static int xe_info_init_early(struct xe_device *xe, > xe->info.has_gsc_nvm = desc->has_gsc_nvm; > xe->info.has_heci_gscfi = desc->has_heci_gscfi; > xe->info.has_heci_cscfi = desc->has_heci_cscfi; > + xe->info.has_i2c = desc->has_i2c; > xe->info.has_late_bind = desc->has_late_bind; > xe->info.has_llc = desc->has_llc; > xe->info.has_mert = desc->has_mert; > diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h > index f19f35359696..6de23ddf6f68 100644 > --- a/drivers/gpu/drm/xe/xe_pci_types.h > +++ b/drivers/gpu/drm/xe/xe_pci_types.h > @@ -44,6 +44,7 @@ struct xe_device_desc { > u8 has_gsc_nvm:1; > u8 has_heci_gscfi:1; > u8 has_heci_cscfi:1; > + u8 has_i2c:1; > u8 has_late_bind:1; > u8 has_llc:1; > u8 has_mbx_power_limits:1; > -- > 2.43.0 -- heikki