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This > created a race window where the scheduler could run jobs before hardware > state was fully restored. > > This caused failures in eudebug tests (xe_exec_sip_eudebug@breakpoint- > waitsip-*) where TD_CTL register (containing TD_CTL_GLOBAL_DEBUG_ENABLE) > wasn't restored before jobs started executing. Breakpoints would fail to > trigger SIP entry because the debug enable bit wasn't set yet. > > Fix by moving engine register restoration before xe_uc_start(), ensuring > all hardware state is fully restored before any jobs can be scheduled. > > Signed-off-by: Jan Maslak > --- > drivers/gpu/drm/xe/xe_gt.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c > index 7caf781ba9e8..17642d71f98f 100644 > --- a/drivers/gpu/drm/xe/xe_gt.c > +++ b/drivers/gpu/drm/xe/xe_gt.c > @@ -771,13 +771,14 @@ static int do_gt_restart(struct xe_gt *gt) > xe_gt_sriov_pf_init_hw(gt); > > xe_mocs_init(gt); > - err = xe_uc_start(>->uc); > - if (err) > - return err; > > for_each_hw_engine(hwe, gt, id) > xe_reg_sr_apply_mmio(&hwe->reg_sr, gt); > > + err = xe_uc_start(>->uc); > + if (err) > + return err; > + > /* Get CCS mode in sync between sw/hw */ > xe_gt_apply_ccs_mode(gt); > I think you need to move this xe_gt_apply_ccs_mode as that is also writing MMIO registers that should be configured before bring the chip back to a live state. Also I think you need a fixes tag here as this is pretty clearly a bug. Matt > -- > 2.34.1 >