Re: [PATCH v15 06/10] drm/xe: Handle DPT in system memory

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Mon, Dec 08, 2025 at 08:17:17PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> 
> If DPT is allocated from system memory it will be created in the default
> write-back cached mode. This means we need to flush it after populating
> otherwise nothing works.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/xe/display/xe_fb_pin.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> index a22a9182dadb..89ee68c40329 100644
> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> @@ -3,6 +3,7 @@
>   * Copyright © 2021 Intel Corporation
>   */
>  
> +#include <drm/drm_cache.h>
>  #include <drm/ttm/ttm_bo.h>
>  
>  #include "i915_vma.h"
> @@ -162,6 +163,9 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
>  					  rot_info->plane[i].dst_stride);
>  	}
>  
> +	if (!xe_bo_is_vram(dpt) && !xe_bo_is_stolen(dpt))
> +		drm_clflush_virt_range(dpt->vmap.vaddr, dpt_size);

How is anything working currently if the DPT is being
created with the wrong caching mode?

Sounds like someone should fix the DPT creation to correctly
ask for UC/WC. But I suppose someone should measure if WB+flush
is actually faster...

> +
>  	vma->dpt = dpt;
>  	vma->node = dpt->ggtt_node[tile0->id];
>  
> -- 
> 2.52.0

-- 
Ville Syrjälä
Intel