Re: [PATCH 1/1] drm/xe/cri: vram addr range is expanded to bit[17:8]

[Matthew Brost <matthew.brost@intel.com>]

On Fri, Jan 09, 2026 at 09:36:50PM -0800, fei.yang@intel.com wrote:
> From: Fei Yang <fei.yang@intel.com>
> 
> There was a BSpec update to incorporate larger vram size.
> BSpec: 54991
> 
> Signed-off-by: Fei Yang <fei.yang@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_vram.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
> index c64d98bf1723..2159d9c33bb1 100644
> --- a/drivers/gpu/drm/xe/xe_vram.c
> +++ b/drivers/gpu/drm/xe/xe_vram.c
> @@ -155,7 +155,10 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
>  		*tile_offset = 0;
>  	} else {
>  		reg = xe_mmio_read32(&tile->mmio, SG_TILE_ADDR_RANGE(tile->id));
> -		*tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
> +		if (xe->info.platform == XE_CRESCENTISLAND)

I suspect that all future platforms will want to use GENMASK(17, 8), so
maybe an IP version check (e.g., greater than CRI, use GENMASK(17, 8)).

Alternatively, since bits 17–15 are reserved on prior platforms, they
presumably just read as zero—so another option is to blindly use
GENMASK(17, 8).

Matt

> +			*tile_size = (u64)REG_FIELD_GET(GENMASK(17, 8), reg) * SZ_1G;
> +		else
> +			*tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
>  		*tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G;
>  	}
>  
> -- 
> 2.43.0
>