Re: [PATCH 1/1] drm/xe: vram addr range is expanded to bit[17:8]

[Matthew Brost <matthew.brost@intel.com>]

On Mon, Jan 12, 2026 at 02:03:30PM -0800, fei.yang@intel.com wrote:
> From: Fei Yang <fei.yang@intel.com>
> 
> The bit field used to be [14:8] with [17:15] marked as SPARE and
> defaulted to 0. So, simply expand the read to bit[17:8] assuming
> the platforms using only bit[14:8] have zeros in the expanded bits.
> 
> BSpec: 54991
> 
> Signed-off-by: Fei Yang <fei.yang@intel.com>

Reviewed-by: Matthew Brost <matthew.brost@intel.com>

Also future reference single patches series do not need a cover letter.

Matt

> ---
>  drivers/gpu/drm/xe/xe_vram.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
> index c64d98bf1723..4f807eade2b7 100644
> --- a/drivers/gpu/drm/xe/xe_vram.c
> +++ b/drivers/gpu/drm/xe/xe_vram.c
> @@ -155,7 +155,7 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
>  		*tile_offset = 0;
>  	} else {
>  		reg = xe_mmio_read32(&tile->mmio, SG_TILE_ADDR_RANGE(tile->id));
> -		*tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
> +		*tile_size = (u64)REG_FIELD_GET(GENMASK(17, 8), reg) * SZ_1G;
>  		*tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G;
>  	}
>  
> -- 
> 2.43.0
>