From: Matthew Brost <matthew.brost@intel.com>
To: "Summers, Stuart" <stuart.summers@intel.com>
Cc: "intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>
Subject: Re: [PATCH v4 00/12] Context based TLB invalidations
Date: Thu, 15 Jan 2026 17:52:43 -0800 [thread overview]
Message-ID: <aWmZ606/bmio0jty@lstrano-desk.jf.intel.com> (raw)
In-Reply-To: <5f976f6fa03d6e508849593a936281394735af23.camel@intel.com>
On Thu, Jan 15, 2026 at 05:25:56PM -0700, Summers, Stuart wrote:
> Ok at least today, this definitely is going to need to be included with
> [1]. Without that, I'm seeing DMAR faults and various other issues. But
> with [1], I haven't seen any issues yet around the
> registration/deregistration, so I think the ref count model here is
> sound (as discussed inline of course as well).
>
> So:
> Tested-by: Stuart Summers <stuart.summers@intel.com>
Thanks.
>
> The only concern I have at this point is around the ring invalidations.
I have one bug to fix around multi-q too.
> Maybe we can discuss more in that review, but I'm a little hessitant to
> put a full R-B on this series unless we also include that other one or
> fixes that you had suggested (which needs more debug still).
>
I'm not sure ring invalidations is strickly related. I agree would
should reach on conclusion on what needs to be done there though.
I'm fairly behind at the moment. I think for ring invalidations it is
unfortunately going probably be at least week before I have bandwidth
to think about those :(.
Matt
> Thanks,
> Stuart
>
> [1]: https://patchwork.freedesktop.org/series/160057/
>
> On Mon, 2026-01-12 at 18:52 -0800, Matthew Brost wrote:
> > Add support for context based TLB invalidations.
> >
> > Matt
> >
> > Matthew Brost (12):
> > drm/xe: Add normalize_invalidation_range
> > drm/xe: Make usm.asid_to_vm allocation use GFP_NOWAIT
> > drm/xe: Add has_ctx_tlb_inval to device info
> > drm/xe: Add xe_device_asid_to_vm helper
> > drm/xe: Add vm to exec queues association
> > drm/xe: Taint TLB invalidation seqno lock with GFP_KERNEL
> > drm/xe: Rename send_tlb_inval_ppgtt to send_tlb_inval_asid_ppgtt
> > drm/xe: Add send_tlb_inval_ppgtt helper
> > drm/xe: Add xe_tlb_inval_idle helper
> > drm/xe: Add exec queue active vfunc
> > drm/xe: Add context-based invalidation to GuC TLB invalidation
> > backend
> > drm/xe: Enable context TLB invalidations for CI
> >
> > drivers/gpu/drm/xe/xe_device.c | 25 +++
> > drivers/gpu/drm/xe/xe_device.h | 11 +-
> > drivers/gpu/drm/xe/xe_device_types.h | 9 +
> > drivers/gpu/drm/xe/xe_exec_queue.c | 7 +-
> > drivers/gpu/drm/xe/xe_exec_queue_types.h | 5 +
> > drivers/gpu/drm/xe/xe_execlist.c | 7 +
> > drivers/gpu/drm/xe/xe_guc_submit.c | 6 +
> > drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 238 ++++++++++++++++++---
> > --
> > drivers/gpu/drm/xe/xe_pci.c | 2 +
> > drivers/gpu/drm/xe/xe_pci_types.h | 1 +
> > drivers/gpu/drm/xe/xe_tlb_inval.c | 33 ++++
> > drivers/gpu/drm/xe/xe_tlb_inval.h | 2 +
> > drivers/gpu/drm/xe/xe_vm.c | 64 +++++-
> > drivers/gpu/drm/xe/xe_vm.h | 3 +
> > drivers/gpu/drm/xe/xe_vm_types.h | 16 ++
> > 15 files changed, 375 insertions(+), 54 deletions(-)
> >
>
prev parent reply other threads:[~2026-01-16 1:52 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-13 2:52 [PATCH v4 00/12] Context based TLB invalidations Matthew Brost
2026-01-13 2:52 ` [PATCH v4 01/12] drm/xe: Add normalize_invalidation_range Matthew Brost
2026-01-13 2:52 ` [PATCH v4 02/12] drm/xe: Make usm.asid_to_vm allocation use GFP_NOWAIT Matthew Brost
2026-01-13 2:52 ` [PATCH v4 03/12] drm/xe: Add has_ctx_tlb_inval to device info Matthew Brost
2026-01-13 21:24 ` Summers, Stuart
2026-01-13 2:52 ` [PATCH v4 04/12] drm/xe: Add xe_device_asid_to_vm helper Matthew Brost
2026-01-13 2:52 ` [PATCH v4 05/12] drm/xe: Add vm to exec queues association Matthew Brost
2026-01-13 21:26 ` Summers, Stuart
2026-01-13 2:52 ` [PATCH v4 06/12] drm/xe: Taint TLB invalidation seqno lock with GFP_KERNEL Matthew Brost
2026-01-13 2:52 ` [PATCH v4 07/12] drm/xe: Rename send_tlb_inval_ppgtt to send_tlb_inval_asid_ppgtt Matthew Brost
2026-01-13 2:52 ` [PATCH v4 08/12] drm/xe: Add send_tlb_inval_ppgtt helper Matthew Brost
2026-01-13 2:52 ` [PATCH v4 09/12] drm/xe: Add xe_tlb_inval_idle helper Matthew Brost
2026-01-13 2:52 ` [PATCH v4 10/12] drm/xe: Add exec queue active vfunc Matthew Brost
2026-01-13 21:32 ` Summers, Stuart
2026-01-13 22:16 ` Matthew Brost
2026-01-13 22:21 ` Summers, Stuart
2026-01-14 21:17 ` Summers, Stuart
2026-01-13 2:52 ` [PATCH v4 11/12] drm/xe: Add context-based invalidation to GuC TLB invalidation backend Matthew Brost
2026-01-13 21:23 ` Summers, Stuart
2026-01-13 22:08 ` Matthew Brost
2026-01-13 23:25 ` Summers, Stuart
2026-01-14 0:25 ` Matthew Brost
2026-01-13 2:52 ` [PATCH v4 12/12] drm/xe: Enable context TLB invalidations for CI Matthew Brost
2026-01-13 3:00 ` ✓ CI.KUnit: success for Context based TLB invalidations (rev4) Patchwork
2026-01-13 3:41 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-13 9:45 ` ✓ Xe.CI.Full: " Patchwork
2026-01-16 0:25 ` [PATCH v4 00/12] Context based TLB invalidations Summers, Stuart
2026-01-16 1:52 ` Matthew Brost [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aWmZ606/bmio0jty@lstrano-desk.jf.intel.com \
--to=matthew.brost@intel.com \
--cc=intel-xe@lists.freedesktop.org \
--cc=stuart.summers@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox