public inbox for intel-xe@lists.freedesktop.org
 help / color / mirror / Atom feed
* [PATCH] drm/xe: Add POST_SYNC prefix to post sync instructions
@ 2025-04-24  9:29 Ravi Kumar Vodapalli
  2025-04-24 15:37 ` ✓ CI.Patch_applied: success for " Patchwork
                   ` (8 more replies)
  0 siblings, 9 replies; 15+ messages in thread
From: Ravi Kumar Vodapalli @ 2025-04-24  9:29 UTC (permalink / raw)
  To: intel-xe
  Cc: balasubramani.vivekanandan, matthew.d.roper, lucas.demarchi,
	gustavo.sousa, clinton.a.taylor, matthew.s.atwood,
	dnyaneshwar.bhadane, haridhar.kalvala, shekhar.chauhan

In existing code for PIPE CONTROL post sync operation instructions
POST_SYNC prefix is not present in the name, add it so that it will
represent it is a post sync operation type.

Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
---
 drivers/gpu/drm/xe/instructions/xe_gpu_commands.h | 2 +-
 drivers/gpu/drm/xe/xe_ring_ops.c                  | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/instructions/xe_gpu_commands.h b/drivers/gpu/drm/xe/instructions/xe_gpu_commands.h
index 8cfcd3360896..75efdacc4979 100644
--- a/drivers/gpu/drm/xe/instructions/xe_gpu_commands.h
+++ b/drivers/gpu/drm/xe/instructions/xe_gpu_commands.h
@@ -54,7 +54,7 @@
 #define   PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET		(1<<19)
 #define	  PIPE_CONTROL_TLB_INVALIDATE			BIT(18)
 #define   PIPE_CONTROL_PSD_SYNC				(1<<17)
-#define   PIPE_CONTROL_QW_WRITE				(1<<14)
+#define   PIPE_CONTROL_POST_SYNC_QW_WRITE		(1<<14)
 #define   PIPE_CONTROL_DEPTH_STALL			(1<<13)
 #define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12)
 #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11)
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index a7582b097ae6..da50213b78c5 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -145,7 +145,7 @@ static int emit_pipe_invalidate(u32 mask_flags, bool invalidate_tlb, u32 *dw,
 		PIPE_CONTROL_VF_CACHE_INVALIDATE |
 		PIPE_CONTROL_CONST_CACHE_INVALIDATE |
 		PIPE_CONTROL_STATE_CACHE_INVALIDATE |
-		PIPE_CONTROL_QW_WRITE |
+		PIPE_CONTROL_POST_SYNC_QW_WRITE |
 		PIPE_CONTROL_STORE_DATA_INDEX;
 
 	if (invalidate_tlb)
@@ -216,7 +216,7 @@ static int emit_pipe_imm_ggtt(u32 addr, u32 value, bool stall_only, u32 *dw,
 			      int i)
 {
 	u32 flags = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_GLOBAL_GTT_IVB |
-		    PIPE_CONTROL_QW_WRITE;
+		    PIPE_CONTROL_POST_SYNC_QW_WRITE;
 
 	if (!stall_only)
 		flags |= PIPE_CONTROL_FLUSH_ENABLE;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 15+ messages in thread

end of thread, other threads:[~2026-03-24  6:38 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-04-24  9:29 [PATCH] drm/xe: Add POST_SYNC prefix to post sync instructions Ravi Kumar Vodapalli
2025-04-24 15:37 ` ✓ CI.Patch_applied: success for " Patchwork
2025-04-24 15:37 ` ✗ CI.checkpatch: warning " Patchwork
2025-04-24 15:38 ` ✓ CI.KUnit: success " Patchwork
2025-04-24 15:47 ` ✓ CI.Build: " Patchwork
2025-04-24 15:49 ` ✗ CI.Hooks: failure " Patchwork
2025-04-24 15:50 ` ✓ CI.checksparse: success " Patchwork
2025-04-24 16:36 ` ✓ Xe.CI.BAT: " Patchwork
2025-04-25 12:27 ` ✗ Xe.CI.Full: failure " Patchwork
2025-05-12  6:42 ` [PATCH] " Bhadane, Dnyaneshwar
2025-05-21 12:50   ` Vodapalli, Ravi Kumar
2026-02-19 19:33   ` Matthew Brost
2026-03-23 19:27     ` Vodapalli, Ravi Kumar
2026-03-24  6:37       ` Bhadane, Dnyaneshwar
2026-03-23 19:43     ` Vodapalli, Ravi Kumar

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox