From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B0D1FC616A for ; Fri, 13 Sep 2024 17:58:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6698010E096; Fri, 13 Sep 2024 17:58:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="U+zhdEIl"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8D83A10E096; Fri, 13 Sep 2024 17:58:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726250290; x=1757786290; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=H7Yz3dfytNZ1zvBYOm2N1qFKjIgWDm5DFgICqnKD8M4=; b=U+zhdEIldYLjVi8wghapJYqQWo8zoRdG/ZKJIvIeMNqor9ggQgMehcte 4JUFR2wMBIxbdhRkODkeiaLISMz9f8vFw+ONTIGaxoun/PC7aNSmbvpCB dJGRshaT980M9qUiqnSLscLZ1fhEhz5Fe+S0Kb1j3zZbalCCNfGISnqEM bQU2bpXEcesW14TqJXaRtYwIbkTDXQayx/8LdJCHjfOWBh/neiGnahtr4 /TSpVaYT+eRwwJbkCGNL3JhSjM4Dfe8Tq9jw8sr49TkJ9jImqVVWJSbAm POZAMO4k4+tocJOEgNN6lftkrMeOhixXcWtUHVGBGaBkFmkhrdUVvLi1P A==; X-CSE-ConnectionGUID: UIuK1v0zQjSxqXG15XJ4Zg== X-CSE-MsgGUID: acmObzNuTDOiP7E5VlewQg== X-IronPort-AV: E=McAfee;i="6700,10204,11194"; a="24985848" X-IronPort-AV: E=Sophos;i="6.10,226,1719903600"; d="scan'208";a="24985848" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2024 10:58:09 -0700 X-CSE-ConnectionGUID: HBwUtqwOTcuGi17ivmaSmA== X-CSE-MsgGUID: 9nzbUaPVT3OCR/UhKEjroA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,226,1719903600"; d="scan'208";a="72735314" Received: from johunt-mobl9.ger.corp.intel.com (HELO [10.245.245.187]) ([10.245.245.187]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2024 10:58:07 -0700 Message-ID: Date: Fri, 13 Sep 2024 19:58:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] drm/xe: Fix DSB buffer coherency To: Matthew Auld , intel-xe@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org References: <20240913114754.7956-1-maarten.lankhorst@linux.intel.com> <20240913114754.7956-2-maarten.lankhorst@linux.intel.com> <41a9a2c5-91c6-4079-b73d-087ebc8d68c5@intel.com> Content-Language: en-US From: Maarten Lankhorst In-Reply-To: <41a9a2c5-91c6-4079-b73d-087ebc8d68c5@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Den 2024-09-13 kl. 14:04, skrev Matthew Auld: > On 13/09/2024 12:47, Maarten Lankhorst wrote: >> Add the scanout flag to force WC caching, and add the memory barrier >> where needed. >> >> Signed-off-by: Maarten Lankhorst >> --- >>   drivers/gpu/drm/xe/display/xe_dsb_buffer.c | 5 +++-- >>   1 file changed, 3 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c >> index f99d901a3214f..f7949bf5426af 100644 >> --- a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c >> +++ b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c >> @@ -48,11 +48,12 @@ bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *d >>       if (!vma) >>           return false; >>   +    /* Set scanout flag for WC mapping */ >>       obj = xe_bo_create_pin_map(xe, xe_device_get_root_tile(xe), >>                      NULL, PAGE_ALIGN(size), >>                      ttm_bo_type_kernel, >>                      XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) | >> -                   XE_BO_FLAG_GGTT); >> +                   XE_BO_FLAG_SCANOUT | XE_BO_FLAG_GGTT); >>       if (IS_ERR(obj)) { >>           kfree(vma); >>           return false; >> @@ -73,5 +74,5 @@ void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf) >>     void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf) >>   { >> -    /* TODO: add xe specific flush_map() for dsb buffer object. */ >> +    xe_device_wmb(dsb_buf->vma->bo->tile->xe); > > Kind of orthogonal, but we could maybe also move the l2 flush here? I assume it's better to flush once at the end. Eww, I didn't see that one. I totally would have if I saw it, the amount of calls for a single 4 byte write would remove any point of using DSB on BMG otherwise. I'll send a followup patch. :) > Reviewed-by: Matthew Auld > >>   }