[PATCH v18 3/9] drm/xe/xelpg: Limit AuxCCS ring buffer programming to Alderlake

Tvrtko Ursulin
2026-03-04T13:03:24Z

At the moment the driver does not support AuxCCS at all due respective
modifiers being hidden from userspace.

As we are about to start enabling them, starting with Alderlake, let us
begin by limiting the ring buffer support to just that initial platform.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/xe/xe_ring_ops.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 53d420d72164..07235a895f4b 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -305,9 +305,9 @@ static bool has_aux_ccs(struct xe_device *xe)
* PVC is a special case that has no compression of either type
* (FlatCCS or AuxCCS). Also, AuxCCS is no longer used from Xe2
* onward, so any future platforms with no FlatCCS will not have
- * AuxCCS either.
+ * AuxCCS, and we explicity do not want to support it on MTL.
*/
- if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC)
+ if (GRAPHICS_VERx100(xe) >= 1270 || xe->info.platform == XE_PVC)
return false;

return !xe->info.has_flat_ccs;
--
2.52.0