Re: [PATCH v2 09/11] drm/xe/xe_ras: Add structures for SoC Internal errors

Mallesh, Koujalagi
2026-03-10T13:02:20Z

On 02-03-2026 03:52 pm, Riana Tauro wrote:
> Add response structures for SoC Internal errors.
>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
> drivers/gpu/drm/xe/xe_ras_types.h | 134 ++++++++++++++++++++++++++++++
> 1 file changed, 134 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> index 221d07efd84c..466db9f47127 100644
> --- a/drivers/gpu/drm/xe/xe_ras_types.h
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -145,4 +145,138 @@ struct xe_ras_compute_error {
> u32 spare_log3;
> } __packed;
>
Add hardware component glossary to more understanding.
> +/**
> + * struct xe_ras_soc_error_source - Source of SOC error
> + */
> +struct xe_ras_soc_error_source {
> + /** @csc: CSC error */
> + u32 csc:1;
> + /** @soc: SOC error */
> + u32 soc:1;
> + /** @reserved: Reserved for future use */
> + u32 reserved:30;
> +} __packed;
> +
> +/**
> + * struct xe_ras_soc_error - SOC error details
> + */
> +struct xe_ras_soc_error {
> + /** @error_source: Error Source */
> + struct xe_ras_soc_error_source error_source;
> + /** @additional_details: Additional details */
> + u32 additional_details[15];
Use Macro
> +} __packed;
> +
> +/**
> + * struct xe_ras_csc_error - CSC error details
> + */
> +struct xe_ras_csc_error {
> + /** @hec_uncorr_err_status: CSC error */
> + u32 hec_uncorr_err_status;
> + /** @hec_uncorr_fw_err_dw0: CSC f/w error */
> + u32 hec_uncorr_fw_err_dw0;
> +} __packed;
> +
> +/**
> + * struct xe_ras_ieh_error - SoC IEH error details
> + */
> +struct xe_ras_ieh_error {
> + /** @ieh_instance: IEH instance */
> + u32 ieh_instance:2;
> + /** @reserved: Reserved for future use */
> + u32 reserved:30;
> + union {
> + /** @global_error_status: Global error status */
> + u32 global_error_status;
> + /** @error_sources_ieh0: Error sources for IEH0 */
> + struct {
> + /** @psf0_psf1_npk: PSF0, PSF1, NPK */
> + u32 psf0_psf1_npk:1;
> + /** @punit: PUNIT */
> + u32 punit:1;
> + /** @reserved_2: Reserved */
> + u32 reserved_2:1;
> + /** @oobmsm: OOBMSM */
> + u32 oobmsm:1;
> + /** @i2c: I2C */
> + u32 i2c:1;
> + /** @pciess_gpma: PCIESS GPMA */
> + u32 pciess_gpma:1;
> + /** @lpioss_pma: LPIOSS PMA */
> + u32 lpioss_pma:1;
> + /** @fabss0_pma: FabSS0 PMA */
> + u32 fabss0_pma:1;
> + /** @fabss1_pma: FabSS1 PMA */
> + u32 fabss1_pma:1;
> + /** @reserved_9: Reserved */
> + u32 reserved_9:1;
> + /** @reserved_10: Reserved */
> + u32 reserved_10:1;
> + /** @reserved_11: Reserved */
> + u32 reserved_11:1;
> + /** @reserved_12: Reserved */
> + u32 reserved_12:1;
> + /** @reserved_13: Reserved */
> + u32 reserved_13:1;
> + /** @memss_ieh1: MEMSS -> IEH1 */
> + u32 memss_ieh1:1;
> + /** @memss_ieh2: MEMSS -> IEH2 */
> + u32 memss_ieh2:1;
> + /** @saf0_mhb0: SAF0 MHB0 */
> + u32 saf0_mhb0:1;
> + /** @saf0_mhb1: SAF0 MHB1 */
> + u32 saf0_mhb1:1;
> + /** @saf0_mhb2: SAF0 MHB2 */
Please remove space
> + u32 saf0_mhb2:1;
> + /** @saf0_mhb3: SAF0 MHB3 */
> + u32 saf0_mhb3:1;
> + /** @saf0_mhb4: SAF0 MHB4 */
> + u32 saf0_mhb4:1;
> + /** @saf0_mhb5: SAF0 MHB5 */
> + u32 saf0_mhb5:1;
> + /** @saf0_mhb6: SAF0 MHB6 */
> + u32 saf0_mhb6:1;
> + /** @saf0_mhb7: SAF0 MHB7 */
> + u32 saf0_mhb7:1;
> + /** @saf1_mhb0: SAF1 MHB0 */
> + u32 saf1_mhb0:1;
> + /** @saf1_mhb1: SAF1 MHB1 */
> + u32 saf1_mhb1:1;
> + /** @saf1_mhb2: SAF1 MHB2 */
> + u32 saf1_mhb2:1;
> + /** @saf1_mhb3: SAF1 MHB3 */
> + u32 saf1_mhb3:1;
> + /** @saf1_mhb4: SAF1 MHB4 */
> + u32 saf1_mhb4:1;
> + /** @saf1_mhb5: SAF1 MHB5 */
> + u32 saf1_mhb5:1;
> + /** @saf1_mhb6: SAF1 MHB6 */
> + u32 saf1_mhb6:1;
> + /** @saf1_mhb7: SAF1 MHB7 */
> + u32 saf1_mhb7:1;
> + } error_sources_ieh0;
> + };
> +
> + /** @lerr_status_ieh0: Local error status of IEH0 */
> + struct {
> + /** @reserved_0: Reserved for future use */
> + u32 reserved_0:1;
> + /** @psf0: PSF0 */
> + u32 psf0:1;
> + /** @psf1: PSF1 */
> + u32 psf1:1;
> + /** @reserved_26: Reserved */
> + u32 reserved_26:26;
Reserved bit 3_28 right?, need to change name
> + /** @npk: NPK */
> + u32 npk:1;
> + /** @reserved_30: Reserved */
> + u32 reserved_30:2;
Reserved bit 30_31 right?
> + } lerr_status_ieh0;
> +
> + /** @gerr_mask: Global error mask */
> + u32 gerr_mask;
> + /** @additional_info: Additional information */
> + u32 additional_info[10];

ditto above

Thanks

-/Mallesh

> +} __packed;
> +
> #endif