Re: [PATCH v21 8/9] drm/xe/display: Add support for AuxCCS

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Tue, Mar 10, 2026 at 12:34:52PM +0000, Tvrtko Ursulin wrote:
> Add support for mapping the auxiliary CCS buffer into the DPT page tables.
> 
> This will allow for better power efficiency by enabling the render
> compression frame buffer modifiers such as
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS in a following patch.
> 
> We do this by refactoring the code a bit so handling for the linear
> auxiliary frame buffer can be added in a tidy way. Also replace some
> hardcoded constants.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> Cc: Michael J. Ruhl <michael.j.ruhl@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

I hope one of them can review this patch.

To me, it would be easier if we could split this patch into smaller
easier to follow patches.

> ---
>  drivers/gpu/drm/xe/display/xe_fb_pin.c | 111 ++++++++++++++++++-------
>  1 file changed, 81 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> index df7d305c6fcd..fe4b66e5c3ad 100644
> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> @@ -49,33 +49,94 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_
>  	*dpt_ofs = ALIGN(*dpt_ofs, 4096);
>  }
>  
> +static unsigned int
> +write_dpt_padding(struct iosys_map *map, unsigned int dest, unsigned int pad)
> +{
> +	/* The DE ignores the PTEs for the padding tiles */
> +	return dest + pad * sizeof(u64);
> +}
> +
> +static unsigned int
> +write_dpt_remapped_linear(struct xe_bo *bo, struct iosys_map *map,
> +			  unsigned int dest,
> +			  const struct intel_remapped_plane_info *plane)
> +{
> +	struct xe_device *xe = xe_bo_device(bo);
> +	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
> +	const u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo,
> +						 xe->pat.idx[XE_CACHE_NONE]);
> +	unsigned int offset = plane->offset * XE_PAGE_SIZE;
> +	unsigned int size = plane->size;
> +
> +	while (size--) {
> +		u64 addr = xe_bo_addr(bo, offset, XE_PAGE_SIZE);
> +
> +		iosys_map_wr(map, dest, u64, addr | pte);
> +		dest += sizeof(u64);
> +		offset += XE_PAGE_SIZE;
> +	}
> +
> +	return dest;
> +}
> +
> +static unsigned int
> +write_dpt_remapped_tiled(struct xe_bo *bo, struct iosys_map *map,
> +			 unsigned int dest,
> +			 const struct intel_remapped_plane_info *plane)
> +{
> +	struct xe_device *xe = xe_bo_device(bo);
> +	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
> +	const u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo,
> +						 xe->pat.idx[XE_CACHE_NONE]);
> +	unsigned int offset, column, row;
> +
> +	for (row = 0; row < plane->height; row++) {
> +		offset = (plane->offset + plane->src_stride * row) *
> +			 XE_PAGE_SIZE;
> +
> +		for (column = 0; column < plane->width; column++) {
> +			u64 addr = xe_bo_addr(bo, offset, XE_PAGE_SIZE);
> +
> +			iosys_map_wr(map, dest, u64, addr | pte);
> +			dest += sizeof(u64);
> +			offset += XE_PAGE_SIZE;
> +		}
> +
> +		dest = write_dpt_padding(map, dest,
> +					 plane->dst_stride - plane->width);
> +	}
> +
> +	return dest;
> +}
> +
>  static void
> -write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs,
> -		   u32 bo_ofs, u32 width, u32 height, u32 src_stride,
> -		   u32 dst_stride)
> +write_dpt_remapped(struct xe_bo *bo,
> +		   const struct intel_remapped_info *remap_info,
> +		   struct iosys_map *map)
>  {
> -	struct xe_device *xe = xe_bo_device(bo);
> -	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
> -	u32 column, row;
> -	u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]);
> +	unsigned int i, dest = 0;
>  
> -	for (row = 0; row < height; row++) {
> -		u32 src_idx = src_stride * row + bo_ofs;
> +	for (i = 0; i < ARRAY_SIZE(remap_info->plane); i++) {
> +		const struct intel_remapped_plane_info *plane =
> +						&remap_info->plane[i];
>  
> -		for (column = 0; column < width; column++) {
> -			u64 addr = xe_bo_addr(bo, src_idx * XE_PAGE_SIZE, XE_PAGE_SIZE);
> -			iosys_map_wr(map, *dpt_ofs, u64, pte | addr);
> +		if (!plane->width && !plane->height && !plane->linear)
> +			continue;
>  
> -			*dpt_ofs += 8;
> -			src_idx++;
> +		if (remap_info->plane_alignment) {
> +			const unsigned int index = dest / sizeof(u64);
> +			const unsigned int pad =
> +				ALIGN(index, remap_info->plane_alignment) -
> +				index;
> +
> +			dest = write_dpt_padding(map, dest, pad);
>  		}
>  
> -		/* The DE ignores the PTEs for the padding tiles */
> -		*dpt_ofs += (dst_stride - width) * 8;
> +		if (plane->linear)
> +			dest = write_dpt_remapped_linear(bo, map, dest, plane);
> +		else
> +			dest = write_dpt_remapped_tiled(bo, map, dest, plane);
>  	}
> -
> -	/* Align to next page */
> -	*dpt_ofs = ALIGN(*dpt_ofs, 4096);
>  }
>  
>  static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
> @@ -138,17 +199,7 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
>  			iosys_map_wr(&dpt->vmap, x * 8, u64, pte | addr);
>  		}
>  	} else if (view->type == I915_GTT_VIEW_REMAPPED) {
> -		const struct intel_remapped_info *remap_info = &view->remapped;
> -		u32 i, dpt_ofs = 0;
> -
> -		for (i = 0; i < ARRAY_SIZE(remap_info->plane); i++)
> -			write_dpt_remapped(bo, &dpt->vmap, &dpt_ofs,
> -					   remap_info->plane[i].offset,
> -					   remap_info->plane[i].width,
> -					   remap_info->plane[i].height,
> -					   remap_info->plane[i].src_stride,
> -					   remap_info->plane[i].dst_stride);
> -
> +		write_dpt_remapped(bo, &view->remapped, &dpt->vmap);
>  	} else {
>  		const struct intel_rotation_info *rot_info = &view->rotated;
>  		u32 i, dpt_ofs = 0;
> -- 
> 2.52.0
>