[PATCH 00/19] Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM

[PATCH 00/19] Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM

[Ankit Nautiyal]

Enable Adaptive Sync SDP for Panel replay + auxless ALPM.
First few patches are fixes in existing AS SDP enablement.
Later patches add the support to send AS SDP for Panel replay with Link
ON and with auxless ALPM (Link-Off). 

This series is in continuation from discussions in [1] [2] and more
recent [3]:

Apart from few patches from [3] new changes include:
- Some clean up in drm/dp Macros
- Add new DPCD bit to get FAVT PAYLOAD FIELDS PARSING SUPPORT.
- Add AS SDP version and PR and VRR specific bits in drm_dp.h.
- Modify AS SDP compute config to accomodate PR with Link On and Link
  Off.
- Program Downspread Ctrl DPCD bits.
- Make way for T1 and T2 AS SDP transmission timing/position.

[1] https://lore.kernel.org/all/1b8c6c6de1e5fe0db83e6ae942dfee7e6f950767.camel@intel.com/
[2] https://lore.kernel.org/all/aPtqdAxDwiuQZbrn@intel.com/
[3] https://lore.kernel.org/intel-gfx/7c2d6f4e-69e6-452a-89cc-5fd4254430bd@intel.com/T/#m6e8beab2cc3b6ff9d61f740f107d83a2f4e08114

Rev2:
 - Drop the redundant version member for AS SDP, and use the member
   revision
 - Drop member to store AS SDP transmission time, use simple helper
   instead.
 - Use Burst mode to write Panel Replay config DPCDs.
 - Split AS SDP configuration in compute_config() and
   compute_config_late() phase.
 - Always enable AS SDP whenever supported by source + sink.

Ankit Nautiyal (19):
  drm/dp: Rename and relocate AS SDP payload field masks
  drm/dp: Clean up DPRX feature enumeration macros
  drm/dp: Add bits for AS SDP FAVT Payload Fields Parsing support
  include/drm/display/dp: Add DPCD registers for configuring Panel
    Replay + VRR
  drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP
  drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink
  drm/i915/dp: Account for AS_SDP guardband only when enabled
  drm/i915/dp: Add a helper to decide if AS SDP can be used
  drm/i915/dp: Skip AS SDP for DP branch devices
  drm/i915/dp: Use revision field of AS SDP data structure
  drm/i915/dp: Add member to intel_dp to store AS SDP v2 support
  drm/i915/psr: Write the PR config DPCDs in burst mode
  drm/i915/display: Add helper for AS SDP transmission time selection
  drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission
    time
  drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless
    ALPM
  drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off
  drm/i915/dp: Split AS SDP computation between compute_config and
    compute_config_late
  drm/i915/dp: Make provision for AS SDP version 1
  drm/i915/dp: Always enable AS SDP if supported by source + sink

 drivers/gpu/drm/i915/display/intel_alpm.c     |  20 ++-
 drivers/gpu/drm/i915/display/intel_display.c  |   3 +-
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 151 ++++++++++++++----
 drivers/gpu/drm/i915/display/intel_dp.h       |   2 +
 .../drm/i915/display/intel_dp_link_training.c |  10 +-
 .../drm/i915/display/intel_dp_link_training.h |   3 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  20 ++-
 drivers/gpu/drm/i915/display/intel_vrr.c      |  10 ++
 include/drm/display/drm_dp.h                  |  23 ++-
 11 files changed, 195 insertions(+), 50 deletions(-)

-- 
2.45.2

[PATCH 01/19] drm/dp: Rename and relocate AS SDP payload field masks

[Ankit Nautiyal]

The AS SDP payload field masks were misnamed and placed under the DPRX
feature enumeration list. These are not DPRX capability bits, but are
payload field masks for the Adaptive Sync SDP.

Relocate both masks next to the AS SDP definitions.
Update users to the corrected names. No functional change.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
 include/drm/display/drm_dp.h            | 5 +++--
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fbb5e2f9c241..cd1539c3268c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5295,8 +5295,8 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	if ((sdp->sdp_header.HB3 & 0x3F) != 9)
 		return -EINVAL;
 
-	as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
-	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
+	as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK;
+	as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
 	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
 	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 8b15d3eeb716..4ea3b5b08a12 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1204,8 +1204,6 @@
 
 #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1         0x2214 /* 2.0 E11 */
 # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED    (1 << 0)
-# define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE		GENMASK(1, 0)
-# define DP_ADAPTIVE_SYNC_SDP_LENGTH				GENMASK(5, 0)
 # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)
 # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED  (1 << 4)
 
@@ -1870,4 +1868,7 @@ enum operation_mode {
 	DP_AS_SDP_FAVT_TRR_REACHED = 0x03
 };
 
+#define DP_AS_SDP_OPERATION_MODE_MASK	GENMASK(1, 0)
+#define DP_AS_SDP_LENGTH_MASK		GENMASK(5, 0)
+
 #endif /* _DRM_DP_H_ */
-- 
2.45.2

[PATCH 02/19] drm/dp: Clean up DPRX feature enumeration macros

[Ankit Nautiyal]

Align the DP_DPRX feature enumeration macros for better readability and
consistency, and use the BIT() macro instead of open-coded shifts.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 include/drm/display/drm_dp.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 4ea3b5b08a12..49f0154eb93c 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1202,10 +1202,10 @@
 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_80_MS	0x04
 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_100_MS	0x05
 
-#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1         0x2214 /* 2.0 E11 */
-# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED    (1 << 0)
-# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)
-# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED  (1 << 4)
+#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1					0x2214 /* 2.0 E11 */
+# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED						BIT(0)
+# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED	BIT(1)
+# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED				BIT(4)
 
 #define DP_128B132B_SUPPORTED_LINK_RATES       0x2215 /* 2.0 */
 # define DP_UHBR10                             (1 << 0)
-- 
2.45.2

[PATCH 03/19] drm/dp: Add bits for AS SDP FAVT Payload Fields Parsing support

[Ankit Nautiyal]

DP v2.1 introduced support for sending AS SDP payload bytes for FAVT.
Add the relavant bits for the same.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 include/drm/display/drm_dp.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 49f0154eb93c..8d172863eba3 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1205,6 +1205,7 @@
 #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1					0x2214 /* 2.0 E11 */
 # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED						BIT(0)
 # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED	BIT(1)
+# define DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED			BIT(2) /* 2.1 */
 # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED				BIT(4)
 
 #define DP_128B132B_SUPPORTED_LINK_RATES       0x2215 /* 2.0 */
-- 
2.45.2

[PATCH 04/19] drm/dp: Add DPCD for configuring AS SDP for PR + VRR

[Ankit Nautiyal]

Add additional DPCDs required to be configured to support VRR with Panel
Replay. These DPCDs are specifically required for configuring Adaptive Sync
SDP and are introduced in DP v2.1.

v2:
 - Correct the shift for the bits. (Ville)
 - Add DP_PR_ prefix for the PR-related fields.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 include/drm/display/drm_dp.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 8d172863eba3..e6752a92d5dc 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -775,6 +775,15 @@
 # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK  (0xf << 3)
 # define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE		 (1 << 7)
 
+#define PANEL_REPLAY_CONFIG3				0x11a /* DP 2.1 */
+# define DP_PR_AS_SDP_SETUP_TIME_SHIFT			6
+# define DP_PR_AS_SDP_SETUP_TIME_MASK			(3 << DP_PR_AS_SDP_SETUP_TIME_SHIFT)
+# define DP_PR_AS_SDP_SETUP_TIME_T1			0
+# define DP_PR_AS_SDP_SETUP_TIME_DYNAMIC		1 /* DP 2.1 Table 2-227 */
+# define DP_PR_AS_SDP_SETUP_TIME_T2			2
+# define DP_PR_AS_SDP_SETUP_TIME(t)			(((t) << DP_PR_AS_SDP_SETUP_TIME_SHIFT) & \
+							 DP_PR_AS_SDP_SETUP_TIME_MASK)
+
 #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
-- 
2.45.2

[PATCH 05/19] drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP

[Ankit Nautiyal]

Correct the bit-shift logic to properly readback the 10 bit target_rr from
DB3 and DB4.

v2: Align the style with readback for vtotal. (Ville)

Fixes: 12ea89291603 ("drm/i915/dp: Add Read/Write support for Adaptive Sync SDP")
Cc: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index cd1539c3268c..108d2e338e3a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5298,7 +5298,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK;
 	as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
-	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
+	as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
 	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
 
 	return 0;
-- 
2.45.2

[PATCH 06/19] drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink

[Ankit Nautiyal]

Currently we do not support VRR with HDMI so skip vrr compute
config step for all DP branch devices.

v2: Restrict VRR on all DP branch devices instead for checking only for
    HDMI. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 8a957804cb97..160e1c24aa4b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -55,6 +55,16 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
 		if (connector->mst.dp)
 			return false;
 		intel_dp = intel_attached_dp(connector);
+		/*
+		 * Among non-MST DP branch devices, only an HDMI 2.1 sink connected
+		 * via a PCON could support VRR. However, supporting VRR through a
+		 * PCON requires non-trivial changes that are not implemented yet.
+		 * Until that support exists, avoid VRR on all DP branch devices.
+		 *
+		 * TODO: Add support for VRR for DP->HDMI 2.1 PCON.
+		 */
+		if (drm_dp_is_branch(intel_dp->dpcd))
+			return false;
 
 		if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))
 			return false;
-- 
2.45.2

[PATCH 07/19] drm/i915/dp: Account for AS_SDP guardband only when enabled

[Ankit Nautiyal]

Currently the intel_dp_sdp_min_guardband() accounts for AS_SDP for all
platforms that support adaptive sync SDP even for configurations where
it cannot be enabled. Instead account for adaptive sync SDP guardband
only when it is enabled.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 108d2e338e3a..10927bc836d6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7364,7 +7364,6 @@ int intel_dp_get_lines_for_sdp(const struct intel_crtc_state *crtc_state, u32 ty
 int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 			       bool assume_all_enabled)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
 	int sdp_guardband = 0;
 
 	if (assume_all_enabled ||
@@ -7379,8 +7378,8 @@ int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 		sdp_guardband = max(sdp_guardband,
 				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_PPS));
 
-	if ((assume_all_enabled && HAS_AS_SDP(display)) ||
-	    crtc_state->infoframes.enable & intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
+	if (crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
 		sdp_guardband = max(sdp_guardband,
 				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_ADAPTIVE_SYNC));
 
-- 
2.45.2

[PATCH 08/19] drm/i915/dp: Add a helper to decide if AS SDP can be used

[Ankit Nautiyal]

Add a helper that determines whether AS SDP can be used for the
current DP configuration. For now this is true only when the sink
supports AS SDP and VRR is enabled, but more conditions may be added
later.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 10927bc836d6..41908f68ffba 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3124,6 +3124,15 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
 	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
 }
 
+static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
+				    struct intel_crtc_state *crtc_state)
+{
+	if (!intel_dp->as_sdp_supported)
+		return false;
+
+	return crtc_state->vrr.enable;
+}
+
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
@@ -3131,7 +3140,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
 
-	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
+	if (!intel_dp_can_use_as_sdp(intel_dp, crtc_state))
 		return;
 
 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
-- 
2.45.2

[PATCH 09/19] drm/i915/dp: Skip AS SDP for DP branch devices

[Ankit Nautiyal]

Currently, VRR is not implmented for DP branch devices.
So skip sending AS SDP for them.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 41908f68ffba..17af68a1a9e5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3130,6 +3130,12 @@ static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
 	if (!intel_dp->as_sdp_supported)
 		return false;
 
+	/*
+	 * #TODO Implement AS SDP for DP branch device.
+	 */
+	if (drm_dp_is_branch(intel_dp->dpcd))
+		return false;
+
 	return crtc_state->vrr.enable;
 }
 
-- 
2.45.2

[PATCH 10/19] drm/i915/dp: Use revision field of AS SDP data structure

[Ankit Nautiyal]

Use the revision field of struct drm_dp_as_sdp instead of current
hardcoding for the AS SDP revisions.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
 drivers/gpu/drm/i915/display/intel_dp.c      | 7 +++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b18ce0c36a64..88e1b503d301 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4900,7 +4900,8 @@ static bool
 intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
 			const struct drm_dp_as_sdp *b)
 {
-	return a->vtotal == b->vtotal &&
+	return a->revision == b->revision &&
+		a->vtotal == b->vtotal &&
 		a->target_rr == b->target_rr &&
 		a->duration_incr_ms == b->duration_incr_ms &&
 		a->duration_decr_ms == b->duration_decr_ms &&
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 17af68a1a9e5..0d2403d48528 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3154,6 +3154,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
 	as_sdp->length = 0x9;
 	as_sdp->duration_incr_ms = 0;
+	as_sdp->revision = 0x2;
 	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
 
 	if (crtc_state->cmrr.enable) {
@@ -5117,7 +5118,7 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
 	/* Prepare AS (Adaptive Sync) SDP Header */
 	sdp->sdp_header.HB0 = 0;
 	sdp->sdp_header.HB1 = as_sdp->sdp_type;
-	sdp->sdp_header.HB2 = 0x02;
+	sdp->sdp_header.HB2 = as_sdp->revision;
 	sdp->sdp_header.HB3 = as_sdp->length;
 
 	/* Fill AS (Adaptive Sync) SDP Payload */
@@ -5304,13 +5305,11 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
 		return -EINVAL;
 
-	if (sdp->sdp_header.HB2 != 0x02)
-		return -EINVAL;
-
 	if ((sdp->sdp_header.HB3 & 0x3F) != 9)
 		return -EINVAL;
 
 	as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK;
+	as_sdp->revision = sdp->sdp_header.HB2;
 	as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
 	as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
-- 
2.45.2

[PATCH 11/19] drm/i915/dp: Add member to intel_dp to store AS SDP v2 support

[Ankit Nautiyal]

DP v2.1 mentions support for FAVT payload fields parsing in DPCD 0x2214
Bit 2. This essentially signals the support for AS SDP version 2, that
allows source to set the version in HB2[4:0] and the payload length in
HB3[5:0] of the AS SDP header.

Read this bit and store the AS SDP v2 capability in intel_dp.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 21 +++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e189f8c39ccb..d783cea06aed 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1870,6 +1870,7 @@ struct intel_dp {
 	/* connector directly attached - won't be use for modeset in mst world */
 	struct intel_connector *attached_connector;
 	bool as_sdp_supported;
+	bool as_sdp_v2_supported;
 
 	struct drm_dp_tunnel *tunnel;
 	bool tunnel_suspended:1;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0d2403d48528..e6148e7f0ebc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6291,6 +6291,24 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
 					       false);
 }
 
+static bool
+intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	u8 rx_features;
+
+	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
+				  DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
+				  &rx_features) < 0) {
+		drm_dbg_kms(display->drm,
+			    "Failed to read DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1\n");
+
+		return false;
+	}
+
+	return rx_features & DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED;
+}
+
 static void
 intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
 {
@@ -6298,6 +6316,9 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
 
 	intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
 		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
+
+	intel_dp->as_sdp_v2_supported = intel_dp->as_sdp_supported &&
+					intel_dp_sink_supports_as_sdp_v2(intel_dp);
 }
 
 static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)
-- 
2.45.2

[PATCH 12/19] drm/i915/psr: Write the PR config DPCDs in burst mode

[Ankit Nautiyal]

Replace the consecutive single-byte writes to PANEL_REPLAY_CONFIG and
CONFIG2 with one drm_dp_dpcd_write() burst starting at PANEL_REPLAY_CONFIG,
reducing AUX transactions.

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5041a5a138d1..ee6e26abd05e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -774,27 +774,33 @@ static bool psr2_su_region_et_valid(struct intel_connector *connector, bool pane
 static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
 				      const struct intel_crtc_state *crtc_state)
 {
-	u8 val = DP_PANEL_REPLAY_ENABLE |
+	struct intel_display *display = to_intel_display(intel_dp);
+	u8 panel_replay_config = DP_PANEL_REPLAY_ENABLE |
 		DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
 		DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
 		DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
 		DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
 	u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;
+	u8 buf[2];
+	int ret;
 
 	if (crtc_state->has_sel_update)
-		val |= DP_PANEL_REPLAY_SU_ENABLE;
+		panel_replay_config |= DP_PANEL_REPLAY_SU_ENABLE;
 
 	if (crtc_state->enable_psr2_su_region_et)
-		val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
+		panel_replay_config |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
 
 	if (crtc_state->req_psr2_sdp_prior_scanline)
 		panel_replay_config2 |=
 			DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE;
 
-	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val);
+	buf[0] = panel_replay_config;
+	buf[1] = panel_replay_config2;
+
+	ret = drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG, buf, sizeof(buf));
 
-	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,
-			   panel_replay_config2);
+	if (ret < 0 || ret != sizeof(buf))
+		drm_dbg_kms(display->drm, "Failed to write Panel Replay Configs\n");
 }
 
 static void _psr_enable_sink(struct intel_dp *intel_dp,
-- 
2.45.2

[PATCH 13/19] drm/i915/display: Add helper for AS SDP transmission time selection

[Ankit Nautiyal]

AS SDP may be transmitted at T1 or T2 depending on Panel Replay and
Adaptive Sync SDP configuration as per DP 2.1. Current we are using
T1 only, but future PR/AS SDP modes/features may require T2 or dynamic
selection.

Introduce a helper to return the appropriate AS SDP transmission time so
that a single value is consistently used for programming PR_ALPM.
For now this returns T1.

v2: Avoid adding new member to crtc_state; use a helper. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 20 +++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.c   |  9 +++++++++
 drivers/gpu/drm/i915/display/intel_dp.h   |  2 ++
 3 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index a7350ce8e716..0a6da3f926d3 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -11,6 +11,7 @@
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
+#include "intel_display_utils.h"
 #include "intel_dp.h"
 #include "intel_dp_aux.h"
 #include "intel_psr.h"
@@ -359,6 +360,23 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
 	crtc_state->has_lobf = true;
 }
 
+static int get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *crtc_state)
+{
+	int as_sdp_setup_time = intel_dp_as_sdp_transmission_time();
+
+	switch (as_sdp_setup_time) {
+	case DP_PR_AS_SDP_SETUP_TIME_T1:
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
+	case DP_PR_AS_SDP_SETUP_TIME_DYNAMIC:
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2;
+	case DP_PR_AS_SDP_SETUP_TIME_T2:
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2;
+	default:
+		MISSING_CASE(as_sdp_setup_time);
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
+	}
+}
+
 static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state)
 {
@@ -382,7 +400,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
 
 		if (intel_dp->as_sdp_supported) {
-			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
+			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
 
 			if (crtc_state->link_off_after_as_sdp_when_pr_active)
 				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e6148e7f0ebc..74a8af3cf18c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7439,3 +7439,12 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 
 	return true;
 }
+
+int intel_dp_as_sdp_transmission_time(void)
+{
+	/*
+	 * For now we use T1 as the transmission time.
+	 * This can be later changed as per requirements.
+	 */
+	return DP_PR_AS_SDP_SETUP_TIME_T1;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 2849b9ecdc71..2e4609d9d05c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -238,4 +238,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
 		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
 
+int intel_dp_as_sdp_transmission_time(void);
+
 #endif /* __INTEL_DP_H__ */
-- 
2.45.2

[PATCH 14/19] drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission time

[Ankit Nautiyal]

Panel Replay requires the AS SDP transmission time to be written into
PANEL_REPLAY_CONFIG3. This field was previously not programmed.

Use the AS SDP transmission-time helper to populate CONFIG3.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index ee6e26abd05e..9add6e0d6f04 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -781,7 +781,8 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
 		DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
 		DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
 	u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;
-	u8 buf[2];
+	u8 panel_replay_config3 = DP_PR_AS_SDP_SETUP_TIME(intel_dp_as_sdp_transmission_time());
+	u8 buf[3];
 	int ret;
 
 	if (crtc_state->has_sel_update)
@@ -796,6 +797,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
 
 	buf[0] = panel_replay_config;
 	buf[1] = panel_replay_config2;
+	buf[2] = panel_replay_config3;
 
 	ret = drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG, buf, sizeof(buf));
 
-- 
2.45.2

[PATCH 15/19] drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless ALPM

[Ankit Nautiyal]

To support Panel Replay with Auxless-ALPM, the source must transmit
Adaptive-Sync SDPs for video timing synchronization while PR is active.
As per the DP spec v2.1, this requires setting DPCD 0x0107[6]
(FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE). This applies whether VRR is enabled
(AVT/FAVT) or fixed-timing mode is used.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 10 ++++++++--
 drivers/gpu/drm/i915/display/intel_dp_link_training.h |  3 ++-
 drivers/gpu/drm/i915/display/intel_dp_mst.c           |  2 +-
 3 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 54c585c59b90..136cabf06fd9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -27,6 +27,7 @@
 #include <drm/display/drm_dp_helper.h>
 #include <drm/drm_print.h>
 
+#include "intel_alpm.h"
 #include "intel_display_core.h"
 #include "intel_display_jiffies.h"
 #include "intel_display_types.h"
@@ -710,11 +711,14 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
 	return true;
 }
 
-void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)
+void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate,
+				     bool is_vrr,
+				     bool is_pr_with_link_off)
 {
 	u8 link_config[2];
 
 	link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
+	link_config[0] |= is_pr_with_link_off ? DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE : 0;
 	link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
 			 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
 	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
@@ -737,7 +741,9 @@ static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
 	  * especially on the first real commit when clearing the inherited flag.
 	  */
 	intel_dp_link_training_set_mode(intel_dp,
-					crtc_state->port_clock, crtc_state->vrr.in_range);
+					crtc_state->port_clock,
+					crtc_state->vrr.in_range,
+					intel_alpm_is_alpm_aux_less(intel_dp, crtc_state));
 }
 
 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 1ba22ed6db08..3591210f8ee6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -18,7 +18,8 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
 bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp);
 
 void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,
-				     int link_rate, bool is_vrr);
+				     int link_rate, bool is_vrr,
+				     bool is_pr_with_link_off);
 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
 				   int link_bw, int rate_select, int lane_count,
 				   bool enhanced_framing);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 887b6de14e46..2201cf7ce015 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -2142,7 +2142,7 @@ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
 
 	intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);
 
-	intel_dp_link_training_set_mode(intel_dp, link_rate, false);
+	intel_dp_link_training_set_mode(intel_dp, link_rate, false, false);
 	intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
 				      drm_dp_enhanced_frame_cap(intel_dp->dpcd));
 
-- 
2.45.2

[PATCH 16/19] drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off

[Ankit Nautiyal]

For Panel Replay with AUX-less ALPM (link-off PR), the source must send
Adaptive-Sync SDP v2. Program DB[1:0] per DP spec v2.1:
- VRR AVT: 00b (variable VTotal)
- VRR FAVT: 10b/11b (TRR not reached/reached)
- Fixed timing with PR link-off (VRR off): 01b (AS disabled; VTotal fixed)

Also, drop the redundant target_rr assignment.

v2: Fix the else case. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 74a8af3cf18c..2b0318e0ceb0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3161,9 +3161,10 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
 		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
 		as_sdp->target_rr_divider = true;
-	} else {
+	} else if (crtc_state->vrr.enable) {
 		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
-		as_sdp->target_rr = 0;
+	} else {
+		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
 	}
 }
 
-- 
2.45.2

[PATCH 17/19] drm/i915/dp: Split AS SDP computation between compute_config and compute_config_late

[Ankit Nautiyal]

Currently we enable AS SDP only when VRR is enabled. As we start using
AS SDP for other features, this becomes a problem. The AS SDP
configuration can change dynamically based on VRR, CMRR, PR, ALPM, etc.
Since these features may be enabled or disabled after the initial
configuration, the AS SDP parameters need to be computed later in the
pipeline.

However, not all of the AS SDP logic can be moved to the late stage:
the VRR guardband optimization depends on knowing early whether AS SDP
can be used. Without this, we would end up accounting for AS SDP on all
platforms that support it, even for panels that do not support AS SDP.
Therefore we set the infoframe enable bit for AS SDP during
compute_config(), before the guardband is computed.

To handle these constraints, split the AS SDP programming into two
phases:

 - intel_dp_compute_as_sdp()
   Runs during compute_config().
   Sets only the infoframe enable bit so that the guardband logic can
   account for AS SDP requirements.

 - intel_dp_as_sdp_compute_config_late()
   Runs during compute_config_late().
   Computes all remaining AS SDP fields based on the features that need
   it.

The late-stage computation is called from
intel_dp_sdp_compute_config_late(), before computing the minimum guardband
for SDPs.

This is a preparatory change. A subsequent patch will always enable AS
SDP when the source and sink support it.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 67 ++++++++++++++++---------
 1 file changed, 44 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2b0318e0ceb0..4d0a7695be5a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3142,30 +3142,17 @@ static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
-	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
-
 	if (!intel_dp_can_use_as_sdp(intel_dp, crtc_state))
 		return;
 
+	/*
+	 * Only set the infoframes.enable flag here.
+	 * The remaining AS SDP fields are programmed in the
+	 * compute_config_late() phase. We need this flag early so that the
+	 * VRR guardband calculation can properly account for AS SDP
+	 * requirements.
+	 */
 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
-
-	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
-	as_sdp->length = 0x9;
-	as_sdp->duration_incr_ms = 0;
-	as_sdp->revision = 0x2;
-	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
-
-	if (crtc_state->cmrr.enable) {
-		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
-		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
-		as_sdp->target_rr_divider = true;
-	} else if (crtc_state->vrr.enable) {
-		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
-	} else {
-		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
-	}
 }
 
 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
@@ -7344,11 +7331,45 @@ void intel_dp_mst_resume(struct intel_display *display)
 }
 
 static
-int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
+void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
+					 struct intel_crtc_state *crtc_state)
+{
+	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+
+	if ((crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)) == 0)
+		return;
+
+	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
+	as_sdp->length = 0x9;
+	as_sdp->duration_incr_ms = 0;
+	as_sdp->revision = 0x2;
+	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
+
+	if (crtc_state->cmrr.enable) {
+		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
+		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
+		as_sdp->target_rr_divider = true;
+	} else if (crtc_state->vrr.enable) {
+		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
+	} else {
+		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
+	}
+}
+
+static
+int intel_dp_sdp_compute_config_late(struct intel_dp *intel_dp,
+				     struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	int guardband = intel_crtc_vblank_length(crtc_state);
-	int min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false);
+	int min_sdp_guardband;
+
+	intel_dp_as_sdp_compute_config_late(intel_dp, crtc_state);
+
+	min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false);
 
 	if (guardband < min_sdp_guardband) {
 		drm_dbg_kms(display->drm, "guardband %d < min sdp guardband %d\n",
@@ -7368,7 +7389,7 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
 
 	intel_psr_compute_config_late(intel_dp, crtc_state);
 
-	ret = intel_dp_sdp_compute_config_late(crtc_state);
+	ret = intel_dp_sdp_compute_config_late(intel_dp, crtc_state);
 	if (ret)
 		return ret;
 
-- 
2.45.2

[PATCH 18/19] drm/i915/dp: Make provision for AS SDP version 1

[Ankit Nautiyal]

Currently we are setting AS SDP version to 2 without checking if the sink
supports it or whether we need to send version 1.

For PR with Link ON, the AS SDP version V1 is used.
When using AS SDP Version 1, AS SDP payload and parity bytes
are all set to zeroes.

Add a helper to compute the AS SDP version based on sink support and
feature requirement.

If AS SDP V2 is supported we use V2, unless Panel Replay with Link On is
enabled, for which we use V1.
If AS SDP V1 is not supported, we always send V1, without the payload.

Bspec: 75639
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4d0a7695be5a..6b45894e40e0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5109,6 +5109,10 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
 	sdp->sdp_header.HB2 = as_sdp->revision;
 	sdp->sdp_header.HB3 = as_sdp->length;
 
+	/* No Payload Data bytes for Version 1 */
+	if (as_sdp->revision == 0x1)
+		return length;
+
 	/* Fill AS (Adaptive Sync) SDP Payload */
 	sdp->db[0] = as_sdp->mode;
 	sdp->db[1] = as_sdp->vtotal & 0xFF;
@@ -7330,6 +7334,19 @@ void intel_dp_mst_resume(struct intel_display *display)
 	}
 }
 
+static bool intel_dp_get_as_sdp_revision(struct intel_dp *intel_dp,
+					 struct intel_crtc_state *crtc_state)
+{
+	if (crtc_state->has_panel_replay &&
+	    !intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
+		return 1;
+
+	if (intel_dp->as_sdp_v2_supported)
+		return 2;
+
+	return 1;
+}
+
 static
 void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
 					 struct intel_crtc_state *crtc_state)
@@ -7345,7 +7362,12 @@ void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
 	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
 	as_sdp->length = 0x9;
 	as_sdp->duration_incr_ms = 0;
-	as_sdp->revision = 0x2;
+	as_sdp->revision = intel_dp_get_as_sdp_revision(intel_dp, crtc_state);
+
+	/* No payload data bytes for Version 1 */
+	if (as_sdp->revision == 1)
+		return;
+
 	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
 
 	if (crtc_state->cmrr.enable) {
-- 
2.45.2

[PATCH 19/19] drm/i915/dp: Always enable AS SDP if supported by source + sink

[Ankit Nautiyal]

Currently AS SDP is only configured when VRR is enabled. However, other
use cases like CMRR, Panel Replay, etc. also send information to the sink
via AS SDPs.

With optimized guardband, we also need to account for wakeup time and other
relevant details that depend on the AS SDP position whenever AS SDP is
enabled. If a feature enabling AS SDP gets turned on later (after modeset),
the guardband might not be sufficient and may need to increase, triggering
a full modeset.

To avoid this, always send AS SDP whenever the source and sink both
support it.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6b45894e40e0..a9ee3d307b3b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3136,7 +3136,7 @@ static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
 	if (drm_dp_is_branch(intel_dp->dpcd))
 		return false;
 
-	return crtc_state->vrr.enable;
+	return true;
 }
 
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
-- 
2.45.2

✓ CI.KUnit: success for Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM (rev2)

[Patchwork]

== Series Details ==

Series: Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM (rev2)
URL   : https://patchwork.freedesktop.org/series/161978/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[12:03:10] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:03:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:03:54] Starting KUnit Kernel (1/1)...
[12:03:54] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:03:54] ================== guc_buf (11 subtests) ===================
[12:03:54] [PASSED] test_smallest
[12:03:54] [PASSED] test_largest
[12:03:54] [PASSED] test_granular
[12:03:54] [PASSED] test_unique
[12:03:54] [PASSED] test_overlap
[12:03:54] [PASSED] test_reusable
[12:03:54] [PASSED] test_too_big
[12:03:54] [PASSED] test_flush
[12:03:54] [PASSED] test_lookup
[12:03:54] [PASSED] test_data
[12:03:54] [PASSED] test_class
[12:03:54] ===================== [PASSED] guc_buf =====================
[12:03:54] =================== guc_dbm (7 subtests) ===================
[12:03:54] [PASSED] test_empty
[12:03:54] [PASSED] test_default
[12:03:54] ======================== test_size  ========================
[12:03:54] [PASSED] 4
[12:03:54] [PASSED] 8
[12:03:54] [PASSED] 32
[12:03:54] [PASSED] 256
[12:03:54] ==================== [PASSED] test_size ====================
[12:03:54] ======================= test_reuse  ========================
[12:03:54] [PASSED] 4
[12:03:54] [PASSED] 8
[12:03:54] [PASSED] 32
[12:03:54] [PASSED] 256
[12:03:54] =================== [PASSED] test_reuse ====================
[12:03:54] =================== test_range_overlap  ====================
[12:03:54] [PASSED] 4
[12:03:54] [PASSED] 8
[12:03:54] [PASSED] 32
[12:03:54] [PASSED] 256
[12:03:54] =============== [PASSED] test_range_overlap ================
[12:03:54] =================== test_range_compact  ====================
[12:03:54] [PASSED] 4
[12:03:54] [PASSED] 8
[12:03:54] [PASSED] 32
[12:03:54] [PASSED] 256
[12:03:54] =============== [PASSED] test_range_compact ================
[12:03:54] ==================== test_range_spare  =====================
[12:03:54] [PASSED] 4
[12:03:54] [PASSED] 8
[12:03:54] [PASSED] 32
[12:03:54] [PASSED] 256
[12:03:54] ================ [PASSED] test_range_spare =================
[12:03:54] ===================== [PASSED] guc_dbm =====================
[12:03:54] =================== guc_idm (6 subtests) ===================
[12:03:54] [PASSED] bad_init
[12:03:54] [PASSED] no_init
[12:03:54] [PASSED] init_fini
[12:03:54] [PASSED] check_used
[12:03:54] [PASSED] check_quota
[12:03:54] [PASSED] check_all
[12:03:54] ===================== [PASSED] guc_idm =====================
[12:03:54] ================== no_relay (3 subtests) ===================
[12:03:54] [PASSED] xe_drops_guc2pf_if_not_ready
[12:03:54] [PASSED] xe_drops_guc2vf_if_not_ready
[12:03:54] [PASSED] xe_rejects_send_if_not_ready
[12:03:54] ==================== [PASSED] no_relay =====================
[12:03:54] ================== pf_relay (14 subtests) ==================
[12:03:54] [PASSED] pf_rejects_guc2pf_too_short
[12:03:54] [PASSED] pf_rejects_guc2pf_too_long
[12:03:54] [PASSED] pf_rejects_guc2pf_no_payload
[12:03:54] [PASSED] pf_fails_no_payload
[12:03:54] [PASSED] pf_fails_bad_origin
[12:03:54] [PASSED] pf_fails_bad_type
[12:03:54] [PASSED] pf_txn_reports_error
[12:03:54] [PASSED] pf_txn_sends_pf2guc
[12:03:54] [PASSED] pf_sends_pf2guc
[12:03:54] [SKIPPED] pf_loopback_nop
[12:03:54] [SKIPPED] pf_loopback_echo
[12:03:54] [SKIPPED] pf_loopback_fail
[12:03:54] [SKIPPED] pf_loopback_busy
[12:03:54] [SKIPPED] pf_loopback_retry
[12:03:54] ==================== [PASSED] pf_relay =====================
[12:03:54] ================== vf_relay (3 subtests) ===================
[12:03:54] [PASSED] vf_rejects_guc2vf_too_short
[12:03:54] [PASSED] vf_rejects_guc2vf_too_long
[12:03:54] [PASSED] vf_rejects_guc2vf_no_payload
[12:03:54] ==================== [PASSED] vf_relay =====================
[12:03:54] ================ pf_gt_config (9 subtests) =================
[12:03:54] [PASSED] fair_contexts_1vf
[12:03:54] [PASSED] fair_doorbells_1vf
[12:03:54] [PASSED] fair_ggtt_1vf
[12:03:54] ====================== fair_vram_1vf  ======================
[12:03:54] [PASSED] 3.50 GiB
[12:03:54] [PASSED] 11.5 GiB
[12:03:54] [PASSED] 15.5 GiB
[12:03:54] [PASSED] 31.5 GiB
[12:03:54] [PASSED] 63.5 GiB
[12:03:54] [PASSED] 1.91 GiB
[12:03:54] ================== [PASSED] fair_vram_1vf ==================
[12:03:54] ================ fair_vram_1vf_admin_only  =================
[12:03:54] [PASSED] 3.50 GiB
[12:03:54] [PASSED] 11.5 GiB
[12:03:54] [PASSED] 15.5 GiB
[12:03:54] [PASSED] 31.5 GiB
[12:03:54] [PASSED] 63.5 GiB
[12:03:54] [PASSED] 1.91 GiB
[12:03:54] ============ [PASSED] fair_vram_1vf_admin_only =============
[12:03:54] ====================== fair_contexts  ======================
[12:03:54] [PASSED] 1 VF
[12:03:54] [PASSED] 2 VFs
[12:03:54] [PASSED] 3 VFs
[12:03:54] [PASSED] 4 VFs
[12:03:54] [PASSED] 5 VFs
[12:03:54] [PASSED] 6 VFs
[12:03:54] [PASSED] 7 VFs
[12:03:54] [PASSED] 8 VFs
[12:03:54] [PASSED] 9 VFs
[12:03:54] [PASSED] 10 VFs
[12:03:54] [PASSED] 11 VFs
[12:03:54] [PASSED] 12 VFs
[12:03:54] [PASSED] 13 VFs
[12:03:54] [PASSED] 14 VFs
[12:03:54] [PASSED] 15 VFs
[12:03:54] [PASSED] 16 VFs
[12:03:54] [PASSED] 17 VFs
[12:03:54] [PASSED] 18 VFs
[12:03:54] [PASSED] 19 VFs
[12:03:54] [PASSED] 20 VFs
[12:03:54] [PASSED] 21 VFs
[12:03:54] [PASSED] 22 VFs
[12:03:54] [PASSED] 23 VFs
[12:03:54] [PASSED] 24 VFs
[12:03:54] [PASSED] 25 VFs
[12:03:54] [PASSED] 26 VFs
[12:03:54] [PASSED] 27 VFs
[12:03:54] [PASSED] 28 VFs
[12:03:54] [PASSED] 29 VFs
[12:03:54] [PASSED] 30 VFs
[12:03:54] [PASSED] 31 VFs
[12:03:54] [PASSED] 32 VFs
[12:03:54] [PASSED] 33 VFs
[12:03:54] [PASSED] 34 VFs
[12:03:54] [PASSED] 35 VFs
[12:03:54] [PASSED] 36 VFs
[12:03:54] [PASSED] 37 VFs
[12:03:54] [PASSED] 38 VFs
[12:03:54] [PASSED] 39 VFs
[12:03:54] [PASSED] 40 VFs
[12:03:54] [PASSED] 41 VFs
[12:03:54] [PASSED] 42 VFs
[12:03:54] [PASSED] 43 VFs
[12:03:54] [PASSED] 44 VFs
[12:03:54] [PASSED] 45 VFs
[12:03:54] [PASSED] 46 VFs
[12:03:54] [PASSED] 47 VFs
[12:03:54] [PASSED] 48 VFs
[12:03:54] [PASSED] 49 VFs
[12:03:54] [PASSED] 50 VFs
[12:03:54] [PASSED] 51 VFs
[12:03:54] [PASSED] 52 VFs
[12:03:54] [PASSED] 53 VFs
[12:03:54] [PASSED] 54 VFs
[12:03:54] [PASSED] 55 VFs
[12:03:54] [PASSED] 56 VFs
[12:03:54] [PASSED] 57 VFs
[12:03:54] [PASSED] 58 VFs
[12:03:54] [PASSED] 59 VFs
[12:03:54] [PASSED] 60 VFs
[12:03:54] [PASSED] 61 VFs
[12:03:54] [PASSED] 62 VFs
[12:03:54] [PASSED] 63 VFs
[12:03:54] ================== [PASSED] fair_contexts ==================
[12:03:54] ===================== fair_doorbells  ======================
[12:03:54] [PASSED] 1 VF
[12:03:54] [PASSED] 2 VFs
[12:03:54] [PASSED] 3 VFs
[12:03:54] [PASSED] 4 VFs
[12:03:54] [PASSED] 5 VFs
[12:03:54] [PASSED] 6 VFs
[12:03:54] [PASSED] 7 VFs
[12:03:54] [PASSED] 8 VFs
[12:03:54] [PASSED] 9 VFs
[12:03:54] [PASSED] 10 VFs
[12:03:54] [PASSED] 11 VFs
[12:03:54] [PASSED] 12 VFs
[12:03:54] [PASSED] 13 VFs
[12:03:54] [PASSED] 14 VFs
[12:03:54] [PASSED] 15 VFs
[12:03:54] [PASSED] 16 VFs
[12:03:54] [PASSED] 17 VFs
[12:03:54] [PASSED] 18 VFs
[12:03:54] [PASSED] 19 VFs
[12:03:54] [PASSED] 20 VFs
[12:03:54] [PASSED] 21 VFs
[12:03:54] [PASSED] 22 VFs
[12:03:54] [PASSED] 23 VFs
[12:03:54] [PASSED] 24 VFs
[12:03:54] [PASSED] 25 VFs
[12:03:54] [PASSED] 26 VFs
[12:03:54] [PASSED] 27 VFs
[12:03:54] [PASSED] 28 VFs
[12:03:54] [PASSED] 29 VFs
[12:03:54] [PASSED] 30 VFs
[12:03:54] [PASSED] 31 VFs
[12:03:54] [PASSED] 32 VFs
[12:03:54] [PASSED] 33 VFs
[12:03:54] [PASSED] 34 VFs
[12:03:54] [PASSED] 35 VFs
[12:03:54] [PASSED] 36 VFs
[12:03:54] [PASSED] 37 VFs
[12:03:54] [PASSED] 38 VFs
[12:03:54] [PASSED] 39 VFs
[12:03:54] [PASSED] 40 VFs
[12:03:54] [PASSED] 41 VFs
[12:03:54] [PASSED] 42 VFs
[12:03:54] [PASSED] 43 VFs
[12:03:54] [PASSED] 44 VFs
[12:03:54] [PASSED] 45 VFs
[12:03:54] [PASSED] 46 VFs
[12:03:54] [PASSED] 47 VFs
[12:03:54] [PASSED] 48 VFs
[12:03:54] [PASSED] 49 VFs
[12:03:54] [PASSED] 50 VFs
[12:03:54] [PASSED] 51 VFs
[12:03:54] [PASSED] 52 VFs
[12:03:54] [PASSED] 53 VFs
[12:03:54] [PASSED] 54 VFs
[12:03:54] [PASSED] 55 VFs
[12:03:54] [PASSED] 56 VFs
[12:03:54] [PASSED] 57 VFs
[12:03:54] [PASSED] 58 VFs
[12:03:54] [PASSED] 59 VFs
[12:03:54] [PASSED] 60 VFs
[12:03:54] [PASSED] 61 VFs
[12:03:54] [PASSED] 62 VFs
[12:03:54] [PASSED] 63 VFs
[12:03:54] ================= [PASSED] fair_doorbells ==================
[12:03:54] ======================== fair_ggtt  ========================
[12:03:54] [PASSED] 1 VF
[12:03:54] [PASSED] 2 VFs
[12:03:54] [PASSED] 3 VFs
[12:03:54] [PASSED] 4 VFs
[12:03:54] [PASSED] 5 VFs
[12:03:54] [PASSED] 6 VFs
[12:03:54] [PASSED] 7 VFs
[12:03:54] [PASSED] 8 VFs
[12:03:54] [PASSED] 9 VFs
[12:03:54] [PASSED] 10 VFs
[12:03:54] [PASSED] 11 VFs
[12:03:54] [PASSED] 12 VFs
[12:03:54] [PASSED] 13 VFs
[12:03:54] [PASSED] 14 VFs
[12:03:54] [PASSED] 15 VFs
[12:03:54] [PASSED] 16 VFs
[12:03:54] [PASSED] 17 VFs
[12:03:54] [PASSED] 18 VFs
[12:03:54] [PASSED] 19 VFs
[12:03:54] [PASSED] 20 VFs
[12:03:54] [PASSED] 21 VFs
[12:03:54] [PASSED] 22 VFs
[12:03:54] [PASSED] 23 VFs
[12:03:54] [PASSED] 24 VFs
[12:03:54] [PASSED] 25 VFs
[12:03:54] [PASSED] 26 VFs
[12:03:54] [PASSED] 27 VFs
[12:03:54] [PASSED] 28 VFs
[12:03:54] [PASSED] 29 VFs
[12:03:54] [PASSED] 30 VFs
[12:03:54] [PASSED] 31 VFs
[12:03:54] [PASSED] 32 VFs
[12:03:54] [PASSED] 33 VFs
[12:03:54] [PASSED] 34 VFs
[12:03:54] [PASSED] 35 VFs
[12:03:54] [PASSED] 36 VFs
[12:03:54] [PASSED] 37 VFs
[12:03:54] [PASSED] 38 VFs
[12:03:54] [PASSED] 39 VFs
[12:03:54] [PASSED] 40 VFs
[12:03:54] [PASSED] 41 VFs
[12:03:54] [PASSED] 42 VFs
[12:03:54] [PASSED] 43 VFs
[12:03:54] [PASSED] 44 VFs
[12:03:54] [PASSED] 45 VFs
[12:03:54] [PASSED] 46 VFs
[12:03:54] [PASSED] 47 VFs
[12:03:54] [PASSED] 48 VFs
[12:03:54] [PASSED] 49 VFs
[12:03:54] [PASSED] 50 VFs
[12:03:54] [PASSED] 51 VFs
[12:03:54] [PASSED] 52 VFs
[12:03:54] [PASSED] 53 VFs
[12:03:54] [PASSED] 54 VFs
[12:03:54] [PASSED] 55 VFs
[12:03:54] [PASSED] 56 VFs
[12:03:54] [PASSED] 57 VFs
[12:03:54] [PASSED] 58 VFs
[12:03:54] [PASSED] 59 VFs
[12:03:54] [PASSED] 60 VFs
[12:03:54] [PASSED] 61 VFs
[12:03:54] [PASSED] 62 VFs
[12:03:54] [PASSED] 63 VFs
[12:03:54] ==================== [PASSED] fair_ggtt ====================
[12:03:54] ======================== fair_vram  ========================
[12:03:54] [PASSED] 1 VF
[12:03:54] [PASSED] 2 VFs
[12:03:54] [PASSED] 3 VFs
[12:03:54] [PASSED] 4 VFs
[12:03:54] [PASSED] 5 VFs
[12:03:54] [PASSED] 6 VFs
[12:03:54] [PASSED] 7 VFs
[12:03:54] [PASSED] 8 VFs
[12:03:54] [PASSED] 9 VFs
[12:03:54] [PASSED] 10 VFs
[12:03:54] [PASSED] 11 VFs
[12:03:54] [PASSED] 12 VFs
[12:03:54] [PASSED] 13 VFs
[12:03:54] [PASSED] 14 VFs
[12:03:54] [PASSED] 15 VFs
[12:03:54] [PASSED] 16 VFs
[12:03:54] [PASSED] 17 VFs
[12:03:54] [PASSED] 18 VFs
[12:03:54] [PASSED] 19 VFs
[12:03:55] [PASSED] 20 VFs
[12:03:55] [PASSED] 21 VFs
[12:03:55] [PASSED] 22 VFs
[12:03:55] [PASSED] 23 VFs
[12:03:55] [PASSED] 24 VFs
[12:03:55] [PASSED] 25 VFs
[12:03:55] [PASSED] 26 VFs
[12:03:55] [PASSED] 27 VFs
[12:03:55] [PASSED] 28 VFs
[12:03:55] [PASSED] 29 VFs
[12:03:55] [PASSED] 30 VFs
[12:03:55] [PASSED] 31 VFs
[12:03:55] [PASSED] 32 VFs
[12:03:55] [PASSED] 33 VFs
[12:03:55] [PASSED] 34 VFs
[12:03:55] [PASSED] 35 VFs
[12:03:55] [PASSED] 36 VFs
[12:03:55] [PASSED] 37 VFs
[12:03:55] [PASSED] 38 VFs
[12:03:55] [PASSED] 39 VFs
[12:03:55] [PASSED] 40 VFs
[12:03:55] [PASSED] 41 VFs
[12:03:55] [PASSED] 42 VFs
[12:03:55] [PASSED] 43 VFs
[12:03:55] [PASSED] 44 VFs
[12:03:55] [PASSED] 45 VFs
[12:03:55] [PASSED] 46 VFs
[12:03:55] [PASSED] 47 VFs
[12:03:55] [PASSED] 48 VFs
[12:03:55] [PASSED] 49 VFs
[12:03:55] [PASSED] 50 VFs
[12:03:55] [PASSED] 51 VFs
[12:03:55] [PASSED] 52 VFs
[12:03:55] [PASSED] 53 VFs
[12:03:55] [PASSED] 54 VFs
[12:03:55] [PASSED] 55 VFs
[12:03:55] [PASSED] 56 VFs
[12:03:55] [PASSED] 57 VFs
[12:03:55] [PASSED] 58 VFs
[12:03:55] [PASSED] 59 VFs
[12:03:55] [PASSED] 60 VFs
[12:03:55] [PASSED] 61 VFs
[12:03:55] [PASSED] 62 VFs
[12:03:55] [PASSED] 63 VFs
[12:03:55] ==================== [PASSED] fair_vram ====================
[12:03:55] ================== [PASSED] pf_gt_config ===================
[12:03:55] ===================== lmtt (1 subtest) =====================
[12:03:55] ======================== test_ops  =========================
[12:03:55] [PASSED] 2-level
[12:03:55] [PASSED] multi-level
[12:03:55] ==================== [PASSED] test_ops =====================
[12:03:55] ====================== [PASSED] lmtt =======================
[12:03:55] ================= pf_service (11 subtests) =================
[12:03:55] [PASSED] pf_negotiate_any
[12:03:55] [PASSED] pf_negotiate_base_match
[12:03:55] [PASSED] pf_negotiate_base_newer
[12:03:55] [PASSED] pf_negotiate_base_next
[12:03:55] [SKIPPED] pf_negotiate_base_older
[12:03:55] [PASSED] pf_negotiate_base_prev
[12:03:55] [PASSED] pf_negotiate_latest_match
[12:03:55] [PASSED] pf_negotiate_latest_newer
[12:03:55] [PASSED] pf_negotiate_latest_next
[12:03:55] [SKIPPED] pf_negotiate_latest_older
[12:03:55] [SKIPPED] pf_negotiate_latest_prev
[12:03:55] =================== [PASSED] pf_service ====================
[12:03:55] ================= xe_guc_g2g (2 subtests) ==================
[12:03:55] ============== xe_live_guc_g2g_kunit_default  ==============
[12:03:55] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[12:03:55] ============== xe_live_guc_g2g_kunit_allmem  ===============
[12:03:55] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[12:03:55] =================== [SKIPPED] xe_guc_g2g ===================
[12:03:55] =================== xe_mocs (2 subtests) ===================
[12:03:55] ================ xe_live_mocs_kernel_kunit  ================
[12:03:55] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[12:03:55] ================ xe_live_mocs_reset_kunit  =================
[12:03:55] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[12:03:55] ==================== [SKIPPED] xe_mocs =====================
[12:03:55] ================= xe_migrate (2 subtests) ==================
[12:03:55] ================= xe_migrate_sanity_kunit  =================
[12:03:55] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[12:03:55] ================== xe_validate_ccs_kunit  ==================
[12:03:55] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[12:03:55] =================== [SKIPPED] xe_migrate ===================
[12:03:55] ================== xe_dma_buf (1 subtest) ==================
[12:03:55] ==================== xe_dma_buf_kunit  =====================
[12:03:55] ================ [SKIPPED] xe_dma_buf_kunit ================
[12:03:55] =================== [SKIPPED] xe_dma_buf ===================
[12:03:55] ================= xe_bo_shrink (1 subtest) =================
[12:03:55] =================== xe_bo_shrink_kunit  ====================
[12:03:55] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[12:03:55] ================== [SKIPPED] xe_bo_shrink ==================
[12:03:55] ==================== xe_bo (2 subtests) ====================
[12:03:55] ================== xe_ccs_migrate_kunit  ===================
[12:03:55] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[12:03:55] ==================== xe_bo_evict_kunit  ====================
[12:03:55] =============== [SKIPPED] xe_bo_evict_kunit ================
[12:03:55] ===================== [SKIPPED] xe_bo ======================
[12:03:55] ==================== args (13 subtests) ====================
[12:03:55] [PASSED] count_args_test
[12:03:55] [PASSED] call_args_example
[12:03:55] [PASSED] call_args_test
[12:03:55] [PASSED] drop_first_arg_example
[12:03:55] [PASSED] drop_first_arg_test
[12:03:55] [PASSED] first_arg_example
[12:03:55] [PASSED] first_arg_test
[12:03:55] [PASSED] last_arg_example
[12:03:55] [PASSED] last_arg_test
[12:03:55] [PASSED] pick_arg_example
[12:03:55] [PASSED] if_args_example
[12:03:55] [PASSED] if_args_test
[12:03:55] [PASSED] sep_comma_example
[12:03:55] ====================== [PASSED] args =======================
[12:03:55] =================== xe_pci (3 subtests) ====================
[12:03:55] ==================== check_graphics_ip  ====================
[12:03:55] [PASSED] 12.00 Xe_LP
[12:03:55] [PASSED] 12.10 Xe_LP+
[12:03:55] [PASSED] 12.55 Xe_HPG
[12:03:55] [PASSED] 12.60 Xe_HPC
[12:03:55] [PASSED] 12.70 Xe_LPG
[12:03:55] [PASSED] 12.71 Xe_LPG
[12:03:55] [PASSED] 12.74 Xe_LPG+
[12:03:55] [PASSED] 20.01 Xe2_HPG
[12:03:55] [PASSED] 20.02 Xe2_HPG
[12:03:55] [PASSED] 20.04 Xe2_LPG
[12:03:55] [PASSED] 30.00 Xe3_LPG
[12:03:55] [PASSED] 30.01 Xe3_LPG
[12:03:55] [PASSED] 30.03 Xe3_LPG
[12:03:55] [PASSED] 30.04 Xe3_LPG
[12:03:55] [PASSED] 30.05 Xe3_LPG
[12:03:55] [PASSED] 35.10 Xe3p_LPG
[12:03:55] [PASSED] 35.11 Xe3p_XPC
[12:03:55] ================ [PASSED] check_graphics_ip ================
[12:03:55] ===================== check_media_ip  ======================
[12:03:55] [PASSED] 12.00 Xe_M
[12:03:55] [PASSED] 12.55 Xe_HPM
[12:03:55] [PASSED] 13.00 Xe_LPM+
[12:03:55] [PASSED] 13.01 Xe2_HPM
[12:03:55] [PASSED] 20.00 Xe2_LPM
[12:03:55] [PASSED] 30.00 Xe3_LPM
[12:03:55] [PASSED] 30.02 Xe3_LPM
[12:03:55] [PASSED] 35.00 Xe3p_LPM
[12:03:55] [PASSED] 35.03 Xe3p_HPM
[12:03:55] ================= [PASSED] check_media_ip ==================
[12:03:55] =================== check_platform_desc  ===================
[12:03:55] [PASSED] 0x9A60 (TIGERLAKE)
[12:03:55] [PASSED] 0x9A68 (TIGERLAKE)
[12:03:55] [PASSED] 0x9A70 (TIGERLAKE)
[12:03:55] [PASSED] 0x9A40 (TIGERLAKE)
[12:03:55] [PASSED] 0x9A49 (TIGERLAKE)
[12:03:55] [PASSED] 0x9A59 (TIGERLAKE)
[12:03:55] [PASSED] 0x9A78 (TIGERLAKE)
[12:03:55] [PASSED] 0x9AC0 (TIGERLAKE)
[12:03:55] [PASSED] 0x9AC9 (TIGERLAKE)
[12:03:55] [PASSED] 0x9AD9 (TIGERLAKE)
[12:03:55] [PASSED] 0x9AF8 (TIGERLAKE)
[12:03:55] [PASSED] 0x4C80 (ROCKETLAKE)
[12:03:55] [PASSED] 0x4C8A (ROCKETLAKE)
[12:03:55] [PASSED] 0x4C8B (ROCKETLAKE)
[12:03:55] [PASSED] 0x4C8C (ROCKETLAKE)
[12:03:55] [PASSED] 0x4C90 (ROCKETLAKE)
[12:03:55] [PASSED] 0x4C9A (ROCKETLAKE)
[12:03:55] [PASSED] 0x4680 (ALDERLAKE_S)
[12:03:55] [PASSED] 0x4682 (ALDERLAKE_S)
[12:03:55] [PASSED] 0x4688 (ALDERLAKE_S)
[12:03:55] [PASSED] 0x468A (ALDERLAKE_S)
[12:03:55] [PASSED] 0x468B (ALDERLAKE_S)
[12:03:55] [PASSED] 0x4690 (ALDERLAKE_S)
[12:03:55] [PASSED] 0x4692 (ALDERLAKE_S)
[12:03:55] [PASSED] 0x4693 (ALDERLAKE_S)
[12:03:55] [PASSED] 0x46A0 (ALDERLAKE_P)
[12:03:55] [PASSED] 0x46A1 (ALDERLAKE_P)
[12:03:55] [PASSED] 0x46A2 (ALDERLAKE_P)
[12:03:55] [PASSED] 0x46A3 (ALDERLAKE_P)
[12:03:55] [PASSED] 0x46A6 (ALDERLAKE_P)
[12:03:55] [PASSED] 0x46A8 (ALDERLAKE_P)
[12:03:55] [PASSED] 0x46AA (ALDERLAKE_P)
[12:03:55] [PASSED] 0x462A (ALDERLAKE_P)
[12:03:55] [PASSED] 0x4626 (ALDERLAKE_P)
[12:03:55] [PASSED] 0x4628 (ALDERLAKE_P)
[12:03:55] [PASSED] 0x46B0 (ALDERLAKE_P)
[12:03:55] [PASSED] 0x46B1 (ALDERLAKE_P)
[12:03:55] [PASSED] 0x46B2 (ALDERLAKE_P)
[12:03:55] [PASSED] 0x46B3 (ALDERLAKE_P)
[12:03:55] [PASSED] 0x46C0 (ALDERLAKE_P)
[12:03:55] [PASSED] 0x46C1 (ALDERLAKE_P)
[12:03:55] [PASSED] 0x46C2 (ALDERLAKE_P)
[12:03:55] [PASSED] 0x46C3 (ALDERLAKE_P)
[12:03:55] [PASSED] 0x46D0 (ALDERLAKE_N)
[12:03:55] [PASSED] 0x46D1 (ALDERLAKE_N)
[12:03:55] [PASSED] 0x46D2 (ALDERLAKE_N)
[12:03:55] [PASSED] 0x46D3 (ALDERLAKE_N)
[12:03:55] [PASSED] 0x46D4 (ALDERLAKE_N)
[12:03:55] [PASSED] 0xA721 (ALDERLAKE_P)
[12:03:55] [PASSED] 0xA7A1 (ALDERLAKE_P)
[12:03:55] [PASSED] 0xA7A9 (ALDERLAKE_P)
[12:03:55] [PASSED] 0xA7AC (ALDERLAKE_P)
[12:03:55] [PASSED] 0xA7AD (ALDERLAKE_P)
[12:03:55] [PASSED] 0xA720 (ALDERLAKE_P)
[12:03:55] [PASSED] 0xA7A0 (ALDERLAKE_P)
[12:03:55] [PASSED] 0xA7A8 (ALDERLAKE_P)
[12:03:55] [PASSED] 0xA7AA (ALDERLAKE_P)
[12:03:55] [PASSED] 0xA7AB (ALDERLAKE_P)
[12:03:55] [PASSED] 0xA780 (ALDERLAKE_S)
[12:03:55] [PASSED] 0xA781 (ALDERLAKE_S)
[12:03:55] [PASSED] 0xA782 (ALDERLAKE_S)
[12:03:55] [PASSED] 0xA783 (ALDERLAKE_S)
[12:03:55] [PASSED] 0xA788 (ALDERLAKE_S)
[12:03:55] [PASSED] 0xA789 (ALDERLAKE_S)
[12:03:55] [PASSED] 0xA78A (ALDERLAKE_S)
[12:03:55] [PASSED] 0xA78B (ALDERLAKE_S)
[12:03:55] [PASSED] 0x4905 (DG1)
[12:03:55] [PASSED] 0x4906 (DG1)
[12:03:55] [PASSED] 0x4907 (DG1)
[12:03:55] [PASSED] 0x4908 (DG1)
[12:03:55] [PASSED] 0x4909 (DG1)
[12:03:55] [PASSED] 0x56C0 (DG2)
[12:03:55] [PASSED] 0x56C2 (DG2)
[12:03:55] [PASSED] 0x56C1 (DG2)
[12:03:55] [PASSED] 0x7D51 (METEORLAKE)
[12:03:55] [PASSED] 0x7DD1 (METEORLAKE)
[12:03:55] [PASSED] 0x7D41 (METEORLAKE)
[12:03:55] [PASSED] 0x7D67 (METEORLAKE)
[12:03:55] [PASSED] 0xB640 (METEORLAKE)
[12:03:55] [PASSED] 0x56A0 (DG2)
[12:03:55] [PASSED] 0x56A1 (DG2)
[12:03:55] [PASSED] 0x56A2 (DG2)
[12:03:55] [PASSED] 0x56BE (DG2)
[12:03:55] [PASSED] 0x56BF (DG2)
[12:03:55] [PASSED] 0x5690 (DG2)
[12:03:55] [PASSED] 0x5691 (DG2)
[12:03:55] [PASSED] 0x5692 (DG2)
[12:03:55] [PASSED] 0x56A5 (DG2)
[12:03:55] [PASSED] 0x56A6 (DG2)
[12:03:55] [PASSED] 0x56B0 (DG2)
[12:03:55] [PASSED] 0x56B1 (DG2)
[12:03:55] [PASSED] 0x56BA (DG2)
[12:03:55] [PASSED] 0x56BB (DG2)
[12:03:55] [PASSED] 0x56BC (DG2)
[12:03:55] [PASSED] 0x56BD (DG2)
[12:03:55] [PASSED] 0x5693 (DG2)
[12:03:55] [PASSED] 0x5694 (DG2)
[12:03:55] [PASSED] 0x5695 (DG2)
[12:03:55] [PASSED] 0x56A3 (DG2)
[12:03:55] [PASSED] 0x56A4 (DG2)
[12:03:55] [PASSED] 0x56B2 (DG2)
[12:03:55] [PASSED] 0x56B3 (DG2)
[12:03:55] [PASSED] 0x5696 (DG2)
[12:03:55] [PASSED] 0x5697 (DG2)
[12:03:55] [PASSED] 0xB69 (PVC)
[12:03:55] [PASSED] 0xB6E (PVC)
[12:03:55] [PASSED] 0xBD4 (PVC)
[12:03:55] [PASSED] 0xBD5 (PVC)
[12:03:55] [PASSED] 0xBD6 (PVC)
[12:03:55] [PASSED] 0xBD7 (PVC)
[12:03:55] [PASSED] 0xBD8 (PVC)
[12:03:55] [PASSED] 0xBD9 (PVC)
[12:03:55] [PASSED] 0xBDA (PVC)
[12:03:55] [PASSED] 0xBDB (PVC)
[12:03:55] [PASSED] 0xBE0 (PVC)
[12:03:55] [PASSED] 0xBE1 (PVC)
[12:03:55] [PASSED] 0xBE5 (PVC)
[12:03:55] [PASSED] 0x7D40 (METEORLAKE)
[12:03:55] [PASSED] 0x7D45 (METEORLAKE)
[12:03:55] [PASSED] 0x7D55 (METEORLAKE)
[12:03:55] [PASSED] 0x7D60 (METEORLAKE)
[12:03:55] [PASSED] 0x7DD5 (METEORLAKE)
[12:03:55] [PASSED] 0x6420 (LUNARLAKE)
[12:03:55] [PASSED] 0x64A0 (LUNARLAKE)
[12:03:55] [PASSED] 0x64B0 (LUNARLAKE)
[12:03:55] [PASSED] 0xE202 (BATTLEMAGE)
[12:03:55] [PASSED] 0xE209 (BATTLEMAGE)
[12:03:55] [PASSED] 0xE20B (BATTLEMAGE)
[12:03:55] [PASSED] 0xE20C (BATTLEMAGE)
[12:03:55] [PASSED] 0xE20D (BATTLEMAGE)
[12:03:55] [PASSED] 0xE210 (BATTLEMAGE)
[12:03:55] [PASSED] 0xE211 (BATTLEMAGE)
[12:03:55] [PASSED] 0xE212 (BATTLEMAGE)
[12:03:55] [PASSED] 0xE216 (BATTLEMAGE)
[12:03:55] [PASSED] 0xE220 (BATTLEMAGE)
[12:03:55] [PASSED] 0xE221 (BATTLEMAGE)
[12:03:55] [PASSED] 0xE222 (BATTLEMAGE)
[12:03:55] [PASSED] 0xE223 (BATTLEMAGE)
[12:03:55] [PASSED] 0xB080 (PANTHERLAKE)
[12:03:55] [PASSED] 0xB081 (PANTHERLAKE)
[12:03:55] [PASSED] 0xB082 (PANTHERLAKE)
[12:03:55] [PASSED] 0xB083 (PANTHERLAKE)
[12:03:55] [PASSED] 0xB084 (PANTHERLAKE)
[12:03:55] [PASSED] 0xB085 (PANTHERLAKE)
[12:03:55] [PASSED] 0xB086 (PANTHERLAKE)
[12:03:55] [PASSED] 0xB087 (PANTHERLAKE)
[12:03:55] [PASSED] 0xB08F (PANTHERLAKE)
[12:03:55] [PASSED] 0xB090 (PANTHERLAKE)
[12:03:55] [PASSED] 0xB0A0 (PANTHERLAKE)
[12:03:55] [PASSED] 0xB0B0 (PANTHERLAKE)
[12:03:55] [PASSED] 0xFD80 (PANTHERLAKE)
[12:03:55] [PASSED] 0xFD81 (PANTHERLAKE)
[12:03:55] [PASSED] 0xD740 (NOVALAKE_S)
[12:03:55] [PASSED] 0xD741 (NOVALAKE_S)
[12:03:55] [PASSED] 0xD742 (NOVALAKE_S)
[12:03:55] [PASSED] 0xD743 (NOVALAKE_S)
[12:03:55] [PASSED] 0xD744 (NOVALAKE_S)
[12:03:55] [PASSED] 0xD745 (NOVALAKE_S)
[12:03:55] [PASSED] 0x674C (CRESCENTISLAND)
[12:03:55] [PASSED] 0xD750 (NOVALAKE_P)
[12:03:55] [PASSED] 0xD751 (NOVALAKE_P)
[12:03:55] [PASSED] 0xD752 (NOVALAKE_P)
[12:03:55] [PASSED] 0xD753 (NOVALAKE_P)
[12:03:55] [PASSED] 0xD754 (NOVALAKE_P)
[12:03:55] [PASSED] 0xD755 (NOVALAKE_P)
[12:03:55] [PASSED] 0xD756 (NOVALAKE_P)
[12:03:55] [PASSED] 0xD757 (NOVALAKE_P)
[12:03:55] [PASSED] 0xD75F (NOVALAKE_P)
[12:03:55] =============== [PASSED] check_platform_desc ===============
[12:03:55] ===================== [PASSED] xe_pci ======================
[12:03:55] =================== xe_rtp (2 subtests) ====================
[12:03:55] =============== xe_rtp_process_to_sr_tests  ================
[12:03:55] [PASSED] coalesce-same-reg
[12:03:55] [PASSED] no-match-no-add
[12:03:55] [PASSED] match-or
[12:03:55] [PASSED] match-or-xfail
[12:03:55] [PASSED] no-match-no-add-multiple-rules
[12:03:55] [PASSED] two-regs-two-entries
[12:03:55] [PASSED] clr-one-set-other
[12:03:55] [PASSED] set-field
[12:03:55] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[12:03:55] [PASSED] conflict-not-disjoint
[12:03:55] [PASSED] conflict-reg-type
[12:03:55] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[12:03:55] ================== xe_rtp_process_tests  ===================
[12:03:55] [PASSED] active1
[12:03:55] [PASSED] active2
[12:03:55] [PASSED] active-inactive
[12:03:55] [PASSED] inactive-active
[12:03:55] [PASSED] inactive-1st_or_active-inactive
[12:03:55] [PASSED] inactive-2nd_or_active-inactive
[12:03:55] [PASSED] inactive-last_or_active-inactive
[12:03:55] [PASSED] inactive-no_or_active-inactive
[12:03:55] ============== [PASSED] xe_rtp_process_tests ===============
[12:03:55] ===================== [PASSED] xe_rtp ======================
[12:03:55] ==================== xe_wa (1 subtest) =====================
[12:03:55] ======================== xe_wa_gt  =========================
[12:03:55] [PASSED] TIGERLAKE B0
[12:03:55] [PASSED] DG1 A0
[12:03:55] [PASSED] DG1 B0
[12:03:55] [PASSED] ALDERLAKE_S A0
[12:03:55] [PASSED] ALDERLAKE_S B0
[12:03:55] [PASSED] ALDERLAKE_S C0
[12:03:55] [PASSED] ALDERLAKE_S D0
[12:03:55] [PASSED] ALDERLAKE_P A0
[12:03:55] [PASSED] ALDERLAKE_P B0
[12:03:55] [PASSED] ALDERLAKE_P C0
[12:03:55] [PASSED] ALDERLAKE_S RPLS D0
[12:03:55] [PASSED] ALDERLAKE_P RPLU E0
[12:03:55] [PASSED] DG2 G10 C0
[12:03:55] [PASSED] DG2 G11 B1
[12:03:55] [PASSED] DG2 G12 A1
[12:03:55] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:03:55] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:03:55] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[12:03:55] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[12:03:55] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[12:03:55] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[12:03:55] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[12:03:55] ==================== [PASSED] xe_wa_gt =====================
[12:03:55] ====================== [PASSED] xe_wa ======================
[12:03:55] ============================================================
[12:03:55] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[12:03:55] Elapsed time: 44.253s total, 4.198s configuring, 39.436s building, 0.595s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[12:03:55] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:03:56] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:04:41] Starting KUnit Kernel (1/1)...
[12:04:41] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:04:41] ============ drm_test_pick_cmdline (2 subtests) ============
[12:04:41] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[12:04:41] =============== drm_test_pick_cmdline_named  ===============
[12:04:41] [PASSED] NTSC
[12:04:41] [PASSED] NTSC-J
[12:04:41] [PASSED] PAL
[12:04:41] [PASSED] PAL-M
[12:04:41] =========== [PASSED] drm_test_pick_cmdline_named ===========
[12:04:41] ============== [PASSED] drm_test_pick_cmdline ==============
[12:04:41] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[12:04:41] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[12:04:41] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[12:04:41] =========== drm_validate_clone_mode (2 subtests) ===========
[12:04:41] ============== drm_test_check_in_clone_mode  ===============
[12:04:41] [PASSED] in_clone_mode
[12:04:41] [PASSED] not_in_clone_mode
[12:04:41] ========== [PASSED] drm_test_check_in_clone_mode ===========
[12:04:41] =============== drm_test_check_valid_clones  ===============
[12:04:41] [PASSED] not_in_clone_mode
[12:04:41] [PASSED] valid_clone
[12:04:41] [PASSED] invalid_clone
[12:04:41] =========== [PASSED] drm_test_check_valid_clones ===========
[12:04:41] ============= [PASSED] drm_validate_clone_mode =============
[12:04:41] ============= drm_validate_modeset (1 subtest) =============
[12:04:41] [PASSED] drm_test_check_connector_changed_modeset
[12:04:41] ============== [PASSED] drm_validate_modeset ===============
[12:04:41] ====== drm_test_bridge_get_current_state (2 subtests) ======
[12:04:41] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[12:04:41] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[12:04:41] ======== [PASSED] drm_test_bridge_get_current_state ========
[12:04:41] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[12:04:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[12:04:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[12:04:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[12:04:41] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[12:04:41] ============== drm_bridge_alloc (2 subtests) ===============
[12:04:41] [PASSED] drm_test_drm_bridge_alloc_basic
[12:04:41] [PASSED] drm_test_drm_bridge_alloc_get_put
[12:04:41] ================ [PASSED] drm_bridge_alloc =================
[12:04:41] ============= drm_cmdline_parser (40 subtests) =============
[12:04:41] [PASSED] drm_test_cmdline_force_d_only
[12:04:41] [PASSED] drm_test_cmdline_force_D_only_dvi
[12:04:41] [PASSED] drm_test_cmdline_force_D_only_hdmi
[12:04:41] [PASSED] drm_test_cmdline_force_D_only_not_digital
[12:04:41] [PASSED] drm_test_cmdline_force_e_only
[12:04:41] [PASSED] drm_test_cmdline_res
[12:04:41] [PASSED] drm_test_cmdline_res_vesa
[12:04:41] [PASSED] drm_test_cmdline_res_vesa_rblank
[12:04:41] [PASSED] drm_test_cmdline_res_rblank
[12:04:41] [PASSED] drm_test_cmdline_res_bpp
[12:04:41] [PASSED] drm_test_cmdline_res_refresh
[12:04:41] [PASSED] drm_test_cmdline_res_bpp_refresh
[12:04:41] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[12:04:41] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[12:04:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[12:04:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[12:04:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[12:04:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[12:04:41] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[12:04:41] [PASSED] drm_test_cmdline_res_margins_force_on
[12:04:41] [PASSED] drm_test_cmdline_res_vesa_margins
[12:04:41] [PASSED] drm_test_cmdline_name
[12:04:41] [PASSED] drm_test_cmdline_name_bpp
[12:04:41] [PASSED] drm_test_cmdline_name_option
[12:04:41] [PASSED] drm_test_cmdline_name_bpp_option
[12:04:41] [PASSED] drm_test_cmdline_rotate_0
[12:04:41] [PASSED] drm_test_cmdline_rotate_90
[12:04:41] [PASSED] drm_test_cmdline_rotate_180
[12:04:41] [PASSED] drm_test_cmdline_rotate_270
[12:04:41] [PASSED] drm_test_cmdline_hmirror
[12:04:41] [PASSED] drm_test_cmdline_vmirror
[12:04:41] [PASSED] drm_test_cmdline_margin_options
[12:04:41] [PASSED] drm_test_cmdline_multiple_options
[12:04:41] [PASSED] drm_test_cmdline_bpp_extra_and_option
[12:04:41] [PASSED] drm_test_cmdline_extra_and_option
[12:04:41] [PASSED] drm_test_cmdline_freestanding_options
[12:04:41] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[12:04:41] [PASSED] drm_test_cmdline_panel_orientation
[12:04:41] ================ drm_test_cmdline_invalid  =================
[12:04:41] [PASSED] margin_only
[12:04:41] [PASSED] interlace_only
[12:04:41] [PASSED] res_missing_x
[12:04:41] [PASSED] res_missing_y
[12:04:41] [PASSED] res_bad_y
[12:04:41] [PASSED] res_missing_y_bpp
[12:04:41] [PASSED] res_bad_bpp
[12:04:41] [PASSED] res_bad_refresh
[12:04:41] [PASSED] res_bpp_refresh_force_on_off
[12:04:41] [PASSED] res_invalid_mode
[12:04:41] [PASSED] res_bpp_wrong_place_mode
[12:04:41] [PASSED] name_bpp_refresh
[12:04:41] [PASSED] name_refresh
[12:04:41] [PASSED] name_refresh_wrong_mode
[12:04:41] [PASSED] name_refresh_invalid_mode
[12:04:41] [PASSED] rotate_multiple
[12:04:41] [PASSED] rotate_invalid_val
[12:04:41] [PASSED] rotate_truncated
[12:04:41] [PASSED] invalid_option
[12:04:41] [PASSED] invalid_tv_option
[12:04:41] [PASSED] truncated_tv_option
[12:04:41] ============ [PASSED] drm_test_cmdline_invalid =============
[12:04:41] =============== drm_test_cmdline_tv_options  ===============
[12:04:41] [PASSED] NTSC
[12:04:41] [PASSED] NTSC_443
[12:04:41] [PASSED] NTSC_J
[12:04:41] [PASSED] PAL
[12:04:41] [PASSED] PAL_M
[12:04:41] [PASSED] PAL_N
[12:04:41] [PASSED] SECAM
[12:04:41] [PASSED] MONO_525
[12:04:41] [PASSED] MONO_625
[12:04:41] =========== [PASSED] drm_test_cmdline_tv_options ===========
[12:04:41] =============== [PASSED] drm_cmdline_parser ================
[12:04:41] ========== drmm_connector_hdmi_init (20 subtests) ==========
[12:04:41] [PASSED] drm_test_connector_hdmi_init_valid
[12:04:41] [PASSED] drm_test_connector_hdmi_init_bpc_8
[12:04:41] [PASSED] drm_test_connector_hdmi_init_bpc_10
[12:04:41] [PASSED] drm_test_connector_hdmi_init_bpc_12
[12:04:41] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[12:04:41] [PASSED] drm_test_connector_hdmi_init_bpc_null
[12:04:41] [PASSED] drm_test_connector_hdmi_init_formats_empty
[12:04:41] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[12:04:41] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[12:04:41] [PASSED] supported_formats=0x9 yuv420_allowed=1
[12:04:41] [PASSED] supported_formats=0x9 yuv420_allowed=0
[12:04:41] [PASSED] supported_formats=0x3 yuv420_allowed=1
[12:04:41] [PASSED] supported_formats=0x3 yuv420_allowed=0
[12:04:41] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:04:41] [PASSED] drm_test_connector_hdmi_init_null_ddc
[12:04:41] [PASSED] drm_test_connector_hdmi_init_null_product
[12:04:41] [PASSED] drm_test_connector_hdmi_init_null_vendor
[12:04:41] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[12:04:41] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[12:04:41] [PASSED] drm_test_connector_hdmi_init_product_valid
[12:04:41] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[12:04:41] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[12:04:41] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[12:04:41] ========= drm_test_connector_hdmi_init_type_valid  =========
[12:04:41] [PASSED] HDMI-A
[12:04:41] [PASSED] HDMI-B
[12:04:41] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[12:04:41] ======== drm_test_connector_hdmi_init_type_invalid  ========
[12:04:41] [PASSED] Unknown
[12:04:41] [PASSED] VGA
[12:04:41] [PASSED] DVI-I
[12:04:41] [PASSED] DVI-D
[12:04:41] [PASSED] DVI-A
[12:04:41] [PASSED] Composite
[12:04:41] [PASSED] SVIDEO
[12:04:41] [PASSED] LVDS
[12:04:41] [PASSED] Component
[12:04:41] [PASSED] DIN
[12:04:41] [PASSED] DP
[12:04:41] [PASSED] TV
[12:04:41] [PASSED] eDP
[12:04:41] [PASSED] Virtual
[12:04:41] [PASSED] DSI
[12:04:41] [PASSED] DPI
[12:04:41] [PASSED] Writeback
[12:04:41] [PASSED] SPI
[12:04:41] [PASSED] USB
[12:04:41] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[12:04:41] ============ [PASSED] drmm_connector_hdmi_init =============
[12:04:41] ============= drmm_connector_init (3 subtests) =============
[12:04:41] [PASSED] drm_test_drmm_connector_init
[12:04:41] [PASSED] drm_test_drmm_connector_init_null_ddc
[12:04:41] ========= drm_test_drmm_connector_init_type_valid  =========
[12:04:41] [PASSED] Unknown
[12:04:41] [PASSED] VGA
[12:04:41] [PASSED] DVI-I
[12:04:41] [PASSED] DVI-D
[12:04:41] [PASSED] DVI-A
[12:04:41] [PASSED] Composite
[12:04:41] [PASSED] SVIDEO
[12:04:41] [PASSED] LVDS
[12:04:41] [PASSED] Component
[12:04:41] [PASSED] DIN
[12:04:41] [PASSED] DP
[12:04:41] [PASSED] HDMI-A
[12:04:41] [PASSED] HDMI-B
[12:04:41] [PASSED] TV
[12:04:41] [PASSED] eDP
[12:04:41] [PASSED] Virtual
[12:04:41] [PASSED] DSI
[12:04:41] [PASSED] DPI
[12:04:41] [PASSED] Writeback
[12:04:41] [PASSED] SPI
[12:04:41] [PASSED] USB
[12:04:41] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[12:04:41] =============== [PASSED] drmm_connector_init ===============
[12:04:41] ========= drm_connector_dynamic_init (6 subtests) ==========
[12:04:41] [PASSED] drm_test_drm_connector_dynamic_init
[12:04:41] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[12:04:41] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[12:04:41] [PASSED] drm_test_drm_connector_dynamic_init_properties
[12:04:41] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[12:04:41] [PASSED] Unknown
[12:04:41] [PASSED] VGA
[12:04:41] [PASSED] DVI-I
[12:04:41] [PASSED] DVI-D
[12:04:41] [PASSED] DVI-A
[12:04:41] [PASSED] Composite
[12:04:41] [PASSED] SVIDEO
[12:04:41] [PASSED] LVDS
[12:04:41] [PASSED] Component
[12:04:41] [PASSED] DIN
[12:04:41] [PASSED] DP
[12:04:41] [PASSED] HDMI-A
[12:04:41] [PASSED] HDMI-B
[12:04:41] [PASSED] TV
[12:04:41] [PASSED] eDP
[12:04:41] [PASSED] Virtual
[12:04:41] [PASSED] DSI
[12:04:41] [PASSED] DPI
[12:04:41] [PASSED] Writeback
[12:04:41] [PASSED] SPI
[12:04:41] [PASSED] USB
[12:04:41] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[12:04:41] ======== drm_test_drm_connector_dynamic_init_name  =========
[12:04:41] [PASSED] Unknown
[12:04:41] [PASSED] VGA
[12:04:41] [PASSED] DVI-I
[12:04:41] [PASSED] DVI-D
[12:04:41] [PASSED] DVI-A
[12:04:41] [PASSED] Composite
[12:04:41] [PASSED] SVIDEO
[12:04:41] [PASSED] LVDS
[12:04:41] [PASSED] Component
[12:04:41] [PASSED] DIN
[12:04:41] [PASSED] DP
[12:04:41] [PASSED] HDMI-A
[12:04:41] [PASSED] HDMI-B
[12:04:41] [PASSED] TV
[12:04:41] [PASSED] eDP
[12:04:41] [PASSED] Virtual
[12:04:41] [PASSED] DSI
[12:04:41] [PASSED] DPI
[12:04:41] [PASSED] Writeback
[12:04:41] [PASSED] SPI
[12:04:41] [PASSED] USB
[12:04:41] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[12:04:41] =========== [PASSED] drm_connector_dynamic_init ============
[12:04:41] ==== drm_connector_dynamic_register_early (4 subtests) =====
[12:04:41] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[12:04:41] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[12:04:41] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[12:04:41] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[12:04:41] ====== [PASSED] drm_connector_dynamic_register_early =======
[12:04:41] ======= drm_connector_dynamic_register (7 subtests) ========
[12:04:41] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[12:04:41] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[12:04:41] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[12:04:41] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[12:04:41] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[12:04:41] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[12:04:41] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[12:04:41] ========= [PASSED] drm_connector_dynamic_register ==========
[12:04:41] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[12:04:41] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[12:04:41] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[12:04:41] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[12:04:41] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[12:04:41] ========== drm_test_get_tv_mode_from_name_valid  ===========
[12:04:41] [PASSED] NTSC
[12:04:41] [PASSED] NTSC-443
[12:04:41] [PASSED] NTSC-J
[12:04:41] [PASSED] PAL
[12:04:41] [PASSED] PAL-M
[12:04:41] [PASSED] PAL-N
[12:04:41] [PASSED] SECAM
[12:04:41] [PASSED] Mono
[12:04:41] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[12:04:41] [PASSED] drm_test_get_tv_mode_from_name_truncated
[12:04:41] ============ [PASSED] drm_get_tv_mode_from_name ============
[12:04:41] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[12:04:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[12:04:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[12:04:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[12:04:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[12:04:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[12:04:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[12:04:41] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[12:04:41] [PASSED] VIC 96
[12:04:41] [PASSED] VIC 97
[12:04:41] [PASSED] VIC 101
[12:04:41] [PASSED] VIC 102
[12:04:41] [PASSED] VIC 106
[12:04:41] [PASSED] VIC 107
[12:04:41] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[12:04:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[12:04:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[12:04:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[12:04:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[12:04:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[12:04:41] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[12:04:41] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[12:04:41] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[12:04:41] [PASSED] Automatic
[12:04:41] [PASSED] Full
[12:04:41] [PASSED] Limited 16:235
[12:04:41] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[12:04:41] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[12:04:41] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[12:04:41] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[12:04:41] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[12:04:41] [PASSED] RGB
[12:04:41] [PASSED] YUV 4:2:0
[12:04:41] [PASSED] YUV 4:2:2
[12:04:41] [PASSED] YUV 4:4:4
[12:04:41] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[12:04:41] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[12:04:41] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[12:04:41] ============= drm_damage_helper (21 subtests) ==============
[12:04:41] [PASSED] drm_test_damage_iter_no_damage
[12:04:41] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[12:04:41] [PASSED] drm_test_damage_iter_no_damage_src_moved
[12:04:41] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[12:04:41] [PASSED] drm_test_damage_iter_no_damage_not_visible
[12:04:41] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[12:04:41] [PASSED] drm_test_damage_iter_no_damage_no_fb
[12:04:41] [PASSED] drm_test_damage_iter_simple_damage
[12:04:41] [PASSED] drm_test_damage_iter_single_damage
[12:04:41] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[12:04:41] [PASSED] drm_test_damage_iter_single_damage_outside_src
[12:04:41] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[12:04:41] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[12:04:41] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[12:04:41] [PASSED] drm_test_damage_iter_single_damage_src_moved
[12:04:41] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[12:04:41] [PASSED] drm_test_damage_iter_damage
[12:04:41] [PASSED] drm_test_damage_iter_damage_one_intersect
[12:04:41] [PASSED] drm_test_damage_iter_damage_one_outside
[12:04:41] [PASSED] drm_test_damage_iter_damage_src_moved
[12:04:41] [PASSED] drm_test_damage_iter_damage_not_visible
[12:04:41] ================ [PASSED] drm_damage_helper ================
[12:04:41] ============== drm_dp_mst_helper (3 subtests) ==============
[12:04:41] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[12:04:41] [PASSED] Clock 154000 BPP 30 DSC disabled
[12:04:41] [PASSED] Clock 234000 BPP 30 DSC disabled
[12:04:41] [PASSED] Clock 297000 BPP 24 DSC disabled
[12:04:41] [PASSED] Clock 332880 BPP 24 DSC enabled
[12:04:41] [PASSED] Clock 324540 BPP 24 DSC enabled
[12:04:41] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[12:04:41] ============== drm_test_dp_mst_calc_pbn_div  ===============
[12:04:41] [PASSED] Link rate 2000000 lane count 4
[12:04:41] [PASSED] Link rate 2000000 lane count 2
[12:04:41] [PASSED] Link rate 2000000 lane count 1
[12:04:41] [PASSED] Link rate 1350000 lane count 4
[12:04:41] [PASSED] Link rate 1350000 lane count 2
[12:04:41] [PASSED] Link rate 1350000 lane count 1
[12:04:41] [PASSED] Link rate 1000000 lane count 4
[12:04:41] [PASSED] Link rate 1000000 lane count 2
[12:04:41] [PASSED] Link rate 1000000 lane count 1
[12:04:41] [PASSED] Link rate 810000 lane count 4
[12:04:41] [PASSED] Link rate 810000 lane count 2
[12:04:41] [PASSED] Link rate 810000 lane count 1
[12:04:41] [PASSED] Link rate 540000 lane count 4
[12:04:41] [PASSED] Link rate 540000 lane count 2
[12:04:41] [PASSED] Link rate 540000 lane count 1
[12:04:41] [PASSED] Link rate 270000 lane count 4
[12:04:41] [PASSED] Link rate 270000 lane count 2
[12:04:41] [PASSED] Link rate 270000 lane count 1
[12:04:41] [PASSED] Link rate 162000 lane count 4
[12:04:41] [PASSED] Link rate 162000 lane count 2
[12:04:41] [PASSED] Link rate 162000 lane count 1
[12:04:41] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[12:04:41] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[12:04:41] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[12:04:41] [PASSED] DP_POWER_UP_PHY with port number
[12:04:41] [PASSED] DP_POWER_DOWN_PHY with port number
[12:04:41] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[12:04:41] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[12:04:41] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[12:04:41] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[12:04:41] [PASSED] DP_QUERY_PAYLOAD with port number
[12:04:41] [PASSED] DP_QUERY_PAYLOAD with VCPI
[12:04:41] [PASSED] DP_REMOTE_DPCD_READ with port number
[12:04:41] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[12:04:41] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[12:04:41] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[12:04:41] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[12:04:41] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[12:04:41] [PASSED] DP_REMOTE_I2C_READ with port number
[12:04:41] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[12:04:41] [PASSED] DP_REMOTE_I2C_READ with transactions array
[12:04:41] [PASSED] DP_REMOTE_I2C_WRITE with port number
[12:04:41] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[12:04:41] [PASSED] DP_REMOTE_I2C_WRITE with data array
[12:04:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[12:04:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[12:04:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[12:04:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[12:04:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[12:04:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[12:04:41] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[12:04:41] ================ [PASSED] drm_dp_mst_helper ================
[12:04:41] ================== drm_exec (7 subtests) ===================
[12:04:41] [PASSED] sanitycheck
[12:04:41] [PASSED] test_lock
[12:04:41] [PASSED] test_lock_unlock
[12:04:41] [PASSED] test_duplicates
[12:04:41] [PASSED] test_prepare
[12:04:41] [PASSED] test_prepare_array
[12:04:41] [PASSED] test_multiple_loops
[12:04:41] ==================== [PASSED] drm_exec =====================
[12:04:41] =========== drm_format_helper_test (17 subtests) ===========
[12:04:41] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[12:04:41] [PASSED] single_pixel_source_buffer
[12:04:41] [PASSED] single_pixel_clip_rectangle
[12:04:41] [PASSED] well_known_colors
[12:04:41] [PASSED] destination_pitch
[12:04:41] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[12:04:41] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[12:04:41] [PASSED] single_pixel_source_buffer
[12:04:41] [PASSED] single_pixel_clip_rectangle
[12:04:41] [PASSED] well_known_colors
[12:04:41] [PASSED] destination_pitch
[12:04:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[12:04:41] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[12:04:41] [PASSED] single_pixel_source_buffer
[12:04:41] [PASSED] single_pixel_clip_rectangle
[12:04:41] [PASSED] well_known_colors
[12:04:41] [PASSED] destination_pitch
[12:04:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[12:04:41] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[12:04:41] [PASSED] single_pixel_source_buffer
[12:04:41] [PASSED] single_pixel_clip_rectangle
[12:04:41] [PASSED] well_known_colors
[12:04:41] [PASSED] destination_pitch
[12:04:41] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[12:04:41] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[12:04:41] [PASSED] single_pixel_source_buffer
[12:04:41] [PASSED] single_pixel_clip_rectangle
[12:04:41] [PASSED] well_known_colors
[12:04:41] [PASSED] destination_pitch
[12:04:41] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[12:04:41] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[12:04:41] [PASSED] single_pixel_source_buffer
[12:04:41] [PASSED] single_pixel_clip_rectangle
[12:04:41] [PASSED] well_known_colors
[12:04:41] [PASSED] destination_pitch
[12:04:41] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[12:04:41] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[12:04:41] [PASSED] single_pixel_source_buffer
[12:04:41] [PASSED] single_pixel_clip_rectangle
[12:04:41] [PASSED] well_known_colors
[12:04:41] [PASSED] destination_pitch
[12:04:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[12:04:41] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[12:04:41] [PASSED] single_pixel_source_buffer
[12:04:41] [PASSED] single_pixel_clip_rectangle
[12:04:41] [PASSED] well_known_colors
[12:04:41] [PASSED] destination_pitch
[12:04:41] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[12:04:41] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[12:04:41] [PASSED] single_pixel_source_buffer
[12:04:41] [PASSED] single_pixel_clip_rectangle
[12:04:41] [PASSED] well_known_colors
[12:04:41] [PASSED] destination_pitch
[12:04:41] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[12:04:41] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[12:04:41] [PASSED] single_pixel_source_buffer
[12:04:41] [PASSED] single_pixel_clip_rectangle
[12:04:41] [PASSED] well_known_colors
[12:04:41] [PASSED] destination_pitch
[12:04:41] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[12:04:41] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[12:04:41] [PASSED] single_pixel_source_buffer
[12:04:41] [PASSED] single_pixel_clip_rectangle
[12:04:41] [PASSED] well_known_colors
[12:04:41] [PASSED] destination_pitch
[12:04:41] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[12:04:41] ============== drm_test_fb_xrgb8888_to_mono  ===============
[12:04:41] [PASSED] single_pixel_source_buffer
[12:04:41] [PASSED] single_pixel_clip_rectangle
[12:04:41] [PASSED] well_known_colors
[12:04:41] [PASSED] destination_pitch
[12:04:41] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[12:04:41] ==================== drm_test_fb_swab  =====================
[12:04:41] [PASSED] single_pixel_source_buffer
[12:04:41] [PASSED] single_pixel_clip_rectangle
[12:04:41] [PASSED] well_known_colors
[12:04:41] [PASSED] destination_pitch
[12:04:41] ================ [PASSED] drm_test_fb_swab =================
[12:04:41] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[12:04:41] [PASSED] single_pixel_source_buffer
[12:04:41] [PASSED] single_pixel_clip_rectangle
[12:04:41] [PASSED] well_known_colors
[12:04:41] [PASSED] destination_pitch
[12:04:41] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[12:04:41] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[12:04:41] [PASSED] single_pixel_source_buffer
[12:04:41] [PASSED] single_pixel_clip_rectangle
[12:04:41] [PASSED] well_known_colors
[12:04:41] [PASSED] destination_pitch
[12:04:41] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[12:04:41] ================= drm_test_fb_clip_offset  =================
[12:04:41] [PASSED] pass through
[12:04:41] [PASSED] horizontal offset
[12:04:41] [PASSED] vertical offset
[12:04:41] [PASSED] horizontal and vertical offset
[12:04:41] [PASSED] horizontal offset (custom pitch)
[12:04:41] [PASSED] vertical offset (custom pitch)
[12:04:41] [PASSED] horizontal and vertical offset (custom pitch)
[12:04:41] ============= [PASSED] drm_test_fb_clip_offset =============
[12:04:41] =================== drm_test_fb_memcpy  ====================
[12:04:41] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[12:04:41] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[12:04:41] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[12:04:41] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[12:04:41] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[12:04:41] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[12:04:41] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[12:04:41] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[12:04:41] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[12:04:41] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[12:04:41] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[12:04:41] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[12:04:41] =============== [PASSED] drm_test_fb_memcpy ================
[12:04:41] ============= [PASSED] drm_format_helper_test ==============
[12:04:41] ================= drm_format (18 subtests) =================
[12:04:41] [PASSED] drm_test_format_block_width_invalid
[12:04:41] [PASSED] drm_test_format_block_width_one_plane
[12:04:41] [PASSED] drm_test_format_block_width_two_plane
[12:04:41] [PASSED] drm_test_format_block_width_three_plane
[12:04:41] [PASSED] drm_test_format_block_width_tiled
[12:04:41] [PASSED] drm_test_format_block_height_invalid
[12:04:41] [PASSED] drm_test_format_block_height_one_plane
[12:04:41] [PASSED] drm_test_format_block_height_two_plane
[12:04:41] [PASSED] drm_test_format_block_height_three_plane
[12:04:41] [PASSED] drm_test_format_block_height_tiled
[12:04:41] [PASSED] drm_test_format_min_pitch_invalid
[12:04:41] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[12:04:41] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[12:04:41] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[12:04:41] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[12:04:41] [PASSED] drm_test_format_min_pitch_two_plane
[12:04:41] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[12:04:41] [PASSED] drm_test_format_min_pitch_tiled
[12:04:41] =================== [PASSED] drm_format ====================
[12:04:41] ============== drm_framebuffer (10 subtests) ===============
[12:04:41] ========== drm_test_framebuffer_check_src_coords  ==========
[12:04:41] [PASSED] Success: source fits into fb
[12:04:41] [PASSED] Fail: overflowing fb with x-axis coordinate
[12:04:41] [PASSED] Fail: overflowing fb with y-axis coordinate
[12:04:41] [PASSED] Fail: overflowing fb with source width
[12:04:41] [PASSED] Fail: overflowing fb with source height
[12:04:41] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[12:04:41] [PASSED] drm_test_framebuffer_cleanup
[12:04:41] =============== drm_test_framebuffer_create  ===============
[12:04:41] [PASSED] ABGR8888 normal sizes
[12:04:41] [PASSED] ABGR8888 max sizes
[12:04:41] [PASSED] ABGR8888 pitch greater than min required
[12:04:41] [PASSED] ABGR8888 pitch less than min required
[12:04:41] [PASSED] ABGR8888 Invalid width
[12:04:41] [PASSED] ABGR8888 Invalid buffer handle
[12:04:41] [PASSED] No pixel format
[12:04:41] [PASSED] ABGR8888 Width 0
[12:04:41] [PASSED] ABGR8888 Height 0
[12:04:41] [PASSED] ABGR8888 Out of bound height * pitch combination
[12:04:41] [PASSED] ABGR8888 Large buffer offset
[12:04:41] [PASSED] ABGR8888 Buffer offset for inexistent plane
[12:04:41] [PASSED] ABGR8888 Invalid flag
[12:04:41] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[12:04:41] [PASSED] ABGR8888 Valid buffer modifier
[12:04:41] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[12:04:41] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[12:04:41] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[12:04:41] [PASSED] NV12 Normal sizes
[12:04:41] [PASSED] NV12 Max sizes
[12:04:41] [PASSED] NV12 Invalid pitch
[12:04:41] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[12:04:41] [PASSED] NV12 different  modifier per-plane
[12:04:41] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[12:04:41] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[12:04:41] [PASSED] NV12 Modifier for inexistent plane
[12:04:41] [PASSED] NV12 Handle for inexistent plane
[12:04:41] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[12:04:41] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[12:04:41] [PASSED] YVU420 Normal sizes
[12:04:41] [PASSED] YVU420 Max sizes
[12:04:41] [PASSED] YVU420 Invalid pitch
[12:04:41] [PASSED] YVU420 Different pitches
[12:04:41] [PASSED] YVU420 Different buffer offsets/pitches
[12:04:41] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[12:04:41] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[12:04:41] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[12:04:41] [PASSED] YVU420 Valid modifier
[12:04:41] [PASSED] YVU420 Different modifiers per plane
[12:04:41] [PASSED] YVU420 Modifier for inexistent plane
[12:04:41] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[12:04:41] [PASSED] X0L2 Normal sizes
[12:04:41] [PASSED] X0L2 Max sizes
[12:04:41] [PASSED] X0L2 Invalid pitch
[12:04:41] [PASSED] X0L2 Pitch greater than minimum required
[12:04:41] [PASSED] X0L2 Handle for inexistent plane
[12:04:41] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[12:04:41] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[12:04:41] [PASSED] X0L2 Valid modifier
[12:04:41] [PASSED] X0L2 Modifier for inexistent plane
[12:04:41] =========== [PASSED] drm_test_framebuffer_create ===========
[12:04:41] [PASSED] drm_test_framebuffer_free
[12:04:41] [PASSED] drm_test_framebuffer_init
[12:04:41] [PASSED] drm_test_framebuffer_init_bad_format
[12:04:41] [PASSED] drm_test_framebuffer_init_dev_mismatch
[12:04:41] [PASSED] drm_test_framebuffer_lookup
[12:04:41] [PASSED] drm_test_framebuffer_lookup_inexistent
[12:04:41] [PASSED] drm_test_framebuffer_modifiers_not_supported
[12:04:41] ================= [PASSED] drm_framebuffer =================
[12:04:41] ================ drm_gem_shmem (8 subtests) ================
[12:04:41] [PASSED] drm_gem_shmem_test_obj_create
[12:04:41] [PASSED] drm_gem_shmem_test_obj_create_private
[12:04:41] [PASSED] drm_gem_shmem_test_pin_pages
[12:04:41] [PASSED] drm_gem_shmem_test_vmap
[12:04:41] [PASSED] drm_gem_shmem_test_get_sg_table
[12:04:41] [PASSED] drm_gem_shmem_test_get_pages_sgt
[12:04:41] [PASSED] drm_gem_shmem_test_madvise
[12:04:41] [PASSED] drm_gem_shmem_test_purge
[12:04:41] ================== [PASSED] drm_gem_shmem ==================
[12:04:41] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[12:04:41] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[12:04:41] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[12:04:41] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[12:04:41] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[12:04:41] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[12:04:41] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[12:04:41] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[12:04:41] [PASSED] Automatic
[12:04:41] [PASSED] Full
[12:04:41] [PASSED] Limited 16:235
[12:04:41] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[12:04:41] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[12:04:41] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[12:04:41] [PASSED] drm_test_check_disable_connector
[12:04:41] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[12:04:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[12:04:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[12:04:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[12:04:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[12:04:41] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[12:04:41] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[12:04:41] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[12:04:41] [PASSED] drm_test_check_output_bpc_dvi
[12:04:41] [PASSED] drm_test_check_output_bpc_format_vic_1
[12:04:41] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[12:04:41] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[12:04:41] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[12:04:41] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[12:04:41] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[12:04:41] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[12:04:41] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[12:04:41] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[12:04:41] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[12:04:41] [PASSED] drm_test_check_broadcast_rgb_value
[12:04:41] [PASSED] drm_test_check_bpc_8_value
[12:04:41] [PASSED] drm_test_check_bpc_10_value
[12:04:41] [PASSED] drm_test_check_bpc_12_value
[12:04:41] [PASSED] drm_test_check_format_value
[12:04:41] [PASSED] drm_test_check_tmds_char_value
[12:04:41] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[12:04:41] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[12:04:41] [PASSED] drm_test_check_mode_valid
[12:04:41] [PASSED] drm_test_check_mode_valid_reject
[12:04:41] [PASSED] drm_test_check_mode_valid_reject_rate
[12:04:41] [PASSED] drm_test_check_mode_valid_reject_max_clock
[12:04:41] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[12:04:41] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[12:04:41] [PASSED] drm_test_check_infoframes
[12:04:41] [PASSED] drm_test_check_reject_avi_infoframe
[12:04:41] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[12:04:41] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[12:04:41] [PASSED] drm_test_check_reject_audio_infoframe
[12:04:41] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[12:04:41] ================= drm_managed (2 subtests) =================
[12:04:41] [PASSED] drm_test_managed_release_action
[12:04:41] [PASSED] drm_test_managed_run_action
[12:04:41] =================== [PASSED] drm_managed ===================
[12:04:41] =================== drm_mm (6 subtests) ====================
[12:04:41] [PASSED] drm_test_mm_init
[12:04:41] [PASSED] drm_test_mm_debug
[12:04:41] [PASSED] drm_test_mm_align32
[12:04:41] [PASSED] drm_test_mm_align64
[12:04:41] [PASSED] drm_test_mm_lowest
[12:04:41] [PASSED] drm_test_mm_highest
[12:04:41] ===================== [PASSED] drm_mm ======================
[12:04:41] ============= drm_modes_analog_tv (5 subtests) =============
[12:04:41] [PASSED] drm_test_modes_analog_tv_mono_576i
[12:04:41] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[12:04:41] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[12:04:41] [PASSED] drm_test_modes_analog_tv_pal_576i
[12:04:41] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[12:04:41] =============== [PASSED] drm_modes_analog_tv ===============
[12:04:41] ============== drm_plane_helper (2 subtests) ===============
[12:04:41] =============== drm_test_check_plane_state  ================
[12:04:41] [PASSED] clipping_simple
[12:04:41] [PASSED] clipping_rotate_reflect
[12:04:41] [PASSED] positioning_simple
[12:04:41] [PASSED] upscaling
[12:04:41] [PASSED] downscaling
[12:04:41] [PASSED] rounding1
[12:04:41] [PASSED] rounding2
[12:04:41] [PASSED] rounding3
[12:04:41] [PASSED] rounding4
[12:04:41] =========== [PASSED] drm_test_check_plane_state ============
[12:04:41] =========== drm_test_check_invalid_plane_state  ============
[12:04:41] [PASSED] positioning_invalid
[12:04:41] [PASSED] upscaling_invalid
[12:04:41] [PASSED] downscaling_invalid
[12:04:41] ======= [PASSED] drm_test_check_invalid_plane_state ========
[12:04:41] ================ [PASSED] drm_plane_helper =================
[12:04:41] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[12:04:41] ====== drm_test_connector_helper_tv_get_modes_check  =======
[12:04:41] [PASSED] None
[12:04:41] [PASSED] PAL
[12:04:41] [PASSED] NTSC
[12:04:41] [PASSED] Both, NTSC Default
[12:04:41] [PASSED] Both, PAL Default
[12:04:41] [PASSED] Both, NTSC Default, with PAL on command-line
[12:04:41] [PASSED] Both, PAL Default, with NTSC on command-line
[12:04:41] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[12:04:41] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[12:04:41] ================== drm_rect (9 subtests) ===================
[12:04:41] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[12:04:41] [PASSED] drm_test_rect_clip_scaled_not_clipped
[12:04:41] [PASSED] drm_test_rect_clip_scaled_clipped
[12:04:41] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[12:04:41] ================= drm_test_rect_intersect  =================
[12:04:41] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[12:04:41] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[12:04:41] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[12:04:41] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[12:04:41] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[12:04:41] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[12:04:41] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[12:04:41] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[12:04:41] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[12:04:41] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[12:04:41] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[12:04:41] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[12:04:41] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[12:04:41] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[12:04:41] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[12:04:41] ============= [PASSED] drm_test_rect_intersect =============
[12:04:41] ================ drm_test_rect_calc_hscale  ================
[12:04:41] [PASSED] normal use
[12:04:41] [PASSED] out of max range
[12:04:41] [PASSED] out of min range
[12:04:41] [PASSED] zero dst
[12:04:41] [PASSED] negative src
[12:04:41] [PASSED] negative dst
[12:04:41] ============ [PASSED] drm_test_rect_calc_hscale ============
[12:04:41] ================ drm_test_rect_calc_vscale  ================
[12:04:41] [PASSED] normal use
[12:04:41] [PASSED] out of max range
[12:04:41] [PASSED] out of min range
[12:04:41] [PASSED] zero dst
[12:04:41] [PASSED] negative src
[12:04:41] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[12:04:41] ============ [PASSED] drm_test_rect_calc_vscale ============
[12:04:41] ================== drm_test_rect_rotate  ===================
[12:04:41] [PASSED] reflect-x
[12:04:41] [PASSED] reflect-y
[12:04:41] [PASSED] rotate-0
[12:04:41] [PASSED] rotate-90
[12:04:41] [PASSED] rotate-180
[12:04:41] [PASSED] rotate-270
[12:04:41] ============== [PASSED] drm_test_rect_rotate ===============
[12:04:41] ================ drm_test_rect_rotate_inv  =================
[12:04:41] [PASSED] reflect-x
[12:04:41] [PASSED] reflect-y
[12:04:41] [PASSED] rotate-0
[12:04:41] [PASSED] rotate-90
[12:04:41] [PASSED] rotate-180
[12:04:41] [PASSED] rotate-270
[12:04:41] ============ [PASSED] drm_test_rect_rotate_inv =============
[12:04:41] ==================== [PASSED] drm_rect =====================
[12:04:41] ============ drm_sysfb_modeset_test (1 subtest) ============
[12:04:41] ============ drm_test_sysfb_build_fourcc_list  =============
[12:04:41] [PASSED] no native formats
[12:04:41] [PASSED] XRGB8888 as native format
[12:04:41] [PASSED] remove duplicates
[12:04:41] [PASSED] convert alpha formats
[12:04:41] [PASSED] random formats
[12:04:41] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[12:04:41] ============= [PASSED] drm_sysfb_modeset_test ==============
[12:04:41] ================== drm_fixp (2 subtests) ===================
[12:04:41] [PASSED] drm_test_int2fixp
[12:04:41] [PASSED] drm_test_sm2fixp
[12:04:41] ==================== [PASSED] drm_fixp =====================
[12:04:41] ============================================================
[12:04:41] Testing complete. Ran 621 tests: passed: 621
[12:04:41] Elapsed time: 46.145s total, 1.716s configuring, 44.212s building, 0.194s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[12:04:41] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:04:44] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:05:00] Starting KUnit Kernel (1/1)...
[12:05:00] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:05:00] ================= ttm_device (5 subtests) ==================
[12:05:00] [PASSED] ttm_device_init_basic
[12:05:00] [PASSED] ttm_device_init_multiple
[12:05:00] [PASSED] ttm_device_fini_basic
[12:05:00] [PASSED] ttm_device_init_no_vma_man
[12:05:00] ================== ttm_device_init_pools  ==================
[12:05:00] [PASSED] No DMA allocations, no DMA32 required
[12:05:00] [PASSED] DMA allocations, DMA32 required
[12:05:00] [PASSED] No DMA allocations, DMA32 required
[12:05:00] [PASSED] DMA allocations, no DMA32 required
[12:05:00] ============== [PASSED] ttm_device_init_pools ==============
[12:05:00] =================== [PASSED] ttm_device ====================
[12:05:00] ================== ttm_pool (8 subtests) ===================
[12:05:00] ================== ttm_pool_alloc_basic  ===================
[12:05:00] [PASSED] One page
[12:05:00] [PASSED] More than one page
[12:05:00] [PASSED] Above the allocation limit
[12:05:00] [PASSED] One page, with coherent DMA mappings enabled
[12:05:00] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:05:00] ============== [PASSED] ttm_pool_alloc_basic ===============
[12:05:00] ============== ttm_pool_alloc_basic_dma_addr  ==============
[12:05:00] [PASSED] One page
[12:05:00] [PASSED] More than one page
[12:05:00] [PASSED] Above the allocation limit
[12:05:00] [PASSED] One page, with coherent DMA mappings enabled
[12:05:00] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:05:00] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[12:05:00] [PASSED] ttm_pool_alloc_order_caching_match
[12:05:00] [PASSED] ttm_pool_alloc_caching_mismatch
[12:05:00] [PASSED] ttm_pool_alloc_order_mismatch
[12:05:00] [PASSED] ttm_pool_free_dma_alloc
[12:05:00] [PASSED] ttm_pool_free_no_dma_alloc
[12:05:00] [PASSED] ttm_pool_fini_basic
[12:05:00] ==================== [PASSED] ttm_pool =====================
[12:05:00] ================ ttm_resource (8 subtests) =================
[12:05:00] ================= ttm_resource_init_basic  =================
[12:05:00] [PASSED] Init resource in TTM_PL_SYSTEM
[12:05:00] [PASSED] Init resource in TTM_PL_VRAM
[12:05:00] [PASSED] Init resource in a private placement
[12:05:00] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[12:05:00] ============= [PASSED] ttm_resource_init_basic =============
[12:05:00] [PASSED] ttm_resource_init_pinned
[12:05:00] [PASSED] ttm_resource_fini_basic
[12:05:00] [PASSED] ttm_resource_manager_init_basic
[12:05:00] [PASSED] ttm_resource_manager_usage_basic
[12:05:00] [PASSED] ttm_resource_manager_set_used_basic
[12:05:00] [PASSED] ttm_sys_man_alloc_basic
[12:05:00] [PASSED] ttm_sys_man_free_basic
[12:05:00] ================== [PASSED] ttm_resource ===================
[12:05:00] =================== ttm_tt (15 subtests) ===================
[12:05:00] ==================== ttm_tt_init_basic  ====================
[12:05:00] [PASSED] Page-aligned size
[12:05:00] [PASSED] Extra pages requested
[12:05:00] ================ [PASSED] ttm_tt_init_basic ================
[12:05:00] [PASSED] ttm_tt_init_misaligned
[12:05:00] [PASSED] ttm_tt_fini_basic
[12:05:00] [PASSED] ttm_tt_fini_sg
[12:05:00] [PASSED] ttm_tt_fini_shmem
[12:05:00] [PASSED] ttm_tt_create_basic
[12:05:00] [PASSED] ttm_tt_create_invalid_bo_type
[12:05:00] [PASSED] ttm_tt_create_ttm_exists
[12:05:00] [PASSED] ttm_tt_create_failed
[12:05:00] [PASSED] ttm_tt_destroy_basic
[12:05:00] [PASSED] ttm_tt_populate_null_ttm
[12:05:00] [PASSED] ttm_tt_populate_populated_ttm
[12:05:00] [PASSED] ttm_tt_unpopulate_basic
[12:05:00] [PASSED] ttm_tt_unpopulate_empty_ttm
[12:05:00] [PASSED] ttm_tt_swapin_basic
[12:05:00] ===================== [PASSED] ttm_tt ======================
[12:05:00] =================== ttm_bo (14 subtests) ===================
[12:05:00] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[12:05:00] [PASSED] Cannot be interrupted and sleeps
[12:05:00] [PASSED] Cannot be interrupted, locks straight away
[12:05:00] [PASSED] Can be interrupted, sleeps
[12:05:00] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[12:05:00] [PASSED] ttm_bo_reserve_locked_no_sleep
[12:05:00] [PASSED] ttm_bo_reserve_no_wait_ticket
[12:05:00] [PASSED] ttm_bo_reserve_double_resv
[12:05:00] [PASSED] ttm_bo_reserve_interrupted
[12:05:00] [PASSED] ttm_bo_reserve_deadlock
[12:05:00] [PASSED] ttm_bo_unreserve_basic
[12:05:00] [PASSED] ttm_bo_unreserve_pinned
[12:05:00] [PASSED] ttm_bo_unreserve_bulk
[12:05:00] [PASSED] ttm_bo_fini_basic
[12:05:00] [PASSED] ttm_bo_fini_shared_resv
[12:05:00] [PASSED] ttm_bo_pin_basic
[12:05:00] [PASSED] ttm_bo_pin_unpin_resource
[12:05:00] [PASSED] ttm_bo_multiple_pin_one_unpin
[12:05:00] ===================== [PASSED] ttm_bo ======================
[12:05:00] ============== ttm_bo_validate (21 subtests) ===============
[12:05:00] ============== ttm_bo_init_reserved_sys_man  ===============
[12:05:00] [PASSED] Buffer object for userspace
[12:05:00] [PASSED] Kernel buffer object
[12:05:00] [PASSED] Shared buffer object
[12:05:00] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[12:05:00] ============== ttm_bo_init_reserved_mock_man  ==============
[12:05:00] [PASSED] Buffer object for userspace
[12:05:00] [PASSED] Kernel buffer object
[12:05:00] [PASSED] Shared buffer object
[12:05:00] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[12:05:00] [PASSED] ttm_bo_init_reserved_resv
[12:05:00] ================== ttm_bo_validate_basic  ==================
[12:05:00] [PASSED] Buffer object for userspace
[12:05:00] [PASSED] Kernel buffer object
[12:05:00] [PASSED] Shared buffer object
[12:05:00] ============== [PASSED] ttm_bo_validate_basic ==============
[12:05:00] [PASSED] ttm_bo_validate_invalid_placement
[12:05:00] ============= ttm_bo_validate_same_placement  ==============
[12:05:00] [PASSED] System manager
[12:05:00] [PASSED] VRAM manager
[12:05:00] ========= [PASSED] ttm_bo_validate_same_placement ==========
[12:05:00] [PASSED] ttm_bo_validate_failed_alloc
[12:05:00] [PASSED] ttm_bo_validate_pinned
[12:05:00] [PASSED] ttm_bo_validate_busy_placement
[12:05:00] ================ ttm_bo_validate_multihop  =================
[12:05:00] [PASSED] Buffer object for userspace
[12:05:00] [PASSED] Kernel buffer object
[12:05:00] [PASSED] Shared buffer object
[12:05:00] ============ [PASSED] ttm_bo_validate_multihop =============
[12:05:00] ========== ttm_bo_validate_no_placement_signaled  ==========
[12:05:00] [PASSED] Buffer object in system domain, no page vector
[12:05:00] [PASSED] Buffer object in system domain with an existing page vector
[12:05:00] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[12:05:00] ======== ttm_bo_validate_no_placement_not_signaled  ========
[12:05:00] [PASSED] Buffer object for userspace
[12:05:00] [PASSED] Kernel buffer object
[12:05:00] [PASSED] Shared buffer object
[12:05:00] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[12:05:00] [PASSED] ttm_bo_validate_move_fence_signaled
[12:05:00] ========= ttm_bo_validate_move_fence_not_signaled  =========
[12:05:00] [PASSED] Waits for GPU
[12:05:00] [PASSED] Tries to lock straight away
[12:05:00] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[12:05:00] [PASSED] ttm_bo_validate_happy_evict
[12:05:00] [PASSED] ttm_bo_validate_all_pinned_evict
[12:05:00] [PASSED] ttm_bo_validate_allowed_only_evict
[12:05:00] [PASSED] ttm_bo_validate_deleted_evict
[12:05:00] [PASSED] ttm_bo_validate_busy_domain_evict
[12:05:00] [PASSED] ttm_bo_validate_evict_gutting
[12:05:00] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[12:05:00] ================= [PASSED] ttm_bo_validate =================
[12:05:00] ============================================================
[12:05:00] Testing complete. Ran 101 tests: passed: 101
[12:05:00] Elapsed time: 18.849s total, 2.628s configuring, 15.947s building, 0.255s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3558 bytes --]

== Series Details ==

Series: Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM (rev2)
URL   : https://patchwork.freedesktop.org/series/161978/
State : success

== Summary ==

CI Bug Log - changes from xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149_BAT -> xe-pw-161978v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-161978v2_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-bmg-2:          [PASS][1] -> [ABORT][2] ([Intel XE#7249])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html
    - bat-bmg-1:          [PASS][3] -> [DMESG-WARN][4] ([Intel XE#7433]) +1 other test dmesg-warn
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/bat-bmg-1/igt@core_hotunplug@unbind-rebind.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/bat-bmg-1/igt@core_hotunplug@unbind-rebind.html

  * igt@xe_module_load@load:
    - bat-bmg-3:          [PASS][5] -> [DMESG-WARN][6] ([Intel XE#7433])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/bat-bmg-3/igt@xe_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/bat-bmg-3/igt@xe_module_load@load.html
    - bat-bmg-2:          [PASS][7] -> [DMESG-WARN][8] ([Intel XE#7433])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/bat-bmg-2/igt@xe_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/bat-bmg-2/igt@xe_module_load@load.html

  
#### Possible fixes ####

  * igt@xe_waitfence@engine:
    - bat-dg2-oem2:       [FAIL][9] ([Intel XE#6519]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/bat-dg2-oem2/igt@xe_waitfence@engine.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/bat-dg2-oem2/igt@xe_waitfence@engine.html

  * igt@xe_waitfence@reltime:
    - bat-dg2-oem2:       [FAIL][11] ([Intel XE#6520]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/bat-dg2-oem2/igt@xe_waitfence@reltime.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/bat-dg2-oem2/igt@xe_waitfence@reltime.html

  
  [Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519
  [Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520
  [Intel XE#7249]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7249
  [Intel XE#7433]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7433


Build changes
-------------

  * IGT: IGT_8792 -> IGT_8793
  * Linux: xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149 -> xe-pw-161978v2

  IGT_8792: 8792
  IGT_8793: c623172fdd4dd92bb23dbc55b3930c40266c3e59 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149: 9a6bac4a4a289d3ac043f885758d208ccf07f149
  xe-pw-161978v2: 161978v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/index.html

[-- Attachment #2: Type: text/html, Size: 4375 bytes --]

✓ Xe.CI.FULL: success for Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 26200 bytes --]

== Series Details ==

Series: Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM (rev2)
URL   : https://patchwork.freedesktop.org/series/161978/
State : success

== Summary ==

CI Bug Log - changes from xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149_FULL -> xe-pw-161978v2_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-161978v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-lnl:          NOTRUN -> [SKIP][1] ([Intel XE#1407]) +2 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-4/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
    - shard-lnl:          NOTRUN -> [SKIP][2] ([Intel XE#1124]) +3 other tests skip
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-3/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-lnl:          NOTRUN -> [SKIP][3] ([Intel XE#2191] / [Intel XE#7373])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-7/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-3-displays-3840x2160p:
    - shard-lnl:          NOTRUN -> [SKIP][4] ([Intel XE#367] / [Intel XE#7354])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-6/igt@kms_bw@linear-tiling-3-displays-3840x2160p.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][5] ([Intel XE#2887]) +2 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-8/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs@pipe-c-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][6] ([Intel XE#2669] / [Intel XE#7389]) +3 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-5/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs@pipe-c-edp-1.html

  * igt@kms_chamelium_color@gamma:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#306] / [Intel XE#7358])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-3/igt@kms_chamelium_color@gamma.html

  * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#373]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-7/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html

  * igt@kms_content_protection@type1:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#3278] / [Intel XE#6973])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-2/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-offscreen-64x21:
    - shard-lnl:          NOTRUN -> [SKIP][10] ([Intel XE#1424]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-8/igt@kms_cursor_crc@cursor-offscreen-64x21.html

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#309] / [Intel XE#7343]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-8/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#1397] / [Intel XE#7385])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#7178] / [Intel XE#7351])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#7179])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-7/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#6312] / [Intel XE#651]) +4 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-8/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-6/igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#656]) +9 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#6312])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier:
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#7283])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-6/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#2763] / [Intel XE#6886]) +3 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a.html

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          [PASS][22] -> [FAIL][23] ([Intel XE#7340] / [Intel XE#7504])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-lnl-7/igt@kms_pm_dc@dc5-dpms.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-2/igt@kms_pm_dc@dc5-dpms.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-lnl:          [PASS][24] -> [FAIL][25] ([Intel XE#7340]) +1 other test fail
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-lnl-5/igt@kms_pm_dc@dc6-psr.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-5/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#2893] / [Intel XE#7304]) +3 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-7/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr@pr-cursor-plane-move:
    - shard-lnl:          NOTRUN -> [SKIP][27] ([Intel XE#1406]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-1/igt@kms_psr@pr-cursor-plane-move.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-1/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@xe_compute@ccs-mode-compute-kernel:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#1447] / [Intel XE#7469])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-5/igt@xe_compute@ccs-mode-compute-kernel.html

  * igt@xe_evict@evict-beng-mixed-threads-small-multi-vm:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#6540] / [Intel XE#688]) +4 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-4/igt@xe_evict@evict-beng-mixed-threads-small-multi-vm.html

  * igt@xe_exec_balancer@once-cm-parallel-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#7482]) +5 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-6/igt@xe_exec_balancer@once-cm-parallel-rebind.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#1392]) +3 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-6/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][33] ([Intel XE#7136]) +3 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-7/igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind.html

  * igt@xe_exec_multi_queue@max-queues-priority-smem:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#6874]) +10 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-1/igt@xe_exec_multi_queue@max-queues-priority-smem.html

  * igt@xe_exec_sip_eudebug@breakpoint-writesip-twice:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#4837])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-5/igt@xe_exec_sip_eudebug@breakpoint-writesip-twice.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma:
    - shard-lnl:          [PASS][36] -> [FAIL][37] ([Intel XE#5625])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-lnl-1/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-7/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html

  * igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#7138]) +3 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-8/igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr.html

  * igt@xe_peer2peer@read:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#1061] / [Intel XE#7326] / [Intel XE#7353])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-1/igt@xe_peer2peer@read.html

  * igt@xe_pm@d3cold-mocs:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#2284] / [Intel XE#7370])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-8/igt@xe_pm@d3cold-mocs.html

  * igt@xe_query@multigpu-query-topology:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#944])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-3/igt@xe_query@multigpu-query-topology.html

  * igt@xe_sriov_admin@bulk-sched-priority-vfs-disabled:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#7174])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-8/igt@xe_sriov_admin@bulk-sched-priority-vfs-disabled.html

  * igt@xe_sriov_flr@flr-vfs-parallel:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#4273])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-6/igt@xe_sriov_flr@flr-vfs-parallel.html

  
#### Possible fixes ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-linear:
    - shard-lnl:          [FAIL][44] ([Intel XE#5993] / [Intel XE#6054]) -> [PASS][45] +3 other tests pass
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-lnl-7/igt@kms_async_flips@async-flip-with-page-flip-events-linear.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-1/igt@kms_async_flips@async-flip-with-page-flip-events-linear.html

  * igt@kms_async_flips@test-cursor-atomic:
    - shard-lnl:          [SKIP][46] ([Intel XE#7519]) -> [PASS][47] +7 other tests pass
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-lnl-3/igt@kms_async_flips@test-cursor-atomic.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-2/igt@kms_async_flips@test-cursor-atomic.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [FAIL][48] ([Intel XE#2142]) -> [PASS][49] +1 other test pass
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-lnl-8/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-lnl-1/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  
#### Warnings ####

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [SKIP][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75]) ([Intel XE#2457] / [Intel XE#7405]) -> ([DMESG-WARN][76], [DMESG-WARN][77], [DMESG-WARN][78], [DMESG-WARN][79], [DMESG-WARN][80], [DMESG-WARN][81], [DMESG-WARN][82], [DMESG-WARN][83], [DMESG-WARN][84], [DMESG-WARN][85], [DMESG-WARN][86], [DMESG-WARN][87], [DMESG-WARN][88], [DMESG-WARN][89], [DMESG-WARN][90], [DMESG-WARN][91], [DMESG-WARN][92], [DMESG-WARN][93], [DMESG-WARN][94], [DMESG-WARN][95], [DMESG-WARN][96], [DMESG-WARN][97], [DMESG-WARN][98], [DMESG-WARN][99], [DMESG-WARN][100]) ([Intel XE#7433])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-5/igt@xe_module_load@load.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-3/igt@xe_module_load@load.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-1/igt@xe_module_load@load.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-3/igt@xe_module_load@load.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-1/igt@xe_module_load@load.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-7/igt@xe_module_load@load.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-10/igt@xe_module_load@load.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-10/igt@xe_module_load@load.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-4/igt@xe_module_load@load.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-4/igt@xe_module_load@load.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-2/igt@xe_module_load@load.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-2/igt@xe_module_load@load.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-3/igt@xe_module_load@load.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-8/igt@xe_module_load@load.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-8/igt@xe_module_load@load.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-5/igt@xe_module_load@load.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-5/igt@xe_module_load@load.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-9/igt@xe_module_load@load.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-1/igt@xe_module_load@load.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-9/igt@xe_module_load@load.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-6/igt@xe_module_load@load.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-7/igt@xe_module_load@load.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-6/igt@xe_module_load@load.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-2/igt@xe_module_load@load.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-9/igt@xe_module_load@load.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149/shard-bmg-3/igt@xe_module_load@load.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-3/igt@xe_module_load@load.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-3/igt@xe_module_load@load.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-3/igt@xe_module_load@load.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-6/igt@xe_module_load@load.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-6/igt@xe_module_load@load.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-8/igt@xe_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-8/igt@xe_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-8/igt@xe_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-4/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-4/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-4/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-10/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-10/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-1/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-1/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-7/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-7/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-7/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-9/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-9/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-9/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-2/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-2/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-5/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/shard-bmg-5/igt@xe_module_load@load.html

  
  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3278]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3278
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5993]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5993
  [Intel XE#6054]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6054
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6973]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6973
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7174
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7326]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7326
  [Intel XE#7340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7340
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7353]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7353
  [Intel XE#7354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7354
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7373
  [Intel XE#7385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7385
  [Intel XE#7389]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7389
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7433]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7433
  [Intel XE#7469]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7469
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7504
  [Intel XE#7519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7519
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_8792 -> IGT_8793
  * Linux: xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149 -> xe-pw-161978v2

  IGT_8792: 8792
  IGT_8793: c623172fdd4dd92bb23dbc55b3930c40266c3e59 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4698-9a6bac4a4a289d3ac043f885758d208ccf07f149: 9a6bac4a4a289d3ac043f885758d208ccf07f149
  xe-pw-161978v2: 161978v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v2/index.html

[-- Attachment #2: Type: text/html, Size: 28147 bytes --]

Re: [PATCH 01/19] drm/dp: Rename and relocate AS SDP payload field masks

[Ville Syrjälä]

On Wed, Mar 11, 2026 at 05:05:53PM +0530, Ankit Nautiyal wrote:
> The AS SDP payload field masks were misnamed and placed under the DPRX
> feature enumeration list. These are not DPRX capability bits, but are
> payload field masks for the Adaptive Sync SDP.
> 
> Relocate both masks next to the AS SDP definitions.
> Update users to the corrected names. No functional change.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
>  include/drm/display/drm_dp.h            | 5 +++--
>  2 files changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index fbb5e2f9c241..cd1539c3268c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5295,8 +5295,8 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
>  	if ((sdp->sdp_header.HB3 & 0x3F) != 9)
>  		return -EINVAL;
>  
> -	as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
> -	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
> +	as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK;
> +	as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK;
>  	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
>  	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
>  	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 8b15d3eeb716..4ea3b5b08a12 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -1204,8 +1204,6 @@
>  
>  #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1         0x2214 /* 2.0 E11 */
>  # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED    (1 << 0)
> -# define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE		GENMASK(1, 0)
> -# define DP_ADAPTIVE_SYNC_SDP_LENGTH				GENMASK(5, 0)
>  # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)
>  # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED  (1 << 4)
>  
> @@ -1870,4 +1868,7 @@ enum operation_mode {
>  	DP_AS_SDP_FAVT_TRR_REACHED = 0x03
>  };
>  
> +#define DP_AS_SDP_OPERATION_MODE_MASK	GENMASK(1, 0)
> +#define DP_AS_SDP_LENGTH_MASK		GENMASK(5, 0)

The way all the SDP stuff is organized in drm_dp.h very messy.
It's not at all clear which bytes each define/enum corresponds
to. Someone should try to clean it all up properly...

But at least this is better than what we have now, so
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +
>  #endif /* _DRM_DP_H_ */
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 02/19] drm/dp: Clean up DPRX feature enumeration macros

[Ville Syrjälä]

On Wed, Mar 11, 2026 at 05:05:54PM +0530, Ankit Nautiyal wrote:
> Align the DP_DPRX feature enumeration macros for better readability and
> consistency, and use the BIT() macro instead of open-coded shifts.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

If we really want to go for BIT() someone should do a full pass
over the whole file...

In the meantime
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  include/drm/display/drm_dp.h | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 4ea3b5b08a12..49f0154eb93c 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -1202,10 +1202,10 @@
>  # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_80_MS	0x04
>  # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_100_MS	0x05
>  
> -#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1         0x2214 /* 2.0 E11 */
> -# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED    (1 << 0)
> -# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)
> -# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED  (1 << 4)
> +#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1					0x2214 /* 2.0 E11 */
> +# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED						BIT(0)
> +# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED	BIT(1)
> +# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED				BIT(4)
>  
>  #define DP_128B132B_SUPPORTED_LINK_RATES       0x2215 /* 2.0 */
>  # define DP_UHBR10                             (1 << 0)
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 03/19] drm/dp: Add bits for AS SDP FAVT Payload Fields Parsing support

[Ville Syrjälä]

On Wed, Mar 11, 2026 at 05:05:55PM +0530, Ankit Nautiyal wrote:
> DP v2.1 introduced support for sending AS SDP payload bytes for FAVT.
> Add the relavant bits for the same.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  include/drm/display/drm_dp.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 49f0154eb93c..8d172863eba3 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -1205,6 +1205,7 @@
>  #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1					0x2214 /* 2.0 E11 */
>  # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED						BIT(0)
>  # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED	BIT(1)
> +# define DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED			BIT(2) /* 2.1 */

I wonder if this is what we should use to detect AS SDP v2 support?
The rule is that we can't send AS SDP v2 unless the sink is DP-2.1
or eDP-1.5.

eDP-1.5 we can supposedly identify from EDP_DPCD_REV (or EDP_REV
as it's now called in eDP-1.5+), but AFAIK there is no real way
to identify a DP-2.1 sink :/

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED				BIT(4)
>  
>  #define DP_128B132B_SUPPORTED_LINK_RATES       0x2215 /* 2.0 */
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 04/19] drm/dp: Add DPCD for configuring AS SDP for PR + VRR

[Ville Syrjälä]

On Wed, Mar 11, 2026 at 05:05:56PM +0530, Ankit Nautiyal wrote:
> Add additional DPCDs required to be configured to support VRR with Panel
> Replay. These DPCDs are specifically required for configuring Adaptive Sync
> SDP and are introduced in DP v2.1.
> 
> v2:
>  - Correct the shift for the bits. (Ville)
>  - Add DP_PR_ prefix for the PR-related fields.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  include/drm/display/drm_dp.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 8d172863eba3..e6752a92d5dc 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -775,6 +775,15 @@
>  # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK  (0xf << 3)
>  # define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE		 (1 << 7)
>  
> +#define PANEL_REPLAY_CONFIG3				0x11a /* DP 2.1 */
> +# define DP_PR_AS_SDP_SETUP_TIME_SHIFT			6
> +# define DP_PR_AS_SDP_SETUP_TIME_MASK			(3 << DP_PR_AS_SDP_SETUP_TIME_SHIFT)
> +# define DP_PR_AS_SDP_SETUP_TIME_T1			0
> +# define DP_PR_AS_SDP_SETUP_TIME_DYNAMIC		1 /* DP 2.1 Table 2-227 */
> +# define DP_PR_AS_SDP_SETUP_TIME_T2			2

The usual rule in drm_dp.h seems to be to define the values
as already shifted.

> +# define DP_PR_AS_SDP_SETUP_TIME(t)			(((t) << DP_PR_AS_SDP_SETUP_TIME_SHIFT) & \
> +							 DP_PR_AS_SDP_SETUP_TIME_MASK)
> +
>  #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
>  #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
>  #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 10/19] drm/i915/dp: Use revision field of AS SDP data structure

[Ville Syrjälä]

On Wed, Mar 11, 2026 at 05:06:02PM +0530, Ankit Nautiyal wrote:
> Use the revision field of struct drm_dp_as_sdp instead of current
> hardcoding for the AS SDP revisions.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
>  drivers/gpu/drm/i915/display/intel_dp.c      | 7 +++----
>  2 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b18ce0c36a64..88e1b503d301 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4900,7 +4900,8 @@ static bool
>  intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
>  			const struct drm_dp_as_sdp *b)
>  {
> -	return a->vtotal == b->vtotal &&
> +	return a->revision == b->revision &&

Someone should add the check for the type and length as well
(and other relevant stuff in the header if any). But that
can be a separate patch.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +		a->vtotal == b->vtotal &&
>  		a->target_rr == b->target_rr &&
>  		a->duration_incr_ms == b->duration_incr_ms &&
>  		a->duration_decr_ms == b->duration_decr_ms &&
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 17af68a1a9e5..0d2403d48528 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3154,6 +3154,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>  	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
>  	as_sdp->length = 0x9;
>  	as_sdp->duration_incr_ms = 0;
> +	as_sdp->revision = 0x2;
>  	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
>  
>  	if (crtc_state->cmrr.enable) {
> @@ -5117,7 +5118,7 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
>  	/* Prepare AS (Adaptive Sync) SDP Header */
>  	sdp->sdp_header.HB0 = 0;
>  	sdp->sdp_header.HB1 = as_sdp->sdp_type;
> -	sdp->sdp_header.HB2 = 0x02;
> +	sdp->sdp_header.HB2 = as_sdp->revision;
>  	sdp->sdp_header.HB3 = as_sdp->length;
>  
>  	/* Fill AS (Adaptive Sync) SDP Payload */
> @@ -5304,13 +5305,11 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
>  	if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
>  		return -EINVAL;
>  
> -	if (sdp->sdp_header.HB2 != 0x02)
> -		return -EINVAL;
> -
>  	if ((sdp->sdp_header.HB3 & 0x3F) != 9)
>  		return -EINVAL;
>  
>  	as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK;
> +	as_sdp->revision = sdp->sdp_header.HB2;
>  	as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK;
>  	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
>  	as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 11/19] drm/i915/dp: Add member to intel_dp to store AS SDP v2 support

[Ville Syrjälä]

On Wed, Mar 11, 2026 at 05:06:03PM +0530, Ankit Nautiyal wrote:
> DP v2.1 mentions support for FAVT payload fields parsing in DPCD 0x2214
> Bit 2. This essentially signals the support for AS SDP version 2, that
> allows source to set the version in HB2[4:0] and the payload length in
> HB3[5:0] of the AS SDP header.
> 
> Read this bit and store the AS SDP v2 capability in intel_dp.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 21 +++++++++++++++++++
>  2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e189f8c39ccb..d783cea06aed 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1870,6 +1870,7 @@ struct intel_dp {
>  	/* connector directly attached - won't be use for modeset in mst world */
>  	struct intel_connector *attached_connector;
>  	bool as_sdp_supported;
> +	bool as_sdp_v2_supported;
>  
>  	struct drm_dp_tunnel *tunnel;
>  	bool tunnel_suspended:1;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0d2403d48528..e6148e7f0ebc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6291,6 +6291,24 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
>  					       false);
>  }
>  
> +static bool
> +intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	u8 rx_features;
> +
> +	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
> +				  DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
> +				  &rx_features) < 0) {
> +		drm_dbg_kms(display->drm,
> +			    "Failed to read DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1\n");
> +
> +		return false;
> +	}
> +
> +	return rx_features & DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED;

Hmm. So the name seems to imply it's only about the FAVT stuff.
But even when running in AVT mode some of the payload bytes
can still be valid. Dunno how much the other stuff actually matters
for VRR itself, but I think for PR the coasting vtotal would at
least be important if we don't send AS SDP while in PR active
state.

The problematic case would be if we have to send the AS SDP
for VRR purposes, but want to suspend it during PR active
for power savings, assuming the sink has the
!ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR capability.

So I suppose we might want to also check for PR+ALPM here,
in case some of those don't also set the
DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED bit.

Sadly there doesn't seem to be a proper AS SDP v2 supported
bit anywhere. We just have to guess based on other capabilities :(

> +}
> +
>  static void
>  intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
>  {
> @@ -6298,6 +6316,9 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
>  
>  	intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
>  		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
> +
> +	intel_dp->as_sdp_v2_supported = intel_dp->as_sdp_supported &&
> +					intel_dp_sink_supports_as_sdp_v2(intel_dp);
>  }
>  
>  static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 12/19] drm/i915/psr: Write the PR config DPCDs in burst mode

[Ville Syrjälä]

On Wed, Mar 11, 2026 at 05:06:04PM +0530, Ankit Nautiyal wrote:
> Replace the consecutive single-byte writes to PANEL_REPLAY_CONFIG and
> CONFIG2 with one drm_dp_dpcd_write() burst starting at PANEL_REPLAY_CONFIG,
> reducing AUX transactions.
> 
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 18 ++++++++++++------
>  1 file changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 5041a5a138d1..ee6e26abd05e 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -774,27 +774,33 @@ static bool psr2_su_region_et_valid(struct intel_connector *connector, bool pane
>  static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
>  				      const struct intel_crtc_state *crtc_state)
>  {
> -	u8 val = DP_PANEL_REPLAY_ENABLE |
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	u8 panel_replay_config = DP_PANEL_REPLAY_ENABLE |
>  		DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
>  		DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
>  		DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
>  		DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
>  	u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;
> +	u8 buf[2];

u8 panel_replay_config[2];

would reduce the number of variables we have to contend with.

> +	int ret;
>  
>  	if (crtc_state->has_sel_update)
> -		val |= DP_PANEL_REPLAY_SU_ENABLE;
> +		panel_replay_config |= DP_PANEL_REPLAY_SU_ENABLE;
>  
>  	if (crtc_state->enable_psr2_su_region_et)
> -		val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
> +		panel_replay_config |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
>  
>  	if (crtc_state->req_psr2_sdp_prior_scanline)
>  		panel_replay_config2 |=
>  			DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE;
>  
> -	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val);
> +	buf[0] = panel_replay_config;
> +	buf[1] = panel_replay_config2;
> +
> +	ret = drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG, buf, sizeof(buf));
>  
> -	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,
> -			   panel_replay_config2);
> +	if (ret < 0 || ret != sizeof(buf))

The < 0 check is redunadnt.

> +		drm_dbg_kms(display->drm, "Failed to write Panel Replay Configs\n");
>  }
>  
>  static void _psr_enable_sink(struct intel_dp *intel_dp,
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 13/19] drm/i915/display: Add helper for AS SDP transmission time selection

[Ville Syrjälä]

On Wed, Mar 11, 2026 at 05:06:05PM +0530, Ankit Nautiyal wrote:
> AS SDP may be transmitted at T1 or T2 depending on Panel Replay and
> Adaptive Sync SDP configuration as per DP 2.1. Current we are using
> T1 only, but future PR/AS SDP modes/features may require T2 or dynamic
> selection.
> 
> Introduce a helper to return the appropriate AS SDP transmission time so
> that a single value is consistently used for programming PR_ALPM.
> For now this returns T1.
> 
> v2: Avoid adding new member to crtc_state; use a helper. (Ville)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 20 +++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_dp.c   |  9 +++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h   |  2 ++
>  3 files changed, 30 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index a7350ce8e716..0a6da3f926d3 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -11,6 +11,7 @@
>  #include "intel_crtc.h"
>  #include "intel_de.h"
>  #include "intel_display_types.h"
> +#include "intel_display_utils.h"
>  #include "intel_dp.h"
>  #include "intel_dp_aux.h"
>  #include "intel_psr.h"
> @@ -359,6 +360,23 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
>  	crtc_state->has_lobf = true;
>  }
>  
> +static int get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *crtc_state)

The type should be u32 since it returns a (partial) register value.

> +{
> +	int as_sdp_setup_time = intel_dp_as_sdp_transmission_time();
> +
> +	switch (as_sdp_setup_time) {
> +	case DP_PR_AS_SDP_SETUP_TIME_T1:
> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
> +	case DP_PR_AS_SDP_SETUP_TIME_DYNAMIC:
> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2;
> +	case DP_PR_AS_SDP_SETUP_TIME_T2:
> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2;
> +	default:
> +		MISSING_CASE(as_sdp_setup_time);
> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
> +	}
> +}
> +
>  static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  			       const struct intel_crtc_state *crtc_state)
>  {
> @@ -382,7 +400,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
>  
>  		if (intel_dp->as_sdp_supported) {
> -			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
> +			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
>  
>  			if (crtc_state->link_off_after_as_sdp_when_pr_active)
>  				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index e6148e7f0ebc..74a8af3cf18c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7439,3 +7439,12 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>  
>  	return true;
>  }
> +
> +int intel_dp_as_sdp_transmission_time(void)
> +{
> +	/*
> +	 * For now we use T1 as the transmission time.
> +	 * This can be later changed as per requirements.
> +	 */

IIRC Bspec actually says we must use T1.

> +	return DP_PR_AS_SDP_SETUP_TIME_T1;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 2849b9ecdc71..2e4609d9d05c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -238,4 +238,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>  	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>  		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
>  
> +int intel_dp_as_sdp_transmission_time(void);
> +
>  #endif /* __INTEL_DP_H__ */
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 16/19] drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off

[Ville Syrjälä]

On Wed, Mar 11, 2026 at 05:06:08PM +0530, Ankit Nautiyal wrote:
> For Panel Replay with AUX-less ALPM (link-off PR), the source must send
> Adaptive-Sync SDP v2. Program DB[1:0] per DP spec v2.1:
> - VRR AVT: 00b (variable VTotal)
> - VRR FAVT: 10b/11b (TRR not reached/reached)
> - Fixed timing with PR link-off (VRR off): 01b (AS disabled; VTotal fixed)
> 
> Also, drop the redundant target_rr assignment.
> 
> v2: Fix the else case. (Ville)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 74a8af3cf18c..2b0318e0ceb0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3161,9 +3161,10 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>  		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
>  		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
>  		as_sdp->target_rr_divider = true;
> -	} else {
> +	} else if (crtc_state->vrr.enable) {

Due to the lack of fastset for this we pretty much need a
s/crtc_state->vrr.enable/vrr_possible()/ pass over everything.

But for now this is at least more correct than the current thing, so
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
> -		as_sdp->target_rr = 0;
> +	} else {
> +		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
>  	}
>  }
>  
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 18/19] drm/i915/dp: Make provision for AS SDP version 1

[Ville Syrjälä]

On Wed, Mar 11, 2026 at 05:06:10PM +0530, Ankit Nautiyal wrote:
> Currently we are setting AS SDP version to 2 without checking if the sink
> supports it or whether we need to send version 1.
> 
> For PR with Link ON, the AS SDP version V1 is used.
> When using AS SDP Version 1, AS SDP payload and parity bytes
> are all set to zeroes.
> 
> Add a helper to compute the AS SDP version based on sink support and
> feature requirement.
> 
> If AS SDP V2 is supported we use V2, unless Panel Replay with Link On is
> enabled, for which we use V1.
> If AS SDP V1 is not supported, we always send V1, without the payload.
> 
> Bspec: 75639
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 24 +++++++++++++++++++++++-
>  1 file changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4d0a7695be5a..6b45894e40e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5109,6 +5109,10 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
>  	sdp->sdp_header.HB2 = as_sdp->revision;
>  	sdp->sdp_header.HB3 = as_sdp->length;
>  
> +	/* No Payload Data bytes for Version 1 */
> +	if (as_sdp->revision == 0x1)
> +		return length;
> +
>  	/* Fill AS (Adaptive Sync) SDP Payload */
>  	sdp->db[0] = as_sdp->mode;
>  	sdp->db[1] = as_sdp->vtotal & 0xFF;
> @@ -7330,6 +7334,19 @@ void intel_dp_mst_resume(struct intel_display *display)
>  	}
>  }
>  
> +static bool intel_dp_get_as_sdp_revision(struct intel_dp *intel_dp,
> +					 struct intel_crtc_state *crtc_state)
> +{
> +	if (crtc_state->has_panel_replay &&
> +	    !intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
> +		return 1;

The bogus v1 in PR link ON requirement got nuked from bspec.

> +
> +	if (intel_dp->as_sdp_v2_supported)
> +		return 2;
> +
> +	return 1;
> +}
> +
>  static
>  void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
>  					 struct intel_crtc_state *crtc_state)
> @@ -7345,7 +7362,12 @@ void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
>  	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
>  	as_sdp->length = 0x9;
>  	as_sdp->duration_incr_ms = 0;
> -	as_sdp->revision = 0x2;
> +	as_sdp->revision = intel_dp_get_as_sdp_revision(intel_dp, crtc_state);
> +
> +	/* No payload data bytes for Version 1 */
> +	if (as_sdp->revision == 1)
> +		return;
> +
>  	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
>  
>  	if (crtc_state->cmrr.enable) {
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 02/19] drm/dp: Clean up DPRX feature enumeration macros

[Jani Nikula]

On Fri, 13 Mar 2026, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Mar 11, 2026 at 05:05:54PM +0530, Ankit Nautiyal wrote:
>> Align the DP_DPRX feature enumeration macros for better readability and
>> consistency, and use the BIT() macro instead of open-coded shifts.
>> 
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
> If we really want to go for BIT() someone should do a full pass
> over the whole file...

Should also use BIT_U8() and GENMASK_U8().

>
> In the meantime
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>> ---
>>  include/drm/display/drm_dp.h | 8 ++++----
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>> 
>> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
>> index 4ea3b5b08a12..49f0154eb93c 100644
>> --- a/include/drm/display/drm_dp.h
>> +++ b/include/drm/display/drm_dp.h
>> @@ -1202,10 +1202,10 @@
>>  # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_80_MS	0x04
>>  # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_100_MS	0x05
>>  
>> -#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1         0x2214 /* 2.0 E11 */
>> -# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED    (1 << 0)
>> -# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)
>> -# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED  (1 << 4)
>> +#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1					0x2214 /* 2.0 E11 */
>> +# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED						BIT(0)
>> +# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED	BIT(1)
>> +# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED				BIT(4)
>>  
>>  #define DP_128B132B_SUPPORTED_LINK_RATES       0x2215 /* 2.0 */
>>  # define DP_UHBR10                             (1 << 0)
>> -- 
>> 2.45.2

-- 
Jani Nikula, Intel

Re: [PATCH 02/19] drm/dp: Clean up DPRX feature enumeration macros

[Nautiyal, Ankit K]

On 3/17/2026 9:35 PM, Jani Nikula wrote:
> On Fri, 13 Mar 2026, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>> On Wed, Mar 11, 2026 at 05:05:54PM +0530, Ankit Nautiyal wrote:
>>> Align the DP_DPRX feature enumeration macros for better readability and
>>> consistency, and use the BIT() macro instead of open-coded shifts.
>>>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> If we really want to go for BIT() someone should do a full pass
>> over the whole file...
> Should also use BIT_U8() and GENMASK_U8().


Thanks for the review and the suggestions.

Agreed that a proper conversion to BIT(), BIT_U8(), and GENMASK_U8()
should really be done consistently across the whole file. That would
be a larger cleanup and probably deserves a separate patch/series.

For this change I’ve kept the scope intentionally minimal and focused
only on the touched definitions.

Thanks again for the review.


Regards,

Ankit

>
>> In the meantime
>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>>> ---
>>>   include/drm/display/drm_dp.h | 8 ++++----
>>>   1 file changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
>>> index 4ea3b5b08a12..49f0154eb93c 100644
>>> --- a/include/drm/display/drm_dp.h
>>> +++ b/include/drm/display/drm_dp.h
>>> @@ -1202,10 +1202,10 @@
>>>   # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_80_MS	0x04
>>>   # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_100_MS	0x05
>>>   
>>> -#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1         0x2214 /* 2.0 E11 */
>>> -# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED    (1 << 0)
>>> -# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)
>>> -# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED  (1 << 4)
>>> +#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1					0x2214 /* 2.0 E11 */
>>> +# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED						BIT(0)
>>> +# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED	BIT(1)
>>> +# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED				BIT(4)
>>>   
>>>   #define DP_128B132B_SUPPORTED_LINK_RATES       0x2215 /* 2.0 */
>>>   # define DP_UHBR10                             (1 << 0)
>>> -- 
>>> 2.45.2

Re: [PATCH 04/19] drm/dp: Add DPCD for configuring AS SDP for PR + VRR

[Nautiyal, Ankit K]

On 3/13/2026 5:22 PM, Ville Syrjälä wrote:
> On Wed, Mar 11, 2026 at 05:05:56PM +0530, Ankit Nautiyal wrote:
>> Add additional DPCDs required to be configured to support VRR with Panel
>> Replay. These DPCDs are specifically required for configuring Adaptive Sync
>> SDP and are introduced in DP v2.1.
>>
>> v2:
>>   - Correct the shift for the bits. (Ville)
>>   - Add DP_PR_ prefix for the PR-related fields.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   include/drm/display/drm_dp.h | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
>> index 8d172863eba3..e6752a92d5dc 100644
>> --- a/include/drm/display/drm_dp.h
>> +++ b/include/drm/display/drm_dp.h
>> @@ -775,6 +775,15 @@
>>   # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK  (0xf << 3)
>>   # define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE		 (1 << 7)
>>   
>> +#define PANEL_REPLAY_CONFIG3				0x11a /* DP 2.1 */
>> +# define DP_PR_AS_SDP_SETUP_TIME_SHIFT			6
>> +# define DP_PR_AS_SDP_SETUP_TIME_MASK			(3 << DP_PR_AS_SDP_SETUP_TIME_SHIFT)
>> +# define DP_PR_AS_SDP_SETUP_TIME_T1			0
>> +# define DP_PR_AS_SDP_SETUP_TIME_DYNAMIC		1 /* DP 2.1 Table 2-227 */
>> +# define DP_PR_AS_SDP_SETUP_TIME_T2			2
> The usual rule in drm_dp.h seems to be to define the values
> as already shifted.


Hmm.. I think I wanted to represent the 3 setup time config with 0, 1 ,2 
which I am using later in switch case.

But to be consistent with the file, I will define the values as already 
shifted, we can still use them in switch case I suppose.


Regards,

Ankit


>
>> +# define DP_PR_AS_SDP_SETUP_TIME(t)			(((t) << DP_PR_AS_SDP_SETUP_TIME_SHIFT) & \
>> +							 DP_PR_AS_SDP_SETUP_TIME_MASK)
>> +
>>   #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
>>   #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
>>   #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
>> -- 
>> 2.45.2

Re: [PATCH 10/19] drm/i915/dp: Use revision field of AS SDP data structure

[Nautiyal, Ankit K]

On 3/13/2026 5:25 PM, Ville Syrjälä wrote:
> On Wed, Mar 11, 2026 at 05:06:02PM +0530, Ankit Nautiyal wrote:
>> Use the revision field of struct drm_dp_as_sdp instead of current
>> hardcoding for the AS SDP revisions.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
>>   drivers/gpu/drm/i915/display/intel_dp.c      | 7 +++----
>>   2 files changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index b18ce0c36a64..88e1b503d301 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -4900,7 +4900,8 @@ static bool
>>   intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
>>   			const struct drm_dp_as_sdp *b)
>>   {
>> -	return a->vtotal == b->vtotal &&
>> +	return a->revision == b->revision &&
> Someone should add the check for the type and length as well
> (and other relevant stuff in the header if any). But that
> can be a separate patch.


Agreed. I will make a separate patch for this.

Regards,
Ankit

>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>> +		a->vtotal == b->vtotal &&
>>   		a->target_rr == b->target_rr &&
>>   		a->duration_incr_ms == b->duration_incr_ms &&
>>   		a->duration_decr_ms == b->duration_decr_ms &&
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 17af68a1a9e5..0d2403d48528 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -3154,6 +3154,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>>   	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
>>   	as_sdp->length = 0x9;
>>   	as_sdp->duration_incr_ms = 0;
>> +	as_sdp->revision = 0x2;
>>   	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
>>   
>>   	if (crtc_state->cmrr.enable) {
>> @@ -5117,7 +5118,7 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
>>   	/* Prepare AS (Adaptive Sync) SDP Header */
>>   	sdp->sdp_header.HB0 = 0;
>>   	sdp->sdp_header.HB1 = as_sdp->sdp_type;
>> -	sdp->sdp_header.HB2 = 0x02;
>> +	sdp->sdp_header.HB2 = as_sdp->revision;
>>   	sdp->sdp_header.HB3 = as_sdp->length;
>>   
>>   	/* Fill AS (Adaptive Sync) SDP Payload */
>> @@ -5304,13 +5305,11 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
>>   	if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
>>   		return -EINVAL;
>>   
>> -	if (sdp->sdp_header.HB2 != 0x02)
>> -		return -EINVAL;
>> -
>>   	if ((sdp->sdp_header.HB3 & 0x3F) != 9)
>>   		return -EINVAL;
>>   
>>   	as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK;
>> +	as_sdp->revision = sdp->sdp_header.HB2;
>>   	as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK;
>>   	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
>>   	as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
>> -- 
>> 2.45.2

Re: [PATCH 11/19] drm/i915/dp: Add member to intel_dp to store AS SDP v2 support

[Nautiyal, Ankit K]

On 3/13/2026 6:01 PM, Ville Syrjälä wrote:
> On Wed, Mar 11, 2026 at 05:06:03PM +0530, Ankit Nautiyal wrote:
>> DP v2.1 mentions support for FAVT payload fields parsing in DPCD 0x2214
>> Bit 2. This essentially signals the support for AS SDP version 2, that
>> allows source to set the version in HB2[4:0] and the payload length in
>> HB3[5:0] of the AS SDP header.
>>
>> Read this bit and store the AS SDP v2 capability in intel_dp.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   .../drm/i915/display/intel_display_types.h    |  1 +
>>   drivers/gpu/drm/i915/display/intel_dp.c       | 21 +++++++++++++++++++
>>   2 files changed, 22 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index e189f8c39ccb..d783cea06aed 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1870,6 +1870,7 @@ struct intel_dp {
>>   	/* connector directly attached - won't be use for modeset in mst world */
>>   	struct intel_connector *attached_connector;
>>   	bool as_sdp_supported;
>> +	bool as_sdp_v2_supported;
>>   
>>   	struct drm_dp_tunnel *tunnel;
>>   	bool tunnel_suspended:1;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 0d2403d48528..e6148e7f0ebc 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -6291,6 +6291,24 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
>>   					       false);
>>   }
>>   
>> +static bool
>> +intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp)
>> +{
>> +	struct intel_display *display = to_intel_display(intel_dp);
>> +	u8 rx_features;
>> +
>> +	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
>> +				  DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
>> +				  &rx_features) < 0) {
>> +		drm_dbg_kms(display->drm,
>> +			    "Failed to read DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1\n");
>> +
>> +		return false;
>> +	}
>> +
>> +	return rx_features & DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED;
> Hmm. So the name seems to imply it's only about the FAVT stuff.
> But even when running in AVT mode some of the payload bytes
> can still be valid. Dunno how much the other stuff actually matters
> for VRR itself, but I think for PR the coasting vtotal would at
> least be important if we don't send AS SDP while in PR active
> state.
>
> The problematic case would be if we have to send the AS SDP
> for VRR purposes, but want to suspend it during PR active
> for power savings, assuming the sink has the
> !ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR capability.
>
> So I suppose we might want to also check for PR+ALPM here,
> in case some of those don't also set the
> DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED bit.


Thanks for pointing it out. I will have a look and consider these bits 
as well.

As you have rightly said, we are just guessing based on what is 
implicitly implied in the description and behaviour of these bits.

Regards,

Ankit


>
> Sadly there doesn't seem to be a proper AS SDP v2 supported
> bit anywhere. We just have to guess based on other capabilities :(
>
>> +}
>> +
>>   static void
>>   intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
>>   {
>> @@ -6298,6 +6316,9 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
>>   
>>   	intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
>>   		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
>> +
>> +	intel_dp->as_sdp_v2_supported = intel_dp->as_sdp_supported &&
>> +					intel_dp_sink_supports_as_sdp_v2(intel_dp);
>>   }
>>   
>>   static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)
>> -- 
>> 2.45.2

Re: [PATCH 12/19] drm/i915/psr: Write the PR config DPCDs in burst mode

[Nautiyal, Ankit K]

On 3/13/2026 6:04 PM, Ville Syrjälä wrote:
> On Wed, Mar 11, 2026 at 05:06:04PM +0530, Ankit Nautiyal wrote:
>> Replace the consecutive single-byte writes to PANEL_REPLAY_CONFIG and
>> CONFIG2 with one drm_dp_dpcd_write() burst starting at PANEL_REPLAY_CONFIG,
>> reducing AUX transactions.
>>
>> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_psr.c | 18 ++++++++++++------
>>   1 file changed, 12 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 5041a5a138d1..ee6e26abd05e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -774,27 +774,33 @@ static bool psr2_su_region_et_valid(struct intel_connector *connector, bool pane
>>   static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
>>   				      const struct intel_crtc_state *crtc_state)
>>   {
>> -	u8 val = DP_PANEL_REPLAY_ENABLE |
>> +	struct intel_display *display = to_intel_display(intel_dp);
>> +	u8 panel_replay_config = DP_PANEL_REPLAY_ENABLE |
>>   		DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
>>   		DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
>>   		DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
>>   		DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
>>   	u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;
>> +	u8 buf[2];
> u8 panel_replay_config[2];
>
> would reduce the number of variables we have to contend with.


Makes sense. I will change as suggested in the next version.


>
>> +	int ret;
>>   
>>   	if (crtc_state->has_sel_update)
>> -		val |= DP_PANEL_REPLAY_SU_ENABLE;
>> +		panel_replay_config |= DP_PANEL_REPLAY_SU_ENABLE;
>>   
>>   	if (crtc_state->enable_psr2_su_region_et)
>> -		val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
>> +		panel_replay_config |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
>>   
>>   	if (crtc_state->req_psr2_sdp_prior_scanline)
>>   		panel_replay_config2 |=
>>   			DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE;
>>   
>> -	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val);
>> +	buf[0] = panel_replay_config;
>> +	buf[1] = panel_replay_config2;
>> +
>> +	ret = drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG, buf, sizeof(buf));
>>   
>> -	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,
>> -			   panel_replay_config2);
>> +	if (ret < 0 || ret != sizeof(buf))
> The < 0 check is redunadnt.

You are right, the other condition is sufficient. I will drop the 
redundant check.

Regards,
Ankit


>
>> +		drm_dbg_kms(display->drm, "Failed to write Panel Replay Configs\n");
>>   }
>>   
>>   static void _psr_enable_sink(struct intel_dp *intel_dp,
>> -- 
>> 2.45.2

Re: [PATCH 13/19] drm/i915/display: Add helper for AS SDP transmission time selection

[Nautiyal, Ankit K]

On 3/13/2026 6:06 PM, Ville Syrjälä wrote:
> On Wed, Mar 11, 2026 at 05:06:05PM +0530, Ankit Nautiyal wrote:
>> AS SDP may be transmitted at T1 or T2 depending on Panel Replay and
>> Adaptive Sync SDP configuration as per DP 2.1. Current we are using
>> T1 only, but future PR/AS SDP modes/features may require T2 or dynamic
>> selection.
>>
>> Introduce a helper to return the appropriate AS SDP transmission time so
>> that a single value is consistently used for programming PR_ALPM.
>> For now this returns T1.
>>
>> v2: Avoid adding new member to crtc_state; use a helper. (Ville)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_alpm.c | 20 +++++++++++++++++++-
>>   drivers/gpu/drm/i915/display/intel_dp.c   |  9 +++++++++
>>   drivers/gpu/drm/i915/display/intel_dp.h   |  2 ++
>>   3 files changed, 30 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
>> index a7350ce8e716..0a6da3f926d3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
>> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
>> @@ -11,6 +11,7 @@
>>   #include "intel_crtc.h"
>>   #include "intel_de.h"
>>   #include "intel_display_types.h"
>> +#include "intel_display_utils.h"
>>   #include "intel_dp.h"
>>   #include "intel_dp_aux.h"
>>   #include "intel_psr.h"
>> @@ -359,6 +360,23 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
>>   	crtc_state->has_lobf = true;
>>   }
>>   
>> +static int get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *crtc_state)
> The type should be u32 since it returns a (partial) register value.

Ohh yes. I will change this.


>
>> +{
>> +	int as_sdp_setup_time = intel_dp_as_sdp_transmission_time();
>> +
>> +	switch (as_sdp_setup_time) {
>> +	case DP_PR_AS_SDP_SETUP_TIME_T1:
>> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
>> +	case DP_PR_AS_SDP_SETUP_TIME_DYNAMIC:
>> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2;
>> +	case DP_PR_AS_SDP_SETUP_TIME_T2:
>> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2;
>> +	default:
>> +		MISSING_CASE(as_sdp_setup_time);
>> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
>> +	}
>> +}
>> +
>>   static void lnl_alpm_configure(struct intel_dp *intel_dp,
>>   			       const struct intel_crtc_state *crtc_state)
>>   {
>> @@ -382,7 +400,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>>   			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
>>   
>>   		if (intel_dp->as_sdp_supported) {
>> -			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
>> +			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
>>   
>>   			if (crtc_state->link_off_after_as_sdp_when_pr_active)
>>   				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index e6148e7f0ebc..74a8af3cf18c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -7439,3 +7439,12 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>>   
>>   	return true;
>>   }
>> +
>> +int intel_dp_as_sdp_transmission_time(void)
>> +{
>> +	/*
>> +	 * For now we use T1 as the transmission time.
>> +	 * This can be later changed as per requirements.
>> +	 */
> IIRC Bspec actually says we must use T1.


Hmm.. I will check with Bspec and update the relavent Bspec number too.

Regards,
Ankit


>
>> +	return DP_PR_AS_SDP_SETUP_TIME_T1;
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> index 2849b9ecdc71..2e4609d9d05c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -238,4 +238,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>>   	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>>   		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
>>   
>> +int intel_dp_as_sdp_transmission_time(void);
>> +
>>   #endif /* __INTEL_DP_H__ */
>> -- 
>> 2.45.2

Re: [PATCH 18/19] drm/i915/dp: Make provision for AS SDP version 1

[Nautiyal, Ankit K]

On 3/13/2026 6:12 PM, Ville Syrjälä wrote:
> On Wed, Mar 11, 2026 at 05:06:10PM +0530, Ankit Nautiyal wrote:
>> Currently we are setting AS SDP version to 2 without checking if the sink
>> supports it or whether we need to send version 1.
>>
>> For PR with Link ON, the AS SDP version V1 is used.
>> When using AS SDP Version 1, AS SDP payload and parity bytes
>> are all set to zeroes.
>>
>> Add a helper to compute the AS SDP version based on sink support and
>> feature requirement.
>>
>> If AS SDP V2 is supported we use V2, unless Panel Replay with Link On is
>> enabled, for which we use V1.
>> If AS SDP V1 is not supported, we always send V1, without the payload.
>>
>> Bspec: 75639
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 24 +++++++++++++++++++++++-
>>   1 file changed, 23 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 4d0a7695be5a..6b45894e40e0 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -5109,6 +5109,10 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
>>   	sdp->sdp_header.HB2 = as_sdp->revision;
>>   	sdp->sdp_header.HB3 = as_sdp->length;
>>   
>> +	/* No Payload Data bytes for Version 1 */
>> +	if (as_sdp->revision == 0x1)
>> +		return length;
>> +
>>   	/* Fill AS (Adaptive Sync) SDP Payload */
>>   	sdp->db[0] = as_sdp->mode;
>>   	sdp->db[1] = as_sdp->vtotal & 0xFF;
>> @@ -7330,6 +7334,19 @@ void intel_dp_mst_resume(struct intel_display *display)
>>   	}
>>   }
>>   
>> +static bool intel_dp_get_as_sdp_revision(struct intel_dp *intel_dp,
>> +					 struct intel_crtc_state *crtc_state)
>> +{
>> +	if (crtc_state->has_panel_replay &&
>> +	    !intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
>> +		return 1;
> The bogus v1 in PR link ON requirement got nuked from bspec.


Thanks for the clarification. With the updated bspec, this is no longer 
needed. I’ll drop the patch.

Apologies for the late reply and thanks for the reviews and suggestions.


Regards,

Ankit


>
>> +
>> +	if (intel_dp->as_sdp_v2_supported)
>> +		return 2;
>> +
>> +	return 1;
>> +}
>> +
>>   static
>>   void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
>>   					 struct intel_crtc_state *crtc_state)
>> @@ -7345,7 +7362,12 @@ void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
>>   	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
>>   	as_sdp->length = 0x9;
>>   	as_sdp->duration_incr_ms = 0;
>> -	as_sdp->revision = 0x2;
>> +	as_sdp->revision = intel_dp_get_as_sdp_revision(intel_dp, crtc_state);
>> +
>> +	/* No payload data bytes for Version 1 */
>> +	if (as_sdp->revision == 1)
>> +		return;
>> +
>>   	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
>>   
>>   	if (crtc_state->cmrr.enable) {
>> -- 
>> 2.45.2

Re: [PATCH 13/19] drm/i915/display: Add helper for AS SDP transmission time selection

[Nautiyal, Ankit K]

On 3/13/2026 6:06 PM, Ville Syrjälä wrote:
> On Wed, Mar 11, 2026 at 05:06:05PM +0530, Ankit Nautiyal wrote:
>> AS SDP may be transmitted at T1 or T2 depending on Panel Replay and
>> Adaptive Sync SDP configuration as per DP 2.1. Current we are using
>> T1 only, but future PR/AS SDP modes/features may require T2 or dynamic
>> selection.
>>
>> Introduce a helper to return the appropriate AS SDP transmission time so
>> that a single value is consistently used for programming PR_ALPM.
>> For now this returns T1.
>>
>> v2: Avoid adding new member to crtc_state; use a helper. (Ville)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_alpm.c | 20 +++++++++++++++++++-
>>   drivers/gpu/drm/i915/display/intel_dp.c   |  9 +++++++++
>>   drivers/gpu/drm/i915/display/intel_dp.h   |  2 ++
>>   3 files changed, 30 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
>> index a7350ce8e716..0a6da3f926d3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
>> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
>> @@ -11,6 +11,7 @@
>>   #include "intel_crtc.h"
>>   #include "intel_de.h"
>>   #include "intel_display_types.h"
>> +#include "intel_display_utils.h"
>>   #include "intel_dp.h"
>>   #include "intel_dp_aux.h"
>>   #include "intel_psr.h"
>> @@ -359,6 +360,23 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
>>   	crtc_state->has_lobf = true;
>>   }
>>   
>> +static int get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *crtc_state)
> The type should be u32 since it returns a (partial) register value.
>
>> +{
>> +	int as_sdp_setup_time = intel_dp_as_sdp_transmission_time();
>> +
>> +	switch (as_sdp_setup_time) {
>> +	case DP_PR_AS_SDP_SETUP_TIME_T1:
>> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
>> +	case DP_PR_AS_SDP_SETUP_TIME_DYNAMIC:
>> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2;
>> +	case DP_PR_AS_SDP_SETUP_TIME_T2:
>> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2;
>> +	default:
>> +		MISSING_CASE(as_sdp_setup_time);
>> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
>> +	}
>> +}
>> +
>>   static void lnl_alpm_configure(struct intel_dp *intel_dp,
>>   			       const struct intel_crtc_state *crtc_state)
>>   {
>> @@ -382,7 +400,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>>   			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
>>   
>>   		if (intel_dp->as_sdp_supported) {
>> -			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
>> +			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
>>   
>>   			if (crtc_state->link_off_after_as_sdp_when_pr_active)
>>   				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index e6148e7f0ebc..74a8af3cf18c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -7439,3 +7439,12 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>>   
>>   	return true;
>>   }
>> +
>> +int intel_dp_as_sdp_transmission_time(void)
>> +{
>> +	/*
>> +	 * For now we use T1 as the transmission time.
>> +	 * This can be later changed as per requirements.
>> +	 */
> IIRC Bspec actually says we must use T1.


I am a bit confused. As per spec 68920:

"When Panel Replay is inactive (this includes entry and exit frames), 
then the Source will always send the AS SDP on T1.

When Panel Replay is active, then the position of the packet may change 
depending on the V. Total mode and whether the target refresh rate (TRR) 
has been reached or not.

As per the table, T2 is needed for Fixed Vtotal mode and a case of Fixed 
average Vtotal (TRR reached)."

However the above is coming from the DP spec.

Later the spec mentions :

The position of the AS SDPs must be kept at T1 if Software plans on 
doing refresh rate changes while DC6v is enabled

PR_ALPM_CTL[ Adaptive Sync SDP Position ] = 01b (T1 Always)

DPCD 0011Ah[7:6] = 00b


So I guess we can just go with T1 for now?


Regards,

Ankit

>
>> +	return DP_PR_AS_SDP_SETUP_TIME_T1;
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> index 2849b9ecdc71..2e4609d9d05c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -238,4 +238,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>>   	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>>   		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
>>   
>> +int intel_dp_as_sdp_transmission_time(void);
>> +
>>   #endif /* __INTEL_DP_H__ */
>> -- 
>> 2.45.2

[PATCH 01/19] drm/dp: Rename and relocate AS SDP payload field masks

[Ankit Nautiyal]

The AS SDP payload field masks were misnamed and placed under the DPRX
feature enumeration list. These are not DPRX capability bits, but are
payload field masks for the Adaptive Sync SDP.

Relocate both masks next to the AS SDP definitions.
Update users to the corrected names. No functional change.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
 include/drm/display/drm_dp.h            | 5 +++--
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4955bd8b11d7..602efaf500bd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5295,8 +5295,8 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	if ((sdp->sdp_header.HB3 & 0x3F) != 9)
 		return -EINVAL;
 
-	as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
-	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
+	as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK;
+	as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
 	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
 	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 8b15d3eeb716..4ea3b5b08a12 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1204,8 +1204,6 @@
 
 #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1         0x2214 /* 2.0 E11 */
 # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED    (1 << 0)
-# define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE		GENMASK(1, 0)
-# define DP_ADAPTIVE_SYNC_SDP_LENGTH				GENMASK(5, 0)
 # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)
 # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED  (1 << 4)
 
@@ -1870,4 +1868,7 @@ enum operation_mode {
 	DP_AS_SDP_FAVT_TRR_REACHED = 0x03
 };
 
+#define DP_AS_SDP_OPERATION_MODE_MASK	GENMASK(1, 0)
+#define DP_AS_SDP_LENGTH_MASK		GENMASK(5, 0)
+
 #endif /* _DRM_DP_H_ */
-- 
2.45.2