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> } > > -static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder, > - u8 lane_mask, u8 state) > +void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder, > + u8 lane_mask, u8 state) > { > struct intel_display *display = to_intel_display(encoder); > enum port port = encoder->port; > @@ -2837,7 +2837,7 @@ static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder, > /* Update Timeout Value */ > if (intel_de_wait_custom(display, buf_ctl2_reg, > intel_cx0_get_powerdown_update(lane_mask), 0, > - XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL)) > + XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 2, NULL)) > drm_warn(display->drm, > "PHY %c failed to bring out of Lane reset after %dus.\n", > phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US); > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h > index b111a893b428..8c9b97f0922d 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h > @@ -41,6 +41,8 @@ bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a, > const struct intel_cx0pll_state *b); > void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state); > +void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder, > + u8 lane_mask, u8 state); > int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock); > void intel_cx0_setup_powerdown(struct intel_encoder *encoder); > bool intel_cx0_is_hdmi_frl(u32 clock); > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c > index 8c6f60d9e0ac..263e9780b55c 100644 > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c > @@ -42,6 +42,13 @@ intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8 lane_count) > intel_cx0_setup_powerdown(encoder); > } > > +static void > +intel_lt_phy_powerdown_change_sequence(struct intel_encoder *encoder, > + u8 lane_mask, u8 state) > +{ > + intel_cx0_powerdown_change_sequence(encoder, lane_mask, state); > +} > + > static void > intel_lt_phy_lane_reset(struct intel_encoder *encoder, > u8 lane_count) > @@ -69,6 +76,8 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder, > XE3PLPDP_PHY_MODE_MASK, XE3PLPDP_PHY_MODE_DP); > > intel_lt_phy_setup_powerdown(encoder, lane_count); > + intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask, > + XELPDP_P2_STATE_RESET); > > intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port), > XE3PLPD_MACCLK_RESET_0, 0); > @@ -144,6 +153,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder, > { > struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > bool lane_reversal = dig_port->lane_reversal; > + u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); > > /* 1. Enable MacCLK at default 162 MHz frequency. */ > intel_lt_phy_lane_reset(encoder, crtc_state->lane_count); > @@ -152,6 +162,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder, > intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal); > > /* 3. Change owned PHY lanes power to Ready state. */ > + intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask, > + XELPDP_P2_STATE_READY); > + > /* > * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type, > * encoded rate and encoded mode.