Re: [PATCH 19/23] drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless ALPM

Nautiyal, Ankit K
2026-04-07T08:51:38Z

On 4/2/2026 4:18 PM, Ville Syrjälä wrote:
> On Thu, Apr 02, 2026 at 01:34:19PM +0530, Ankit Nautiyal wrote:
>> If a Panel Replay capable sink, supports Async Video timing in
>> PR active state, then source does not necessarily need to send AS SDPs
>> during PR active.
>>
>> However, if asynchronous video timing is not supported, then for PR with
>> Aux-less ALPM, the source must transmit Adaptive-Sync SDPs for video
>> timing synchronization while PR is active.
>>
>> If the source needs to send AS SDP during PR active, this requires setting
>> DPCD 0x0107[6] (FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE). This applies whether
>> VRR is enabled (AVT/FAVT) or fixed-timing mode is used.
>>
>> This bit defines AS SDP timing behavior during PR Active, even if AS SDPs
>> are briefly suspended.
>>
>> Program the relevant Downspread Ctrl DPCD bits accordingly.
>>
>> v2: Instead of Panel Replay check simply use AS SDP enable check. (Ville)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> .../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++++++--
>> .../gpu/drm/i915/display/intel_dp_link_training.h | 3 ++-
>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
>> 3 files changed, 13 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index a26094223f78..8b21c479ebfc 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -27,6 +27,7 @@
>> #include <drm/display/drm_dp_helper.h>
>> #include <drm/drm_print.h>
>>
>> +#include "intel_alpm.h"
>> #include "intel_display_core.h"
>> #include "intel_display_jiffies.h"
>> #include "intel_display_types.h"
>> @@ -34,6 +35,7 @@
>> #include "intel_dp.h"
>> #include "intel_dp_link_training.h"
>> #include "intel_encoder.h"
>> +#include "intel_hdmi.h"
>> #include "intel_hotplug.h"
>> #include "intel_panel.h"
>>
>> @@ -710,11 +712,14 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
>> return true;
>> }
>>
>> -void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)
>> +void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate,
>> + bool is_vrr,
>> + bool as_sdp_enable)
>> {
>> u8 link_config[2];
>>
>> link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
>> + link_config[0] |= as_sdp_enable ? DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE : 0;
>> link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
>> DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
>> drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
>> @@ -737,7 +742,10 @@ static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
>> * especially on the first real commit when clearing the inherited flag.
>> */
>> intel_dp_link_training_set_mode(intel_dp,
>> - crtc_state->port_clock, crtc_state->vrr.in_range);
>> + crtc_state->port_clock,
>> + crtc_state->vrr.in_range,
>> + crtc_state->infoframes.enable &
>> + intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC));
> The bit is only documented to be valid for panel replay capable
> sinks. So we should probably not set it otherwise.
>
> But the weird thing is that the AS SDP DB0[1:0] description does not
> provide for a set of valid values for that case (DPCD 107h[7:6]=10b).
> Either they assumed that AS SDP v1 is used in that case (in which case
> the we'd not be able to support FAVT and maybe some other stuff without
> PR), or it's just an oversight and the same values apply as for
> 107h[7:6]=10b as they do for 107h[7:6]=11b.

Yeah you are right, the spec doesnt say any specific thing for AS SDP
DB0[1:0] when DPCD 107h[7:6]=10b.

It says for values 11b and 01b. As you said, I agree we should have a
Panel Replay check also.

I'll just use:

intel_alpm_is_alpm_aux_less() &&
crtc_state->infoframes.enable &
intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))

Regards,

Ankit

>
>> }
>>
>> void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> index 33dcbde6a408..d3ae8ee38a75 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> @@ -18,7 +18,8 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
>> bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp);
>>
>> void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,
>> - int link_rate, bool is_vrr);
>> + int link_rate, bool is_vrr,
>> + bool as_sdp_enable);
>> void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
>> int link_bw, int rate_select, int lane_count,
>> bool enhanced_framing, bool post_lt_adj_req);
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> index e8de17834dcd..ffd1cf0aad9a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> @@ -2142,7 +2142,7 @@ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
>>
>> intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);
>>
>> - intel_dp_link_training_set_mode(intel_dp, link_rate, false);
>> + intel_dp_link_training_set_mode(intel_dp, link_rate, false, false);
>> intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
>> drm_dp_enhanced_frame_cap(intel_dp->dpcd), false);
>>
>> --
>> 2.45.2