Re: [PATCH 1/3] drm/xe: Add PR_CTR_CTRL/THRSH register definitions

["Michał Winiarski" <michal.winiarski@intel.com>]

On Tue, Mar 03, 2026 at 09:13:52PM +0100, Michal Wajdeczko wrote:
> The Watchdog Counter Control and Watchdog Counter Threshold
> registers are needed for watchdog programming. This watchdog
> will generate the "Media Hang Notify" interrupt.
> 
> Bspec: 45999, 46000
> Bspec: 60373, 60374
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>

Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>

Thanks,
-Michał

> ---
>  drivers/gpu/drm/xe/regs/xe_engine_regs.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index dc5a4fafa70c..1b4a7e9a703d 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -132,6 +132,14 @@
>  #define RING_BBADDR(base)			XE_REG((base) + 0x140)
>  #define RING_BBADDR_UDW(base)			XE_REG((base) + 0x168)
>  
> +#define PR_CTR_CTRL(base)			XE_REG((base) + 0x178)
> +#define   CTR_COUNT_SELECT_FF			REG_BIT(31)
> +#define   CTR_LOGIC_OP_MASK			REG_GENMASK(30, 0)
> +#define     CTR_START				0
> +#define     CTR_STOP				1
> +#define   CTR_LOGIC_OP(OP)			REG_FIELD_PREP(CTR_LOGIC_OP_MASK, CTR_##OP)
> +#define PR_CTR_THRSH(base)			XE_REG((base) + 0x17c)
> +
>  #define BCS_SWCTRL(base)			XE_REG((base) + 0x200, XE_REG_OPTION_MASKED)
>  #define   BCS_SWCTRL_DISABLE_256B		REG_BIT(2)
>  
> -- 
> 2.47.1
>