* [PATCH v3 1/4] drm/xe/sysctrl: Add System Controller
2026-03-12 9:06 [PATCH v3 0/4] Introduce Xe Correctable Error Handling Raag Jadav
@ 2026-03-12 9:06 ` Raag Jadav
2026-03-12 9:06 ` [PATCH v3 2/4] drm/xe/sysctrl: Add system controller interrupt handler Raag Jadav
` (6 subsequent siblings)
7 siblings, 0 replies; 19+ messages in thread
From: Raag Jadav @ 2026-03-12 9:06 UTC (permalink / raw)
To: intel-xe
Cc: matthew.brost, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, mallesh.koujalagi,
soham.purkait, anoop.c.vijay, aravind.iddamsetty, Raag Jadav
From: Anoop Vijay <anoop.c.vijay@intel.com>
Do not review, CI only.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
drivers/gpu/drm/xe/Makefile | 2 +
drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h | 31 ++
drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h | 36 ++
drivers/gpu/drm/xe/xe_device.c | 5 +
drivers/gpu/drm/xe/xe_device_types.h | 6 +
drivers/gpu/drm/xe/xe_pci.c | 2 +
drivers/gpu/drm/xe/xe_pci_types.h | 1 +
drivers/gpu/drm/xe/xe_sysctrl.c | 84 ++++
drivers/gpu/drm/xe/xe_sysctrl.h | 21 +
drivers/gpu/drm/xe/xe_sysctrl_mailbox.c | 364 ++++++++++++++++++
drivers/gpu/drm/xe/xe_sysctrl_mailbox.h | 31 ++
drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 35 ++
drivers/gpu/drm/xe/xe_sysctrl_types.h | 32 ++
13 files changed, 650 insertions(+)
create mode 100644 drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
create mode 100644 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.c
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.h
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_types.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index cbd84ac0d5ab..543eb0b2430b 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -124,6 +124,8 @@ xe-y += xe_bb.o \
xe_step.o \
xe_survivability_mode.o \
xe_sync.o \
+ xe_sysctrl.o \
+ xe_sysctrl_mailbox.o \
xe_tile.o \
xe_tile_sysfs.o \
xe_tlb_inval.o \
diff --git a/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h b/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
new file mode 100644
index 000000000000..bc4793fb21e5
--- /dev/null
+++ b/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_ABI_H_
+#define _XE_SYSCTRL_ABI_H_
+
+#include <linux/types.h>
+
+struct xe_sysctrl_mailbox_schi_msg_hdr {
+ __le32 data;
+} __packed;
+
+struct xe_sysctrl_app_msg_hdr {
+ __le32 data;
+} __packed;
+
+#define SCHI_HDR_GROUP_ID_MASK GENMASK(7, 0)
+#define SCHI_HDR_COMMAND_MASK GENMASK(14, 8)
+#define SCHI_HDR_COMMAND_MAX 0x7f
+#define SCHI_HDR_IS_RESPONSE BIT(15)
+#define SCHI_HDR_RESERVED_MASK GENMASK(23, 16)
+#define SCHI_HDR_RESULT_MASK GENMASK(31, 24)
+
+#define APP_HDR_GROUP_ID_MASK GENMASK(7, 0)
+#define APP_HDR_COMMAND_MASK GENMASK(15, 8)
+#define APP_HDR_VERSION_MASK GENMASK(23, 16)
+#define APP_HDR_RESERVED_MASK GENMASK(31, 24)
+
+#endif
diff --git a/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
new file mode 100644
index 000000000000..30dd78780ea9
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_REGS_H_
+#define _XE_SYSCTRL_REGS_H_
+
+#include "xe_regs.h"
+
+#define SYSCTRL_BASE_OFFSET 0xdb000
+#define SYSCTRL_BASE (SOC_BASE + SYSCTRL_BASE_OFFSET)
+#define SYSCTRL_MAILBOX_INDEX 0x03
+#define SYSCTRL_BAR_LENGTH 0x1000
+
+#define SYSCTRL_MB_CTRL XE_REG(0x10)
+#define SYSCTRL_MB_CTRL_RUN_BUSY REG_BIT(31)
+#define SYSCTRL_MB_CTRL_IRQ REG_BIT(30)
+#define SYSCTRL_MB_CTRL_RUN_BUSY_OUT REG_BIT(29)
+#define SYSCTRL_MB_CTRL_PARAM3_MASK REG_GENMASK(28, 24)
+#define SYSCTRL_MB_CTRL_PARAM2_MASK REG_GENMASK(23, 16)
+#define SYSCTRL_MB_CTRL_PARAM1_MASK REG_GENMASK(15, 8)
+#define SYSCTRL_MB_CTRL_COMMAND_MASK REG_GENMASK(7, 0)
+#define SYSCTRL_MB_CTRL_SCHI_CMD REG_FIELD_PREP(SYSCTRL_MB_CTRL_COMMAND_MASK, 5)
+
+#define SYSCTRL_MB_DATA0 XE_REG(0x14)
+#define SYSCTRL_MB_DATA1 XE_REG(0x18)
+#define SYSCTRL_MB_DATA2 XE_REG(0x1c)
+#define SYSCTRL_MB_DATA3 XE_REG(0x20)
+
+#define SCHI_FRAME_PHASE REG_BIT(24)
+#define SCHI_FRAME_CURRENT_MASK REG_GENMASK(21, 16)
+#define SCHI_FRAME_TOTAL_MASK REG_GENMASK(13, 8)
+#define SCHI_FRAME_COMMAND_MASK REG_GENMASK(7, 0)
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 92d4ffb72f26..f88b2478b7a0 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -65,6 +65,7 @@
#include "xe_survivability_mode.h"
#include "xe_sriov.h"
#include "xe_svm.h"
+#include "xe_sysctrl.h"
#include "xe_tile.h"
#include "xe_ttm_stolen_mgr.h"
#include "xe_ttm_sys_mgr.h"
@@ -991,6 +992,10 @@ int xe_device_probe(struct xe_device *xe)
if (err)
goto err_unregister_display;
+ err = xe_sysctrl_init(xe);
+ if (err)
+ goto err_unregister_display;
+
err = xe_device_sysfs_init(xe);
if (err)
goto err_unregister_display;
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 615218d775b1..150c76b2acaf 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -27,6 +27,7 @@
#include "xe_sriov_vf_ccs_types.h"
#include "xe_step_types.h"
#include "xe_survivability_mode_types.h"
+#include "xe_sysctrl_types.h"
#include "xe_tile_types.h"
#include "xe_validation.h"
@@ -196,6 +197,8 @@ struct xe_device {
u8 has_soc_remapper_telem:1;
/** @info.has_sriov: Supports SR-IOV */
u8 has_sriov:1;
+ /** @info.has_sysctrl: Supports System Controller */
+ u8 has_sysctrl:1;
/** @info.has_usm: Device has unified shared memory support */
u8 has_usm:1;
/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
@@ -508,6 +511,9 @@ struct xe_device {
/** @i2c: I2C host controller */
struct xe_i2c *i2c;
+ /** @sc: System Controller */
+ struct xe_sysctrl sc;
+
/** @atomic_svm_timeslice_ms: Atomic SVM fault timeslice MS */
u32 atomic_svm_timeslice_ms;
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index f252ac3ea82c..d203255281c7 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -465,6 +465,7 @@ static const struct xe_device_desc cri_desc = {
.has_soc_remapper_sysctrl = true,
.has_soc_remapper_telem = true,
.has_sriov = true,
+ .has_sysctrl = true,
.max_gt_per_tile = 2,
MULTI_LRC_MASK,
.require_force_probe = true,
@@ -763,6 +764,7 @@ static int xe_info_init_early(struct xe_device *xe,
xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
desc->has_sriov;
+ xe->info.has_sysctrl = desc->has_sysctrl;
xe->info.skip_guc_pc = desc->skip_guc_pc;
xe->info.skip_mtcfg = desc->skip_mtcfg;
xe->info.skip_pcode = desc->skip_pcode;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 8eee4fb1c57c..08386c5eca27 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -57,6 +57,7 @@ struct xe_device_desc {
u8 has_soc_remapper_sysctrl:1;
u8 has_soc_remapper_telem:1;
u8 has_sriov:1;
+ u8 has_sysctrl:1;
u8 needs_scratch:1;
u8 skip_guc_pc:1;
u8 skip_mtcfg:1;
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
new file mode 100644
index 000000000000..365f73ef680d
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <linux/device.h>
+#include <linux/mutex.h>
+
+#include <drm/drm_managed.h>
+
+#include "regs/xe_sysctrl_regs.h"
+#include "xe_assert.h"
+#include "xe_device.h"
+#include "xe_mmio.h"
+#include "xe_printk.h"
+#include "xe_soc_remapper.h"
+#include "xe_sriov.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_types.h"
+
+/**
+ * DOC: System Controller (sysctrl)
+ *
+ * The System Controller (sysctrl) is an embedded microcontroller in Intel GPUs
+ * responsible for managing various low-level platform functions. Communication
+ * between the driver and the System Controller occurs via a mailbox interface,
+ * enabling the exchange of commands and responses.
+ *
+ * This module provides initialization routines and helper functions to interact
+ * with the System Controller through the mailbox.
+ */
+static void sysctrl_fini(void *arg)
+{
+ struct xe_device *xe = arg;
+
+ xe->soc_remapper.set_sysctrl_region(xe, 0);
+}
+
+/**
+ * xe_sysctrl_init() - Initialize System Controller subsystem
+ * @xe: xe device instance
+ *
+ * Entry point for System Controller initialization, called from xe_device_probe.
+ * This function checks platform support and initializes the system controller.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int xe_sysctrl_init(struct xe_device *xe)
+{
+ struct xe_tile *tile = xe_device_get_root_tile(xe);
+ struct xe_sysctrl *sc = &xe->sc;
+ int ret;
+
+ if (!xe->info.has_sysctrl)
+ return 0;
+
+ if (IS_SRIOV_VF(xe))
+ return 0;
+
+ xe_assert(xe, xe->soc_remapper.set_sysctrl_region);
+
+ xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
+
+ ret = devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
+ if (ret)
+ return ret;
+
+ sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio), GFP_KERNEL);
+ if (!sc->mmio)
+ return -ENOMEM;
+
+ xe_mmio_init(sc->mmio, tile, tile->mmio.regs, tile->mmio.regs_size);
+ sc->mmio->adj_offset = SYSCTRL_BASE;
+ sc->mmio->adj_limit = U32_MAX;
+
+ ret = drmm_mutex_init(&xe->drm, &sc->cmd_lock);
+ if (ret)
+ return ret;
+
+ xe_sysctrl_mailbox_init(sc);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
new file mode 100644
index 000000000000..d5d8735038ae
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_H_
+#define _XE_SYSCTRL_H_
+
+#include <linux/container_of.h>
+
+#include "xe_device_types.h"
+#include "xe_sysctrl_types.h"
+
+static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
+{
+ return container_of(sc, struct xe_device, sc);
+}
+
+int xe_sysctrl_init(struct xe_device *xe);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
new file mode 100644
index 000000000000..b08885cf8dd5
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
@@ -0,0 +1,364 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/cleanup.h>
+#include <linux/container_of.h>
+#include <linux/errno.h>
+#include <linux/minmax.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#include "regs/xe_sysctrl_regs.h"
+#include "xe_device.h"
+#include "xe_device_types.h"
+#include "xe_mmio.h"
+#include "xe_pm.h"
+#include "xe_printk.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_mailbox_types.h"
+#include "xe_sysctrl_types.h"
+
+#define XE_SYSCTRL_SCHI_HDR_GROUP_ID(hdr) \
+ FIELD_GET(SCHI_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_SCHI_HDR_COMMAND(hdr) \
+ FIELD_GET(SCHI_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_SCHI_HDR_IS_RESPONSE(hdr) \
+ FIELD_GET(SCHI_HDR_IS_RESPONSE, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_SCHI_HDR_RESULT(hdr) \
+ FIELD_GET(SCHI_HDR_RESULT_MASK, le32_to_cpu((hdr)->data))
+
+static bool sysctrl_wait_bit_clear(struct xe_sysctrl *sc, u32 bit_mask,
+ unsigned int timeout_ms)
+{
+ int ret;
+
+ ret = xe_mmio_wait32_not(sc->mmio, SYSCTRL_MB_CTRL, bit_mask, bit_mask,
+ timeout_ms * 1000, NULL, false);
+
+ return ret == 0;
+}
+
+static bool sysctrl_wait_bit_set(struct xe_sysctrl *sc, u32 bit_mask,
+ unsigned int timeout_ms)
+{
+ int ret;
+
+ ret = xe_mmio_wait32(sc->mmio, SYSCTRL_MB_CTRL, bit_mask, bit_mask,
+ timeout_ms * 1000, NULL, false);
+
+ return ret == 0;
+}
+
+static int sysctrl_write_frame(struct xe_sysctrl *sc, const void *frame,
+ size_t len)
+{
+ static const struct xe_reg regs[] = {
+ SYSCTRL_MB_DATA0, SYSCTRL_MB_DATA1, SYSCTRL_MB_DATA2, SYSCTRL_MB_DATA3
+ };
+ struct xe_device *xe = sc_to_xe(sc);
+ u32 val[XE_SYSCTRL_MB_FRAME_SIZE / sizeof(u32)] = {0};
+ u32 dw = DIV_ROUND_UP(len, sizeof(u32));
+ u32 i;
+
+ xe_assert(xe, len > 0 && len <= XE_SYSCTRL_MB_FRAME_SIZE);
+
+ memcpy(val, frame, len);
+
+ for (i = 0; i < dw; i++)
+ xe_mmio_write32(sc->mmio, regs[i], val[i]);
+
+ return 0;
+}
+
+static int sysctrl_read_frame(struct xe_sysctrl *sc, void *frame,
+ size_t len)
+{
+ static const struct xe_reg regs[] = {
+ SYSCTRL_MB_DATA0, SYSCTRL_MB_DATA1, SYSCTRL_MB_DATA2, SYSCTRL_MB_DATA3
+ };
+ struct xe_device *xe = sc_to_xe(sc);
+ u32 val[XE_SYSCTRL_MB_FRAME_SIZE / sizeof(u32)] = {0};
+ u32 dw = DIV_ROUND_UP(len, sizeof(u32));
+ u32 i;
+
+ xe_assert(xe, len > 0 && len <= XE_SYSCTRL_MB_FRAME_SIZE);
+
+ for (i = 0; i < dw; i++)
+ val[i] = xe_mmio_read32(sc->mmio, regs[i]);
+
+ memcpy(frame, val, len);
+
+ return 0;
+}
+
+static void sysctrl_clear_response(struct xe_sysctrl *sc)
+{
+ xe_mmio_rmw32(sc->mmio, SYSCTRL_MB_CTRL, SYSCTRL_MB_CTRL_RUN_BUSY_OUT, 0);
+}
+
+static int sysctrl_prepare_command(struct xe_device *xe,
+ u8 group_id, u8 command,
+ const void *data_in, size_t data_in_len,
+ u8 **mbox_cmd, size_t *cmd_size)
+{
+ struct xe_sysctrl_mailbox_schi_msg_hdr *schi_hdr;
+ size_t size;
+ u8 *buffer;
+
+ xe_assert(xe, command <= SCHI_HDR_COMMAND_MAX);
+
+ if (data_in_len > XE_SYSCTRL_MB_MAX_MESSAGE_SIZE - sizeof(*schi_hdr)) {
+ xe_err(xe, "sysctrl: Input data too large: %zu bytes\n", data_in_len);
+ return -EINVAL;
+ }
+
+ size = sizeof(*schi_hdr) + data_in_len;
+
+ buffer = kmalloc(size, GFP_KERNEL);
+ if (!buffer)
+ return -ENOMEM;
+
+ schi_hdr = (struct xe_sysctrl_mailbox_schi_msg_hdr *)buffer;
+ schi_hdr->data = cpu_to_le32(FIELD_PREP(SCHI_HDR_GROUP_ID_MASK, group_id) |
+ FIELD_PREP(SCHI_HDR_COMMAND_MASK, command));
+
+ if (data_in && data_in_len)
+ memcpy(buffer + sizeof(*schi_hdr), data_in, data_in_len);
+
+ *mbox_cmd = buffer;
+ *cmd_size = size;
+
+ return 0;
+}
+
+static int sysctrl_send_frames(struct xe_sysctrl *sc,
+ const u8 *mbox_cmd,
+ size_t cmd_size, unsigned int timeout_ms)
+{
+ struct xe_device *xe = sc_to_xe(sc);
+ u32 ctrl_reg, total_frames, frame;
+ size_t bytes_sent, frame_size;
+
+ total_frames = DIV_ROUND_UP(cmd_size, XE_SYSCTRL_MB_FRAME_SIZE);
+
+ if (!sysctrl_wait_bit_clear(sc, SYSCTRL_MB_CTRL_RUN_BUSY, timeout_ms)) {
+ xe_err(xe, "sysctrl: Mailbox busy\n");
+ return -EBUSY;
+ }
+
+ sc->phase_bit ^= 1;
+ bytes_sent = 0;
+
+ for (frame = 0; frame < total_frames; frame++) {
+ frame_size = min_t(size_t, cmd_size - bytes_sent, XE_SYSCTRL_MB_FRAME_SIZE);
+
+ if (sysctrl_write_frame(sc, mbox_cmd + bytes_sent, frame_size)) {
+ xe_err(xe, "sysctrl: Failed to write frame %u\n", frame);
+ sc->phase_bit = 0;
+ return -EIO;
+ }
+
+ ctrl_reg = SYSCTRL_MB_CTRL_RUN_BUSY |
+ REG_FIELD_PREP(SCHI_FRAME_CURRENT_MASK, frame) |
+ REG_FIELD_PREP(SCHI_FRAME_TOTAL_MASK, total_frames - 1) |
+ SYSCTRL_MB_CTRL_SCHI_CMD |
+ (sc->phase_bit ? SCHI_FRAME_PHASE : 0);
+
+ xe_mmio_write32(sc->mmio, SYSCTRL_MB_CTRL, ctrl_reg);
+
+ if (!sysctrl_wait_bit_clear(sc, SYSCTRL_MB_CTRL_RUN_BUSY, timeout_ms)) {
+ xe_err(xe, "sysctrl: Frame %u acknowledgment timeout\n", frame);
+ sc->phase_bit = 0;
+ return -ETIMEDOUT;
+ }
+
+ bytes_sent += frame_size;
+ }
+
+ return 0;
+}
+
+static int sysctrl_process_frame(struct xe_sysctrl *sc, void *out,
+ size_t frame_size, unsigned int timeout_ms,
+ bool *done)
+{
+ u32 curr_frame, total_frames, ctrl_reg;
+ struct xe_device *xe = sc_to_xe(sc);
+ int ret;
+
+ if (!sysctrl_wait_bit_set(sc, SYSCTRL_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
+ xe_err(xe, "sysctrl: Response frame timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ ctrl_reg = xe_mmio_read32(sc->mmio, SYSCTRL_MB_CTRL);
+ total_frames = FIELD_GET(SCHI_FRAME_TOTAL_MASK, ctrl_reg);
+ curr_frame = FIELD_GET(SCHI_FRAME_CURRENT_MASK, ctrl_reg);
+
+ ret = sysctrl_read_frame(sc, out, frame_size);
+ if (ret)
+ return ret;
+
+ sysctrl_clear_response(sc);
+
+ if (curr_frame == total_frames)
+ *done = true;
+
+ return 0;
+}
+
+static int sysctrl_receive_frames(struct xe_sysctrl *sc,
+ const struct xe_sysctrl_mailbox_schi_msg_hdr *req,
+ void *data_out, size_t data_out_len,
+ size_t *rdata_len, unsigned int timeout_ms)
+{
+ struct xe_sysctrl_mailbox_schi_msg_hdr *schi_hdr;
+ struct xe_device *xe = sc_to_xe(sc);
+ size_t remain = sizeof(*schi_hdr) + data_out_len;
+ u8 *buffer __free(kfree) = kzalloc(remain, GFP_KERNEL);
+ size_t frame_size;
+ bool done = false;
+ int ret = 0;
+ u8 *out;
+
+ if (!buffer)
+ return -ENOMEM;
+
+ out = buffer;
+ while (!done && remain) {
+ frame_size = min_t(size_t, remain, XE_SYSCTRL_MB_FRAME_SIZE);
+
+ ret = sysctrl_process_frame(sc, out, frame_size, timeout_ms,
+ &done);
+ if (ret)
+ return ret;
+
+ remain -= frame_size;
+ out += frame_size;
+ }
+
+ schi_hdr = (struct xe_sysctrl_mailbox_schi_msg_hdr *)buffer;
+
+ if (!XE_SYSCTRL_SCHI_HDR_IS_RESPONSE(schi_hdr) ||
+ XE_SYSCTRL_SCHI_HDR_GROUP_ID(schi_hdr) != XE_SYSCTRL_SCHI_HDR_GROUP_ID(req) ||
+ XE_SYSCTRL_SCHI_HDR_COMMAND(schi_hdr) != XE_SYSCTRL_SCHI_HDR_COMMAND(req)) {
+ xe_err(xe, "sysctrl: Response header mismatch\n");
+ return -EPROTO;
+ }
+
+ if (XE_SYSCTRL_SCHI_HDR_RESULT(schi_hdr) != 0) {
+ xe_err(xe, "sysctrl: Firmware error: 0x%02lx\n",
+ XE_SYSCTRL_SCHI_HDR_RESULT(schi_hdr));
+ return -EIO;
+ }
+
+ memcpy(data_out, schi_hdr + 1, data_out_len);
+ *rdata_len = out - buffer - sizeof(*schi_hdr);
+
+ return 0;
+}
+
+static int sysctrl_send_command(struct xe_sysctrl *sc,
+ const u8 *mbox_cmd, size_t cmd_size,
+ void *data_out, size_t data_out_len,
+ size_t *rdata_len, unsigned int timeout_ms)
+{
+ const struct xe_sysctrl_mailbox_schi_msg_hdr *schi_hdr;
+ size_t received;
+ int ret;
+
+ ret = sysctrl_send_frames(sc, mbox_cmd, cmd_size, timeout_ms);
+ if (ret)
+ return ret;
+
+ if (!data_out || !rdata_len)
+ return 0;
+
+ schi_hdr = (const struct xe_sysctrl_mailbox_schi_msg_hdr *)mbox_cmd;
+
+ ret = sysctrl_receive_frames(sc, schi_hdr, data_out, data_out_len,
+ &received, timeout_ms);
+ if (ret)
+ return ret;
+
+ *rdata_len = received;
+
+ return 0;
+}
+
+/**
+ * xe_sysctrl_mailbox_init - Initialize System Controller mailbox interface
+ * @sc: System controller structure
+ *
+ * Initialize system controller mailbox interface for communication.
+ */
+void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc)
+{
+ u32 ctrl_reg;
+
+ ctrl_reg = xe_mmio_read32(sc->mmio, SYSCTRL_MB_CTRL);
+ sc->phase_bit = (ctrl_reg & SCHI_FRAME_PHASE) ? 1 : 0;
+}
+
+/**
+ * xe_sysctrl_send_command() - Send command to System Controller via mailbox
+ * @sc: System Controller instance
+ * @cmd: Pointer to xe_sysctrl_mailbox_command structure
+ * @rdata_len: Pointer to store actual response data size (can be NULL)
+ *
+ * Send a command to the System Controller using SCHI protocol. Handles
+ * command preparation, fragmentation, transmission, and response reception.
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int xe_sysctrl_send_command(struct xe_sysctrl *sc,
+ struct xe_sysctrl_mailbox_command *cmd,
+ size_t *rdata_len)
+{
+ struct xe_device *xe = sc_to_xe(sc);
+ u8 group_id, command_code;
+ u8 *mbox_cmd = NULL;
+ size_t cmd_size = 0;
+ int ret = 0;
+
+ xe_assert(xe, xe->info.has_sysctrl);
+ xe_assert(xe, cmd->data_in || cmd->data_out);
+ xe_assert(xe, !cmd->data_in || cmd->data_in_len);
+ xe_assert(xe, !cmd->data_out || cmd->data_out_len);
+
+ group_id = XE_SYSCTRL_APP_HDR_GROUP_ID(&cmd->header);
+ command_code = XE_SYSCTRL_APP_HDR_COMMAND(&cmd->header);
+
+ might_sleep();
+
+ ret = sysctrl_prepare_command(xe, group_id, command_code,
+ cmd->data_in, cmd->data_in_len,
+ &mbox_cmd, &cmd_size);
+ if (ret) {
+ xe_err(xe, "sysctrl: Failed to prepare command: %pe\n", ERR_PTR(ret));
+ return ret;
+ }
+
+ guard(xe_pm_runtime)(xe);
+
+ guard(mutex)(&sc->cmd_lock);
+
+ ret = sysctrl_send_command(sc, mbox_cmd, cmd_size,
+ cmd->data_out, cmd->data_out_len, rdata_len,
+ XE_SYSCTRL_MB_DEFAULT_TIMEOUT_MS);
+ if (ret)
+ xe_err(xe, "sysctrl: Mailbox command failed: %pe\n", ERR_PTR(ret));
+
+ kfree(mbox_cmd);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
new file mode 100644
index 000000000000..91460be9e22c
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_MAILBOX_H_
+#define _XE_SYSCTRL_MAILBOX_H_
+
+#include <linux/bitfield.h>
+#include <linux/types.h>
+
+#include "abi/xe_sysctrl_abi.h"
+
+struct xe_sysctrl;
+struct xe_sysctrl_mailbox_command;
+
+#define XE_SYSCTRL_APP_HDR_GROUP_ID(hdr) \
+ FIELD_GET(APP_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_APP_HDR_COMMAND(hdr) \
+ FIELD_GET(APP_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
+ FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
+
+void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
+int xe_sysctrl_send_command(struct xe_sysctrl *sc,
+ struct xe_sysctrl_mailbox_command *cmd,
+ size_t *rdata_len);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
new file mode 100644
index 000000000000..fdf8d1d4e3cd
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_MAILBOX_TYPES_H_
+#define _XE_SYSCTRL_MAILBOX_TYPES_H_
+
+#include <linux/types.h>
+
+#include "abi/xe_sysctrl_abi.h"
+
+/**
+ * struct xe_sysctrl_mailbox_command - System Controller mailbox command
+ */
+struct xe_sysctrl_mailbox_command {
+ /** @header: Application message header containing command information */
+ struct xe_sysctrl_app_msg_hdr header;
+ /** @data_in: Pointer to input payload data (can be NULL if no input data) */
+ void *data_in;
+ /** @data_in_len: Size of input payload in bytes (0 if no input data) */
+ size_t data_in_len;
+ /** @data_out: Pointer to output buffer for response data (can be NULL if no response) */
+ void *data_out;
+ /** @data_out_len: Size of output buffer in bytes (0 if no response expected) */
+ size_t data_out_len;
+};
+
+#define XE_SYSCTRL_MB_FRAME_SIZE 16
+#define XE_SYSCTRL_MB_MAX_FRAMES 64
+#define XE_SYSCTRL_MB_MAX_MESSAGE_SIZE (XE_SYSCTRL_MB_FRAME_SIZE * XE_SYSCTRL_MB_MAX_FRAMES)
+
+#define XE_SYSCTRL_MB_DEFAULT_TIMEOUT_MS 500
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
new file mode 100644
index 000000000000..8217f6befe70
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_TYPES_H_
+#define _XE_SYSCTRL_TYPES_H_
+
+#include <linux/mutex.h>
+#include <linux/types.h>
+
+struct xe_mmio;
+
+/**
+ * struct xe_sysctrl - System Controller driver context
+ *
+ * This structure maintains the runtime state for System Controller
+ * communication. All fields are initialized during xe_sysctrl_init()
+ * and protected appropriately for concurrent access.
+ */
+struct xe_sysctrl {
+ /** @mmio: MMIO region for system control registers */
+ struct xe_mmio *mmio;
+
+ /** @cmd_lock: Mutex protecting mailbox command operations */
+ struct mutex cmd_lock;
+
+ /** @phase_bit: Message boundary phase toggle bit (0 or 1) */
+ bool phase_bit;
+};
+
+#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v3 2/4] drm/xe/sysctrl: Add system controller interrupt handler
2026-03-12 9:06 [PATCH v3 0/4] Introduce Xe Correctable Error Handling Raag Jadav
2026-03-12 9:06 ` [PATCH v3 1/4] drm/xe/sysctrl: Add System Controller Raag Jadav
@ 2026-03-12 9:06 ` Raag Jadav
2026-03-17 5:47 ` Mallesh, Koujalagi
2026-03-12 9:06 ` [PATCH v3 3/4] drm/xe/sysctrl: Add system controller event support Raag Jadav
` (5 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Raag Jadav @ 2026-03-12 9:06 UTC (permalink / raw)
To: intel-xe
Cc: matthew.brost, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, mallesh.koujalagi,
soham.purkait, anoop.c.vijay, aravind.iddamsetty, Raag Jadav
Add system controller interrupt handler which is denoted by 11th bit in
GFX master interrupt register. While at it, add worker for scheduling
system controller work.
Co-developed-by: Soham Purkait <soham.purkait@intel.com>
Signed-off-by: Soham Purkait <soham.purkait@intel.com>
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
v2: Use system_percpu_wq instead of dedicated (Matthew Brost)
---
drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
drivers/gpu/drm/xe/xe_irq.c | 2 ++
drivers/gpu/drm/xe/xe_sysctrl.c | 39 ++++++++++++++++++++++-----
drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
drivers/gpu/drm/xe/xe_sysctrl_types.h | 7 +++++
5 files changed, 43 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
index 9d74f454d3ff..1d6b976c4de0 100644
--- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
@@ -22,6 +22,7 @@
#define DISPLAY_IRQ REG_BIT(16)
#define SOC_H2DMEMINT_IRQ REG_BIT(13)
#define I2C_IRQ REG_BIT(12)
+#define SYSCTRL_IRQ REG_BIT(11)
#define GT_DW_IRQ(x) REG_BIT(x)
/*
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 9a775c6588dc..e9f0b3cad06d 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -24,6 +24,7 @@
#include "xe_mmio.h"
#include "xe_pxp.h"
#include "xe_sriov.h"
+#include "xe_sysctrl.h"
#include "xe_tile.h"
/*
@@ -525,6 +526,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
xe_heci_csc_irq_handler(xe, master_ctl);
xe_display_irq_handler(xe, master_ctl);
xe_i2c_irq_handler(xe, master_ctl);
+ xe_sysctrl_irq_handler(xe, master_ctl);
xe_mert_irq_handler(xe, master_ctl);
gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
index 365f73ef680d..30349df1c04b 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.c
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -8,6 +8,7 @@
#include <drm/drm_managed.h>
+#include "regs/xe_irq_regs.h"
#include "regs/xe_sysctrl_regs.h"
#include "xe_assert.h"
#include "xe_device.h"
@@ -33,10 +34,16 @@
static void sysctrl_fini(void *arg)
{
struct xe_device *xe = arg;
+ struct xe_sysctrl *sc = &xe->sc;
+ cancel_work_sync(&sc->work);
xe->soc_remapper.set_sysctrl_region(xe, 0);
}
+static void xe_sysctrl_work(struct work_struct *work)
+{
+}
+
/**
* xe_sysctrl_init() - Initialize System Controller subsystem
* @xe: xe device instance
@@ -60,12 +67,6 @@ int xe_sysctrl_init(struct xe_device *xe)
xe_assert(xe, xe->soc_remapper.set_sysctrl_region);
- xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
-
- ret = devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
- if (ret)
- return ret;
-
sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio), GFP_KERNEL);
if (!sc->mmio)
return -ENOMEM;
@@ -78,7 +79,31 @@ int xe_sysctrl_init(struct xe_device *xe)
if (ret)
return ret;
+ ret = drmm_mutex_init(&xe->drm, &sc->work_lock);
+ if (ret)
+ return ret;
+
+ xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
xe_sysctrl_mailbox_init(sc);
+ INIT_WORK(&sc->work, xe_sysctrl_work);
- return 0;
+ return devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
+}
+
+/**
+ * xe_sysctrl_irq_handler() - Handler for System Controller interrupts
+ * @xe: xe device instance
+ * @master_ctl: interrupt register
+ *
+ * Handle interrupts generated by System Controller.
+ */
+void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl)
+{
+ struct xe_sysctrl *sc = &xe->sc;
+
+ if (!xe->info.has_sysctrl)
+ return;
+
+ if (master_ctl & SYSCTRL_IRQ)
+ schedule_work(&sc->work);
}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
index d5d8735038ae..ff60d42b52a7 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
@@ -17,5 +17,6 @@ static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
}
int xe_sysctrl_init(struct xe_device *xe);
+void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
index 8217f6befe70..13fbf2990280 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_types.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
@@ -8,6 +8,7 @@
#include <linux/mutex.h>
#include <linux/types.h>
+#include <linux/workqueue_types.h>
struct xe_mmio;
@@ -27,6 +28,12 @@ struct xe_sysctrl {
/** @phase_bit: Message boundary phase toggle bit (0 or 1) */
bool phase_bit;
+
+ /** @work: Pending events work */
+ struct work_struct work;
+
+ /** @work_lock: Mutex protecting pending events */
+ struct mutex work_lock;
};
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v3 2/4] drm/xe/sysctrl: Add system controller interrupt handler
2026-03-12 9:06 ` [PATCH v3 2/4] drm/xe/sysctrl: Add system controller interrupt handler Raag Jadav
@ 2026-03-17 5:47 ` Mallesh, Koujalagi
2026-03-23 11:32 ` Raag Jadav
0 siblings, 1 reply; 19+ messages in thread
From: Mallesh, Koujalagi @ 2026-03-17 5:47 UTC (permalink / raw)
To: Raag Jadav
Cc: matthew.brost, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, soham.purkait,
anoop.c.vijay, aravind.iddamsetty, intel-xe
On 12-03-2026 02:36 pm, Raag Jadav wrote:
> Add system controller interrupt handler which is denoted by 11th bit in
> GFX master interrupt register. While at it, add worker for scheduling
> system controller work.
>
> Co-developed-by: Soham Purkait <soham.purkait@intel.com>
> Signed-off-by: Soham Purkait <soham.purkait@intel.com>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> ---
> v2: Use system_percpu_wq instead of dedicated (Matthew Brost)
> ---
> drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
> drivers/gpu/drm/xe/xe_irq.c | 2 ++
> drivers/gpu/drm/xe/xe_sysctrl.c | 39 ++++++++++++++++++++++-----
> drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
> drivers/gpu/drm/xe/xe_sysctrl_types.h | 7 +++++
> 5 files changed, 43 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> index 9d74f454d3ff..1d6b976c4de0 100644
> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> @@ -22,6 +22,7 @@
> #define DISPLAY_IRQ REG_BIT(16)
> #define SOC_H2DMEMINT_IRQ REG_BIT(13)
> #define I2C_IRQ REG_BIT(12)
> +#define SYSCTRL_IRQ REG_BIT(11)
> #define GT_DW_IRQ(x) REG_BIT(x)
>
> /*
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 9a775c6588dc..e9f0b3cad06d 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -24,6 +24,7 @@
> #include "xe_mmio.h"
> #include "xe_pxp.h"
> #include "xe_sriov.h"
> +#include "xe_sysctrl.h"
> #include "xe_tile.h"
>
> /*
> @@ -525,6 +526,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> xe_heci_csc_irq_handler(xe, master_ctl);
> xe_display_irq_handler(xe, master_ctl);
> xe_i2c_irq_handler(xe, master_ctl);
> + xe_sysctrl_irq_handler(xe, master_ctl);
> xe_mert_irq_handler(xe, master_ctl);
> gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
> }
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> index 365f73ef680d..30349df1c04b 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> @@ -8,6 +8,7 @@
>
> #include <drm/drm_managed.h>
>
> +#include "regs/xe_irq_regs.h"
> #include "regs/xe_sysctrl_regs.h"
> #include "xe_assert.h"
> #include "xe_device.h"
> @@ -33,10 +34,16 @@
> static void sysctrl_fini(void *arg)
> {
> struct xe_device *xe = arg;
> + struct xe_sysctrl *sc = &xe->sc;
>
> + cancel_work_sync(&sc->work);
> xe->soc_remapper.set_sysctrl_region(xe, 0);
> }
>
> +static void xe_sysctrl_work(struct work_struct *work)
> +{
> +}
> +
> /**
> * xe_sysctrl_init() - Initialize System Controller subsystem
> * @xe: xe device instance
> @@ -60,12 +67,6 @@ int xe_sysctrl_init(struct xe_device *xe)
>
> xe_assert(xe, xe->soc_remapper.set_sysctrl_region);
>
> - xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> -
> - ret = devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
> - if (ret)
> - return ret;
> -
> sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio), GFP_KERNEL);
> if (!sc->mmio)
> return -ENOMEM;
> @@ -78,7 +79,31 @@ int xe_sysctrl_init(struct xe_device *xe)
> if (ret)
> return ret;
>
> + ret = drmm_mutex_init(&xe->drm, &sc->work_lock);
> + if (ret)
> + return ret;
> +
> + xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> xe_sysctrl_mailbox_init(sc);
> + INIT_WORK(&sc->work, xe_sysctrl_work);
>
> - return 0;
> + return devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
> +}
> +
> +/**
> + * xe_sysctrl_irq_handler() - Handler for System Controller interrupts
> + * @xe: xe device instance
> + * @master_ctl: interrupt register
> + *
> + * Handle interrupts generated by System Controller.
> + */
> +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl)
> +{
> + struct xe_sysctrl *sc = &xe->sc;
> +
> + if (!xe->info.has_sysctrl)
> + return;
> +
We need to check sc->work.func if NULL then return, since initialization
of interrupt enabled @ line: 923 xe_irq_install() after that line 989:
xe_systctrl_init() set the work.func. In between
xe_sysctrl_irq_handler fired then work.func is NULL and going to
schedule work which lead to panic @ worker->current_func(work).
Thanks,
-/Mallesh
> + if (master_ctl & SYSCTRL_IRQ)
> + schedule_work(&sc->work);
> }
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> index d5d8735038ae..ff60d42b52a7 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> @@ -17,5 +17,6 @@ static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
> }
>
> int xe_sysctrl_init(struct xe_device *xe);
> +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
>
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> index 8217f6befe70..13fbf2990280 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_types.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> @@ -8,6 +8,7 @@
>
> #include <linux/mutex.h>
> #include <linux/types.h>
> +#include <linux/workqueue_types.h>
>
> struct xe_mmio;
>
> @@ -27,6 +28,12 @@ struct xe_sysctrl {
>
> /** @phase_bit: Message boundary phase toggle bit (0 or 1) */
> bool phase_bit;
> +
> + /** @work: Pending events work */
> + struct work_struct work;
> +
> + /** @work_lock: Mutex protecting pending events */
> + struct mutex work_lock;
> };
>
> #endif
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v3 2/4] drm/xe/sysctrl: Add system controller interrupt handler
2026-03-17 5:47 ` Mallesh, Koujalagi
@ 2026-03-23 11:32 ` Raag Jadav
0 siblings, 0 replies; 19+ messages in thread
From: Raag Jadav @ 2026-03-23 11:32 UTC (permalink / raw)
To: Mallesh, Koujalagi
Cc: matthew.brost, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, soham.purkait,
anoop.c.vijay, aravind.iddamsetty, intel-xe
On Tue, Mar 17, 2026 at 11:17:01AM +0530, Mallesh, Koujalagi wrote:
> On 12-03-2026 02:36 pm, Raag Jadav wrote:
> > Add system controller interrupt handler which is denoted by 11th bit in
> > GFX master interrupt register. While at it, add worker for scheduling
> > system controller work.
> >
> > Co-developed-by: Soham Purkait <soham.purkait@intel.com>
> > Signed-off-by: Soham Purkait <soham.purkait@intel.com>
> > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > ---
> > v2: Use system_percpu_wq instead of dedicated (Matthew Brost)
> > ---
> > drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
> > drivers/gpu/drm/xe/xe_irq.c | 2 ++
> > drivers/gpu/drm/xe/xe_sysctrl.c | 39 ++++++++++++++++++++++-----
> > drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
> > drivers/gpu/drm/xe/xe_sysctrl_types.h | 7 +++++
> > 5 files changed, 43 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > index 9d74f454d3ff..1d6b976c4de0 100644
> > --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > @@ -22,6 +22,7 @@
> > #define DISPLAY_IRQ REG_BIT(16)
> > #define SOC_H2DMEMINT_IRQ REG_BIT(13)
> > #define I2C_IRQ REG_BIT(12)
> > +#define SYSCTRL_IRQ REG_BIT(11)
> > #define GT_DW_IRQ(x) REG_BIT(x)
> > /*
> > diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> > index 9a775c6588dc..e9f0b3cad06d 100644
> > --- a/drivers/gpu/drm/xe/xe_irq.c
> > +++ b/drivers/gpu/drm/xe/xe_irq.c
> > @@ -24,6 +24,7 @@
> > #include "xe_mmio.h"
> > #include "xe_pxp.h"
> > #include "xe_sriov.h"
> > +#include "xe_sysctrl.h"
> > #include "xe_tile.h"
> > /*
> > @@ -525,6 +526,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> > xe_heci_csc_irq_handler(xe, master_ctl);
> > xe_display_irq_handler(xe, master_ctl);
> > xe_i2c_irq_handler(xe, master_ctl);
> > + xe_sysctrl_irq_handler(xe, master_ctl);
> > xe_mert_irq_handler(xe, master_ctl);
> > gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
> > }
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> > index 365f73ef680d..30349df1c04b 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> > @@ -8,6 +8,7 @@
> > #include <drm/drm_managed.h>
> > +#include "regs/xe_irq_regs.h"
> > #include "regs/xe_sysctrl_regs.h"
> > #include "xe_assert.h"
> > #include "xe_device.h"
> > @@ -33,10 +34,16 @@
> > static void sysctrl_fini(void *arg)
> > {
> > struct xe_device *xe = arg;
> > + struct xe_sysctrl *sc = &xe->sc;
> > + cancel_work_sync(&sc->work);
> > xe->soc_remapper.set_sysctrl_region(xe, 0);
> > }
> > +static void xe_sysctrl_work(struct work_struct *work)
> > +{
> > +}
> > +
> > /**
> > * xe_sysctrl_init() - Initialize System Controller subsystem
> > * @xe: xe device instance
> > @@ -60,12 +67,6 @@ int xe_sysctrl_init(struct xe_device *xe)
> > xe_assert(xe, xe->soc_remapper.set_sysctrl_region);
> > - xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> > -
> > - ret = devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
> > - if (ret)
> > - return ret;
> > -
> > sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio), GFP_KERNEL);
> > if (!sc->mmio)
> > return -ENOMEM;
> > @@ -78,7 +79,31 @@ int xe_sysctrl_init(struct xe_device *xe)
> > if (ret)
> > return ret;
> > + ret = drmm_mutex_init(&xe->drm, &sc->work_lock);
> > + if (ret)
> > + return ret;
> > +
> > + xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> > xe_sysctrl_mailbox_init(sc);
> > + INIT_WORK(&sc->work, xe_sysctrl_work);
> > - return 0;
> > + return devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
> > +}
> > +
> > +/**
> > + * xe_sysctrl_irq_handler() - Handler for System Controller interrupts
> > + * @xe: xe device instance
> > + * @master_ctl: interrupt register
> > + *
> > + * Handle interrupts generated by System Controller.
> > + */
> > +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl)
> > +{
> > + struct xe_sysctrl *sc = &xe->sc;
> > +
> > + if (!xe->info.has_sysctrl)
> > + return;
> > +
>
> We need to check sc->work.func if NULL then return, since initialization of
> interrupt enabled @ line: 923 xe_irq_install() after that line 989:
> xe_systctrl_init() set the work.func. In between
>
> xe_sysctrl_irq_handler fired then work.func is NULL and going to schedule
> work which lead to panic @ worker->current_func(work).
Sure, thanks.
Raag
> > + if (master_ctl & SYSCTRL_IRQ)
> > + schedule_work(&sc->work);
> > }
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> > index d5d8735038ae..ff60d42b52a7 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> > @@ -17,5 +17,6 @@ static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
> > }
> > int xe_sysctrl_init(struct xe_device *xe);
> > +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
> > #endif
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> > index 8217f6befe70..13fbf2990280 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl_types.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> > @@ -8,6 +8,7 @@
> > #include <linux/mutex.h>
> > #include <linux/types.h>
> > +#include <linux/workqueue_types.h>
> > struct xe_mmio;
> > @@ -27,6 +28,12 @@ struct xe_sysctrl {
> > /** @phase_bit: Message boundary phase toggle bit (0 or 1) */
> > bool phase_bit;
> > +
> > + /** @work: Pending events work */
> > + struct work_struct work;
> > +
> > + /** @work_lock: Mutex protecting pending events */
> > + struct mutex work_lock;
> > };
> > #endif
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 3/4] drm/xe/sysctrl: Add system controller event support
2026-03-12 9:06 [PATCH v3 0/4] Introduce Xe Correctable Error Handling Raag Jadav
2026-03-12 9:06 ` [PATCH v3 1/4] drm/xe/sysctrl: Add System Controller Raag Jadav
2026-03-12 9:06 ` [PATCH v3 2/4] drm/xe/sysctrl: Add system controller interrupt handler Raag Jadav
@ 2026-03-12 9:06 ` Raag Jadav
2026-03-19 14:09 ` Tauro, Riana
2026-03-12 9:06 ` [PATCH v3 4/4] drm/xe/ras: Introduce correctable error handling Raag Jadav
` (4 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Raag Jadav @ 2026-03-12 9:06 UTC (permalink / raw)
To: intel-xe
Cc: matthew.brost, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, mallesh.koujalagi,
soham.purkait, anoop.c.vijay, aravind.iddamsetty, Raag Jadav
System controller reports different types of events to GFX endpoint for
different usecases, add initial support for them. This will be further
extended to service those usecases.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
v2: Handle unexpected response length (Mallesh)
v3: Handle event flood (Mallesh)
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_sysctrl.c | 4 +
drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
drivers/gpu/drm/xe/xe_sysctrl_event.c | 82 +++++++++++++++++++++
drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 52 +++++++++++++
drivers/gpu/drm/xe/xe_sysctrl_mailbox.h | 10 +++
6 files changed, 150 insertions(+)
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 543eb0b2430b..373adb20afb2 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -125,6 +125,7 @@ xe-y += xe_bb.o \
xe_survivability_mode.o \
xe_sync.o \
xe_sysctrl.o \
+ xe_sysctrl_event.o \
xe_sysctrl_mailbox.o \
xe_tile.o \
xe_tile_sysfs.o \
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
index 30349df1c04b..63b9aaf98669 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.c
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -42,6 +42,10 @@ static void sysctrl_fini(void *arg)
static void xe_sysctrl_work(struct work_struct *work)
{
+ struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work);
+
+ guard(mutex)(&sc->work_lock);
+ xe_sysctrl_event(sc);
}
/**
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
index ff60d42b52a7..0821ea44893d 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
@@ -18,5 +18,6 @@ static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
int xe_sysctrl_init(struct xe_device *xe);
void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
+void xe_sysctrl_event(struct xe_sysctrl *sc);
#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
new file mode 100644
index 000000000000..47afca586bd1
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include "xe_device.h"
+#include "xe_irq.h"
+#include "xe_printk.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_event_types.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_mailbox_types.h"
+
+static void xe_sysctrl_get_pending_event(struct xe_sysctrl *sc,
+ struct xe_sysctrl_mailbox_command *command)
+{
+ struct xe_sysctrl_event_response response;
+ struct xe_device *xe = sc_to_xe(sc);
+ u32 count = 0;
+ size_t len;
+ int ret;
+
+ command->data_out = &response;
+ command->data_out_len = sizeof(response);
+
+ do {
+ memset(&response, 0, sizeof(response));
+
+ ret = xe_sysctrl_send_command(sc, command, &len);
+ if (ret) {
+ xe_err(xe, "sysctrl: failed to get pending event %d\n", ret);
+ return;
+ }
+
+ if (len != sizeof(response)) {
+ xe_err(xe, "sysctrl: unexpected pending event response length %ld\n", len);
+ return;
+ }
+
+ if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
+ xe_warn(xe, "[RAS]: error counter threshold crossed\n");
+ } else {
+ xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
+ return;
+ }
+
+ if (++count > XE_SYSCTRL_EVENT_FLOOD) {
+ xe_err(xe, "sysctrl: event flooding\n");
+ return;
+ }
+
+ xe_dbg(xe, "sysctrl: %u events pending\n", response.count);
+ } while (response.count);
+}
+
+static void xe_sysctrl_event_request_prep(struct xe_device *xe,
+ struct xe_sysctrl_app_msg_hdr *header,
+ struct xe_sysctrl_event_request *request)
+{
+ struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+
+ header->data = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
+ REG_FIELD_PREP(APP_HDR_COMMAND_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT);
+
+ request->vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0;
+ request->fn = PCI_FUNC(pdev->devfn);
+}
+
+void xe_sysctrl_event(struct xe_sysctrl *sc)
+{
+ struct xe_sysctrl_mailbox_command command = {};
+ struct xe_sysctrl_event_request request = {};
+ struct xe_sysctrl_app_msg_hdr header = {};
+
+ xe_sysctrl_event_request_prep(sc_to_xe(sc), &header, &request);
+
+ command.header = header;
+ command.data_in = &request;
+ command.data_in_len = sizeof(request);
+
+ xe_sysctrl_get_pending_event(sc, &command);
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
new file mode 100644
index 000000000000..1430a7ee2b39
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_EVENT_TYPES_H_
+#define _XE_SYSCTRL_EVENT_TYPES_H_
+
+#include <linux/types.h>
+
+#define XE_SYSCTRL_EVENT_DATA_LEN 59
+
+/* Modify as needed */
+#define XE_SYSCTRL_EVENT_FLOOD 16
+
+enum xe_sysctrl_event {
+ XE_SYSCTRL_EVENT_THRESHOLD_CROSSED = 1,
+};
+
+/**
+ * struct xe_sysctrl_event_request - Request structure for pending event
+ */
+struct xe_sysctrl_event_request {
+ /** @vector: MSI-X vector that was triggered */
+ u32 vector;
+ /** @fn: Function index (0-7) of PCIe device */
+ u8 fn;
+ /** @reserved: Reserved for future use */
+ u32 reserved:24;
+ /** @reserved2: Reserved for future use */
+ u32 reserved2[2];
+} __packed;
+
+/**
+ * struct xe_sysctrl_event_response - Response structure for pending event
+ */
+struct xe_sysctrl_event_response {
+ /** @count: Number of pending events */
+ u32 count;
+ /** @event: Pending event */
+ enum xe_sysctrl_event event;
+ /** @timestamp: Timestamp of most recent event */
+ u64 timestamp;
+ /** @extended: Event has extended payload */
+ u8 extended:1;
+ /** @reserved: Reserved for future use */
+ u32 reserved:31;
+ /** @data: Generic event data */
+ u32 data[XE_SYSCTRL_EVENT_DATA_LEN];
+} __packed;
+
+#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
index 91460be9e22c..d59a825597d3 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
@@ -23,6 +23,16 @@ struct xe_sysctrl_mailbox_command;
#define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
+/* Command groups */
+enum xe_sysctrl_group {
+ XE_SYSCTRL_GROUP_GFSP = 0x01,
+};
+
+/* Commands supported by GFSP group */
+enum xe_sysctrl_gfsp_cmd {
+ XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
+};
+
void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
int xe_sysctrl_send_command(struct xe_sysctrl *sc,
struct xe_sysctrl_mailbox_command *cmd,
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v3 3/4] drm/xe/sysctrl: Add system controller event support
2026-03-12 9:06 ` [PATCH v3 3/4] drm/xe/sysctrl: Add system controller event support Raag Jadav
@ 2026-03-19 14:09 ` Tauro, Riana
2026-03-23 11:40 ` Raag Jadav
0 siblings, 1 reply; 19+ messages in thread
From: Tauro, Riana @ 2026-03-19 14:09 UTC (permalink / raw)
To: Raag Jadav, intel-xe
Cc: matthew.brost, rodrigo.vivi, michal.wajdeczko, matthew.d.roper,
umesh.nerlige.ramappa, mallesh.koujalagi, soham.purkait,
anoop.c.vijay, aravind.iddamsetty
Hi Raag
On 3/12/2026 2:36 PM, Raag Jadav wrote:
> System controller reports different types of events to GFX endpoint for
> different usecases, add initial support for them. This will be further
> extended to service those usecases.
>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> ---
> v2: Handle unexpected response length (Mallesh)
> v3: Handle event flood (Mallesh)
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/xe_sysctrl.c | 4 +
> drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
> drivers/gpu/drm/xe/xe_sysctrl_event.c | 82 +++++++++++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 52 +++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl_mailbox.h | 10 +++
> 6 files changed, 150 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 543eb0b2430b..373adb20afb2 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -125,6 +125,7 @@ xe-y += xe_bb.o \
> xe_survivability_mode.o \
> xe_sync.o \
> xe_sysctrl.o \
> + xe_sysctrl_event.o \
> xe_sysctrl_mailbox.o \
> xe_tile.o \
> xe_tile_sysfs.o \
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> index 30349df1c04b..63b9aaf98669 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> @@ -42,6 +42,10 @@ static void sysctrl_fini(void *arg)
>
> static void xe_sysctrl_work(struct work_struct *work)
> {
> + struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work);
> +
> + guard(mutex)(&sc->work_lock);
> + xe_sysctrl_event(sc);
> }
>
> /**
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> index ff60d42b52a7..0821ea44893d 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> @@ -18,5 +18,6 @@ static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
>
> int xe_sysctrl_init(struct xe_device *xe);
> void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
> +void xe_sysctrl_event(struct xe_sysctrl *sc);
>
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> new file mode 100644
> index 000000000000..47afca586bd1
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> @@ -0,0 +1,82 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include "xe_device.h"
> +#include "xe_irq.h"
> +#include "xe_printk.h"
> +#include "xe_sysctrl.h"
> +#include "xe_sysctrl_event_types.h"
> +#include "xe_sysctrl_mailbox.h"
> +#include "xe_sysctrl_mailbox_types.h"
> +
> +static void xe_sysctrl_get_pending_event(struct xe_sysctrl *sc,
> + struct xe_sysctrl_mailbox_command *command)
> +{
> + struct xe_sysctrl_event_response response;
> + struct xe_device *xe = sc_to_xe(sc);
> + u32 count = 0;
> + size_t len;
> + int ret;
> +
> + command->data_out = &response;
> + command->data_out_len = sizeof(response);
> +
> + do {
> + memset(&response, 0, sizeof(response));
> +
> + ret = xe_sysctrl_send_command(sc, command, &len);
> + if (ret) {
> + xe_err(xe, "sysctrl: failed to get pending event %d\n", ret);
> + return;
> + }
> +
> + if (len != sizeof(response)) {
> + xe_err(xe, "sysctrl: unexpected pending event response length %ld\n", len);
> + return;
> + }
> +
> + if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
> + xe_warn(xe, "[RAS]: error counter threshold crossed\n");
> + } else {
> + xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
> + return;
> + }
> +
> + if (++count > XE_SYSCTRL_EVENT_FLOOD) {
> + xe_err(xe, "sysctrl: event flooding\n");
> + return;
> + }
> +
> + xe_dbg(xe, "sysctrl: %u events pending\n", response.count);
> + } while (response.count);
> +}
> +
> +static void xe_sysctrl_event_request_prep(struct xe_device *xe,
> + struct xe_sysctrl_app_msg_hdr *header,
> + struct xe_sysctrl_event_request *request)
> +{
> + struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> +
> + header->data = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
> + REG_FIELD_PREP(APP_HDR_COMMAND_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT);
> +
> + request->vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0;
> + request->fn = PCI_FUNC(pdev->devfn);
> +}
> +
> +void xe_sysctrl_event(struct xe_sysctrl *sc)
> +{
> + struct xe_sysctrl_mailbox_command command = {};
> + struct xe_sysctrl_event_request request = {};
> + struct xe_sysctrl_app_msg_hdr header = {};
> +
> + xe_sysctrl_event_request_prep(sc_to_xe(sc), &header, &request);
> +
> + command.header = header;
> + command.data_in = &request;
> + command.data_in_len = sizeof(request);
> +
> + xe_sysctrl_get_pending_event(sc, &command);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> new file mode 100644
> index 000000000000..1430a7ee2b39
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> @@ -0,0 +1,52 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_SYSCTRL_EVENT_TYPES_H_
> +#define _XE_SYSCTRL_EVENT_TYPES_H_
> +
> +#include <linux/types.h>
> +
> +#define XE_SYSCTRL_EVENT_DATA_LEN 59
> +
> +/* Modify as needed */
> +#define XE_SYSCTRL_EVENT_FLOOD 16
> +
> +enum xe_sysctrl_event {
> + XE_SYSCTRL_EVENT_THRESHOLD_CROSSED = 1,
> +};
> +
> +/**
> + * struct xe_sysctrl_event_request - Request structure for pending event
> + */
> +struct xe_sysctrl_event_request {
> + /** @vector: MSI-X vector that was triggered */
> + u32 vector;
> + /** @fn: Function index (0-7) of PCIe device */
> + u8 fn;
> + /** @reserved: Reserved for future use */
> + u32 reserved:24;
> + /** @reserved2: Reserved for future use */
> + u32 reserved2[2];
> +} __packed;
> +
> +/**
> + * struct xe_sysctrl_event_response - Response structure for pending event
> + */
> +struct xe_sysctrl_event_response {
> + /** @count: Number of pending events */
> + u32 count;
> + /** @event: Pending event */
> + enum xe_sysctrl_event event;
> + /** @timestamp: Timestamp of most recent event */
> + u64 timestamp;
> + /** @extended: Event has extended payload */
> + u8 extended:1;
> + /** @reserved: Reserved for future use */
> + u32 reserved:31;
> + /** @data: Generic event data */
> + u32 data[XE_SYSCTRL_EVENT_DATA_LEN];
> +} __packed;
Let's add this in xe_ras_types.h to have a separate RAS layer that
utilizes system controller.
Since multiple functions will be using system controller keeping their
headers and functions in a separate file
will avoid cluttering everything in a single file. Let sysctrl.c only be
an interface to the firmware.
Thanks
Riana
> +
> +#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> index 91460be9e22c..d59a825597d3 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> @@ -23,6 +23,16 @@ struct xe_sysctrl_mailbox_command;
> #define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
> FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
>
> +/* Command groups */
> +enum xe_sysctrl_group {
> + XE_SYSCTRL_GROUP_GFSP = 0x01,
> +};
> +
> +/* Commands supported by GFSP group */
> +enum xe_sysctrl_gfsp_cmd {
> + XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
> +};
> +
> void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
> int xe_sysctrl_send_command(struct xe_sysctrl *sc,
> struct xe_sysctrl_mailbox_command *cmd,
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v3 3/4] drm/xe/sysctrl: Add system controller event support
2026-03-19 14:09 ` Tauro, Riana
@ 2026-03-23 11:40 ` Raag Jadav
2026-03-23 12:27 ` Mallesh, Koujalagi
0 siblings, 1 reply; 19+ messages in thread
From: Raag Jadav @ 2026-03-23 11:40 UTC (permalink / raw)
To: Tauro, Riana
Cc: intel-xe, matthew.brost, rodrigo.vivi, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, mallesh.koujalagi,
soham.purkait, anoop.c.vijay, aravind.iddamsetty
On Thu, Mar 19, 2026 at 07:39:12PM +0530, Tauro, Riana wrote:
> On 3/12/2026 2:36 PM, Raag Jadav wrote:
> > System controller reports different types of events to GFX endpoint for
> > different usecases, add initial support for them. This will be further
> > extended to service those usecases.
> >
> > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > ---
> > v2: Handle unexpected response length (Mallesh)
> > v3: Handle event flood (Mallesh)
> > ---
> > drivers/gpu/drm/xe/Makefile | 1 +
> > drivers/gpu/drm/xe/xe_sysctrl.c | 4 +
> > drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
> > drivers/gpu/drm/xe/xe_sysctrl_event.c | 82 +++++++++++++++++++++
> > drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 52 +++++++++++++
> > drivers/gpu/drm/xe/xe_sysctrl_mailbox.h | 10 +++
> > 6 files changed, 150 insertions(+)
> > create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
> > create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> >
> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > index 543eb0b2430b..373adb20afb2 100644
> > --- a/drivers/gpu/drm/xe/Makefile
> > +++ b/drivers/gpu/drm/xe/Makefile
> > @@ -125,6 +125,7 @@ xe-y += xe_bb.o \
> > xe_survivability_mode.o \
> > xe_sync.o \
> > xe_sysctrl.o \
> > + xe_sysctrl_event.o \
> > xe_sysctrl_mailbox.o \
> > xe_tile.o \
> > xe_tile_sysfs.o \
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> > index 30349df1c04b..63b9aaf98669 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> > @@ -42,6 +42,10 @@ static void sysctrl_fini(void *arg)
> > static void xe_sysctrl_work(struct work_struct *work)
> > {
> > + struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work);
> > +
> > + guard(mutex)(&sc->work_lock);
> > + xe_sysctrl_event(sc);
> > }
> > /**
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> > index ff60d42b52a7..0821ea44893d 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> > @@ -18,5 +18,6 @@ static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
> > int xe_sysctrl_init(struct xe_device *xe);
> > void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
> > +void xe_sysctrl_event(struct xe_sysctrl *sc);
> > #endif
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > new file mode 100644
> > index 000000000000..47afca586bd1
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > @@ -0,0 +1,82 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#include "xe_device.h"
> > +#include "xe_irq.h"
> > +#include "xe_printk.h"
> > +#include "xe_sysctrl.h"
> > +#include "xe_sysctrl_event_types.h"
> > +#include "xe_sysctrl_mailbox.h"
> > +#include "xe_sysctrl_mailbox_types.h"
> > +
> > +static void xe_sysctrl_get_pending_event(struct xe_sysctrl *sc,
> > + struct xe_sysctrl_mailbox_command *command)
> > +{
> > + struct xe_sysctrl_event_response response;
> > + struct xe_device *xe = sc_to_xe(sc);
> > + u32 count = 0;
> > + size_t len;
> > + int ret;
> > +
> > + command->data_out = &response;
> > + command->data_out_len = sizeof(response);
> > +
> > + do {
> > + memset(&response, 0, sizeof(response));
> > +
> > + ret = xe_sysctrl_send_command(sc, command, &len);
> > + if (ret) {
> > + xe_err(xe, "sysctrl: failed to get pending event %d\n", ret);
> > + return;
> > + }
> > +
> > + if (len != sizeof(response)) {
> > + xe_err(xe, "sysctrl: unexpected pending event response length %ld\n", len);
> > + return;
> > + }
> > +
> > + if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
> > + xe_warn(xe, "[RAS]: error counter threshold crossed\n");
> > + } else {
> > + xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
> > + return;
> > + }
> > +
> > + if (++count > XE_SYSCTRL_EVENT_FLOOD) {
> > + xe_err(xe, "sysctrl: event flooding\n");
> > + return;
> > + }
> > +
> > + xe_dbg(xe, "sysctrl: %u events pending\n", response.count);
> > + } while (response.count);
> > +}
> > +
> > +static void xe_sysctrl_event_request_prep(struct xe_device *xe,
> > + struct xe_sysctrl_app_msg_hdr *header,
> > + struct xe_sysctrl_event_request *request)
> > +{
> > + struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> > +
> > + header->data = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
> > + REG_FIELD_PREP(APP_HDR_COMMAND_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT);
> > +
> > + request->vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0;
> > + request->fn = PCI_FUNC(pdev->devfn);
> > +}
> > +
> > +void xe_sysctrl_event(struct xe_sysctrl *sc)
> > +{
> > + struct xe_sysctrl_mailbox_command command = {};
> > + struct xe_sysctrl_event_request request = {};
> > + struct xe_sysctrl_app_msg_hdr header = {};
> > +
> > + xe_sysctrl_event_request_prep(sc_to_xe(sc), &header, &request);
> > +
> > + command.header = header;
> > + command.data_in = &request;
> > + command.data_in_len = sizeof(request);
> > +
> > + xe_sysctrl_get_pending_event(sc, &command);
> > +}
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> > new file mode 100644
> > index 000000000000..1430a7ee2b39
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> > @@ -0,0 +1,52 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_SYSCTRL_EVENT_TYPES_H_
> > +#define _XE_SYSCTRL_EVENT_TYPES_H_
> > +
> > +#include <linux/types.h>
> > +
> > +#define XE_SYSCTRL_EVENT_DATA_LEN 59
> > +
> > +/* Modify as needed */
> > +#define XE_SYSCTRL_EVENT_FLOOD 16
> > +
> > +enum xe_sysctrl_event {
> > + XE_SYSCTRL_EVENT_THRESHOLD_CROSSED = 1,
> > +};
> > +
> > +/**
> > + * struct xe_sysctrl_event_request - Request structure for pending event
> > + */
> > +struct xe_sysctrl_event_request {
> > + /** @vector: MSI-X vector that was triggered */
> > + u32 vector;
> > + /** @fn: Function index (0-7) of PCIe device */
> > + u8 fn;
> > + /** @reserved: Reserved for future use */
> > + u32 reserved:24;
> > + /** @reserved2: Reserved for future use */
> > + u32 reserved2[2];
> > +} __packed;
> > +
> > +/**
> > + * struct xe_sysctrl_event_response - Response structure for pending event
> > + */
> > +struct xe_sysctrl_event_response {
> > + /** @count: Number of pending events */
> > + u32 count;
> > + /** @event: Pending event */
> > + enum xe_sysctrl_event event;
> > + /** @timestamp: Timestamp of most recent event */
> > + u64 timestamp;
> > + /** @extended: Event has extended payload */
> > + u8 extended:1;
> > + /** @reserved: Reserved for future use */
> > + u32 reserved:31;
> > + /** @data: Generic event data */
> > + u32 data[XE_SYSCTRL_EVENT_DATA_LEN];
> > +} __packed;
>
> Let's add this in xe_ras_types.h to have a separate RAS layer that utilizes
> system controller.
>
> Since multiple functions will be using system controller keeping their
> headers and functions in a separate file
>
> will avoid cluttering everything in a single file. Let sysctrl.c only be an
> interface to the firmware.
I had an impression that a sysctrl event is meant for wider usecases than
RAS. Did things change (again)?
Raag
> > +
> > +#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > index 91460be9e22c..d59a825597d3 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > @@ -23,6 +23,16 @@ struct xe_sysctrl_mailbox_command;
> > #define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
> > FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
> > +/* Command groups */
> > +enum xe_sysctrl_group {
> > + XE_SYSCTRL_GROUP_GFSP = 0x01,
> > +};
> > +
> > +/* Commands supported by GFSP group */
> > +enum xe_sysctrl_gfsp_cmd {
> > + XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
> > +};
> > +
> > void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
> > int xe_sysctrl_send_command(struct xe_sysctrl *sc,
> > struct xe_sysctrl_mailbox_command *cmd,
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v3 3/4] drm/xe/sysctrl: Add system controller event support
2026-03-23 11:40 ` Raag Jadav
@ 2026-03-23 12:27 ` Mallesh, Koujalagi
2026-03-24 4:42 ` Raag Jadav
0 siblings, 1 reply; 19+ messages in thread
From: Mallesh, Koujalagi @ 2026-03-23 12:27 UTC (permalink / raw)
To: Raag Jadav
Cc: intel-xe, matthew.brost, rodrigo.vivi, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, soham.purkait,
anoop.c.vijay, aravind.iddamsetty, Riana Tauro
Hi Raag,
On 23-03-2026 05:10 pm, Raag Jadav wrote:
> On Thu, Mar 19, 2026 at 07:39:12PM +0530, Tauro, Riana wrote:
>> On 3/12/2026 2:36 PM, Raag Jadav wrote:
>>> System controller reports different types of events to GFX endpoint for
>>> different usecases, add initial support for them. This will be further
>>> extended to service those usecases.
>>>
>>> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
>>> ---
>>> v2: Handle unexpected response length (Mallesh)
>>> v3: Handle event flood (Mallesh)
>>> ---
>>> drivers/gpu/drm/xe/Makefile | 1 +
>>> drivers/gpu/drm/xe/xe_sysctrl.c | 4 +
>>> drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
>>> drivers/gpu/drm/xe/xe_sysctrl_event.c | 82 +++++++++++++++++++++
>>> drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 52 +++++++++++++
>>> drivers/gpu/drm/xe/xe_sysctrl_mailbox.h | 10 +++
>>> 6 files changed, 150 insertions(+)
>>> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
>>> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
>>>
>>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>>> index 543eb0b2430b..373adb20afb2 100644
>>> --- a/drivers/gpu/drm/xe/Makefile
>>> +++ b/drivers/gpu/drm/xe/Makefile
>>> @@ -125,6 +125,7 @@ xe-y += xe_bb.o \
>>> xe_survivability_mode.o \
>>> xe_sync.o \
>>> xe_sysctrl.o \
>>> + xe_sysctrl_event.o \
>>> xe_sysctrl_mailbox.o \
>>> xe_tile.o \
>>> xe_tile_sysfs.o \
>>> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
>>> index 30349df1c04b..63b9aaf98669 100644
>>> --- a/drivers/gpu/drm/xe/xe_sysctrl.c
>>> +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
>>> @@ -42,6 +42,10 @@ static void sysctrl_fini(void *arg)
>>> static void xe_sysctrl_work(struct work_struct *work)
>>> {
>>> + struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work);
>>> +
>>> + guard(mutex)(&sc->work_lock);
>>> + xe_sysctrl_event(sc);
>>> }
>>> /**
>>> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
>>> index ff60d42b52a7..0821ea44893d 100644
>>> --- a/drivers/gpu/drm/xe/xe_sysctrl.h
>>> +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
>>> @@ -18,5 +18,6 @@ static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
>>> int xe_sysctrl_init(struct xe_device *xe);
>>> void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
>>> +void xe_sysctrl_event(struct xe_sysctrl *sc);
>>> #endif
>>> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
>>> new file mode 100644
>>> index 000000000000..47afca586bd1
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
>>> @@ -0,0 +1,82 @@
>>> +// SPDX-License-Identifier: MIT
>>> +/*
>>> + * Copyright © 2026 Intel Corporation
>>> + */
>>> +
>>> +#include "xe_device.h"
>>> +#include "xe_irq.h"
>>> +#include "xe_printk.h"
>>> +#include "xe_sysctrl.h"
>>> +#include "xe_sysctrl_event_types.h"
>>> +#include "xe_sysctrl_mailbox.h"
>>> +#include "xe_sysctrl_mailbox_types.h"
>>> +
>>> +static void xe_sysctrl_get_pending_event(struct xe_sysctrl *sc,
>>> + struct xe_sysctrl_mailbox_command *command)
>>> +{
>>> + struct xe_sysctrl_event_response response;
>>> + struct xe_device *xe = sc_to_xe(sc);
>>> + u32 count = 0;
>>> + size_t len;
>>> + int ret;
>>> +
Ensure that response structure fits in mailbox buffer by checking
against XE_SYSCTRL_MB_MAX_MESSAGE_SIZE (1024).
Thanks,
-/Mallesh
>>> + command->data_out = &response;
>>> + command->data_out_len = sizeof(response);
>>> +
>>> + do {
>>> + memset(&response, 0, sizeof(response));
>>> +
>>> + ret = xe_sysctrl_send_command(sc, command, &len);
>>> + if (ret) {
>>> + xe_err(xe, "sysctrl: failed to get pending event %d\n", ret);
>>> + return;
>>> + }
>>> +
>>> + if (len != sizeof(response)) {
>>> + xe_err(xe, "sysctrl: unexpected pending event response length %ld\n", len);
>>> + return;
>>> + }
>>> +
>>> + if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
>>> + xe_warn(xe, "[RAS]: error counter threshold crossed\n");
>>> + } else {
>>> + xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
>>> + return;
>>> + }
>>> +
>>> + if (++count > XE_SYSCTRL_EVENT_FLOOD) {
>>> + xe_err(xe, "sysctrl: event flooding\n");
>>> + return;
>>> + }
>>> +
>>> + xe_dbg(xe, "sysctrl: %u events pending\n", response.count);
>>> + } while (response.count);
>>> +}
>>> +
>>> +static void xe_sysctrl_event_request_prep(struct xe_device *xe,
>>> + struct xe_sysctrl_app_msg_hdr *header,
>>> + struct xe_sysctrl_event_request *request)
>>> +{
>>> + struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
>>> +
>>> + header->data = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
>>> + REG_FIELD_PREP(APP_HDR_COMMAND_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT);
>>> +
>>> + request->vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0;
>>> + request->fn = PCI_FUNC(pdev->devfn);
>>> +}
>>> +
>>> +void xe_sysctrl_event(struct xe_sysctrl *sc)
>>> +{
>>> + struct xe_sysctrl_mailbox_command command = {};
>>> + struct xe_sysctrl_event_request request = {};
>>> + struct xe_sysctrl_app_msg_hdr header = {};
>>> +
>>> + xe_sysctrl_event_request_prep(sc_to_xe(sc), &header, &request);
>>> +
>>> + command.header = header;
>>> + command.data_in = &request;
>>> + command.data_in_len = sizeof(request);
>>> +
>>> + xe_sysctrl_get_pending_event(sc, &command);
>>> +}
>>> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
>>> new file mode 100644
>>> index 000000000000..1430a7ee2b39
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
>>> @@ -0,0 +1,52 @@
>>> +/* SPDX-License-Identifier: MIT */
>>> +/*
>>> + * Copyright © 2026 Intel Corporation
>>> + */
>>> +
>>> +#ifndef _XE_SYSCTRL_EVENT_TYPES_H_
>>> +#define _XE_SYSCTRL_EVENT_TYPES_H_
>>> +
>>> +#include <linux/types.h>
>>> +
>>> +#define XE_SYSCTRL_EVENT_DATA_LEN 59
>>> +
>>> +/* Modify as needed */
>>> +#define XE_SYSCTRL_EVENT_FLOOD 16
>>> +
>>> +enum xe_sysctrl_event {
>>> + XE_SYSCTRL_EVENT_THRESHOLD_CROSSED = 1,
>>> +};
>>> +
>>> +/**
>>> + * struct xe_sysctrl_event_request - Request structure for pending event
>>> + */
>>> +struct xe_sysctrl_event_request {
>>> + /** @vector: MSI-X vector that was triggered */
>>> + u32 vector;
>>> + /** @fn: Function index (0-7) of PCIe device */
>>> + u8 fn;
>>> + /** @reserved: Reserved for future use */
>>> + u32 reserved:24;
>>> + /** @reserved2: Reserved for future use */
>>> + u32 reserved2[2];
>>> +} __packed;
>>> +
>>> +/**
>>> + * struct xe_sysctrl_event_response - Response structure for pending event
>>> + */
>>> +struct xe_sysctrl_event_response {
>>> + /** @count: Number of pending events */
>>> + u32 count;
>>> + /** @event: Pending event */
>>> + enum xe_sysctrl_event event;
>>> + /** @timestamp: Timestamp of most recent event */
>>> + u64 timestamp;
>>> + /** @extended: Event has extended payload */
>>> + u8 extended:1;
>>> + /** @reserved: Reserved for future use */
>>> + u32 reserved:31;
>>> + /** @data: Generic event data */
>>> + u32 data[XE_SYSCTRL_EVENT_DATA_LEN];
>>> +} __packed;
>> Let's add this in xe_ras_types.h to have a separate RAS layer that utilizes
>> system controller.
>>
>> Since multiple functions will be using system controller keeping their
>> headers and functions in a separate file
>>
>> will avoid cluttering everything in a single file. Let sysctrl.c only be an
>> interface to the firmware.
> I had an impression that a sysctrl event is meant for wider usecases than
> RAS. Did things change (again)?
>
> Raag
>
>>> +
>>> +#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */
>>> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
>>> index 91460be9e22c..d59a825597d3 100644
>>> --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
>>> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
>>> @@ -23,6 +23,16 @@ struct xe_sysctrl_mailbox_command;
>>> #define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
>>> FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
>>> +/* Command groups */
>>> +enum xe_sysctrl_group {
>>> + XE_SYSCTRL_GROUP_GFSP = 0x01,
>>> +};
>>> +
>>> +/* Commands supported by GFSP group */
>>> +enum xe_sysctrl_gfsp_cmd {
>>> + XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
>>> +};
>>> +
>>> void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
>>> int xe_sysctrl_send_command(struct xe_sysctrl *sc,
>>> struct xe_sysctrl_mailbox_command *cmd,
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v3 3/4] drm/xe/sysctrl: Add system controller event support
2026-03-23 12:27 ` Mallesh, Koujalagi
@ 2026-03-24 4:42 ` Raag Jadav
0 siblings, 0 replies; 19+ messages in thread
From: Raag Jadav @ 2026-03-24 4:42 UTC (permalink / raw)
To: Mallesh, Koujalagi
Cc: intel-xe, matthew.brost, rodrigo.vivi, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, soham.purkait,
anoop.c.vijay, aravind.iddamsetty, Riana Tauro
On Mon, Mar 23, 2026 at 05:57:50PM +0530, Mallesh, Koujalagi wrote:
> On 23-03-2026 05:10 pm, Raag Jadav wrote:
> > On Thu, Mar 19, 2026 at 07:39:12PM +0530, Tauro, Riana wrote:
> > > On 3/12/2026 2:36 PM, Raag Jadav wrote:
> > > > System controller reports different types of events to GFX endpoint for
> > > > different usecases, add initial support for them. This will be further
> > > > extended to service those usecases.
> > > >
> > > > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > > > ---
> > > > v2: Handle unexpected response length (Mallesh)
> > > > v3: Handle event flood (Mallesh)
> > > > ---
> > > > drivers/gpu/drm/xe/Makefile | 1 +
> > > > drivers/gpu/drm/xe/xe_sysctrl.c | 4 +
> > > > drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
> > > > drivers/gpu/drm/xe/xe_sysctrl_event.c | 82 +++++++++++++++++++++
> > > > drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 52 +++++++++++++
> > > > drivers/gpu/drm/xe/xe_sysctrl_mailbox.h | 10 +++
> > > > 6 files changed, 150 insertions(+)
> > > > create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
> > > > create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> > > >
> > > > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > > > index 543eb0b2430b..373adb20afb2 100644
> > > > --- a/drivers/gpu/drm/xe/Makefile
> > > > +++ b/drivers/gpu/drm/xe/Makefile
> > > > @@ -125,6 +125,7 @@ xe-y += xe_bb.o \
> > > > xe_survivability_mode.o \
> > > > xe_sync.o \
> > > > xe_sysctrl.o \
> > > > + xe_sysctrl_event.o \
> > > > xe_sysctrl_mailbox.o \
> > > > xe_tile.o \
> > > > xe_tile_sysfs.o \
> > > > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> > > > index 30349df1c04b..63b9aaf98669 100644
> > > > --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> > > > +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> > > > @@ -42,6 +42,10 @@ static void sysctrl_fini(void *arg)
> > > > static void xe_sysctrl_work(struct work_struct *work)
> > > > {
> > > > + struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work);
> > > > +
> > > > + guard(mutex)(&sc->work_lock);
> > > > + xe_sysctrl_event(sc);
> > > > }
> > > > /**
> > > > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> > > > index ff60d42b52a7..0821ea44893d 100644
> > > > --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> > > > +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> > > > @@ -18,5 +18,6 @@ static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
> > > > int xe_sysctrl_init(struct xe_device *xe);
> > > > void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
> > > > +void xe_sysctrl_event(struct xe_sysctrl *sc);
> > > > #endif
> > > > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > > > new file mode 100644
> > > > index 000000000000..47afca586bd1
> > > > --- /dev/null
> > > > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > > > @@ -0,0 +1,82 @@
> > > > +// SPDX-License-Identifier: MIT
> > > > +/*
> > > > + * Copyright © 2026 Intel Corporation
> > > > + */
> > > > +
> > > > +#include "xe_device.h"
> > > > +#include "xe_irq.h"
> > > > +#include "xe_printk.h"
> > > > +#include "xe_sysctrl.h"
> > > > +#include "xe_sysctrl_event_types.h"
> > > > +#include "xe_sysctrl_mailbox.h"
> > > > +#include "xe_sysctrl_mailbox_types.h"
> > > > +
> > > > +static void xe_sysctrl_get_pending_event(struct xe_sysctrl *sc,
> > > > + struct xe_sysctrl_mailbox_command *command)
> > > > +{
> > > > + struct xe_sysctrl_event_response response;
> > > > + struct xe_device *xe = sc_to_xe(sc);
> > > > + u32 count = 0;
> > > > + size_t len;
> > > > + int ret;
> > > > +
>
> Ensure that response structure fits in mailbox buffer by checking against
> XE_SYSCTRL_MB_MAX_MESSAGE_SIZE (1024).
Any mailbox parameter validation should be part of mailbox call itself and
not for its user to worry about.
Raag
> > > > + command->data_out = &response;
> > > > + command->data_out_len = sizeof(response);
> > > > +
> > > > + do {
> > > > + memset(&response, 0, sizeof(response));
> > > > +
> > > > + ret = xe_sysctrl_send_command(sc, command, &len);
> > > > + if (ret) {
> > > > + xe_err(xe, "sysctrl: failed to get pending event %d\n", ret);
> > > > + return;
> > > > + }
> > > > +
> > > > + if (len != sizeof(response)) {
> > > > + xe_err(xe, "sysctrl: unexpected pending event response length %ld\n", len);
> > > > + return;
> > > > + }
> > > > +
> > > > + if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
> > > > + xe_warn(xe, "[RAS]: error counter threshold crossed\n");
> > > > + } else {
> > > > + xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
> > > > + return;
> > > > + }
> > > > +
> > > > + if (++count > XE_SYSCTRL_EVENT_FLOOD) {
> > > > + xe_err(xe, "sysctrl: event flooding\n");
> > > > + return;
> > > > + }
> > > > +
> > > > + xe_dbg(xe, "sysctrl: %u events pending\n", response.count);
> > > > + } while (response.count);
> > > > +}
> > > > +
> > > > +static void xe_sysctrl_event_request_prep(struct xe_device *xe,
> > > > + struct xe_sysctrl_app_msg_hdr *header,
> > > > + struct xe_sysctrl_event_request *request)
> > > > +{
> > > > + struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> > > > +
> > > > + header->data = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
> > > > + REG_FIELD_PREP(APP_HDR_COMMAND_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT);
> > > > +
> > > > + request->vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0;
> > > > + request->fn = PCI_FUNC(pdev->devfn);
> > > > +}
> > > > +
> > > > +void xe_sysctrl_event(struct xe_sysctrl *sc)
> > > > +{
> > > > + struct xe_sysctrl_mailbox_command command = {};
> > > > + struct xe_sysctrl_event_request request = {};
> > > > + struct xe_sysctrl_app_msg_hdr header = {};
> > > > +
> > > > + xe_sysctrl_event_request_prep(sc_to_xe(sc), &header, &request);
> > > > +
> > > > + command.header = header;
> > > > + command.data_in = &request;
> > > > + command.data_in_len = sizeof(request);
> > > > +
> > > > + xe_sysctrl_get_pending_event(sc, &command);
> > > > +}
> > > > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> > > > new file mode 100644
> > > > index 000000000000..1430a7ee2b39
> > > > --- /dev/null
> > > > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> > > > @@ -0,0 +1,52 @@
> > > > +/* SPDX-License-Identifier: MIT */
> > > > +/*
> > > > + * Copyright © 2026 Intel Corporation
> > > > + */
> > > > +
> > > > +#ifndef _XE_SYSCTRL_EVENT_TYPES_H_
> > > > +#define _XE_SYSCTRL_EVENT_TYPES_H_
> > > > +
> > > > +#include <linux/types.h>
> > > > +
> > > > +#define XE_SYSCTRL_EVENT_DATA_LEN 59
> > > > +
> > > > +/* Modify as needed */
> > > > +#define XE_SYSCTRL_EVENT_FLOOD 16
> > > > +
> > > > +enum xe_sysctrl_event {
> > > > + XE_SYSCTRL_EVENT_THRESHOLD_CROSSED = 1,
> > > > +};
> > > > +
> > > > +/**
> > > > + * struct xe_sysctrl_event_request - Request structure for pending event
> > > > + */
> > > > +struct xe_sysctrl_event_request {
> > > > + /** @vector: MSI-X vector that was triggered */
> > > > + u32 vector;
> > > > + /** @fn: Function index (0-7) of PCIe device */
> > > > + u8 fn;
> > > > + /** @reserved: Reserved for future use */
> > > > + u32 reserved:24;
> > > > + /** @reserved2: Reserved for future use */
> > > > + u32 reserved2[2];
> > > > +} __packed;
> > > > +
> > > > +/**
> > > > + * struct xe_sysctrl_event_response - Response structure for pending event
> > > > + */
> > > > +struct xe_sysctrl_event_response {
> > > > + /** @count: Number of pending events */
> > > > + u32 count;
> > > > + /** @event: Pending event */
> > > > + enum xe_sysctrl_event event;
> > > > + /** @timestamp: Timestamp of most recent event */
> > > > + u64 timestamp;
> > > > + /** @extended: Event has extended payload */
> > > > + u8 extended:1;
> > > > + /** @reserved: Reserved for future use */
> > > > + u32 reserved:31;
> > > > + /** @data: Generic event data */
> > > > + u32 data[XE_SYSCTRL_EVENT_DATA_LEN];
> > > > +} __packed;
> > > Let's add this in xe_ras_types.h to have a separate RAS layer that utilizes
> > > system controller.
> > >
> > > Since multiple functions will be using system controller keeping their
> > > headers and functions in a separate file
> > >
> > > will avoid cluttering everything in a single file. Let sysctrl.c only be an
> > > interface to the firmware.
> > I had an impression that a sysctrl event is meant for wider usecases than
> > RAS. Did things change (again)?
> >
> > Raag
> >
> > > > +
> > > > +#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */
> > > > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > > > index 91460be9e22c..d59a825597d3 100644
> > > > --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > > > +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > > > @@ -23,6 +23,16 @@ struct xe_sysctrl_mailbox_command;
> > > > #define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
> > > > FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
> > > > +/* Command groups */
> > > > +enum xe_sysctrl_group {
> > > > + XE_SYSCTRL_GROUP_GFSP = 0x01,
> > > > +};
> > > > +
> > > > +/* Commands supported by GFSP group */
> > > > +enum xe_sysctrl_gfsp_cmd {
> > > > + XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
> > > > +};
> > > > +
> > > > void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
> > > > int xe_sysctrl_send_command(struct xe_sysctrl *sc,
> > > > struct xe_sysctrl_mailbox_command *cmd,
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 4/4] drm/xe/ras: Introduce correctable error handling
2026-03-12 9:06 [PATCH v3 0/4] Introduce Xe Correctable Error Handling Raag Jadav
` (2 preceding siblings ...)
2026-03-12 9:06 ` [PATCH v3 3/4] drm/xe/sysctrl: Add system controller event support Raag Jadav
@ 2026-03-12 9:06 ` Raag Jadav
2026-03-19 14:00 ` Tauro, Riana
2026-03-12 10:27 ` ✗ CI.checkpatch: warning for Introduce Xe Correctable Error Handling (rev3) Patchwork
` (3 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Raag Jadav @ 2026-03-12 9:06 UTC (permalink / raw)
To: intel-xe
Cc: matthew.brost, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, mallesh.koujalagi,
soham.purkait, anoop.c.vijay, aravind.iddamsetty, Raag Jadav
Add initial support for correctable error handling which is serviced
using system controller event. Currently we only log the errors in
dmesg but this serves as a foundation for RAS infrastructure and will
be further extended to facilitate other RAS features.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_ras.c | 89 +++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_ras.h | 14 +++++
drivers/gpu/drm/xe/xe_ras_types.h | 73 ++++++++++++++++++++++
drivers/gpu/drm/xe/xe_sysctrl_event.c | 3 +-
5 files changed, 179 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/xe/xe_ras.c
create mode 100644 drivers/gpu/drm/xe/xe_ras.h
create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 373adb20afb2..9811cf732260 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -113,6 +113,7 @@ xe-y += xe_bb.o \
xe_pxp_submit.o \
xe_query.o \
xe_range_fence.o \
+ xe_ras.o \
xe_reg_sr.o \
xe_reg_whitelist.o \
xe_ring_ops.o \
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
new file mode 100644
index 000000000000..37a996a6abf8
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include "xe_assert.h"
+#include "xe_printk.h"
+#include "xe_ras.h"
+#include "xe_ras_types.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_event_types.h"
+
+/* Severity of detected errors */
+enum xe_ras_severity {
+ XE_RAS_SEV_NOT_SUPPORTED = 0,
+ XE_RAS_SEV_CORRECTABLE,
+ XE_RAS_SEV_UNCORRECTABLE,
+ XE_RAS_SEV_INFORMATIONAL,
+ XE_RAS_SEV_MAX
+};
+
+/* Major IP blocks/components where errors can originate */
+enum xe_ras_component {
+ XE_RAS_COMP_NOT_SUPPORTED = 0,
+ XE_RAS_COMP_DEVICE_MEMORY,
+ XE_RAS_COMP_CORE_COMPUTE,
+ XE_RAS_COMP_RESERVED,
+ XE_RAS_COMP_PCIE,
+ XE_RAS_COMP_FABRIC,
+ XE_RAS_COMP_SOC_INTERNAL,
+ XE_RAS_COMP_MAX
+};
+
+static const char *const xe_ras_severities[] = {
+ [XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported",
+ [XE_RAS_SEV_CORRECTABLE] = "Correctable",
+ [XE_RAS_SEV_UNCORRECTABLE] = "Uncorrectable",
+ [XE_RAS_SEV_INFORMATIONAL] = "Informational",
+};
+static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
+
+static const char *const xe_ras_components[] = {
+ [XE_RAS_COMP_NOT_SUPPORTED] = "Not Supported",
+ [XE_RAS_COMP_DEVICE_MEMORY] = "Device Memory",
+ [XE_RAS_COMP_CORE_COMPUTE] = "Core Compute",
+ [XE_RAS_COMP_RESERVED] = "Reserved",
+ [XE_RAS_COMP_PCIE] = "PCIe",
+ [XE_RAS_COMP_FABRIC] = "Fabric",
+ [XE_RAS_COMP_SOC_INTERNAL] = "SoC Internal",
+};
+static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
+
+static inline const char *sev_to_str(struct xe_device *xe, u32 sev)
+{
+ xe_assert(xe, sev < XE_RAS_SEV_MAX);
+
+ return sev < XE_RAS_SEV_MAX ? xe_ras_severities[sev] : "Unknown";
+}
+
+static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
+{
+ xe_assert(xe, comp < XE_RAS_COMP_MAX);
+
+ return comp < XE_RAS_COMP_MAX ? xe_ras_components[comp] : "Unknown";
+}
+
+void xe_ras_event_log(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response)
+{
+ struct xe_ras_event_threshold_crossed *pending = (void *)&response->data;
+ struct xe_ras_error *errors = pending->counters;
+ struct xe_device *xe = sc_to_xe(sc);
+ u32 cid, sev, comp, inst, cause;
+ u8 tile;
+
+ xe_assert(xe, pending->ncounters < XE_RAS_NUM_COUNTERS);
+ xe_warn(xe, "[RAS]: threshold crossed, %u new errors\n", pending->ncounters);
+
+ for (cid = 0; cid < pending->ncounters && cid < XE_RAS_NUM_COUNTERS; cid++) {
+ sev = errors[cid].common.severity;
+ comp = errors[cid].common.component;
+
+ tile = errors[cid].product.unit.tile;
+ inst = errors[cid].product.unit.instance;
+ cause = errors[cid].product.cause.cause;
+
+ xe_warn(xe, "[RAS]: Tile:%u Instance:%u Component:%s Error:%s Cause:%#x\n",
+ tile, inst, comp_to_str(xe, sev), sev_to_str(xe, comp), cause);
+ }
+}
diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
new file mode 100644
index 000000000000..22f035fa498d
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_ras.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_RAS_H_
+#define _XE_RAS_H_
+
+struct xe_sysctrl;
+struct xe_sysctrl_event_response;
+
+void xe_ras_event_log(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
new file mode 100644
index 000000000000..2982c4696b6d
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_ras_types.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_RAS_TYPES_H_
+#define _XE_RAS_TYPES_H_
+
+#include <linux/types.h>
+
+#define XE_RAS_NUM_COUNTERS 16
+
+/**
+ * struct xe_ras_error_common - Error fields that are common across all products
+ */
+struct xe_ras_error_common {
+ /** @severity: Error severity */
+ u8 severity;
+ /** @component: IP block where error originated */
+ u8 component;
+} __packed;
+
+/**
+ * struct xe_ras_error_unit - Error unit information
+ */
+struct xe_ras_error_unit {
+ /** @tile: Tile identifier */
+ u8 tile;
+ /** @instance: Instance identifier specific to IP */
+ u32 instance;
+} __packed;
+
+/**
+ * struct xe_ras_error_cause - Error cause information
+ */
+struct xe_ras_error_cause {
+ /** @cause: Cause/checker */
+ u32 cause;
+ /** @reserved: For future use */
+ u8 reserved;
+} __packed;
+
+/**
+ * struct xe_ras_error_product - Error fields that are specific to the product
+ */
+struct xe_ras_error_product {
+ /** @unit: Unit within IP block */
+ struct xe_ras_error_unit unit;
+ /** @cause: Cause/checker */
+ struct xe_ras_error_cause cause;
+} __packed;
+
+/**
+ * struct xe_ras_error - Combines common and product-specific parts
+ */
+struct xe_ras_error {
+ /** @common: Common error type and component */
+ struct xe_ras_error_common common;
+ /** @product: Product-specific unit and cause */
+ struct xe_ras_error_product product;
+} __packed;
+
+/**
+ * struct xe_ras_event_threshold_crossed - Event data for threshold crossed event
+ */
+struct xe_ras_event_threshold_crossed {
+ /** @ncounters: Number of error counters that crossed thresholds */
+ u32 ncounters;
+ /** @counters: Array of error counters that crossed threshold */
+ struct xe_ras_error counters[XE_RAS_NUM_COUNTERS];
+} __packed;
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
index 47afca586bd1..1833ecadd9a1 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_event.c
+++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
@@ -6,6 +6,7 @@
#include "xe_device.h"
#include "xe_irq.h"
#include "xe_printk.h"
+#include "xe_ras.h"
#include "xe_sysctrl.h"
#include "xe_sysctrl_event_types.h"
#include "xe_sysctrl_mailbox.h"
@@ -38,7 +39,7 @@ static void xe_sysctrl_get_pending_event(struct xe_sysctrl *sc,
}
if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
- xe_warn(xe, "[RAS]: error counter threshold crossed\n");
+ xe_ras_event_log(sc, &response);
} else {
xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
return;
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v3 4/4] drm/xe/ras: Introduce correctable error handling
2026-03-12 9:06 ` [PATCH v3 4/4] drm/xe/ras: Introduce correctable error handling Raag Jadav
@ 2026-03-19 14:00 ` Tauro, Riana
2026-03-23 11:45 ` Raag Jadav
0 siblings, 1 reply; 19+ messages in thread
From: Tauro, Riana @ 2026-03-19 14:00 UTC (permalink / raw)
To: Raag Jadav, intel-xe
Cc: matthew.brost, rodrigo.vivi, michal.wajdeczko, matthew.d.roper,
umesh.nerlige.ramappa, mallesh.koujalagi, soham.purkait,
anoop.c.vijay, aravind.iddamsetty
Hi Raag
On 3/12/2026 2:36 PM, Raag Jadav wrote:
> Add initial support for correctable error handling which is serviced
> using system controller event. Currently we only log the errors in
> dmesg but this serves as a foundation for RAS infrastructure and will
> be further extended to facilitate other RAS features.
>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/xe_ras.c | 89 +++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_ras.h | 14 +++++
> drivers/gpu/drm/xe/xe_ras_types.h | 73 ++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl_event.c | 3 +-
> 5 files changed, 179 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/xe/xe_ras.c
> create mode 100644 drivers/gpu/drm/xe/xe_ras.h
> create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 373adb20afb2..9811cf732260 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -113,6 +113,7 @@ xe-y += xe_bb.o \
> xe_pxp_submit.o \
> xe_query.o \
> xe_range_fence.o \
> + xe_ras.o \
> xe_reg_sr.o \
> xe_reg_whitelist.o \
> xe_ring_ops.o \
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> new file mode 100644
> index 000000000000..37a996a6abf8
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -0,0 +1,89 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include "xe_assert.h"
> +#include "xe_printk.h"
> +#include "xe_ras.h"
> +#include "xe_ras_types.h"
> +#include "xe_sysctrl.h"
> +#include "xe_sysctrl_event_types.h"
> +
> +/* Severity of detected errors */
> +enum xe_ras_severity {
> + XE_RAS_SEV_NOT_SUPPORTED = 0,
> + XE_RAS_SEV_CORRECTABLE,
> + XE_RAS_SEV_UNCORRECTABLE,
> + XE_RAS_SEV_INFORMATIONAL,
> + XE_RAS_SEV_MAX
> +};
> +
> +/* Major IP blocks/components where errors can originate */
> +enum xe_ras_component {
> + XE_RAS_COMP_NOT_SUPPORTED = 0,
> + XE_RAS_COMP_DEVICE_MEMORY,
> + XE_RAS_COMP_CORE_COMPUTE,
> + XE_RAS_COMP_RESERVED,
> + XE_RAS_COMP_PCIE,
> + XE_RAS_COMP_FABRIC,
> + XE_RAS_COMP_SOC_INTERNAL,
> + XE_RAS_COMP_MAX
> +};
> +
> +static const char *const xe_ras_severities[] = {
> + [XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported",
> + [XE_RAS_SEV_CORRECTABLE] = "Correctable",
> + [XE_RAS_SEV_UNCORRECTABLE] = "Uncorrectable",
> + [XE_RAS_SEV_INFORMATIONAL] = "Informational",
> +};
> +static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
> +
> +static const char *const xe_ras_components[] = {
> + [XE_RAS_COMP_NOT_SUPPORTED] = "Not Supported",
> + [XE_RAS_COMP_DEVICE_MEMORY] = "Device Memory",
> + [XE_RAS_COMP_CORE_COMPUTE] = "Core Compute",
> + [XE_RAS_COMP_RESERVED] = "Reserved",
> + [XE_RAS_COMP_PCIE] = "PCIe",
> + [XE_RAS_COMP_FABRIC] = "Fabric",
> + [XE_RAS_COMP_SOC_INTERNAL] = "SoC Internal",
> +};
> +static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
> +
> +static inline const char *sev_to_str(struct xe_device *xe, u32 sev)
> +{
> + xe_assert(xe, sev < XE_RAS_SEV_MAX);
> +
> + return sev < XE_RAS_SEV_MAX ? xe_ras_severities[sev] : "Unknown";
> +}
> +
> +static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
> +{
> + xe_assert(xe, comp < XE_RAS_COMP_MAX);
> +
> + return comp < XE_RAS_COMP_MAX ? xe_ras_components[comp] : "Unknown";
> +}
> +
> +void xe_ras_event_log(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response)
> +{
> + struct xe_ras_event_threshold_crossed *pending = (void *)&response->data;
> + struct xe_ras_error *errors = pending->counters;
> + struct xe_device *xe = sc_to_xe(sc);
> + u32 cid, sev, comp, inst, cause;
> + u8 tile;
> +
> + xe_assert(xe, pending->ncounters < XE_RAS_NUM_COUNTERS);
> + xe_warn(xe, "[RAS]: threshold crossed, %u new errors\n", pending->ncounters);
> +
> + for (cid = 0; cid < pending->ncounters && cid < XE_RAS_NUM_COUNTERS; cid++) {
> + sev = errors[cid].common.severity;
> + comp = errors[cid].common.component;
> +
> + tile = errors[cid].product.unit.tile;
> + inst = errors[cid].product.unit.instance;
> + cause = errors[cid].product.cause.cause;
> +
> + xe_warn(xe, "[RAS]: Tile:%u Instance:%u Component:%s Error:%s Cause:%#x\n",
> + tile, inst, comp_to_str(xe, sev), sev_to_str(xe, comp), cause);
We can have minimal logging here with only severity and component and
add additional logging
in following patches.
> + }
> +}
> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> new file mode 100644
> index 000000000000..22f035fa498d
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_ras.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_RAS_H_
> +#define _XE_RAS_H_
> +
> +struct xe_sysctrl;
> +struct xe_sysctrl_event_response;
> +
> +void xe_ras_event_log(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response);
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> new file mode 100644
> index 000000000000..2982c4696b6d
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -0,0 +1,73 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_RAS_TYPES_H_
> +#define _XE_RAS_TYPES_H_
> +
> +#include <linux/types.h>
> +
> +#define XE_RAS_NUM_COUNTERS 16
> +
> +/**
> + * struct xe_ras_error_common - Error fields that are common across all products
> + */
> +struct xe_ras_error_common {
> + /** @severity: Error severity */
> + u8 severity;
> + /** @component: IP block where error originated */
> + u8 component;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_unit - Error unit information
> + */
> +struct xe_ras_error_unit {
> + /** @tile: Tile identifier */
> + u8 tile;
> + /** @instance: Instance identifier specific to IP */
> + u32 instance;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_cause - Error cause information
> + */
> +struct xe_ras_error_cause {
> + /** @cause: Cause/checker */
> + u32 cause;
> + /** @reserved: For future use */
> + u8 reserved;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_product - Error fields that are specific to the product
> + */
> +struct xe_ras_error_product {
> + /** @unit: Unit within IP block */
> + struct xe_ras_error_unit unit;
> + /** @cause: Cause/checker */
> + struct xe_ras_error_cause cause;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error - Combines common and product-specific parts
> + */
> +struct xe_ras_error {
error_class ?
Thanks
Riana
> + /** @common: Common error type and component */
> + struct xe_ras_error_common common;
> + /** @product: Product-specific unit and cause */
> + struct xe_ras_error_product product;
> +} __packed;
> +
> +/**
> + * struct xe_ras_event_threshold_crossed - Event data for threshold crossed event
> + */
> +struct xe_ras_event_threshold_crossed {
> + /** @ncounters: Number of error counters that crossed thresholds */
> + u32 ncounters;
> + /** @counters: Array of error counters that crossed threshold */
> + struct xe_ras_error counters[XE_RAS_NUM_COUNTERS];
> +} __packed;
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> index 47afca586bd1..1833ecadd9a1 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_event.c
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> @@ -6,6 +6,7 @@
> #include "xe_device.h"
> #include "xe_irq.h"
> #include "xe_printk.h"
> +#include "xe_ras.h"
> #include "xe_sysctrl.h"
> #include "xe_sysctrl_event_types.h"
> #include "xe_sysctrl_mailbox.h"
> @@ -38,7 +39,7 @@ static void xe_sysctrl_get_pending_event(struct xe_sysctrl *sc,
> }
>
> if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
> - xe_warn(xe, "[RAS]: error counter threshold crossed\n");
> + xe_ras_event_log(sc, &response);
> } else {
> xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
> return;
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v3 4/4] drm/xe/ras: Introduce correctable error handling
2026-03-19 14:00 ` Tauro, Riana
@ 2026-03-23 11:45 ` Raag Jadav
2026-03-23 14:46 ` Mallesh, Koujalagi
0 siblings, 1 reply; 19+ messages in thread
From: Raag Jadav @ 2026-03-23 11:45 UTC (permalink / raw)
To: Tauro, Riana
Cc: intel-xe, matthew.brost, rodrigo.vivi, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, mallesh.koujalagi,
soham.purkait, anoop.c.vijay, aravind.iddamsetty
On Thu, Mar 19, 2026 at 07:30:06PM +0530, Tauro, Riana wrote:
> On 3/12/2026 2:36 PM, Raag Jadav wrote:
> > Add initial support for correctable error handling which is serviced
> > using system controller event. Currently we only log the errors in
> > dmesg but this serves as a foundation for RAS infrastructure and will
> > be further extended to facilitate other RAS features.
> >
> > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > ---
> > drivers/gpu/drm/xe/Makefile | 1 +
> > drivers/gpu/drm/xe/xe_ras.c | 89 +++++++++++++++++++++++++++
> > drivers/gpu/drm/xe/xe_ras.h | 14 +++++
> > drivers/gpu/drm/xe/xe_ras_types.h | 73 ++++++++++++++++++++++
> > drivers/gpu/drm/xe/xe_sysctrl_event.c | 3 +-
> > 5 files changed, 179 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/xe/xe_ras.c
> > create mode 100644 drivers/gpu/drm/xe/xe_ras.h
> > create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
> >
> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > index 373adb20afb2..9811cf732260 100644
> > --- a/drivers/gpu/drm/xe/Makefile
> > +++ b/drivers/gpu/drm/xe/Makefile
> > @@ -113,6 +113,7 @@ xe-y += xe_bb.o \
> > xe_pxp_submit.o \
> > xe_query.o \
> > xe_range_fence.o \
> > + xe_ras.o \
> > xe_reg_sr.o \
> > xe_reg_whitelist.o \
> > xe_ring_ops.o \
> > diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> > new file mode 100644
> > index 000000000000..37a996a6abf8
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_ras.c
> > @@ -0,0 +1,89 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#include "xe_assert.h"
> > +#include "xe_printk.h"
> > +#include "xe_ras.h"
> > +#include "xe_ras_types.h"
> > +#include "xe_sysctrl.h"
> > +#include "xe_sysctrl_event_types.h"
> > +
> > +/* Severity of detected errors */
> > +enum xe_ras_severity {
> > + XE_RAS_SEV_NOT_SUPPORTED = 0,
> > + XE_RAS_SEV_CORRECTABLE,
> > + XE_RAS_SEV_UNCORRECTABLE,
> > + XE_RAS_SEV_INFORMATIONAL,
> > + XE_RAS_SEV_MAX
> > +};
> > +
> > +/* Major IP blocks/components where errors can originate */
> > +enum xe_ras_component {
> > + XE_RAS_COMP_NOT_SUPPORTED = 0,
> > + XE_RAS_COMP_DEVICE_MEMORY,
> > + XE_RAS_COMP_CORE_COMPUTE,
> > + XE_RAS_COMP_RESERVED,
> > + XE_RAS_COMP_PCIE,
> > + XE_RAS_COMP_FABRIC,
> > + XE_RAS_COMP_SOC_INTERNAL,
> > + XE_RAS_COMP_MAX
> > +};
> > +
> > +static const char *const xe_ras_severities[] = {
> > + [XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported",
> > + [XE_RAS_SEV_CORRECTABLE] = "Correctable",
> > + [XE_RAS_SEV_UNCORRECTABLE] = "Uncorrectable",
> > + [XE_RAS_SEV_INFORMATIONAL] = "Informational",
> > +};
> > +static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
> > +
> > +static const char *const xe_ras_components[] = {
> > + [XE_RAS_COMP_NOT_SUPPORTED] = "Not Supported",
> > + [XE_RAS_COMP_DEVICE_MEMORY] = "Device Memory",
> > + [XE_RAS_COMP_CORE_COMPUTE] = "Core Compute",
> > + [XE_RAS_COMP_RESERVED] = "Reserved",
> > + [XE_RAS_COMP_PCIE] = "PCIe",
> > + [XE_RAS_COMP_FABRIC] = "Fabric",
> > + [XE_RAS_COMP_SOC_INTERNAL] = "SoC Internal",
> > +};
> > +static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
> > +
> > +static inline const char *sev_to_str(struct xe_device *xe, u32 sev)
> > +{
> > + xe_assert(xe, sev < XE_RAS_SEV_MAX);
> > +
> > + return sev < XE_RAS_SEV_MAX ? xe_ras_severities[sev] : "Unknown";
> > +}
> > +
> > +static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
> > +{
> > + xe_assert(xe, comp < XE_RAS_COMP_MAX);
> > +
> > + return comp < XE_RAS_COMP_MAX ? xe_ras_components[comp] : "Unknown";
> > +}
> > +
> > +void xe_ras_event_log(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response)
> > +{
> > + struct xe_ras_event_threshold_crossed *pending = (void *)&response->data;
> > + struct xe_ras_error *errors = pending->counters;
> > + struct xe_device *xe = sc_to_xe(sc);
> > + u32 cid, sev, comp, inst, cause;
> > + u8 tile;
> > +
> > + xe_assert(xe, pending->ncounters < XE_RAS_NUM_COUNTERS);
> > + xe_warn(xe, "[RAS]: threshold crossed, %u new errors\n", pending->ncounters);
> > +
> > + for (cid = 0; cid < pending->ncounters && cid < XE_RAS_NUM_COUNTERS; cid++) {
> > + sev = errors[cid].common.severity;
> > + comp = errors[cid].common.component;
> > +
> > + tile = errors[cid].product.unit.tile;
> > + inst = errors[cid].product.unit.instance;
> > + cause = errors[cid].product.cause.cause;
> > +
> > + xe_warn(xe, "[RAS]: Tile:%u Instance:%u Component:%s Error:%s Cause:%#x\n",
> > + tile, inst, comp_to_str(xe, sev), sev_to_str(xe, comp), cause);
>
> We can have minimal logging here with only severity and component and add
> additional logging
>
> in following patches.
I plan to remove it entirely once we have cper in place, but until that
happens (and given the fragility of things) it'll good for debugging.
> > + }
> > +}
> > diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> > new file mode 100644
> > index 000000000000..22f035fa498d
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_ras.h
> > @@ -0,0 +1,14 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_RAS_H_
> > +#define _XE_RAS_H_
> > +
> > +struct xe_sysctrl;
> > +struct xe_sysctrl_event_response;
> > +
> > +void xe_ras_event_log(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response);
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> > new file mode 100644
> > index 000000000000..2982c4696b6d
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> > @@ -0,0 +1,73 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_RAS_TYPES_H_
> > +#define _XE_RAS_TYPES_H_
> > +
> > +#include <linux/types.h>
> > +
> > +#define XE_RAS_NUM_COUNTERS 16
> > +
> > +/**
> > + * struct xe_ras_error_common - Error fields that are common across all products
> > + */
> > +struct xe_ras_error_common {
> > + /** @severity: Error severity */
> > + u8 severity;
> > + /** @component: IP block where error originated */
> > + u8 component;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_error_unit - Error unit information
> > + */
> > +struct xe_ras_error_unit {
> > + /** @tile: Tile identifier */
> > + u8 tile;
> > + /** @instance: Instance identifier specific to IP */
> > + u32 instance;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_error_cause - Error cause information
> > + */
> > +struct xe_ras_error_cause {
> > + /** @cause: Cause/checker */
> > + u32 cause;
> > + /** @reserved: For future use */
> > + u8 reserved;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_error_product - Error fields that are specific to the product
> > + */
> > +struct xe_ras_error_product {
> > + /** @unit: Unit within IP block */
> > + struct xe_ras_error_unit unit;
> > + /** @cause: Cause/checker */
> > + struct xe_ras_error_cause cause;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_error - Combines common and product-specific parts
> > + */
> > +struct xe_ras_error {
>
> error_class ?
I know that how it's in the spec, but it's full of needless verbiage that
doesn't add much to the meaning. I'm fine either way.
Raag
> > + /** @common: Common error type and component */
> > + struct xe_ras_error_common common;
> > + /** @product: Product-specific unit and cause */
> > + struct xe_ras_error_product product;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_event_threshold_crossed - Event data for threshold crossed event
> > + */
> > +struct xe_ras_event_threshold_crossed {
> > + /** @ncounters: Number of error counters that crossed thresholds */
> > + u32 ncounters;
> > + /** @counters: Array of error counters that crossed threshold */
> > + struct xe_ras_error counters[XE_RAS_NUM_COUNTERS];
> > +} __packed;
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > index 47afca586bd1..1833ecadd9a1 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > @@ -6,6 +6,7 @@
> > #include "xe_device.h"
> > #include "xe_irq.h"
> > #include "xe_printk.h"
> > +#include "xe_ras.h"
> > #include "xe_sysctrl.h"
> > #include "xe_sysctrl_event_types.h"
> > #include "xe_sysctrl_mailbox.h"
> > @@ -38,7 +39,7 @@ static void xe_sysctrl_get_pending_event(struct xe_sysctrl *sc,
> > }
> > if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
> > - xe_warn(xe, "[RAS]: error counter threshold crossed\n");
> > + xe_ras_event_log(sc, &response);
> > } else {
> > xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
> > return;
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v3 4/4] drm/xe/ras: Introduce correctable error handling
2026-03-23 11:45 ` Raag Jadav
@ 2026-03-23 14:46 ` Mallesh, Koujalagi
2026-03-24 4:43 ` Raag Jadav
0 siblings, 1 reply; 19+ messages in thread
From: Mallesh, Koujalagi @ 2026-03-23 14:46 UTC (permalink / raw)
To: Raag Jadav
Cc: intel-xe, matthew.brost, rodrigo.vivi, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, soham.purkait,
anoop.c.vijay, aravind.iddamsetty, Riana Tauro
On 23-03-2026 05:15 pm, Raag Jadav wrote:
> On Thu, Mar 19, 2026 at 07:30:06PM +0530, Tauro, Riana wrote:
>> On 3/12/2026 2:36 PM, Raag Jadav wrote:
>>> Add initial support for correctable error handling which is serviced
>>> using system controller event. Currently we only log the errors in
>>> dmesg but this serves as a foundation for RAS infrastructure and will
>>> be further extended to facilitate other RAS features.
>>>
>>> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
>>> ---
>>> drivers/gpu/drm/xe/Makefile | 1 +
>>> drivers/gpu/drm/xe/xe_ras.c | 89 +++++++++++++++++++++++++++
>>> drivers/gpu/drm/xe/xe_ras.h | 14 +++++
>>> drivers/gpu/drm/xe/xe_ras_types.h | 73 ++++++++++++++++++++++
>>> drivers/gpu/drm/xe/xe_sysctrl_event.c | 3 +-
>>> 5 files changed, 179 insertions(+), 1 deletion(-)
>>> create mode 100644 drivers/gpu/drm/xe/xe_ras.c
>>> create mode 100644 drivers/gpu/drm/xe/xe_ras.h
>>> create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
>>>
>>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>>> index 373adb20afb2..9811cf732260 100644
>>> --- a/drivers/gpu/drm/xe/Makefile
>>> +++ b/drivers/gpu/drm/xe/Makefile
>>> @@ -113,6 +113,7 @@ xe-y += xe_bb.o \
>>> xe_pxp_submit.o \
>>> xe_query.o \
>>> xe_range_fence.o \
>>> + xe_ras.o \
>>> xe_reg_sr.o \
>>> xe_reg_whitelist.o \
>>> xe_ring_ops.o \
>>> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
>>> new file mode 100644
>>> index 000000000000..37a996a6abf8
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/xe/xe_ras.c
>>> @@ -0,0 +1,89 @@
>>> +// SPDX-License-Identifier: MIT
>>> +/*
>>> + * Copyright © 2026 Intel Corporation
>>> + */
>>> +
>>> +#include "xe_assert.h"
>>> +#include "xe_printk.h"
>>> +#include "xe_ras.h"
>>> +#include "xe_ras_types.h"
>>> +#include "xe_sysctrl.h"
>>> +#include "xe_sysctrl_event_types.h"
>>> +
>>> +/* Severity of detected errors */
>>> +enum xe_ras_severity {
>>> + XE_RAS_SEV_NOT_SUPPORTED = 0,
>>> + XE_RAS_SEV_CORRECTABLE,
>>> + XE_RAS_SEV_UNCORRECTABLE,
>>> + XE_RAS_SEV_INFORMATIONAL,
>>> + XE_RAS_SEV_MAX
>>> +};
>>> +
>>> +/* Major IP blocks/components where errors can originate */
>>> +enum xe_ras_component {
>>> + XE_RAS_COMP_NOT_SUPPORTED = 0,
>>> + XE_RAS_COMP_DEVICE_MEMORY,
>>> + XE_RAS_COMP_CORE_COMPUTE,
>>> + XE_RAS_COMP_RESERVED,
>>> + XE_RAS_COMP_PCIE,
>>> + XE_RAS_COMP_FABRIC,
>>> + XE_RAS_COMP_SOC_INTERNAL,
>>> + XE_RAS_COMP_MAX
>>> +};
>>> +
>>> +static const char *const xe_ras_severities[] = {
>>> + [XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported",
>>> + [XE_RAS_SEV_CORRECTABLE] = "Correctable",
>>> + [XE_RAS_SEV_UNCORRECTABLE] = "Uncorrectable",
>>> + [XE_RAS_SEV_INFORMATIONAL] = "Informational",
>>> +};
>>> +static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
>>> +
>>> +static const char *const xe_ras_components[] = {
>>> + [XE_RAS_COMP_NOT_SUPPORTED] = "Not Supported",
>>> + [XE_RAS_COMP_DEVICE_MEMORY] = "Device Memory",
>>> + [XE_RAS_COMP_CORE_COMPUTE] = "Core Compute",
>>> + [XE_RAS_COMP_RESERVED] = "Reserved",
>>> + [XE_RAS_COMP_PCIE] = "PCIe",
>>> + [XE_RAS_COMP_FABRIC] = "Fabric",
>>> + [XE_RAS_COMP_SOC_INTERNAL] = "SoC Internal",
>>> +};
>>> +static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
>>> +
>>> +static inline const char *sev_to_str(struct xe_device *xe, u32 sev)
>>> +{
>>> + xe_assert(xe, sev < XE_RAS_SEV_MAX);
>>> +
>>> + return sev < XE_RAS_SEV_MAX ? xe_ras_severities[sev] : "Unknown";
>>> +}
>>> +
>>> +static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
>>> +{
>>> + xe_assert(xe, comp < XE_RAS_COMP_MAX);
>>> +
>>> + return comp < XE_RAS_COMP_MAX ? xe_ras_components[comp] : "Unknown";
>>> +}
>>> +
>>> +void xe_ras_event_log(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response)
>>> +{
>>> + struct xe_ras_event_threshold_crossed *pending = (void *)&response->data;
>>> + struct xe_ras_error *errors = pending->counters;
>>> + struct xe_device *xe = sc_to_xe(sc);
>>> + u32 cid, sev, comp, inst, cause;
>>> + u8 tile;
>>> +
>>> + xe_assert(xe, pending->ncounters < XE_RAS_NUM_COUNTERS);
>>> + xe_warn(xe, "[RAS]: threshold crossed, %u new errors\n", pending->ncounters);
>>> +
>>> + for (cid = 0; cid < pending->ncounters && cid < XE_RAS_NUM_COUNTERS; cid++) {
>>> + sev = errors[cid].common.severity;
>>> + comp = errors[cid].common.component;
>>> +
>>> + tile = errors[cid].product.unit.tile;
>>> + inst = errors[cid].product.unit.instance;
>>> + cause = errors[cid].product.cause.cause;
>>> +
>>> + xe_warn(xe, "[RAS]: Tile:%u Instance:%u Component:%s Error:%s Cause:%#x\n",
>>> + tile, inst, comp_to_str(xe, sev), sev_to_str(xe, comp), cause);
Please fix Severity/Component Parameter Swap.
Thanks,
-/Mallesh
>> We can have minimal logging here with only severity and component and add
>> additional logging
>>
>> in following patches.
> I plan to remove it entirely once we have cper in place, but until that
> happens (and given the fragility of things) it'll good for debugging.
>
>>> + }
>>> +}
>>> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
>>> new file mode 100644
>>> index 000000000000..22f035fa498d
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/xe/xe_ras.h
>>> @@ -0,0 +1,14 @@
>>> +/* SPDX-License-Identifier: MIT */
>>> +/*
>>> + * Copyright © 2026 Intel Corporation
>>> + */
>>> +
>>> +#ifndef _XE_RAS_H_
>>> +#define _XE_RAS_H_
>>> +
>>> +struct xe_sysctrl;
>>> +struct xe_sysctrl_event_response;
>>> +
>>> +void xe_ras_event_log(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response);
>>> +
>>> +#endif
>>> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
>>> new file mode 100644
>>> index 000000000000..2982c4696b6d
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
>>> @@ -0,0 +1,73 @@
>>> +/* SPDX-License-Identifier: MIT */
>>> +/*
>>> + * Copyright © 2026 Intel Corporation
>>> + */
>>> +
>>> +#ifndef _XE_RAS_TYPES_H_
>>> +#define _XE_RAS_TYPES_H_
>>> +
>>> +#include <linux/types.h>
>>> +
>>> +#define XE_RAS_NUM_COUNTERS 16
>>> +
>>> +/**
>>> + * struct xe_ras_error_common - Error fields that are common across all products
>>> + */
>>> +struct xe_ras_error_common {
>>> + /** @severity: Error severity */
>>> + u8 severity;
>>> + /** @component: IP block where error originated */
>>> + u8 component;
>>> +} __packed;
>>> +
>>> +/**
>>> + * struct xe_ras_error_unit - Error unit information
>>> + */
>>> +struct xe_ras_error_unit {
>>> + /** @tile: Tile identifier */
>>> + u8 tile;
>>> + /** @instance: Instance identifier specific to IP */
>>> + u32 instance;
>>> +} __packed;
>>> +
>>> +/**
>>> + * struct xe_ras_error_cause - Error cause information
>>> + */
>>> +struct xe_ras_error_cause {
>>> + /** @cause: Cause/checker */
>>> + u32 cause;
>>> + /** @reserved: For future use */
>>> + u8 reserved;
>>> +} __packed;
>>> +
>>> +/**
>>> + * struct xe_ras_error_product - Error fields that are specific to the product
>>> + */
>>> +struct xe_ras_error_product {
>>> + /** @unit: Unit within IP block */
>>> + struct xe_ras_error_unit unit;
>>> + /** @cause: Cause/checker */
>>> + struct xe_ras_error_cause cause;
>>> +} __packed;
>>> +
>>> +/**
>>> + * struct xe_ras_error - Combines common and product-specific parts
>>> + */
>>> +struct xe_ras_error {
>> error_class ?
> I know that how it's in the spec, but it's full of needless verbiage that
> doesn't add much to the meaning. I'm fine either way.
>
> Raag
>
>>> + /** @common: Common error type and component */
>>> + struct xe_ras_error_common common;
>>> + /** @product: Product-specific unit and cause */
>>> + struct xe_ras_error_product product;
>>> +} __packed;
>>> +
>>> +/**
>>> + * struct xe_ras_event_threshold_crossed - Event data for threshold crossed event
>>> + */
>>> +struct xe_ras_event_threshold_crossed {
>>> + /** @ncounters: Number of error counters that crossed thresholds */
>>> + u32 ncounters;
>>> + /** @counters: Array of error counters that crossed threshold */
>>> + struct xe_ras_error counters[XE_RAS_NUM_COUNTERS];
>>> +} __packed;
>>> +
>>> +#endif
>>> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
>>> index 47afca586bd1..1833ecadd9a1 100644
>>> --- a/drivers/gpu/drm/xe/xe_sysctrl_event.c
>>> +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
>>> @@ -6,6 +6,7 @@
>>> #include "xe_device.h"
>>> #include "xe_irq.h"
>>> #include "xe_printk.h"
>>> +#include "xe_ras.h"
>>> #include "xe_sysctrl.h"
>>> #include "xe_sysctrl_event_types.h"
>>> #include "xe_sysctrl_mailbox.h"
>>> @@ -38,7 +39,7 @@ static void xe_sysctrl_get_pending_event(struct xe_sysctrl *sc,
>>> }
>>> if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
>>> - xe_warn(xe, "[RAS]: error counter threshold crossed\n");
>>> + xe_ras_event_log(sc, &response);
>>> } else {
>>> xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
>>> return;
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v3 4/4] drm/xe/ras: Introduce correctable error handling
2026-03-23 14:46 ` Mallesh, Koujalagi
@ 2026-03-24 4:43 ` Raag Jadav
0 siblings, 0 replies; 19+ messages in thread
From: Raag Jadav @ 2026-03-24 4:43 UTC (permalink / raw)
To: Mallesh, Koujalagi
Cc: intel-xe, matthew.brost, rodrigo.vivi, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, soham.purkait,
anoop.c.vijay, aravind.iddamsetty, Riana Tauro
On Mon, Mar 23, 2026 at 08:16:23PM +0530, Mallesh, Koujalagi wrote:
> On 23-03-2026 05:15 pm, Raag Jadav wrote:
> > On Thu, Mar 19, 2026 at 07:30:06PM +0530, Tauro, Riana wrote:
> > > On 3/12/2026 2:36 PM, Raag Jadav wrote:
> > > > Add initial support for correctable error handling which is serviced
> > > > using system controller event. Currently we only log the errors in
> > > > dmesg but this serves as a foundation for RAS infrastructure and will
> > > > be further extended to facilitate other RAS features.
> > > >
> > > > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > > > ---
> > > > drivers/gpu/drm/xe/Makefile | 1 +
> > > > drivers/gpu/drm/xe/xe_ras.c | 89 +++++++++++++++++++++++++++
> > > > drivers/gpu/drm/xe/xe_ras.h | 14 +++++
> > > > drivers/gpu/drm/xe/xe_ras_types.h | 73 ++++++++++++++++++++++
> > > > drivers/gpu/drm/xe/xe_sysctrl_event.c | 3 +-
> > > > 5 files changed, 179 insertions(+), 1 deletion(-)
> > > > create mode 100644 drivers/gpu/drm/xe/xe_ras.c
> > > > create mode 100644 drivers/gpu/drm/xe/xe_ras.h
> > > > create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
> > > >
> > > > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > > > index 373adb20afb2..9811cf732260 100644
> > > > --- a/drivers/gpu/drm/xe/Makefile
> > > > +++ b/drivers/gpu/drm/xe/Makefile
> > > > @@ -113,6 +113,7 @@ xe-y += xe_bb.o \
> > > > xe_pxp_submit.o \
> > > > xe_query.o \
> > > > xe_range_fence.o \
> > > > + xe_ras.o \
> > > > xe_reg_sr.o \
> > > > xe_reg_whitelist.o \
> > > > xe_ring_ops.o \
> > > > diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> > > > new file mode 100644
> > > > index 000000000000..37a996a6abf8
> > > > --- /dev/null
> > > > +++ b/drivers/gpu/drm/xe/xe_ras.c
> > > > @@ -0,0 +1,89 @@
> > > > +// SPDX-License-Identifier: MIT
> > > > +/*
> > > > + * Copyright © 2026 Intel Corporation
> > > > + */
> > > > +
> > > > +#include "xe_assert.h"
> > > > +#include "xe_printk.h"
> > > > +#include "xe_ras.h"
> > > > +#include "xe_ras_types.h"
> > > > +#include "xe_sysctrl.h"
> > > > +#include "xe_sysctrl_event_types.h"
> > > > +
> > > > +/* Severity of detected errors */
> > > > +enum xe_ras_severity {
> > > > + XE_RAS_SEV_NOT_SUPPORTED = 0,
> > > > + XE_RAS_SEV_CORRECTABLE,
> > > > + XE_RAS_SEV_UNCORRECTABLE,
> > > > + XE_RAS_SEV_INFORMATIONAL,
> > > > + XE_RAS_SEV_MAX
> > > > +};
> > > > +
> > > > +/* Major IP blocks/components where errors can originate */
> > > > +enum xe_ras_component {
> > > > + XE_RAS_COMP_NOT_SUPPORTED = 0,
> > > > + XE_RAS_COMP_DEVICE_MEMORY,
> > > > + XE_RAS_COMP_CORE_COMPUTE,
> > > > + XE_RAS_COMP_RESERVED,
> > > > + XE_RAS_COMP_PCIE,
> > > > + XE_RAS_COMP_FABRIC,
> > > > + XE_RAS_COMP_SOC_INTERNAL,
> > > > + XE_RAS_COMP_MAX
> > > > +};
> > > > +
> > > > +static const char *const xe_ras_severities[] = {
> > > > + [XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported",
> > > > + [XE_RAS_SEV_CORRECTABLE] = "Correctable",
> > > > + [XE_RAS_SEV_UNCORRECTABLE] = "Uncorrectable",
> > > > + [XE_RAS_SEV_INFORMATIONAL] = "Informational",
> > > > +};
> > > > +static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
> > > > +
> > > > +static const char *const xe_ras_components[] = {
> > > > + [XE_RAS_COMP_NOT_SUPPORTED] = "Not Supported",
> > > > + [XE_RAS_COMP_DEVICE_MEMORY] = "Device Memory",
> > > > + [XE_RAS_COMP_CORE_COMPUTE] = "Core Compute",
> > > > + [XE_RAS_COMP_RESERVED] = "Reserved",
> > > > + [XE_RAS_COMP_PCIE] = "PCIe",
> > > > + [XE_RAS_COMP_FABRIC] = "Fabric",
> > > > + [XE_RAS_COMP_SOC_INTERNAL] = "SoC Internal",
> > > > +};
> > > > +static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
> > > > +
> > > > +static inline const char *sev_to_str(struct xe_device *xe, u32 sev)
> > > > +{
> > > > + xe_assert(xe, sev < XE_RAS_SEV_MAX);
> > > > +
> > > > + return sev < XE_RAS_SEV_MAX ? xe_ras_severities[sev] : "Unknown";
> > > > +}
> > > > +
> > > > +static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
> > > > +{
> > > > + xe_assert(xe, comp < XE_RAS_COMP_MAX);
> > > > +
> > > > + return comp < XE_RAS_COMP_MAX ? xe_ras_components[comp] : "Unknown";
> > > > +}
> > > > +
> > > > +void xe_ras_event_log(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response)
> > > > +{
> > > > + struct xe_ras_event_threshold_crossed *pending = (void *)&response->data;
> > > > + struct xe_ras_error *errors = pending->counters;
> > > > + struct xe_device *xe = sc_to_xe(sc);
> > > > + u32 cid, sev, comp, inst, cause;
> > > > + u8 tile;
> > > > +
> > > > + xe_assert(xe, pending->ncounters < XE_RAS_NUM_COUNTERS);
> > > > + xe_warn(xe, "[RAS]: threshold crossed, %u new errors\n", pending->ncounters);
> > > > +
> > > > + for (cid = 0; cid < pending->ncounters && cid < XE_RAS_NUM_COUNTERS; cid++) {
> > > > + sev = errors[cid].common.severity;
> > > > + comp = errors[cid].common.component;
> > > > +
> > > > + tile = errors[cid].product.unit.tile;
> > > > + inst = errors[cid].product.unit.instance;
> > > > + cause = errors[cid].product.cause.cause;
> > > > +
> > > > + xe_warn(xe, "[RAS]: Tile:%u Instance:%u Component:%s Error:%s Cause:%#x\n",
> > > > + tile, inst, comp_to_str(xe, sev), sev_to_str(xe, comp), cause);
>
> Please fix Severity/Component Parameter Swap.
Yep, missed it.
Raag
> > > We can have minimal logging here with only severity and component and add
> > > additional logging
> > >
> > > in following patches.
> > I plan to remove it entirely once we have cper in place, but until that
> > happens (and given the fragility of things) it'll good for debugging.
> >
> > > > + }
> > > > +}
> > > > diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> > > > new file mode 100644
> > > > index 000000000000..22f035fa498d
> > > > --- /dev/null
> > > > +++ b/drivers/gpu/drm/xe/xe_ras.h
> > > > @@ -0,0 +1,14 @@
> > > > +/* SPDX-License-Identifier: MIT */
> > > > +/*
> > > > + * Copyright © 2026 Intel Corporation
> > > > + */
> > > > +
> > > > +#ifndef _XE_RAS_H_
> > > > +#define _XE_RAS_H_
> > > > +
> > > > +struct xe_sysctrl;
> > > > +struct xe_sysctrl_event_response;
> > > > +
> > > > +void xe_ras_event_log(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response);
> > > > +
> > > > +#endif
> > > > diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> > > > new file mode 100644
> > > > index 000000000000..2982c4696b6d
> > > > --- /dev/null
> > > > +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> > > > @@ -0,0 +1,73 @@
> > > > +/* SPDX-License-Identifier: MIT */
> > > > +/*
> > > > + * Copyright © 2026 Intel Corporation
> > > > + */
> > > > +
> > > > +#ifndef _XE_RAS_TYPES_H_
> > > > +#define _XE_RAS_TYPES_H_
> > > > +
> > > > +#include <linux/types.h>
> > > > +
> > > > +#define XE_RAS_NUM_COUNTERS 16
> > > > +
> > > > +/**
> > > > + * struct xe_ras_error_common - Error fields that are common across all products
> > > > + */
> > > > +struct xe_ras_error_common {
> > > > + /** @severity: Error severity */
> > > > + u8 severity;
> > > > + /** @component: IP block where error originated */
> > > > + u8 component;
> > > > +} __packed;
> > > > +
> > > > +/**
> > > > + * struct xe_ras_error_unit - Error unit information
> > > > + */
> > > > +struct xe_ras_error_unit {
> > > > + /** @tile: Tile identifier */
> > > > + u8 tile;
> > > > + /** @instance: Instance identifier specific to IP */
> > > > + u32 instance;
> > > > +} __packed;
> > > > +
> > > > +/**
> > > > + * struct xe_ras_error_cause - Error cause information
> > > > + */
> > > > +struct xe_ras_error_cause {
> > > > + /** @cause: Cause/checker */
> > > > + u32 cause;
> > > > + /** @reserved: For future use */
> > > > + u8 reserved;
> > > > +} __packed;
> > > > +
> > > > +/**
> > > > + * struct xe_ras_error_product - Error fields that are specific to the product
> > > > + */
> > > > +struct xe_ras_error_product {
> > > > + /** @unit: Unit within IP block */
> > > > + struct xe_ras_error_unit unit;
> > > > + /** @cause: Cause/checker */
> > > > + struct xe_ras_error_cause cause;
> > > > +} __packed;
> > > > +
> > > > +/**
> > > > + * struct xe_ras_error - Combines common and product-specific parts
> > > > + */
> > > > +struct xe_ras_error {
> > > error_class ?
> > I know that how it's in the spec, but it's full of needless verbiage that
> > doesn't add much to the meaning. I'm fine either way.
> >
> > Raag
> >
> > > > + /** @common: Common error type and component */
> > > > + struct xe_ras_error_common common;
> > > > + /** @product: Product-specific unit and cause */
> > > > + struct xe_ras_error_product product;
> > > > +} __packed;
> > > > +
> > > > +/**
> > > > + * struct xe_ras_event_threshold_crossed - Event data for threshold crossed event
> > > > + */
> > > > +struct xe_ras_event_threshold_crossed {
> > > > + /** @ncounters: Number of error counters that crossed thresholds */
> > > > + u32 ncounters;
> > > > + /** @counters: Array of error counters that crossed threshold */
> > > > + struct xe_ras_error counters[XE_RAS_NUM_COUNTERS];
> > > > +} __packed;
> > > > +
> > > > +#endif
> > > > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > > > index 47afca586bd1..1833ecadd9a1 100644
> > > > --- a/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > > > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > > > @@ -6,6 +6,7 @@
> > > > #include "xe_device.h"
> > > > #include "xe_irq.h"
> > > > #include "xe_printk.h"
> > > > +#include "xe_ras.h"
> > > > #include "xe_sysctrl.h"
> > > > #include "xe_sysctrl_event_types.h"
> > > > #include "xe_sysctrl_mailbox.h"
> > > > @@ -38,7 +39,7 @@ static void xe_sysctrl_get_pending_event(struct xe_sysctrl *sc,
> > > > }
> > > > if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
> > > > - xe_warn(xe, "[RAS]: error counter threshold crossed\n");
> > > > + xe_ras_event_log(sc, &response);
> > > > } else {
> > > > xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
> > > > return;
^ permalink raw reply [flat|nested] 19+ messages in thread
* ✗ CI.checkpatch: warning for Introduce Xe Correctable Error Handling (rev3)
2026-03-12 9:06 [PATCH v3 0/4] Introduce Xe Correctable Error Handling Raag Jadav
` (3 preceding siblings ...)
2026-03-12 9:06 ` [PATCH v3 4/4] drm/xe/ras: Introduce correctable error handling Raag Jadav
@ 2026-03-12 10:27 ` Patchwork
2026-03-12 10:28 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2026-03-12 10:27 UTC (permalink / raw)
To: Raag Jadav; +Cc: intel-xe
== Series Details ==
Series: Introduce Xe Correctable Error Handling (rev3)
URL : https://patchwork.freedesktop.org/series/160184/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 7f5afc3640464ff04b27d2ae1ee2635021c317b3
Author: Raag Jadav <raag.jadav@intel.com>
Date: Thu Mar 12 14:36:57 2026 +0530
drm/xe/ras: Introduce correctable error handling
Add initial support for correctable error handling which is serviced
using system controller event. Currently we only log the errors in
dmesg but this serves as a foundation for RAS infrastructure and will
be further extended to facilitate other RAS features.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
+ /mt/dim checkpatch a0e231ebb0df84f6febf147ee5fcaafd40c2dafe drm-intel
e888fb13cfad drm/xe/sysctrl: Add System Controller
-:24: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#24:
new file mode 100644
-:537: WARNING:LINE_SPACING: Missing a blank line after declarations
#537: FILE: drivers/gpu/drm/xe/xe_sysctrl_mailbox.c:227:
+ size_t remain = sizeof(*schi_hdr) + data_out_len;
+ u8 *buffer __free(kfree) = kzalloc(remain, GFP_KERNEL);
-:790: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Anoop Vijay <anoop.c.vijay@intel.com>'
total: 1 errors, 2 warnings, 0 checks, 704 lines checked
faccaf4f539a drm/xe/sysctrl: Add system controller interrupt handler
5a9a480770d6 drm/xe/sysctrl: Add system controller event support
-:51: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 173 lines checked
7f5afc364046 drm/xe/ras: Introduce correctable error handling
-:26: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#26:
new file mode 100644
-:70: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#70: FILE: drivers/gpu/drm/xe/xe_ras.c:40:
+};
+static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
-:81: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#81: FILE: drivers/gpu/drm/xe/xe_ras.c:51:
+};
+static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
total: 0 errors, 1 warnings, 2 checks, 198 lines checked
^ permalink raw reply [flat|nested] 19+ messages in thread* ✓ CI.KUnit: success for Introduce Xe Correctable Error Handling (rev3)
2026-03-12 9:06 [PATCH v3 0/4] Introduce Xe Correctable Error Handling Raag Jadav
` (4 preceding siblings ...)
2026-03-12 10:27 ` ✗ CI.checkpatch: warning for Introduce Xe Correctable Error Handling (rev3) Patchwork
@ 2026-03-12 10:28 ` Patchwork
2026-03-12 11:15 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-13 6:22 ` ✓ Xe.CI.FULL: " Patchwork
7 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2026-03-12 10:28 UTC (permalink / raw)
To: Raag Jadav; +Cc: intel-xe
== Series Details ==
Series: Introduce Xe Correctable Error Handling (rev3)
URL : https://patchwork.freedesktop.org/series/160184/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[10:27:32] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:27:36] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:28:07] Starting KUnit Kernel (1/1)...
[10:28:07] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:28:07] ================== guc_buf (11 subtests) ===================
[10:28:07] [PASSED] test_smallest
[10:28:07] [PASSED] test_largest
[10:28:07] [PASSED] test_granular
[10:28:07] [PASSED] test_unique
[10:28:07] [PASSED] test_overlap
[10:28:07] [PASSED] test_reusable
[10:28:07] [PASSED] test_too_big
[10:28:07] [PASSED] test_flush
[10:28:07] [PASSED] test_lookup
[10:28:07] [PASSED] test_data
[10:28:07] [PASSED] test_class
[10:28:07] ===================== [PASSED] guc_buf =====================
[10:28:07] =================== guc_dbm (7 subtests) ===================
[10:28:07] [PASSED] test_empty
[10:28:07] [PASSED] test_default
[10:28:07] ======================== test_size ========================
[10:28:07] [PASSED] 4
[10:28:07] [PASSED] 8
[10:28:07] [PASSED] 32
[10:28:07] [PASSED] 256
[10:28:07] ==================== [PASSED] test_size ====================
[10:28:07] ======================= test_reuse ========================
[10:28:07] [PASSED] 4
[10:28:07] [PASSED] 8
[10:28:07] [PASSED] 32
[10:28:07] [PASSED] 256
[10:28:07] =================== [PASSED] test_reuse ====================
[10:28:07] =================== test_range_overlap ====================
[10:28:07] [PASSED] 4
[10:28:07] [PASSED] 8
[10:28:07] [PASSED] 32
[10:28:07] [PASSED] 256
[10:28:07] =============== [PASSED] test_range_overlap ================
[10:28:07] =================== test_range_compact ====================
[10:28:07] [PASSED] 4
[10:28:07] [PASSED] 8
[10:28:07] [PASSED] 32
[10:28:07] [PASSED] 256
[10:28:07] =============== [PASSED] test_range_compact ================
[10:28:07] ==================== test_range_spare =====================
[10:28:07] [PASSED] 4
[10:28:07] [PASSED] 8
[10:28:07] [PASSED] 32
[10:28:07] [PASSED] 256
[10:28:07] ================ [PASSED] test_range_spare =================
[10:28:07] ===================== [PASSED] guc_dbm =====================
[10:28:07] =================== guc_idm (6 subtests) ===================
[10:28:07] [PASSED] bad_init
[10:28:07] [PASSED] no_init
[10:28:07] [PASSED] init_fini
[10:28:07] [PASSED] check_used
[10:28:07] [PASSED] check_quota
[10:28:07] [PASSED] check_all
[10:28:07] ===================== [PASSED] guc_idm =====================
[10:28:07] ================== no_relay (3 subtests) ===================
[10:28:07] [PASSED] xe_drops_guc2pf_if_not_ready
[10:28:07] [PASSED] xe_drops_guc2vf_if_not_ready
[10:28:07] [PASSED] xe_rejects_send_if_not_ready
[10:28:07] ==================== [PASSED] no_relay =====================
[10:28:07] ================== pf_relay (14 subtests) ==================
[10:28:07] [PASSED] pf_rejects_guc2pf_too_short
[10:28:07] [PASSED] pf_rejects_guc2pf_too_long
[10:28:07] [PASSED] pf_rejects_guc2pf_no_payload
[10:28:07] [PASSED] pf_fails_no_payload
[10:28:07] [PASSED] pf_fails_bad_origin
[10:28:07] [PASSED] pf_fails_bad_type
[10:28:07] [PASSED] pf_txn_reports_error
[10:28:07] [PASSED] pf_txn_sends_pf2guc
[10:28:07] [PASSED] pf_sends_pf2guc
[10:28:07] [SKIPPED] pf_loopback_nop
[10:28:07] [SKIPPED] pf_loopback_echo
[10:28:07] [SKIPPED] pf_loopback_fail
[10:28:07] [SKIPPED] pf_loopback_busy
[10:28:07] [SKIPPED] pf_loopback_retry
[10:28:07] ==================== [PASSED] pf_relay =====================
[10:28:07] ================== vf_relay (3 subtests) ===================
[10:28:07] [PASSED] vf_rejects_guc2vf_too_short
[10:28:07] [PASSED] vf_rejects_guc2vf_too_long
[10:28:07] [PASSED] vf_rejects_guc2vf_no_payload
[10:28:07] ==================== [PASSED] vf_relay =====================
[10:28:07] ================ pf_gt_config (9 subtests) =================
[10:28:07] [PASSED] fair_contexts_1vf
[10:28:07] [PASSED] fair_doorbells_1vf
[10:28:07] [PASSED] fair_ggtt_1vf
[10:28:07] ====================== fair_vram_1vf ======================
[10:28:07] [PASSED] 3.50 GiB
[10:28:07] [PASSED] 11.5 GiB
[10:28:07] [PASSED] 15.5 GiB
[10:28:07] [PASSED] 31.5 GiB
[10:28:07] [PASSED] 63.5 GiB
[10:28:07] [PASSED] 1.91 GiB
[10:28:07] ================== [PASSED] fair_vram_1vf ==================
[10:28:07] ================ fair_vram_1vf_admin_only =================
[10:28:07] [PASSED] 3.50 GiB
[10:28:07] [PASSED] 11.5 GiB
[10:28:07] [PASSED] 15.5 GiB
[10:28:07] [PASSED] 31.5 GiB
[10:28:07] [PASSED] 63.5 GiB
[10:28:07] [PASSED] 1.91 GiB
[10:28:07] ============ [PASSED] fair_vram_1vf_admin_only =============
[10:28:07] ====================== fair_contexts ======================
[10:28:07] [PASSED] 1 VF
[10:28:07] [PASSED] 2 VFs
[10:28:07] [PASSED] 3 VFs
[10:28:07] [PASSED] 4 VFs
[10:28:07] [PASSED] 5 VFs
[10:28:07] [PASSED] 6 VFs
[10:28:07] [PASSED] 7 VFs
[10:28:07] [PASSED] 8 VFs
[10:28:07] [PASSED] 9 VFs
[10:28:07] [PASSED] 10 VFs
[10:28:07] [PASSED] 11 VFs
[10:28:07] [PASSED] 12 VFs
[10:28:07] [PASSED] 13 VFs
[10:28:07] [PASSED] 14 VFs
[10:28:07] [PASSED] 15 VFs
[10:28:07] [PASSED] 16 VFs
[10:28:07] [PASSED] 17 VFs
[10:28:07] [PASSED] 18 VFs
[10:28:07] [PASSED] 19 VFs
[10:28:07] [PASSED] 20 VFs
[10:28:07] [PASSED] 21 VFs
[10:28:07] [PASSED] 22 VFs
[10:28:07] [PASSED] 23 VFs
[10:28:07] [PASSED] 24 VFs
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[10:28:07] [PASSED] 26 VFs
[10:28:07] [PASSED] 27 VFs
[10:28:07] [PASSED] 28 VFs
[10:28:07] [PASSED] 29 VFs
[10:28:07] [PASSED] 30 VFs
[10:28:07] [PASSED] 31 VFs
[10:28:07] [PASSED] 32 VFs
[10:28:07] [PASSED] 33 VFs
[10:28:07] [PASSED] 34 VFs
[10:28:07] [PASSED] 35 VFs
[10:28:07] [PASSED] 36 VFs
[10:28:07] [PASSED] 37 VFs
[10:28:07] [PASSED] 38 VFs
[10:28:07] [PASSED] 39 VFs
[10:28:07] [PASSED] 40 VFs
[10:28:07] [PASSED] 41 VFs
[10:28:07] [PASSED] 42 VFs
[10:28:07] [PASSED] 43 VFs
[10:28:07] [PASSED] 44 VFs
[10:28:07] [PASSED] 45 VFs
[10:28:07] [PASSED] 46 VFs
[10:28:07] [PASSED] 47 VFs
[10:28:07] [PASSED] 48 VFs
[10:28:07] [PASSED] 49 VFs
[10:28:07] [PASSED] 50 VFs
[10:28:07] [PASSED] 51 VFs
[10:28:07] [PASSED] 52 VFs
[10:28:07] [PASSED] 53 VFs
[10:28:07] [PASSED] 54 VFs
[10:28:07] [PASSED] 55 VFs
[10:28:07] [PASSED] 56 VFs
[10:28:07] [PASSED] 57 VFs
[10:28:07] [PASSED] 58 VFs
[10:28:07] [PASSED] 59 VFs
[10:28:07] [PASSED] 60 VFs
[10:28:07] [PASSED] 61 VFs
[10:28:07] [PASSED] 62 VFs
[10:28:07] [PASSED] 63 VFs
[10:28:07] ================== [PASSED] fair_contexts ==================
[10:28:07] ===================== fair_doorbells ======================
[10:28:07] [PASSED] 1 VF
[10:28:07] [PASSED] 2 VFs
[10:28:07] [PASSED] 3 VFs
[10:28:07] [PASSED] 4 VFs
[10:28:07] [PASSED] 5 VFs
[10:28:07] [PASSED] 6 VFs
[10:28:07] [PASSED] 7 VFs
[10:28:07] [PASSED] 8 VFs
[10:28:07] [PASSED] 9 VFs
[10:28:07] [PASSED] 10 VFs
[10:28:07] [PASSED] 11 VFs
[10:28:07] [PASSED] 12 VFs
[10:28:07] [PASSED] 13 VFs
[10:28:07] [PASSED] 14 VFs
[10:28:07] [PASSED] 15 VFs
[10:28:07] [PASSED] 16 VFs
[10:28:07] [PASSED] 17 VFs
[10:28:07] [PASSED] 18 VFs
[10:28:07] [PASSED] 19 VFs
[10:28:07] [PASSED] 20 VFs
[10:28:07] [PASSED] 21 VFs
[10:28:07] [PASSED] 22 VFs
[10:28:07] [PASSED] 23 VFs
[10:28:07] [PASSED] 24 VFs
[10:28:07] [PASSED] 25 VFs
[10:28:07] [PASSED] 26 VFs
[10:28:07] [PASSED] 27 VFs
[10:28:07] [PASSED] 28 VFs
[10:28:07] [PASSED] 29 VFs
[10:28:07] [PASSED] 30 VFs
[10:28:07] [PASSED] 31 VFs
[10:28:07] [PASSED] 32 VFs
[10:28:07] [PASSED] 33 VFs
[10:28:07] [PASSED] 34 VFs
[10:28:07] [PASSED] 35 VFs
[10:28:07] [PASSED] 36 VFs
[10:28:07] [PASSED] 37 VFs
[10:28:07] [PASSED] 38 VFs
[10:28:07] [PASSED] 39 VFs
[10:28:07] [PASSED] 40 VFs
[10:28:07] [PASSED] 41 VFs
[10:28:07] [PASSED] 42 VFs
[10:28:07] [PASSED] 43 VFs
[10:28:07] [PASSED] 44 VFs
[10:28:07] [PASSED] 45 VFs
[10:28:07] [PASSED] 46 VFs
[10:28:07] [PASSED] 47 VFs
[10:28:07] [PASSED] 48 VFs
[10:28:07] [PASSED] 49 VFs
[10:28:07] [PASSED] 50 VFs
[10:28:07] [PASSED] 51 VFs
[10:28:07] [PASSED] 52 VFs
[10:28:07] [PASSED] 53 VFs
[10:28:07] [PASSED] 54 VFs
[10:28:07] [PASSED] 55 VFs
[10:28:07] [PASSED] 56 VFs
[10:28:07] [PASSED] 57 VFs
[10:28:07] [PASSED] 58 VFs
[10:28:07] [PASSED] 59 VFs
[10:28:07] [PASSED] 60 VFs
[10:28:07] [PASSED] 61 VFs
[10:28:07] [PASSED] 62 VFs
[10:28:07] [PASSED] 63 VFs
[10:28:07] ================= [PASSED] fair_doorbells ==================
[10:28:07] ======================== fair_ggtt ========================
[10:28:07] [PASSED] 1 VF
[10:28:07] [PASSED] 2 VFs
[10:28:07] [PASSED] 3 VFs
[10:28:07] [PASSED] 4 VFs
[10:28:07] [PASSED] 5 VFs
[10:28:07] [PASSED] 6 VFs
[10:28:07] [PASSED] 7 VFs
[10:28:07] [PASSED] 8 VFs
[10:28:07] [PASSED] 9 VFs
[10:28:07] [PASSED] 10 VFs
[10:28:07] [PASSED] 11 VFs
[10:28:07] [PASSED] 12 VFs
[10:28:07] [PASSED] 13 VFs
[10:28:07] [PASSED] 14 VFs
[10:28:07] [PASSED] 15 VFs
[10:28:07] [PASSED] 16 VFs
[10:28:07] [PASSED] 17 VFs
[10:28:07] [PASSED] 18 VFs
[10:28:07] [PASSED] 19 VFs
[10:28:07] [PASSED] 20 VFs
[10:28:07] [PASSED] 21 VFs
[10:28:07] [PASSED] 22 VFs
[10:28:07] [PASSED] 23 VFs
[10:28:07] [PASSED] 24 VFs
[10:28:07] [PASSED] 25 VFs
[10:28:07] [PASSED] 26 VFs
[10:28:07] [PASSED] 27 VFs
[10:28:07] [PASSED] 28 VFs
[10:28:07] [PASSED] 29 VFs
[10:28:07] [PASSED] 30 VFs
[10:28:07] [PASSED] 31 VFs
[10:28:07] [PASSED] 32 VFs
[10:28:07] [PASSED] 33 VFs
[10:28:07] [PASSED] 34 VFs
[10:28:07] [PASSED] 35 VFs
[10:28:07] [PASSED] 36 VFs
[10:28:07] [PASSED] 37 VFs
[10:28:07] [PASSED] 38 VFs
[10:28:07] [PASSED] 39 VFs
[10:28:07] [PASSED] 40 VFs
[10:28:07] [PASSED] 41 VFs
[10:28:07] [PASSED] 42 VFs
[10:28:07] [PASSED] 43 VFs
[10:28:07] [PASSED] 44 VFs
[10:28:07] [PASSED] 45 VFs
[10:28:07] [PASSED] 46 VFs
[10:28:07] [PASSED] 47 VFs
[10:28:07] [PASSED] 48 VFs
[10:28:07] [PASSED] 49 VFs
[10:28:07] [PASSED] 50 VFs
[10:28:07] [PASSED] 51 VFs
[10:28:07] [PASSED] 52 VFs
[10:28:07] [PASSED] 53 VFs
[10:28:07] [PASSED] 54 VFs
[10:28:07] [PASSED] 55 VFs
[10:28:07] [PASSED] 56 VFs
[10:28:07] [PASSED] 57 VFs
[10:28:07] [PASSED] 58 VFs
[10:28:07] [PASSED] 59 VFs
[10:28:07] [PASSED] 60 VFs
[10:28:07] [PASSED] 61 VFs
[10:28:07] [PASSED] 62 VFs
[10:28:07] [PASSED] 63 VFs
[10:28:07] ==================== [PASSED] fair_ggtt ====================
[10:28:07] ======================== fair_vram ========================
[10:28:07] [PASSED] 1 VF
[10:28:07] [PASSED] 2 VFs
[10:28:07] [PASSED] 3 VFs
[10:28:07] [PASSED] 4 VFs
[10:28:07] [PASSED] 5 VFs
[10:28:07] [PASSED] 6 VFs
[10:28:07] [PASSED] 7 VFs
[10:28:07] [PASSED] 8 VFs
[10:28:07] [PASSED] 9 VFs
[10:28:07] [PASSED] 10 VFs
[10:28:07] [PASSED] 11 VFs
[10:28:07] [PASSED] 12 VFs
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[10:28:07] [PASSED] 15 VFs
[10:28:07] [PASSED] 16 VFs
[10:28:07] [PASSED] 17 VFs
[10:28:07] [PASSED] 18 VFs
[10:28:07] [PASSED] 19 VFs
[10:28:07] [PASSED] 20 VFs
[10:28:07] [PASSED] 21 VFs
[10:28:07] [PASSED] 22 VFs
[10:28:07] [PASSED] 23 VFs
[10:28:07] [PASSED] 24 VFs
[10:28:07] [PASSED] 25 VFs
[10:28:07] [PASSED] 26 VFs
[10:28:07] [PASSED] 27 VFs
[10:28:07] [PASSED] 28 VFs
[10:28:07] [PASSED] 29 VFs
[10:28:07] [PASSED] 30 VFs
[10:28:07] [PASSED] 31 VFs
[10:28:07] [PASSED] 32 VFs
[10:28:07] [PASSED] 33 VFs
[10:28:07] [PASSED] 34 VFs
[10:28:07] [PASSED] 35 VFs
[10:28:07] [PASSED] 36 VFs
[10:28:07] [PASSED] 37 VFs
[10:28:07] [PASSED] 38 VFs
[10:28:07] [PASSED] 39 VFs
[10:28:07] [PASSED] 40 VFs
[10:28:07] [PASSED] 41 VFs
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[10:28:07] [PASSED] 43 VFs
[10:28:07] [PASSED] 44 VFs
[10:28:07] [PASSED] 45 VFs
[10:28:07] [PASSED] 46 VFs
[10:28:07] [PASSED] 47 VFs
[10:28:07] [PASSED] 48 VFs
[10:28:07] [PASSED] 49 VFs
[10:28:07] [PASSED] 50 VFs
[10:28:07] [PASSED] 51 VFs
[10:28:07] [PASSED] 52 VFs
[10:28:07] [PASSED] 53 VFs
[10:28:07] [PASSED] 54 VFs
[10:28:07] [PASSED] 55 VFs
[10:28:07] [PASSED] 56 VFs
[10:28:07] [PASSED] 57 VFs
[10:28:07] [PASSED] 58 VFs
[10:28:07] [PASSED] 59 VFs
[10:28:07] [PASSED] 60 VFs
[10:28:07] [PASSED] 61 VFs
[10:28:07] [PASSED] 62 VFs
[10:28:07] [PASSED] 63 VFs
[10:28:07] ==================== [PASSED] fair_vram ====================
[10:28:07] ================== [PASSED] pf_gt_config ===================
[10:28:07] ===================== lmtt (1 subtest) =====================
[10:28:07] ======================== test_ops =========================
[10:28:07] [PASSED] 2-level
[10:28:07] [PASSED] multi-level
[10:28:07] ==================== [PASSED] test_ops =====================
[10:28:07] ====================== [PASSED] lmtt =======================
[10:28:07] ================= pf_service (11 subtests) =================
[10:28:07] [PASSED] pf_negotiate_any
[10:28:07] [PASSED] pf_negotiate_base_match
[10:28:07] [PASSED] pf_negotiate_base_newer
[10:28:07] [PASSED] pf_negotiate_base_next
[10:28:07] [SKIPPED] pf_negotiate_base_older
[10:28:07] [PASSED] pf_negotiate_base_prev
[10:28:07] [PASSED] pf_negotiate_latest_match
[10:28:07] [PASSED] pf_negotiate_latest_newer
[10:28:07] [PASSED] pf_negotiate_latest_next
[10:28:07] [SKIPPED] pf_negotiate_latest_older
[10:28:07] [SKIPPED] pf_negotiate_latest_prev
[10:28:07] =================== [PASSED] pf_service ====================
[10:28:07] ================= xe_guc_g2g (2 subtests) ==================
[10:28:07] ============== xe_live_guc_g2g_kunit_default ==============
[10:28:07] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[10:28:07] ============== xe_live_guc_g2g_kunit_allmem ===============
[10:28:07] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[10:28:07] =================== [SKIPPED] xe_guc_g2g ===================
[10:28:07] =================== xe_mocs (2 subtests) ===================
[10:28:07] ================ xe_live_mocs_kernel_kunit ================
[10:28:07] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:28:07] ================ xe_live_mocs_reset_kunit =================
[10:28:07] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:28:07] ==================== [SKIPPED] xe_mocs =====================
[10:28:07] ================= xe_migrate (2 subtests) ==================
[10:28:07] ================= xe_migrate_sanity_kunit =================
[10:28:07] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:28:07] ================== xe_validate_ccs_kunit ==================
[10:28:07] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:28:07] =================== [SKIPPED] xe_migrate ===================
[10:28:07] ================== xe_dma_buf (1 subtest) ==================
[10:28:07] ==================== xe_dma_buf_kunit =====================
[10:28:07] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:28:07] =================== [SKIPPED] xe_dma_buf ===================
[10:28:07] ================= xe_bo_shrink (1 subtest) =================
[10:28:07] =================== xe_bo_shrink_kunit ====================
[10:28:07] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:28:07] ================== [SKIPPED] xe_bo_shrink ==================
[10:28:07] ==================== xe_bo (2 subtests) ====================
[10:28:07] ================== xe_ccs_migrate_kunit ===================
[10:28:07] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:28:07] ==================== xe_bo_evict_kunit ====================
[10:28:07] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:28:07] ===================== [SKIPPED] xe_bo ======================
[10:28:07] ==================== args (13 subtests) ====================
[10:28:07] [PASSED] count_args_test
[10:28:07] [PASSED] call_args_example
[10:28:07] [PASSED] call_args_test
[10:28:07] [PASSED] drop_first_arg_example
[10:28:07] [PASSED] drop_first_arg_test
[10:28:07] [PASSED] first_arg_example
[10:28:07] [PASSED] first_arg_test
[10:28:07] [PASSED] last_arg_example
[10:28:07] [PASSED] last_arg_test
[10:28:07] [PASSED] pick_arg_example
[10:28:07] [PASSED] if_args_example
[10:28:07] [PASSED] if_args_test
[10:28:07] [PASSED] sep_comma_example
[10:28:07] ====================== [PASSED] args =======================
[10:28:07] =================== xe_pci (3 subtests) ====================
[10:28:07] ==================== check_graphics_ip ====================
[10:28:07] [PASSED] 12.00 Xe_LP
[10:28:07] [PASSED] 12.10 Xe_LP+
[10:28:07] [PASSED] 12.55 Xe_HPG
[10:28:07] [PASSED] 12.60 Xe_HPC
[10:28:07] [PASSED] 12.70 Xe_LPG
[10:28:07] [PASSED] 12.71 Xe_LPG
[10:28:07] [PASSED] 12.74 Xe_LPG+
[10:28:07] [PASSED] 20.01 Xe2_HPG
[10:28:07] [PASSED] 20.02 Xe2_HPG
[10:28:07] [PASSED] 20.04 Xe2_LPG
[10:28:07] [PASSED] 30.00 Xe3_LPG
[10:28:07] [PASSED] 30.01 Xe3_LPG
[10:28:07] [PASSED] 30.03 Xe3_LPG
[10:28:07] [PASSED] 30.04 Xe3_LPG
[10:28:07] [PASSED] 30.05 Xe3_LPG
[10:28:07] [PASSED] 35.10 Xe3p_LPG
[10:28:07] [PASSED] 35.11 Xe3p_XPC
[10:28:07] ================ [PASSED] check_graphics_ip ================
[10:28:07] ===================== check_media_ip ======================
[10:28:07] [PASSED] 12.00 Xe_M
[10:28:07] [PASSED] 12.55 Xe_HPM
[10:28:07] [PASSED] 13.00 Xe_LPM+
[10:28:07] [PASSED] 13.01 Xe2_HPM
[10:28:07] [PASSED] 20.00 Xe2_LPM
[10:28:07] [PASSED] 30.00 Xe3_LPM
[10:28:07] [PASSED] 30.02 Xe3_LPM
[10:28:07] [PASSED] 35.00 Xe3p_LPM
[10:28:07] [PASSED] 35.03 Xe3p_HPM
[10:28:07] ================= [PASSED] check_media_ip ==================
[10:28:07] =================== check_platform_desc ===================
[10:28:07] [PASSED] 0x9A60 (TIGERLAKE)
[10:28:07] [PASSED] 0x9A68 (TIGERLAKE)
[10:28:07] [PASSED] 0x9A70 (TIGERLAKE)
[10:28:07] [PASSED] 0x9A40 (TIGERLAKE)
[10:28:07] [PASSED] 0x9A49 (TIGERLAKE)
[10:28:07] [PASSED] 0x9A59 (TIGERLAKE)
[10:28:07] [PASSED] 0x9A78 (TIGERLAKE)
[10:28:07] [PASSED] 0x9AC0 (TIGERLAKE)
[10:28:07] [PASSED] 0x9AC9 (TIGERLAKE)
[10:28:07] [PASSED] 0x9AD9 (TIGERLAKE)
[10:28:07] [PASSED] 0x9AF8 (TIGERLAKE)
[10:28:07] [PASSED] 0x4C80 (ROCKETLAKE)
[10:28:07] [PASSED] 0x4C8A (ROCKETLAKE)
[10:28:07] [PASSED] 0x4C8B (ROCKETLAKE)
[10:28:07] [PASSED] 0x4C8C (ROCKETLAKE)
[10:28:07] [PASSED] 0x4C90 (ROCKETLAKE)
[10:28:07] [PASSED] 0x4C9A (ROCKETLAKE)
[10:28:07] [PASSED] 0x4680 (ALDERLAKE_S)
[10:28:07] [PASSED] 0x4682 (ALDERLAKE_S)
[10:28:07] [PASSED] 0x4688 (ALDERLAKE_S)
[10:28:07] [PASSED] 0x468A (ALDERLAKE_S)
[10:28:07] [PASSED] 0x468B (ALDERLAKE_S)
[10:28:07] [PASSED] 0x4690 (ALDERLAKE_S)
[10:28:07] [PASSED] 0x4692 (ALDERLAKE_S)
[10:28:07] [PASSED] 0x4693 (ALDERLAKE_S)
[10:28:07] [PASSED] 0x46A0 (ALDERLAKE_P)
[10:28:07] [PASSED] 0x46A1 (ALDERLAKE_P)
[10:28:07] [PASSED] 0x46A2 (ALDERLAKE_P)
[10:28:07] [PASSED] 0x46A3 (ALDERLAKE_P)
[10:28:07] [PASSED] 0x46A6 (ALDERLAKE_P)
[10:28:07] [PASSED] 0x46A8 (ALDERLAKE_P)
[10:28:07] [PASSED] 0x46AA (ALDERLAKE_P)
[10:28:07] [PASSED] 0x462A (ALDERLAKE_P)
[10:28:07] [PASSED] 0x4626 (ALDERLAKE_P)
[10:28:07] [PASSED] 0x4628 (ALDERLAKE_P)
[10:28:07] [PASSED] 0x46B0 (ALDERLAKE_P)
[10:28:07] [PASSED] 0x46B1 (ALDERLAKE_P)
[10:28:07] [PASSED] 0x46B2 (ALDERLAKE_P)
[10:28:07] [PASSED] 0x46B3 (ALDERLAKE_P)
[10:28:07] [PASSED] 0x46C0 (ALDERLAKE_P)
[10:28:07] [PASSED] 0x46C1 (ALDERLAKE_P)
[10:28:07] [PASSED] 0x46C2 (ALDERLAKE_P)
[10:28:07] [PASSED] 0x46C3 (ALDERLAKE_P)
[10:28:07] [PASSED] 0x46D0 (ALDERLAKE_N)
[10:28:07] [PASSED] 0x46D1 (ALDERLAKE_N)
[10:28:07] [PASSED] 0x46D2 (ALDERLAKE_N)
[10:28:07] [PASSED] 0x46D3 (ALDERLAKE_N)
[10:28:07] [PASSED] 0x46D4 (ALDERLAKE_N)
[10:28:07] [PASSED] 0xA721 (ALDERLAKE_P)
[10:28:07] [PASSED] 0xA7A1 (ALDERLAKE_P)
[10:28:07] [PASSED] 0xA7A9 (ALDERLAKE_P)
[10:28:07] [PASSED] 0xA7AC (ALDERLAKE_P)
[10:28:07] [PASSED] 0xA7AD (ALDERLAKE_P)
[10:28:07] [PASSED] 0xA720 (ALDERLAKE_P)
[10:28:07] [PASSED] 0xA7A0 (ALDERLAKE_P)
[10:28:07] [PASSED] 0xA7A8 (ALDERLAKE_P)
[10:28:07] [PASSED] 0xA7AA (ALDERLAKE_P)
[10:28:07] [PASSED] 0xA7AB (ALDERLAKE_P)
[10:28:07] [PASSED] 0xA780 (ALDERLAKE_S)
[10:28:07] [PASSED] 0xA781 (ALDERLAKE_S)
[10:28:07] [PASSED] 0xA782 (ALDERLAKE_S)
[10:28:07] [PASSED] 0xA783 (ALDERLAKE_S)
[10:28:07] [PASSED] 0xA788 (ALDERLAKE_S)
[10:28:07] [PASSED] 0xA789 (ALDERLAKE_S)
[10:28:07] [PASSED] 0xA78A (ALDERLAKE_S)
[10:28:07] [PASSED] 0xA78B (ALDERLAKE_S)
[10:28:07] [PASSED] 0x4905 (DG1)
[10:28:07] [PASSED] 0x4906 (DG1)
[10:28:07] [PASSED] 0x4907 (DG1)
[10:28:07] [PASSED] 0x4908 (DG1)
[10:28:07] [PASSED] 0x4909 (DG1)
[10:28:07] [PASSED] 0x56C0 (DG2)
[10:28:07] [PASSED] 0x56C2 (DG2)
[10:28:07] [PASSED] 0x56C1 (DG2)
[10:28:07] [PASSED] 0x7D51 (METEORLAKE)
[10:28:07] [PASSED] 0x7DD1 (METEORLAKE)
[10:28:07] [PASSED] 0x7D41 (METEORLAKE)
[10:28:07] [PASSED] 0x7D67 (METEORLAKE)
[10:28:07] [PASSED] 0xB640 (METEORLAKE)
[10:28:07] [PASSED] 0x56A0 (DG2)
[10:28:07] [PASSED] 0x56A1 (DG2)
[10:28:07] [PASSED] 0x56A2 (DG2)
[10:28:07] [PASSED] 0x56BE (DG2)
[10:28:07] [PASSED] 0x56BF (DG2)
[10:28:07] [PASSED] 0x5690 (DG2)
[10:28:07] [PASSED] 0x5691 (DG2)
[10:28:07] [PASSED] 0x5692 (DG2)
[10:28:07] [PASSED] 0x56A5 (DG2)
[10:28:07] [PASSED] 0x56A6 (DG2)
[10:28:07] [PASSED] 0x56B0 (DG2)
[10:28:07] [PASSED] 0x56B1 (DG2)
[10:28:07] [PASSED] 0x56BA (DG2)
[10:28:07] [PASSED] 0x56BB (DG2)
[10:28:07] [PASSED] 0x56BC (DG2)
[10:28:07] [PASSED] 0x56BD (DG2)
[10:28:07] [PASSED] 0x5693 (DG2)
[10:28:07] [PASSED] 0x5694 (DG2)
[10:28:07] [PASSED] 0x5695 (DG2)
[10:28:07] [PASSED] 0x56A3 (DG2)
[10:28:07] [PASSED] 0x56A4 (DG2)
[10:28:07] [PASSED] 0x56B2 (DG2)
[10:28:07] [PASSED] 0x56B3 (DG2)
[10:28:07] [PASSED] 0x5696 (DG2)
[10:28:07] [PASSED] 0x5697 (DG2)
[10:28:07] [PASSED] 0xB69 (PVC)
[10:28:07] [PASSED] 0xB6E (PVC)
[10:28:07] [PASSED] 0xBD4 (PVC)
[10:28:07] [PASSED] 0xBD5 (PVC)
[10:28:07] [PASSED] 0xBD6 (PVC)
[10:28:07] [PASSED] 0xBD7 (PVC)
[10:28:07] [PASSED] 0xBD8 (PVC)
[10:28:07] [PASSED] 0xBD9 (PVC)
[10:28:07] [PASSED] 0xBDA (PVC)
[10:28:07] [PASSED] 0xBDB (PVC)
[10:28:07] [PASSED] 0xBE0 (PVC)
[10:28:07] [PASSED] 0xBE1 (PVC)
[10:28:07] [PASSED] 0xBE5 (PVC)
[10:28:07] [PASSED] 0x7D40 (METEORLAKE)
[10:28:07] [PASSED] 0x7D45 (METEORLAKE)
[10:28:07] [PASSED] 0x7D55 (METEORLAKE)
[10:28:07] [PASSED] 0x7D60 (METEORLAKE)
[10:28:07] [PASSED] 0x7DD5 (METEORLAKE)
[10:28:07] [PASSED] 0x6420 (LUNARLAKE)
[10:28:07] [PASSED] 0x64A0 (LUNARLAKE)
[10:28:07] [PASSED] 0x64B0 (LUNARLAKE)
[10:28:07] [PASSED] 0xE202 (BATTLEMAGE)
[10:28:07] [PASSED] 0xE209 (BATTLEMAGE)
[10:28:07] [PASSED] 0xE20B (BATTLEMAGE)
[10:28:07] [PASSED] 0xE20C (BATTLEMAGE)
[10:28:07] [PASSED] 0xE20D (BATTLEMAGE)
[10:28:07] [PASSED] 0xE210 (BATTLEMAGE)
[10:28:07] [PASSED] 0xE211 (BATTLEMAGE)
[10:28:07] [PASSED] 0xE212 (BATTLEMAGE)
[10:28:07] [PASSED] 0xE216 (BATTLEMAGE)
[10:28:07] [PASSED] 0xE220 (BATTLEMAGE)
[10:28:07] [PASSED] 0xE221 (BATTLEMAGE)
[10:28:07] [PASSED] 0xE222 (BATTLEMAGE)
[10:28:07] [PASSED] 0xE223 (BATTLEMAGE)
[10:28:07] [PASSED] 0xB080 (PANTHERLAKE)
[10:28:07] [PASSED] 0xB081 (PANTHERLAKE)
[10:28:07] [PASSED] 0xB082 (PANTHERLAKE)
[10:28:07] [PASSED] 0xB083 (PANTHERLAKE)
[10:28:07] [PASSED] 0xB084 (PANTHERLAKE)
[10:28:07] [PASSED] 0xB085 (PANTHERLAKE)
[10:28:07] [PASSED] 0xB086 (PANTHERLAKE)
[10:28:07] [PASSED] 0xB087 (PANTHERLAKE)
[10:28:07] [PASSED] 0xB08F (PANTHERLAKE)
[10:28:07] [PASSED] 0xB090 (PANTHERLAKE)
[10:28:07] [PASSED] 0xB0A0 (PANTHERLAKE)
[10:28:07] [PASSED] 0xB0B0 (PANTHERLAKE)
[10:28:07] [PASSED] 0xFD80 (PANTHERLAKE)
[10:28:07] [PASSED] 0xFD81 (PANTHERLAKE)
[10:28:07] [PASSED] 0xD740 (NOVALAKE_S)
[10:28:07] [PASSED] 0xD741 (NOVALAKE_S)
[10:28:07] [PASSED] 0xD742 (NOVALAKE_S)
[10:28:07] [PASSED] 0xD743 (NOVALAKE_S)
[10:28:07] [PASSED] 0xD744 (NOVALAKE_S)
[10:28:07] [PASSED] 0xD745 (NOVALAKE_S)
[10:28:07] [PASSED] 0x674C (CRESCENTISLAND)
[10:28:07] [PASSED] 0xD750 (NOVALAKE_P)
[10:28:07] [PASSED] 0xD751 (NOVALAKE_P)
[10:28:07] [PASSED] 0xD752 (NOVALAKE_P)
[10:28:07] [PASSED] 0xD753 (NOVALAKE_P)
[10:28:07] [PASSED] 0xD754 (NOVALAKE_P)
[10:28:07] [PASSED] 0xD755 (NOVALAKE_P)
[10:28:07] [PASSED] 0xD756 (NOVALAKE_P)
[10:28:07] [PASSED] 0xD757 (NOVALAKE_P)
[10:28:07] [PASSED] 0xD75F (NOVALAKE_P)
[10:28:07] =============== [PASSED] check_platform_desc ===============
[10:28:07] ===================== [PASSED] xe_pci ======================
[10:28:07] =================== xe_rtp (2 subtests) ====================
[10:28:07] =============== xe_rtp_process_to_sr_tests ================
[10:28:07] [PASSED] coalesce-same-reg
[10:28:07] [PASSED] no-match-no-add
[10:28:07] [PASSED] match-or
[10:28:07] [PASSED] match-or-xfail
[10:28:07] [PASSED] no-match-no-add-multiple-rules
[10:28:07] [PASSED] two-regs-two-entries
[10:28:07] [PASSED] clr-one-set-other
[10:28:07] [PASSED] set-field
[10:28:07] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[10:28:07] [PASSED] conflict-not-disjoint
[10:28:07] [PASSED] conflict-reg-type
[10:28:07] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:28:07] ================== xe_rtp_process_tests ===================
[10:28:07] [PASSED] active1
[10:28:07] [PASSED] active2
[10:28:07] [PASSED] active-inactive
[10:28:07] [PASSED] inactive-active
[10:28:07] [PASSED] inactive-1st_or_active-inactive
[10:28:07] [PASSED] inactive-2nd_or_active-inactive
[10:28:07] [PASSED] inactive-last_or_active-inactive
[10:28:07] [PASSED] inactive-no_or_active-inactive
[10:28:07] ============== [PASSED] xe_rtp_process_tests ===============
[10:28:07] ===================== [PASSED] xe_rtp ======================
[10:28:07] ==================== xe_wa (1 subtest) =====================
[10:28:07] ======================== xe_wa_gt =========================
[10:28:07] [PASSED] TIGERLAKE B0
[10:28:07] [PASSED] DG1 A0
[10:28:07] [PASSED] DG1 B0
[10:28:07] [PASSED] ALDERLAKE_S A0
[10:28:07] [PASSED] ALDERLAKE_S B0
[10:28:07] [PASSED] ALDERLAKE_S C0
[10:28:07] [PASSED] ALDERLAKE_S D0
[10:28:07] [PASSED] ALDERLAKE_P A0
[10:28:07] [PASSED] ALDERLAKE_P B0
[10:28:07] [PASSED] ALDERLAKE_P C0
[10:28:07] [PASSED] ALDERLAKE_S RPLS D0
[10:28:07] [PASSED] ALDERLAKE_P RPLU E0
[10:28:07] [PASSED] DG2 G10 C0
[10:28:07] [PASSED] DG2 G11 B1
[10:28:07] [PASSED] DG2 G12 A1
[10:28:07] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:28:07] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:28:07] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[10:28:07] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[10:28:07] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[10:28:07] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[10:28:07] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[10:28:07] ==================== [PASSED] xe_wa_gt =====================
[10:28:07] ====================== [PASSED] xe_wa ======================
[10:28:07] ============================================================
[10:28:07] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[10:28:07] Elapsed time: 35.445s total, 4.283s configuring, 30.546s building, 0.592s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:28:07] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:28:09] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:28:33] Starting KUnit Kernel (1/1)...
[10:28:33] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:28:33] ============ drm_test_pick_cmdline (2 subtests) ============
[10:28:33] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[10:28:33] =============== drm_test_pick_cmdline_named ===============
[10:28:33] [PASSED] NTSC
[10:28:33] [PASSED] NTSC-J
[10:28:33] [PASSED] PAL
[10:28:33] [PASSED] PAL-M
[10:28:33] =========== [PASSED] drm_test_pick_cmdline_named ===========
[10:28:33] ============== [PASSED] drm_test_pick_cmdline ==============
[10:28:33] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[10:28:33] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[10:28:33] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[10:28:33] =========== drm_validate_clone_mode (2 subtests) ===========
[10:28:33] ============== drm_test_check_in_clone_mode ===============
[10:28:33] [PASSED] in_clone_mode
[10:28:33] [PASSED] not_in_clone_mode
[10:28:33] ========== [PASSED] drm_test_check_in_clone_mode ===========
[10:28:33] =============== drm_test_check_valid_clones ===============
[10:28:33] [PASSED] not_in_clone_mode
[10:28:33] [PASSED] valid_clone
[10:28:33] [PASSED] invalid_clone
[10:28:33] =========== [PASSED] drm_test_check_valid_clones ===========
[10:28:33] ============= [PASSED] drm_validate_clone_mode =============
[10:28:33] ============= drm_validate_modeset (1 subtest) =============
[10:28:33] [PASSED] drm_test_check_connector_changed_modeset
[10:28:33] ============== [PASSED] drm_validate_modeset ===============
[10:28:33] ====== drm_test_bridge_get_current_state (2 subtests) ======
[10:28:33] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[10:28:33] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[10:28:33] ======== [PASSED] drm_test_bridge_get_current_state ========
[10:28:33] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[10:28:33] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[10:28:33] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[10:28:33] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[10:28:33] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[10:28:33] ============== drm_bridge_alloc (2 subtests) ===============
[10:28:33] [PASSED] drm_test_drm_bridge_alloc_basic
[10:28:33] [PASSED] drm_test_drm_bridge_alloc_get_put
[10:28:33] ================ [PASSED] drm_bridge_alloc =================
[10:28:33] ============= drm_cmdline_parser (40 subtests) =============
[10:28:33] [PASSED] drm_test_cmdline_force_d_only
[10:28:33] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:28:33] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:28:33] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:28:33] [PASSED] drm_test_cmdline_force_e_only
[10:28:33] [PASSED] drm_test_cmdline_res
[10:28:33] [PASSED] drm_test_cmdline_res_vesa
[10:28:33] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:28:33] [PASSED] drm_test_cmdline_res_rblank
[10:28:33] [PASSED] drm_test_cmdline_res_bpp
[10:28:33] [PASSED] drm_test_cmdline_res_refresh
[10:28:33] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:28:33] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:28:33] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:28:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:28:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:28:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:28:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:28:33] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:28:33] [PASSED] drm_test_cmdline_res_margins_force_on
[10:28:33] [PASSED] drm_test_cmdline_res_vesa_margins
[10:28:33] [PASSED] drm_test_cmdline_name
[10:28:33] [PASSED] drm_test_cmdline_name_bpp
[10:28:33] [PASSED] drm_test_cmdline_name_option
[10:28:33] [PASSED] drm_test_cmdline_name_bpp_option
[10:28:33] [PASSED] drm_test_cmdline_rotate_0
[10:28:33] [PASSED] drm_test_cmdline_rotate_90
[10:28:33] [PASSED] drm_test_cmdline_rotate_180
[10:28:33] [PASSED] drm_test_cmdline_rotate_270
[10:28:33] [PASSED] drm_test_cmdline_hmirror
[10:28:33] [PASSED] drm_test_cmdline_vmirror
[10:28:33] [PASSED] drm_test_cmdline_margin_options
[10:28:33] [PASSED] drm_test_cmdline_multiple_options
[10:28:33] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:28:33] [PASSED] drm_test_cmdline_extra_and_option
[10:28:33] [PASSED] drm_test_cmdline_freestanding_options
[10:28:33] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:28:33] [PASSED] drm_test_cmdline_panel_orientation
[10:28:33] ================ drm_test_cmdline_invalid =================
[10:28:33] [PASSED] margin_only
[10:28:33] [PASSED] interlace_only
[10:28:33] [PASSED] res_missing_x
[10:28:33] [PASSED] res_missing_y
[10:28:33] [PASSED] res_bad_y
[10:28:33] [PASSED] res_missing_y_bpp
[10:28:33] [PASSED] res_bad_bpp
[10:28:33] [PASSED] res_bad_refresh
[10:28:33] [PASSED] res_bpp_refresh_force_on_off
[10:28:33] [PASSED] res_invalid_mode
[10:28:33] [PASSED] res_bpp_wrong_place_mode
[10:28:33] [PASSED] name_bpp_refresh
[10:28:33] [PASSED] name_refresh
[10:28:33] [PASSED] name_refresh_wrong_mode
[10:28:33] [PASSED] name_refresh_invalid_mode
[10:28:33] [PASSED] rotate_multiple
[10:28:33] [PASSED] rotate_invalid_val
[10:28:33] [PASSED] rotate_truncated
[10:28:33] [PASSED] invalid_option
[10:28:33] [PASSED] invalid_tv_option
[10:28:33] [PASSED] truncated_tv_option
[10:28:33] ============ [PASSED] drm_test_cmdline_invalid =============
[10:28:33] =============== drm_test_cmdline_tv_options ===============
[10:28:33] [PASSED] NTSC
[10:28:33] [PASSED] NTSC_443
[10:28:33] [PASSED] NTSC_J
[10:28:33] [PASSED] PAL
[10:28:33] [PASSED] PAL_M
[10:28:33] [PASSED] PAL_N
[10:28:33] [PASSED] SECAM
[10:28:33] [PASSED] MONO_525
[10:28:33] [PASSED] MONO_625
[10:28:33] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:28:33] =============== [PASSED] drm_cmdline_parser ================
[10:28:33] ========== drmm_connector_hdmi_init (20 subtests) ==========
[10:28:33] [PASSED] drm_test_connector_hdmi_init_valid
[10:28:33] [PASSED] drm_test_connector_hdmi_init_bpc_8
[10:28:33] [PASSED] drm_test_connector_hdmi_init_bpc_10
[10:28:33] [PASSED] drm_test_connector_hdmi_init_bpc_12
[10:28:33] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[10:28:33] [PASSED] drm_test_connector_hdmi_init_bpc_null
[10:28:33] [PASSED] drm_test_connector_hdmi_init_formats_empty
[10:28:33] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[10:28:33] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:28:33] [PASSED] supported_formats=0x9 yuv420_allowed=1
[10:28:33] [PASSED] supported_formats=0x9 yuv420_allowed=0
[10:28:33] [PASSED] supported_formats=0x3 yuv420_allowed=1
[10:28:33] [PASSED] supported_formats=0x3 yuv420_allowed=0
[10:28:33] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:28:33] [PASSED] drm_test_connector_hdmi_init_null_ddc
[10:28:33] [PASSED] drm_test_connector_hdmi_init_null_product
[10:28:33] [PASSED] drm_test_connector_hdmi_init_null_vendor
[10:28:33] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[10:28:33] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[10:28:33] [PASSED] drm_test_connector_hdmi_init_product_valid
[10:28:33] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[10:28:33] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[10:28:33] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[10:28:33] ========= drm_test_connector_hdmi_init_type_valid =========
[10:28:33] [PASSED] HDMI-A
[10:28:33] [PASSED] HDMI-B
[10:28:33] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[10:28:33] ======== drm_test_connector_hdmi_init_type_invalid ========
[10:28:33] [PASSED] Unknown
[10:28:33] [PASSED] VGA
[10:28:33] [PASSED] DVI-I
[10:28:33] [PASSED] DVI-D
[10:28:33] [PASSED] DVI-A
[10:28:33] [PASSED] Composite
[10:28:33] [PASSED] SVIDEO
[10:28:33] [PASSED] LVDS
[10:28:33] [PASSED] Component
[10:28:33] [PASSED] DIN
[10:28:33] [PASSED] DP
[10:28:33] [PASSED] TV
[10:28:33] [PASSED] eDP
[10:28:33] [PASSED] Virtual
[10:28:33] [PASSED] DSI
[10:28:33] [PASSED] DPI
[10:28:33] [PASSED] Writeback
[10:28:33] [PASSED] SPI
[10:28:33] [PASSED] USB
[10:28:33] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[10:28:33] ============ [PASSED] drmm_connector_hdmi_init =============
[10:28:33] ============= drmm_connector_init (3 subtests) =============
[10:28:33] [PASSED] drm_test_drmm_connector_init
[10:28:33] [PASSED] drm_test_drmm_connector_init_null_ddc
[10:28:33] ========= drm_test_drmm_connector_init_type_valid =========
[10:28:33] [PASSED] Unknown
[10:28:33] [PASSED] VGA
[10:28:33] [PASSED] DVI-I
[10:28:33] [PASSED] DVI-D
[10:28:33] [PASSED] DVI-A
[10:28:33] [PASSED] Composite
[10:28:33] [PASSED] SVIDEO
[10:28:33] [PASSED] LVDS
[10:28:33] [PASSED] Component
[10:28:33] [PASSED] DIN
[10:28:33] [PASSED] DP
[10:28:33] [PASSED] HDMI-A
[10:28:33] [PASSED] HDMI-B
[10:28:33] [PASSED] TV
[10:28:33] [PASSED] eDP
[10:28:33] [PASSED] Virtual
[10:28:33] [PASSED] DSI
[10:28:33] [PASSED] DPI
[10:28:33] [PASSED] Writeback
[10:28:33] [PASSED] SPI
[10:28:33] [PASSED] USB
[10:28:33] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[10:28:33] =============== [PASSED] drmm_connector_init ===============
[10:28:33] ========= drm_connector_dynamic_init (6 subtests) ==========
[10:28:33] [PASSED] drm_test_drm_connector_dynamic_init
[10:28:33] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[10:28:33] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[10:28:33] [PASSED] drm_test_drm_connector_dynamic_init_properties
[10:28:33] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[10:28:33] [PASSED] Unknown
[10:28:33] [PASSED] VGA
[10:28:33] [PASSED] DVI-I
[10:28:33] [PASSED] DVI-D
[10:28:33] [PASSED] DVI-A
[10:28:33] [PASSED] Composite
[10:28:33] [PASSED] SVIDEO
[10:28:33] [PASSED] LVDS
[10:28:33] [PASSED] Component
[10:28:33] [PASSED] DIN
[10:28:33] [PASSED] DP
[10:28:33] [PASSED] HDMI-A
[10:28:33] [PASSED] HDMI-B
[10:28:33] [PASSED] TV
[10:28:33] [PASSED] eDP
[10:28:33] [PASSED] Virtual
[10:28:33] [PASSED] DSI
[10:28:33] [PASSED] DPI
[10:28:33] [PASSED] Writeback
[10:28:33] [PASSED] SPI
[10:28:33] [PASSED] USB
[10:28:33] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[10:28:33] ======== drm_test_drm_connector_dynamic_init_name =========
[10:28:33] [PASSED] Unknown
[10:28:33] [PASSED] VGA
[10:28:33] [PASSED] DVI-I
[10:28:33] [PASSED] DVI-D
[10:28:33] [PASSED] DVI-A
[10:28:33] [PASSED] Composite
[10:28:33] [PASSED] SVIDEO
[10:28:33] [PASSED] LVDS
[10:28:33] [PASSED] Component
[10:28:33] [PASSED] DIN
[10:28:33] [PASSED] DP
[10:28:33] [PASSED] HDMI-A
[10:28:33] [PASSED] HDMI-B
[10:28:33] [PASSED] TV
[10:28:33] [PASSED] eDP
[10:28:33] [PASSED] Virtual
[10:28:33] [PASSED] DSI
[10:28:33] [PASSED] DPI
[10:28:33] [PASSED] Writeback
[10:28:33] [PASSED] SPI
[10:28:33] [PASSED] USB
[10:28:33] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[10:28:33] =========== [PASSED] drm_connector_dynamic_init ============
[10:28:33] ==== drm_connector_dynamic_register_early (4 subtests) =====
[10:28:33] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[10:28:33] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[10:28:33] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[10:28:33] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[10:28:33] ====== [PASSED] drm_connector_dynamic_register_early =======
[10:28:33] ======= drm_connector_dynamic_register (7 subtests) ========
[10:28:33] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[10:28:33] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[10:28:33] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[10:28:33] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[10:28:33] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[10:28:33] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[10:28:33] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[10:28:33] ========= [PASSED] drm_connector_dynamic_register ==========
[10:28:33] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[10:28:33] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[10:28:33] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[10:28:33] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[10:28:33] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:28:33] ========== drm_test_get_tv_mode_from_name_valid ===========
[10:28:33] [PASSED] NTSC
[10:28:33] [PASSED] NTSC-443
[10:28:33] [PASSED] NTSC-J
[10:28:33] [PASSED] PAL
[10:28:33] [PASSED] PAL-M
[10:28:33] [PASSED] PAL-N
[10:28:33] [PASSED] SECAM
[10:28:33] [PASSED] Mono
[10:28:33] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:28:33] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:28:33] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:28:33] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[10:28:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[10:28:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[10:28:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[10:28:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[10:28:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[10:28:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[10:28:33] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[10:28:33] [PASSED] VIC 96
[10:28:33] [PASSED] VIC 97
[10:28:33] [PASSED] VIC 101
[10:28:33] [PASSED] VIC 102
[10:28:33] [PASSED] VIC 106
[10:28:33] [PASSED] VIC 107
[10:28:33] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[10:28:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[10:28:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[10:28:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[10:28:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[10:28:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[10:28:33] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[10:28:33] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[10:28:33] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[10:28:33] [PASSED] Automatic
[10:28:33] [PASSED] Full
[10:28:33] [PASSED] Limited 16:235
[10:28:33] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[10:28:33] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[10:28:33] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[10:28:33] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[10:28:33] === drm_test_drm_hdmi_connector_get_output_format_name ====
[10:28:33] [PASSED] RGB
[10:28:33] [PASSED] YUV 4:2:0
[10:28:33] [PASSED] YUV 4:2:2
[10:28:33] [PASSED] YUV 4:4:4
[10:28:33] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[10:28:33] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[10:28:33] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[10:28:33] ============= drm_damage_helper (21 subtests) ==============
[10:28:33] [PASSED] drm_test_damage_iter_no_damage
[10:28:33] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:28:33] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:28:33] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:28:33] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:28:33] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:28:33] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:28:33] [PASSED] drm_test_damage_iter_simple_damage
[10:28:33] [PASSED] drm_test_damage_iter_single_damage
[10:28:33] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:28:33] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:28:33] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:28:33] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:28:33] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:28:33] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:28:33] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:28:33] [PASSED] drm_test_damage_iter_damage
[10:28:33] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:28:33] [PASSED] drm_test_damage_iter_damage_one_outside
[10:28:33] [PASSED] drm_test_damage_iter_damage_src_moved
[10:28:33] [PASSED] drm_test_damage_iter_damage_not_visible
[10:28:33] ================ [PASSED] drm_damage_helper ================
[10:28:33] ============== drm_dp_mst_helper (3 subtests) ==============
[10:28:33] ============== drm_test_dp_mst_calc_pbn_mode ==============
[10:28:33] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:28:33] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:28:33] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:28:33] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:28:33] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:28:33] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:28:33] ============== drm_test_dp_mst_calc_pbn_div ===============
[10:28:33] [PASSED] Link rate 2000000 lane count 4
[10:28:33] [PASSED] Link rate 2000000 lane count 2
[10:28:33] [PASSED] Link rate 2000000 lane count 1
[10:28:33] [PASSED] Link rate 1350000 lane count 4
[10:28:33] [PASSED] Link rate 1350000 lane count 2
[10:28:33] [PASSED] Link rate 1350000 lane count 1
[10:28:33] [PASSED] Link rate 1000000 lane count 4
[10:28:33] [PASSED] Link rate 1000000 lane count 2
[10:28:33] [PASSED] Link rate 1000000 lane count 1
[10:28:33] [PASSED] Link rate 810000 lane count 4
[10:28:33] [PASSED] Link rate 810000 lane count 2
[10:28:33] [PASSED] Link rate 810000 lane count 1
[10:28:33] [PASSED] Link rate 540000 lane count 4
[10:28:33] [PASSED] Link rate 540000 lane count 2
[10:28:33] [PASSED] Link rate 540000 lane count 1
[10:28:33] [PASSED] Link rate 270000 lane count 4
[10:28:33] [PASSED] Link rate 270000 lane count 2
[10:28:33] [PASSED] Link rate 270000 lane count 1
[10:28:33] [PASSED] Link rate 162000 lane count 4
[10:28:33] [PASSED] Link rate 162000 lane count 2
[10:28:33] [PASSED] Link rate 162000 lane count 1
[10:28:33] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[10:28:33] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[10:28:33] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:28:33] [PASSED] DP_POWER_UP_PHY with port number
[10:28:33] [PASSED] DP_POWER_DOWN_PHY with port number
[10:28:33] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:28:33] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:28:33] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:28:33] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:28:33] [PASSED] DP_QUERY_PAYLOAD with port number
[10:28:33] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:28:33] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:28:33] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:28:33] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:28:33] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:28:33] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:28:33] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:28:33] [PASSED] DP_REMOTE_I2C_READ with port number
[10:28:33] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:28:33] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:28:33] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:28:33] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:28:33] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:28:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:28:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:28:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:28:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:28:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:28:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:28:33] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:28:33] ================ [PASSED] drm_dp_mst_helper ================
[10:28:33] ================== drm_exec (7 subtests) ===================
[10:28:33] [PASSED] sanitycheck
[10:28:33] [PASSED] test_lock
[10:28:33] [PASSED] test_lock_unlock
[10:28:33] [PASSED] test_duplicates
[10:28:33] [PASSED] test_prepare
[10:28:33] [PASSED] test_prepare_array
[10:28:33] [PASSED] test_multiple_loops
[10:28:33] ==================== [PASSED] drm_exec =====================
[10:28:33] =========== drm_format_helper_test (17 subtests) ===========
[10:28:33] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[10:28:33] [PASSED] single_pixel_source_buffer
[10:28:33] [PASSED] single_pixel_clip_rectangle
[10:28:33] [PASSED] well_known_colors
[10:28:33] [PASSED] destination_pitch
[10:28:33] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:28:33] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[10:28:33] [PASSED] single_pixel_source_buffer
[10:28:33] [PASSED] single_pixel_clip_rectangle
[10:28:33] [PASSED] well_known_colors
[10:28:33] [PASSED] destination_pitch
[10:28:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:28:33] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[10:28:33] [PASSED] single_pixel_source_buffer
[10:28:33] [PASSED] single_pixel_clip_rectangle
[10:28:33] [PASSED] well_known_colors
[10:28:33] [PASSED] destination_pitch
[10:28:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:28:33] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[10:28:33] [PASSED] single_pixel_source_buffer
[10:28:33] [PASSED] single_pixel_clip_rectangle
[10:28:33] [PASSED] well_known_colors
[10:28:33] [PASSED] destination_pitch
[10:28:33] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:28:33] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[10:28:33] [PASSED] single_pixel_source_buffer
[10:28:33] [PASSED] single_pixel_clip_rectangle
[10:28:33] [PASSED] well_known_colors
[10:28:33] [PASSED] destination_pitch
[10:28:33] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:28:33] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[10:28:33] [PASSED] single_pixel_source_buffer
[10:28:33] [PASSED] single_pixel_clip_rectangle
[10:28:33] [PASSED] well_known_colors
[10:28:33] [PASSED] destination_pitch
[10:28:33] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:28:33] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[10:28:33] [PASSED] single_pixel_source_buffer
[10:28:33] [PASSED] single_pixel_clip_rectangle
[10:28:33] [PASSED] well_known_colors
[10:28:33] [PASSED] destination_pitch
[10:28:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:28:33] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[10:28:33] [PASSED] single_pixel_source_buffer
[10:28:33] [PASSED] single_pixel_clip_rectangle
[10:28:33] [PASSED] well_known_colors
[10:28:33] [PASSED] destination_pitch
[10:28:33] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[10:28:33] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[10:28:33] [PASSED] single_pixel_source_buffer
[10:28:33] [PASSED] single_pixel_clip_rectangle
[10:28:33] [PASSED] well_known_colors
[10:28:33] [PASSED] destination_pitch
[10:28:33] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:28:33] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[10:28:33] [PASSED] single_pixel_source_buffer
[10:28:33] [PASSED] single_pixel_clip_rectangle
[10:28:33] [PASSED] well_known_colors
[10:28:33] [PASSED] destination_pitch
[10:28:33] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:28:33] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[10:28:33] [PASSED] single_pixel_source_buffer
[10:28:33] [PASSED] single_pixel_clip_rectangle
[10:28:33] [PASSED] well_known_colors
[10:28:33] [PASSED] destination_pitch
[10:28:33] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:28:33] ============== drm_test_fb_xrgb8888_to_mono ===============
[10:28:33] [PASSED] single_pixel_source_buffer
[10:28:33] [PASSED] single_pixel_clip_rectangle
[10:28:33] [PASSED] well_known_colors
[10:28:33] [PASSED] destination_pitch
[10:28:33] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:28:33] ==================== drm_test_fb_swab =====================
[10:28:33] [PASSED] single_pixel_source_buffer
[10:28:33] [PASSED] single_pixel_clip_rectangle
[10:28:33] [PASSED] well_known_colors
[10:28:33] [PASSED] destination_pitch
[10:28:33] ================ [PASSED] drm_test_fb_swab =================
[10:28:33] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[10:28:33] [PASSED] single_pixel_source_buffer
[10:28:33] [PASSED] single_pixel_clip_rectangle
[10:28:33] [PASSED] well_known_colors
[10:28:33] [PASSED] destination_pitch
[10:28:33] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[10:28:33] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[10:28:33] [PASSED] single_pixel_source_buffer
[10:28:33] [PASSED] single_pixel_clip_rectangle
[10:28:33] [PASSED] well_known_colors
[10:28:33] [PASSED] destination_pitch
[10:28:33] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[10:28:33] ================= drm_test_fb_clip_offset =================
[10:28:33] [PASSED] pass through
[10:28:33] [PASSED] horizontal offset
[10:28:33] [PASSED] vertical offset
[10:28:33] [PASSED] horizontal and vertical offset
[10:28:33] [PASSED] horizontal offset (custom pitch)
[10:28:33] [PASSED] vertical offset (custom pitch)
[10:28:33] [PASSED] horizontal and vertical offset (custom pitch)
[10:28:33] ============= [PASSED] drm_test_fb_clip_offset =============
[10:28:33] =================== drm_test_fb_memcpy ====================
[10:28:33] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[10:28:33] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[10:28:33] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[10:28:33] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[10:28:33] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[10:28:33] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[10:28:33] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[10:28:33] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[10:28:33] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[10:28:33] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[10:28:33] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[10:28:33] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[10:28:33] =============== [PASSED] drm_test_fb_memcpy ================
[10:28:33] ============= [PASSED] drm_format_helper_test ==============
[10:28:33] ================= drm_format (18 subtests) =================
[10:28:33] [PASSED] drm_test_format_block_width_invalid
[10:28:33] [PASSED] drm_test_format_block_width_one_plane
[10:28:33] [PASSED] drm_test_format_block_width_two_plane
[10:28:33] [PASSED] drm_test_format_block_width_three_plane
[10:28:33] [PASSED] drm_test_format_block_width_tiled
[10:28:33] [PASSED] drm_test_format_block_height_invalid
[10:28:33] [PASSED] drm_test_format_block_height_one_plane
[10:28:33] [PASSED] drm_test_format_block_height_two_plane
[10:28:33] [PASSED] drm_test_format_block_height_three_plane
[10:28:33] [PASSED] drm_test_format_block_height_tiled
[10:28:33] [PASSED] drm_test_format_min_pitch_invalid
[10:28:33] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:28:33] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:28:33] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:28:33] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:28:33] [PASSED] drm_test_format_min_pitch_two_plane
[10:28:33] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:28:33] [PASSED] drm_test_format_min_pitch_tiled
[10:28:33] =================== [PASSED] drm_format ====================
[10:28:33] ============== drm_framebuffer (10 subtests) ===============
[10:28:33] ========== drm_test_framebuffer_check_src_coords ==========
[10:28:33] [PASSED] Success: source fits into fb
[10:28:33] [PASSED] Fail: overflowing fb with x-axis coordinate
[10:28:33] [PASSED] Fail: overflowing fb with y-axis coordinate
[10:28:33] [PASSED] Fail: overflowing fb with source width
[10:28:33] [PASSED] Fail: overflowing fb with source height
[10:28:33] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[10:28:33] [PASSED] drm_test_framebuffer_cleanup
[10:28:33] =============== drm_test_framebuffer_create ===============
[10:28:33] [PASSED] ABGR8888 normal sizes
[10:28:33] [PASSED] ABGR8888 max sizes
[10:28:33] [PASSED] ABGR8888 pitch greater than min required
[10:28:33] [PASSED] ABGR8888 pitch less than min required
[10:28:33] [PASSED] ABGR8888 Invalid width
[10:28:33] [PASSED] ABGR8888 Invalid buffer handle
[10:28:33] [PASSED] No pixel format
[10:28:33] [PASSED] ABGR8888 Width 0
[10:28:33] [PASSED] ABGR8888 Height 0
[10:28:33] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:28:33] [PASSED] ABGR8888 Large buffer offset
[10:28:33] [PASSED] ABGR8888 Buffer offset for inexistent plane
[10:28:33] [PASSED] ABGR8888 Invalid flag
[10:28:33] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:28:33] [PASSED] ABGR8888 Valid buffer modifier
[10:28:33] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:28:33] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:28:33] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:28:33] [PASSED] NV12 Normal sizes
[10:28:33] [PASSED] NV12 Max sizes
[10:28:33] [PASSED] NV12 Invalid pitch
[10:28:33] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:28:33] [PASSED] NV12 different modifier per-plane
[10:28:33] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:28:33] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:28:33] [PASSED] NV12 Modifier for inexistent plane
[10:28:33] [PASSED] NV12 Handle for inexistent plane
[10:28:33] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:28:33] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:28:33] [PASSED] YVU420 Normal sizes
[10:28:33] [PASSED] YVU420 Max sizes
[10:28:33] [PASSED] YVU420 Invalid pitch
[10:28:33] [PASSED] YVU420 Different pitches
[10:28:33] [PASSED] YVU420 Different buffer offsets/pitches
[10:28:33] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:28:33] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:28:33] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:28:33] [PASSED] YVU420 Valid modifier
[10:28:33] [PASSED] YVU420 Different modifiers per plane
[10:28:33] [PASSED] YVU420 Modifier for inexistent plane
[10:28:33] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[10:28:33] [PASSED] X0L2 Normal sizes
[10:28:33] [PASSED] X0L2 Max sizes
[10:28:33] [PASSED] X0L2 Invalid pitch
[10:28:33] [PASSED] X0L2 Pitch greater than minimum required
[10:28:33] [PASSED] X0L2 Handle for inexistent plane
[10:28:33] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:28:33] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:28:33] [PASSED] X0L2 Valid modifier
[10:28:33] [PASSED] X0L2 Modifier for inexistent plane
[10:28:33] =========== [PASSED] drm_test_framebuffer_create ===========
[10:28:33] [PASSED] drm_test_framebuffer_free
[10:28:33] [PASSED] drm_test_framebuffer_init
[10:28:33] [PASSED] drm_test_framebuffer_init_bad_format
[10:28:33] [PASSED] drm_test_framebuffer_init_dev_mismatch
[10:28:33] [PASSED] drm_test_framebuffer_lookup
[10:28:33] [PASSED] drm_test_framebuffer_lookup_inexistent
[10:28:33] [PASSED] drm_test_framebuffer_modifiers_not_supported
[10:28:33] ================= [PASSED] drm_framebuffer =================
[10:28:33] ================ drm_gem_shmem (8 subtests) ================
[10:28:33] [PASSED] drm_gem_shmem_test_obj_create
[10:28:33] [PASSED] drm_gem_shmem_test_obj_create_private
[10:28:33] [PASSED] drm_gem_shmem_test_pin_pages
[10:28:33] [PASSED] drm_gem_shmem_test_vmap
[10:28:33] [PASSED] drm_gem_shmem_test_get_sg_table
[10:28:33] [PASSED] drm_gem_shmem_test_get_pages_sgt
[10:28:33] [PASSED] drm_gem_shmem_test_madvise
[10:28:33] [PASSED] drm_gem_shmem_test_purge
[10:28:33] ================== [PASSED] drm_gem_shmem ==================
[10:28:33] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[10:28:33] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[10:28:33] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[10:28:33] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[10:28:33] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[10:28:33] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[10:28:33] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[10:28:33] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[10:28:33] [PASSED] Automatic
[10:28:33] [PASSED] Full
[10:28:33] [PASSED] Limited 16:235
[10:28:33] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[10:28:33] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[10:28:33] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[10:28:33] [PASSED] drm_test_check_disable_connector
[10:28:33] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[10:28:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[10:28:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[10:28:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[10:28:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[10:28:33] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[10:28:33] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[10:28:33] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[10:28:33] [PASSED] drm_test_check_output_bpc_dvi
[10:28:33] [PASSED] drm_test_check_output_bpc_format_vic_1
[10:28:33] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[10:28:33] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[10:28:33] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[10:28:33] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[10:28:33] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[10:28:33] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[10:28:33] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[10:28:33] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[10:28:33] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[10:28:33] [PASSED] drm_test_check_broadcast_rgb_value
[10:28:33] [PASSED] drm_test_check_bpc_8_value
[10:28:33] [PASSED] drm_test_check_bpc_10_value
[10:28:33] [PASSED] drm_test_check_bpc_12_value
[10:28:33] [PASSED] drm_test_check_format_value
[10:28:33] [PASSED] drm_test_check_tmds_char_value
[10:28:33] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[10:28:33] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[10:28:33] [PASSED] drm_test_check_mode_valid
[10:28:33] [PASSED] drm_test_check_mode_valid_reject
[10:28:33] [PASSED] drm_test_check_mode_valid_reject_rate
[10:28:33] [PASSED] drm_test_check_mode_valid_reject_max_clock
[10:28:33] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[10:28:33] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[10:28:33] [PASSED] drm_test_check_infoframes
[10:28:33] [PASSED] drm_test_check_reject_avi_infoframe
[10:28:33] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[10:28:33] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[10:28:33] [PASSED] drm_test_check_reject_audio_infoframe
[10:28:33] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[10:28:33] ================= drm_managed (2 subtests) =================
[10:28:33] [PASSED] drm_test_managed_release_action
[10:28:33] [PASSED] drm_test_managed_run_action
[10:28:33] =================== [PASSED] drm_managed ===================
[10:28:33] =================== drm_mm (6 subtests) ====================
[10:28:33] [PASSED] drm_test_mm_init
[10:28:33] [PASSED] drm_test_mm_debug
[10:28:33] [PASSED] drm_test_mm_align32
[10:28:33] [PASSED] drm_test_mm_align64
[10:28:33] [PASSED] drm_test_mm_lowest
[10:28:33] [PASSED] drm_test_mm_highest
[10:28:33] ===================== [PASSED] drm_mm ======================
[10:28:33] ============= drm_modes_analog_tv (5 subtests) =============
[10:28:33] [PASSED] drm_test_modes_analog_tv_mono_576i
[10:28:33] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:28:33] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:28:33] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:28:33] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:28:33] =============== [PASSED] drm_modes_analog_tv ===============
[10:28:33] ============== drm_plane_helper (2 subtests) ===============
[10:28:33] =============== drm_test_check_plane_state ================
[10:28:33] [PASSED] clipping_simple
[10:28:33] [PASSED] clipping_rotate_reflect
[10:28:33] [PASSED] positioning_simple
[10:28:33] [PASSED] upscaling
[10:28:33] [PASSED] downscaling
[10:28:33] [PASSED] rounding1
[10:28:33] [PASSED] rounding2
[10:28:33] [PASSED] rounding3
[10:28:33] [PASSED] rounding4
[10:28:33] =========== [PASSED] drm_test_check_plane_state ============
[10:28:33] =========== drm_test_check_invalid_plane_state ============
[10:28:33] [PASSED] positioning_invalid
[10:28:33] [PASSED] upscaling_invalid
[10:28:33] [PASSED] downscaling_invalid
[10:28:33] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:28:33] ================ [PASSED] drm_plane_helper =================
[10:28:33] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:28:33] ====== drm_test_connector_helper_tv_get_modes_check =======
[10:28:33] [PASSED] None
[10:28:33] [PASSED] PAL
[10:28:33] [PASSED] NTSC
[10:28:33] [PASSED] Both, NTSC Default
[10:28:33] [PASSED] Both, PAL Default
[10:28:33] [PASSED] Both, NTSC Default, with PAL on command-line
[10:28:33] [PASSED] Both, PAL Default, with NTSC on command-line
[10:28:33] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:28:33] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:28:33] ================== drm_rect (9 subtests) ===================
[10:28:33] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:28:33] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:28:33] [PASSED] drm_test_rect_clip_scaled_clipped
[10:28:33] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:28:33] ================= drm_test_rect_intersect =================
[10:28:33] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:28:33] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:28:33] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:28:33] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:28:33] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:28:33] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:28:33] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:28:33] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:28:33] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:28:33] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:28:33] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:28:33] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:28:33] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:28:33] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:28:33] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[10:28:33] ============= [PASSED] drm_test_rect_intersect =============
[10:28:33] ================ drm_test_rect_calc_hscale ================
[10:28:33] [PASSED] normal use
[10:28:33] [PASSED] out of max range
[10:28:33] [PASSED] out of min range
[10:28:33] [PASSED] zero dst
[10:28:33] [PASSED] negative src
[10:28:33] [PASSED] negative dst
[10:28:33] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:28:33] ================ drm_test_rect_calc_vscale ================
[10:28:33] [PASSED] normal use
[10:28:33] [PASSED] out of max range
[10:28:33] [PASSED] out of min range
[10:28:33] [PASSED] zero dst
[10:28:33] [PASSED] negative src
[10:28:34] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[10:28:34] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:28:34] ================== drm_test_rect_rotate ===================
[10:28:34] [PASSED] reflect-x
[10:28:34] [PASSED] reflect-y
[10:28:34] [PASSED] rotate-0
[10:28:34] [PASSED] rotate-90
[10:28:34] [PASSED] rotate-180
[10:28:34] [PASSED] rotate-270
[10:28:34] ============== [PASSED] drm_test_rect_rotate ===============
[10:28:34] ================ drm_test_rect_rotate_inv =================
[10:28:34] [PASSED] reflect-x
[10:28:34] [PASSED] reflect-y
[10:28:34] [PASSED] rotate-0
[10:28:34] [PASSED] rotate-90
[10:28:34] [PASSED] rotate-180
[10:28:34] [PASSED] rotate-270
[10:28:34] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:28:34] ==================== [PASSED] drm_rect =====================
[10:28:34] ============ drm_sysfb_modeset_test (1 subtest) ============
[10:28:34] ============ drm_test_sysfb_build_fourcc_list =============
[10:28:34] [PASSED] no native formats
[10:28:34] [PASSED] XRGB8888 as native format
[10:28:34] [PASSED] remove duplicates
[10:28:34] [PASSED] convert alpha formats
[10:28:34] [PASSED] random formats
[10:28:34] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[10:28:34] ============= [PASSED] drm_sysfb_modeset_test ==============
[10:28:34] ================== drm_fixp (2 subtests) ===================
[10:28:34] [PASSED] drm_test_int2fixp
[10:28:34] [PASSED] drm_test_sm2fixp
[10:28:34] ==================== [PASSED] drm_fixp =====================
[10:28:34] ============================================================
[10:28:34] Testing complete. Ran 621 tests: passed: 621
[10:28:34] Elapsed time: 26.071s total, 1.668s configuring, 24.186s building, 0.182s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[10:28:34] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:28:35] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:28:45] Starting KUnit Kernel (1/1)...
[10:28:45] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:28:45] ================= ttm_device (5 subtests) ==================
[10:28:45] [PASSED] ttm_device_init_basic
[10:28:45] [PASSED] ttm_device_init_multiple
[10:28:45] [PASSED] ttm_device_fini_basic
[10:28:45] [PASSED] ttm_device_init_no_vma_man
[10:28:45] ================== ttm_device_init_pools ==================
[10:28:45] [PASSED] No DMA allocations, no DMA32 required
[10:28:45] [PASSED] DMA allocations, DMA32 required
[10:28:45] [PASSED] No DMA allocations, DMA32 required
[10:28:45] [PASSED] DMA allocations, no DMA32 required
[10:28:45] ============== [PASSED] ttm_device_init_pools ==============
[10:28:45] =================== [PASSED] ttm_device ====================
[10:28:45] ================== ttm_pool (8 subtests) ===================
[10:28:45] ================== ttm_pool_alloc_basic ===================
[10:28:45] [PASSED] One page
[10:28:45] [PASSED] More than one page
[10:28:45] [PASSED] Above the allocation limit
[10:28:45] [PASSED] One page, with coherent DMA mappings enabled
[10:28:45] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:28:45] ============== [PASSED] ttm_pool_alloc_basic ===============
[10:28:45] ============== ttm_pool_alloc_basic_dma_addr ==============
[10:28:45] [PASSED] One page
[10:28:45] [PASSED] More than one page
[10:28:45] [PASSED] Above the allocation limit
[10:28:45] [PASSED] One page, with coherent DMA mappings enabled
[10:28:45] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:28:45] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[10:28:45] [PASSED] ttm_pool_alloc_order_caching_match
[10:28:45] [PASSED] ttm_pool_alloc_caching_mismatch
[10:28:45] [PASSED] ttm_pool_alloc_order_mismatch
[10:28:45] [PASSED] ttm_pool_free_dma_alloc
[10:28:45] [PASSED] ttm_pool_free_no_dma_alloc
[10:28:45] [PASSED] ttm_pool_fini_basic
[10:28:45] ==================== [PASSED] ttm_pool =====================
[10:28:45] ================ ttm_resource (8 subtests) =================
[10:28:45] ================= ttm_resource_init_basic =================
[10:28:45] [PASSED] Init resource in TTM_PL_SYSTEM
[10:28:45] [PASSED] Init resource in TTM_PL_VRAM
[10:28:45] [PASSED] Init resource in a private placement
[10:28:45] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[10:28:45] ============= [PASSED] ttm_resource_init_basic =============
[10:28:45] [PASSED] ttm_resource_init_pinned
[10:28:45] [PASSED] ttm_resource_fini_basic
[10:28:45] [PASSED] ttm_resource_manager_init_basic
[10:28:45] [PASSED] ttm_resource_manager_usage_basic
[10:28:45] [PASSED] ttm_resource_manager_set_used_basic
[10:28:45] [PASSED] ttm_sys_man_alloc_basic
[10:28:45] [PASSED] ttm_sys_man_free_basic
[10:28:45] ================== [PASSED] ttm_resource ===================
[10:28:45] =================== ttm_tt (15 subtests) ===================
[10:28:45] ==================== ttm_tt_init_basic ====================
[10:28:45] [PASSED] Page-aligned size
[10:28:45] [PASSED] Extra pages requested
[10:28:45] ================ [PASSED] ttm_tt_init_basic ================
[10:28:45] [PASSED] ttm_tt_init_misaligned
[10:28:45] [PASSED] ttm_tt_fini_basic
[10:28:45] [PASSED] ttm_tt_fini_sg
[10:28:45] [PASSED] ttm_tt_fini_shmem
[10:28:45] [PASSED] ttm_tt_create_basic
[10:28:45] [PASSED] ttm_tt_create_invalid_bo_type
[10:28:45] [PASSED] ttm_tt_create_ttm_exists
[10:28:45] [PASSED] ttm_tt_create_failed
[10:28:45] [PASSED] ttm_tt_destroy_basic
[10:28:45] [PASSED] ttm_tt_populate_null_ttm
[10:28:45] [PASSED] ttm_tt_populate_populated_ttm
[10:28:45] [PASSED] ttm_tt_unpopulate_basic
[10:28:45] [PASSED] ttm_tt_unpopulate_empty_ttm
[10:28:45] [PASSED] ttm_tt_swapin_basic
[10:28:45] ===================== [PASSED] ttm_tt ======================
[10:28:45] =================== ttm_bo (14 subtests) ===================
[10:28:45] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[10:28:45] [PASSED] Cannot be interrupted and sleeps
[10:28:45] [PASSED] Cannot be interrupted, locks straight away
[10:28:45] [PASSED] Can be interrupted, sleeps
[10:28:45] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[10:28:45] [PASSED] ttm_bo_reserve_locked_no_sleep
[10:28:45] [PASSED] ttm_bo_reserve_no_wait_ticket
[10:28:45] [PASSED] ttm_bo_reserve_double_resv
[10:28:45] [PASSED] ttm_bo_reserve_interrupted
[10:28:45] [PASSED] ttm_bo_reserve_deadlock
[10:28:45] [PASSED] ttm_bo_unreserve_basic
[10:28:45] [PASSED] ttm_bo_unreserve_pinned
[10:28:45] [PASSED] ttm_bo_unreserve_bulk
[10:28:45] [PASSED] ttm_bo_fini_basic
[10:28:45] [PASSED] ttm_bo_fini_shared_resv
[10:28:45] [PASSED] ttm_bo_pin_basic
[10:28:45] [PASSED] ttm_bo_pin_unpin_resource
[10:28:45] [PASSED] ttm_bo_multiple_pin_one_unpin
[10:28:45] ===================== [PASSED] ttm_bo ======================
[10:28:45] ============== ttm_bo_validate (21 subtests) ===============
[10:28:45] ============== ttm_bo_init_reserved_sys_man ===============
[10:28:45] [PASSED] Buffer object for userspace
[10:28:45] [PASSED] Kernel buffer object
[10:28:45] [PASSED] Shared buffer object
[10:28:45] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[10:28:45] ============== ttm_bo_init_reserved_mock_man ==============
[10:28:45] [PASSED] Buffer object for userspace
[10:28:45] [PASSED] Kernel buffer object
[10:28:45] [PASSED] Shared buffer object
[10:28:45] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[10:28:45] [PASSED] ttm_bo_init_reserved_resv
[10:28:45] ================== ttm_bo_validate_basic ==================
[10:28:45] [PASSED] Buffer object for userspace
[10:28:45] [PASSED] Kernel buffer object
[10:28:45] [PASSED] Shared buffer object
[10:28:45] ============== [PASSED] ttm_bo_validate_basic ==============
[10:28:45] [PASSED] ttm_bo_validate_invalid_placement
[10:28:45] ============= ttm_bo_validate_same_placement ==============
[10:28:45] [PASSED] System manager
[10:28:45] [PASSED] VRAM manager
[10:28:45] ========= [PASSED] ttm_bo_validate_same_placement ==========
[10:28:45] [PASSED] ttm_bo_validate_failed_alloc
[10:28:45] [PASSED] ttm_bo_validate_pinned
[10:28:45] [PASSED] ttm_bo_validate_busy_placement
[10:28:45] ================ ttm_bo_validate_multihop =================
[10:28:45] [PASSED] Buffer object for userspace
[10:28:45] [PASSED] Kernel buffer object
[10:28:45] [PASSED] Shared buffer object
[10:28:45] ============ [PASSED] ttm_bo_validate_multihop =============
[10:28:45] ========== ttm_bo_validate_no_placement_signaled ==========
[10:28:45] [PASSED] Buffer object in system domain, no page vector
[10:28:45] [PASSED] Buffer object in system domain with an existing page vector
[10:28:45] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[10:28:45] ======== ttm_bo_validate_no_placement_not_signaled ========
[10:28:45] [PASSED] Buffer object for userspace
[10:28:45] [PASSED] Kernel buffer object
[10:28:45] [PASSED] Shared buffer object
[10:28:45] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[10:28:45] [PASSED] ttm_bo_validate_move_fence_signaled
[10:28:45] ========= ttm_bo_validate_move_fence_not_signaled =========
[10:28:45] [PASSED] Waits for GPU
[10:28:45] [PASSED] Tries to lock straight away
[10:28:45] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[10:28:45] [PASSED] ttm_bo_validate_happy_evict
[10:28:45] [PASSED] ttm_bo_validate_all_pinned_evict
[10:28:45] [PASSED] ttm_bo_validate_allowed_only_evict
[10:28:45] [PASSED] ttm_bo_validate_deleted_evict
[10:28:45] [PASSED] ttm_bo_validate_busy_domain_evict
[10:28:45] [PASSED] ttm_bo_validate_evict_gutting
[10:28:45] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[10:28:45] ================= [PASSED] ttm_bo_validate =================
[10:28:45] ============================================================
[10:28:45] Testing complete. Ran 101 tests: passed: 101
[10:28:45] Elapsed time: 11.251s total, 1.677s configuring, 9.358s building, 0.176s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 19+ messages in thread* ✓ Xe.CI.BAT: success for Introduce Xe Correctable Error Handling (rev3)
2026-03-12 9:06 [PATCH v3 0/4] Introduce Xe Correctable Error Handling Raag Jadav
` (5 preceding siblings ...)
2026-03-12 10:28 ` ✓ CI.KUnit: success " Patchwork
@ 2026-03-12 11:15 ` Patchwork
2026-03-13 6:22 ` ✓ Xe.CI.FULL: " Patchwork
7 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2026-03-12 11:15 UTC (permalink / raw)
To: Raag Jadav; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 2797 bytes --]
== Series Details ==
Series: Introduce Xe Correctable Error Handling (rev3)
URL : https://patchwork.freedesktop.org/series/160184/
State : success
== Summary ==
CI Bug Log - changes from xe-4704-169ea69ad8f2fb0a126608399386e4580bb2d0b0_BAT -> xe-pw-160184v3_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (14 -> 14)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-160184v3_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1:
- bat-adlp-7: [PASS][1] -> [DMESG-WARN][2] ([Intel XE#7483])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4704-169ea69ad8f2fb0a126608399386e4580bb2d0b0/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html
#### Possible fixes ####
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- bat-adlp-7: [DMESG-WARN][3] ([Intel XE#7483]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4704-169ea69ad8f2fb0a126608399386e4580bb2d0b0/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
* igt@xe_waitfence@engine:
- bat-dg2-oem2: [FAIL][5] ([Intel XE#6519]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4704-169ea69ad8f2fb0a126608399386e4580bb2d0b0/bat-dg2-oem2/igt@xe_waitfence@engine.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/bat-dg2-oem2/igt@xe_waitfence@engine.html
* igt@xe_waitfence@reltime:
- bat-dg2-oem2: [FAIL][7] ([Intel XE#6520]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4704-169ea69ad8f2fb0a126608399386e4580bb2d0b0/bat-dg2-oem2/igt@xe_waitfence@reltime.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/bat-dg2-oem2/igt@xe_waitfence@reltime.html
[Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519
[Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520
[Intel XE#7483]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7483
Build changes
-------------
* IGT: IGT_8797 -> IGT_8798
* Linux: xe-4704-169ea69ad8f2fb0a126608399386e4580bb2d0b0 -> xe-pw-160184v3
IGT_8797: 8797
IGT_8798: 8798
xe-4704-169ea69ad8f2fb0a126608399386e4580bb2d0b0: 169ea69ad8f2fb0a126608399386e4580bb2d0b0
xe-pw-160184v3: 160184v3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/index.html
[-- Attachment #2: Type: text/html, Size: 3533 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread* ✓ Xe.CI.FULL: success for Introduce Xe Correctable Error Handling (rev3)
2026-03-12 9:06 [PATCH v3 0/4] Introduce Xe Correctable Error Handling Raag Jadav
` (6 preceding siblings ...)
2026-03-12 11:15 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-03-13 6:22 ` Patchwork
7 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2026-03-13 6:22 UTC (permalink / raw)
To: Raag Jadav; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 10046 bytes --]
== Series Details ==
Series: Introduce Xe Correctable Error Handling (rev3)
URL : https://patchwork.freedesktop.org/series/160184/
State : success
== Summary ==
CI Bug Log - changes from xe-4704-169ea69ad8f2fb0a126608399386e4580bb2d0b0_FULL -> xe-pw-160184v3_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-160184v3_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-lnl: NOTRUN -> [SKIP][1] ([Intel XE#3658] / [Intel XE#7360])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-lnl: NOTRUN -> [SKIP][2] ([Intel XE#1407])
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-8/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p:
- shard-lnl: NOTRUN -> [SKIP][3] ([Intel XE#2191] / [Intel XE#7373])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-5/igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
- shard-lnl: NOTRUN -> [SKIP][4] ([Intel XE#3432])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-5/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs:
- shard-lnl: NOTRUN -> [SKIP][5] ([Intel XE#2887])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-8/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs.html
* igt@kms_cursor_crc@cursor-sliding-32x32:
- shard-lnl: NOTRUN -> [SKIP][6] ([Intel XE#1424])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-2/igt@kms_cursor_crc@cursor-sliding-32x32.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
- shard-lnl: NOTRUN -> [SKIP][7] ([Intel XE#309] / [Intel XE#7343]) +1 other test skip
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-7/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
* igt@kms_feature_discovery@display-3x:
- shard-lnl: NOTRUN -> [SKIP][8] ([Intel XE#703] / [Intel XE#7448])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-7/igt@kms_feature_discovery@display-3x.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling:
- shard-lnl: NOTRUN -> [SKIP][9] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][10] ([Intel XE#1397] / [Intel XE#7385])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-shrfb-draw-mmap-wc:
- shard-lnl: NOTRUN -> [SKIP][11] ([Intel XE#6312])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-6/igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-2p-rte:
- shard-lnl: NOTRUN -> [SKIP][12] ([Intel XE#656]) +3 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-3/igt@kms_frontbuffer_tracking@drrs-2p-rte.html
* igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render:
- shard-lnl: NOTRUN -> [SKIP][13] ([Intel XE#6312] / [Intel XE#651]) +2 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-8/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
- shard-lnl: NOTRUN -> [SKIP][14] ([Intel XE#2893] / [Intel XE#7304])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-8/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html
* igt@kms_psr@fbc-pr-cursor-plane-move:
- shard-lnl: NOTRUN -> [SKIP][15] ([Intel XE#1406])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-4/igt@kms_psr@fbc-pr-cursor-plane-move.html
* igt@xe_eudebug@vma-ufence-faultable:
- shard-lnl: NOTRUN -> [SKIP][16] ([Intel XE#4837])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-8/igt@xe_eudebug@vma-ufence-faultable.html
* igt@xe_evict@evict-beng-threads-small-multi-vm:
- shard-lnl: NOTRUN -> [SKIP][17] ([Intel XE#6540] / [Intel XE#688]) +1 other test skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-2/igt@xe_evict@evict-beng-threads-small-multi-vm.html
* igt@xe_exec_balancer@many-parallel-userptr:
- shard-lnl: NOTRUN -> [SKIP][18] ([Intel XE#7482])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-1/igt@xe_exec_balancer@many-parallel-userptr.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind:
- shard-lnl: NOTRUN -> [SKIP][19] ([Intel XE#1392]) +1 other test skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-4/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind.html
* igt@xe_exec_multi_queue@many-execs-close-fd:
- shard-lnl: NOTRUN -> [SKIP][20] ([Intel XE#6874]) +3 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-7/igt@xe_exec_multi_queue@many-execs-close-fd.html
* igt@xe_exec_threads@threads-multi-queue-mixed-rebind:
- shard-lnl: NOTRUN -> [SKIP][21] ([Intel XE#7138])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-2/igt@xe_exec_threads@threads-multi-queue-mixed-rebind.html
* igt@xe_multigpu_svm@mgpu-concurrent-access-basic:
- shard-lnl: NOTRUN -> [SKIP][22] ([Intel XE#6964])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-5/igt@xe_multigpu_svm@mgpu-concurrent-access-basic.html
* igt@xe_pat@pat-index-xelpg:
- shard-lnl: NOTRUN -> [SKIP][23] ([Intel XE#979])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-1/igt@xe_pat@pat-index-xelpg.html
#### Possible fixes ####
* igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
- shard-lnl: [FAIL][24] ([Intel XE#2142]) -> [PASS][25] +1 other test pass
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4704-169ea69ad8f2fb0a126608399386e4580bb2d0b0/shard-lnl-7/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/shard-lnl-3/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703
[Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
[Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
[Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
[Intel XE#7360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7360
[Intel XE#7373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7373
[Intel XE#7385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7385
[Intel XE#7448]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7448
[Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
[Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979
Build changes
-------------
* IGT: IGT_8797 -> IGT_8798
* Linux: xe-4704-169ea69ad8f2fb0a126608399386e4580bb2d0b0 -> xe-pw-160184v3
IGT_8797: 8797
IGT_8798: 8798
xe-4704-169ea69ad8f2fb0a126608399386e4580bb2d0b0: 169ea69ad8f2fb0a126608399386e4580bb2d0b0
xe-pw-160184v3: 160184v3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v3/index.html
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