Re: [PATCH] drm/xe: Skip media GT TLB invalidation when VM has no queues mapped

[Matthew Brost <matthew.brost@intel.com>]

On Mon, Mar 23, 2026 at 10:13:28AM -0600, Summers, Stuart wrote:
> On Wed, 2026-03-04 at 15:37 -0800, Matthew Brost wrote:
> > If no exec queues from a VM are mapped on the media GT, issuing a
> > PPGTT TLB invalidation for that GT requires an rc6 wake which is
> > expensive.
> > 
> > Skip the media GT TLB invalidation when the VM has no exec queues
> > mapped on it. If TLB invalidations are already in-flight on that GT
> > we can't break fence ordering, so issue a dummy GGTT invalidation
> > instead to maintain seqno ordering.
> > 
> > This optimization is particularly impactful for SVM workloads which
> > may or may not use the media GT. Average TLB invalidation time drops
> > from ~75us to ~18us in such benchmarks.
> 
> So.. what if the user creates the VM, binds it, and only then creates
> an exec queue and submits?
> 

I would think the TLBs would be empty but something is clearly wrong in
patch per CI and perhaps this is the problem. Need to dig into failures
this week.

Matt
 
> -Stuart
> 
> > 
> > Assisted-by: GitHub Copilot:claude-sonnet-4.6 # Documentation only.
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 43
> > +++++++++++++++++++++++++--
> >  1 file changed, 41 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > index ced58f46f846..20c34469d9a5 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > +++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > @@ -205,14 +205,53 @@ static int send_tlb_inval_asid_ppgtt(struct
> > xe_tlb_inval *tlb_inval, u32 seqno,
> >                                      struct drm_suballoc *prl_sa)
> >  {
> >         struct xe_guc *guc = tlb_inval->private;
> > +       struct xe_device *xe = guc_to_xe(guc);
> > +       struct xe_gt *gt = guc_to_gt(guc);
> > +       struct xe_vm *vm;
> > +       int err = 0, id = guc_to_gt(guc)->info.id;
> >  
> >         lockdep_assert_held(&tlb_inval->seqno_lock);
> >  
> >         if (guc_to_xe(guc)->info.force_execlist)
> >                 return -ECANCELED;
> >  
> > -       return send_tlb_inval_ppgtt(guc, seqno, start, end, asid,
> > -                                   XE_GUC_TLB_INVAL_PAGE_SELECTIVE,
> > prl_sa);
> > +       if (!xe_gt_is_media_type(gt))
> > +               return send_tlb_inval_ppgtt(guc, seqno, start, end,
> > asid,
> > +                                          
> > XE_GUC_TLB_INVAL_PAGE_SELECTIVE,
> > +                                           prl_sa);
> > +
> > +       /* Try to skip media GT TLB invalidations */
> > +
> > +       vm = xe_device_asid_to_vm(xe, asid);
> > +       if (IS_ERR(vm))
> > +               return PTR_ERR(vm);
> > +
> > +       down_read(&vm->exec_queues.lock);
> > +
> > +       if (!vm->exec_queues.count[id]) {
> > +               /*
> > +                * We can't break fence ordering for TLB invalidation
> > jobs, if
> > +                * TLB invalidations are inflight issue a dummy
> > invalidation to
> > +                * maintain ordering. Nor can we move safely the
> > seqno_recv when
> > +                * returning -ECANCELED if TLB invalidations are in
> > flight. Use
> > +                * GGTT invalidation as dummy invalidation given ASID
> > +                * invalidations are unsupported here.
> > +                */
> > +               if (xe_tlb_inval_idle(tlb_inval))
> > +                       err = -ECANCELED;
> > +               else
> > +                       err = send_tlb_inval_ggtt(tlb_inval, seqno);
> > +               goto err_unlock;
> > +       }
> > +
> > +       err = send_tlb_inval_ppgtt(guc, seqno, start, end, asid,
> > +                                  XE_GUC_TLB_INVAL_PAGE_SELECTIVE,
> > prl_sa);
> > +
> > +err_unlock:
> > +       up_read(&vm->exec_queues.lock);
> > +       xe_vm_put(vm);
> > +
> > +       return err;
> >  }
> >  
> >  static int send_tlb_inval_ctx_ppgtt(struct xe_tlb_inval *tlb_inval,
> > u32 seqno,
>