[PATCH 0/8] drm/i915: move more display dependencies from i915

[PATCH 0/8] drm/i915: move more display dependencies from i915

[Luca Coelho]

Hi,

This series continues my work of refactoring the clock gating
initialization, so that i915 doesn't do display-specific stuff.

With this, all register dependencies should be gone.

Please review.

Cheers,
Luca.


Luca Coelho (8):
  drm/i915: move SKL clock gating init to display
  drm/i915: move KBL clock gating init to display
  drm/i915/display: move CFL clock gating init to display
  drm/i915/display: move BXT clock gating init to display
  drm/i915/display: move GLK clock gating init to display
  drm/i915/display: move HSW and BDW clock gating init to display
  drm/i915/display: move pre-HSW clock gating init to display
  drm/i915: remove HAS_PCH_NOP() dependency from clock gating

 drivers/gpu/drm/i915/Makefile                 |   1 +
 .../i915/display/intel_display_clock_gating.c | 258 ++++++++++++++++++
 .../i915/display/intel_display_clock_gating.h |  43 +++
 drivers/gpu/drm/i915/intel_clock_gating.c     | 229 ++--------------
 4 files changed, 319 insertions(+), 212 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.h

-- 
2.53.0

[PATCH 1/8] drm/i915: move SKL clock gating init to display

[Luca Coelho]

Move the SKL-specific display clock gating programming into a new file
inside display.

This removes dependency from intel_clock_gating.c to the display's
intel_pch.h file, so we can remove the include statement.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |  1 +
 .../i915/display/intel_display_clock_gating.c | 19 +++++++++++++++++++
 .../i915/display/intel_display_clock_gating.h | 17 +++++++++++++++++
 drivers/gpu/drm/i915/intel_clock_gating.c     |  8 ++------
 4 files changed, 39 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index be976a90c5a6..89232873d4b7 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -254,6 +254,7 @@ i915-y += \
 	display/intel_crtc_state_dump.o \
 	display/intel_cursor.o \
 	display/intel_dbuf_bw.o \
+	display/intel_display_clock_gating.o \
 	display/intel_display.o \
 	display/intel_display_conversion.o \
 	display/intel_display_driver.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
new file mode 100644
index 000000000000..4a94593335e0
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2026 Intel Corporation
+ */
+
+#include <drm/intel/intel_gmd_misc_regs.h>
+
+#include "intel_de.h"
+#include "intel_display_clock_gating.h"
+#include "intel_display_regs.h"
+
+void intel_display_skl_init_clock_gating(struct intel_display *display)
+{
+	/*
+	 * WaFbcTurnOffFbcWatermark:skl
+	 * Display WA #0562: skl
+	 */
+	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
new file mode 100644
index 000000000000..c93997417dcb
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2026 Intel Corporation
+ */
+
+#ifndef __INTEL_DISPLAY_CLOCK_GATING_H__
+#define __INTEL_DISPLAY_CLOCK_GATING_H__
+
+struct intel_display;
+
+#ifdef I915
+void intel_display_skl_init_clock_gating(struct intel_display *display);
+#else
+static inline void intel_display_skl_init_clock_gating(struct intel_display *display) {}
+#endif
+
+#endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index ee2489a2fbe7..454334fef5e7 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -31,9 +31,9 @@
 
 #include "display/i9xx_plane_regs.h"
 #include "display/intel_display.h"
+#include "display/intel_display_clock_gating.h"
 #include "display/intel_display_core.h"
 #include "display/intel_display_regs.h"
-#include "display/intel_pch.h"
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_mcr.h"
@@ -349,11 +349,7 @@ static void skl_init_clock_gating(struct drm_i915_private *i915)
 	/* WAC6entrylatency:skl */
 	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
 
-	/*
-	 * WaFbcTurnOffFbcWatermark:skl
-	 * Display WA #0562: skl
-	 */
-	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+	intel_display_skl_init_clock_gating(i915->display);
 }
 
 static void bdw_init_clock_gating(struct drm_i915_private *i915)
-- 
2.53.0

[PATCH 2/8] drm/i915: move KBL clock gating init to display

[Luca Coelho]

Move the KBL-specific display clock gating programming into a
display intel_display_clock_gating.c, to remove more dependencies from
i915 to display registers.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../gpu/drm/i915/display/intel_display_clock_gating.c    | 9 +++++++++
 .../gpu/drm/i915/display/intel_display_clock_gating.h    | 2 ++
 drivers/gpu/drm/i915/intel_clock_gating.c                | 6 +-----
 3 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index 4a94593335e0..508735212d6b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -17,3 +17,12 @@ void intel_display_skl_init_clock_gating(struct intel_display *display)
 	 */
 	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
 }
+
+void intel_display_kbl_init_clock_gating(struct intel_display *display)
+{
+	/*
+	 * WaFbcTurnOffFbcWatermark:kbl
+	 * Display WA #0562: kbl
+	 */
+	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index c93997417dcb..d4f33b23e0b0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -10,8 +10,10 @@ struct intel_display;
 
 #ifdef I915
 void intel_display_skl_init_clock_gating(struct intel_display *display);
+void intel_display_kbl_init_clock_gating(struct intel_display *display);
 #else
 static inline void intel_display_skl_init_clock_gating(struct intel_display *display) {}
+static inline void intel_display_kbl_init_clock_gating(struct intel_display *display) {}
 #endif
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 454334fef5e7..5f7910dbe164 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -331,11 +331,7 @@ static void kbl_init_clock_gating(struct drm_i915_private *i915)
 		intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1,
 				 0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
 
-	/*
-	 * WaFbcTurnOffFbcWatermark:kbl
-	 * Display WA #0562: kbl
-	 */
-	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+	intel_display_kbl_init_clock_gating(i915->display);
 }
 
 static void skl_init_clock_gating(struct drm_i915_private *i915)
-- 
2.53.0

[PATCH 3/8] drm/i915/display: move CFL clock gating init to display

[Luca Coelho]

Move the CFL/CML-specific display clock gating programming into
display intel_display_clock_gating.c, to remove more dependencies from
i915 to display registers.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../gpu/drm/i915/display/intel_display_clock_gating.c    | 9 +++++++++
 .../gpu/drm/i915/display/intel_display_clock_gating.h    | 2 ++
 drivers/gpu/drm/i915/intel_clock_gating.c                | 6 +-----
 3 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index 508735212d6b..82ea21d7377d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -26,3 +26,12 @@ void intel_display_kbl_init_clock_gating(struct intel_display *display)
 	 */
 	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
 }
+
+void intel_display_cfl_init_clock_gating(struct intel_display *display)
+{
+	/*
+	 * WaFbcTurnOffFbcWatermark:cfl
+	 * Display WA #0562: cfl
+	 */
+	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index d4f33b23e0b0..e0833c5452c5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -11,9 +11,11 @@ struct intel_display;
 #ifdef I915
 void intel_display_skl_init_clock_gating(struct intel_display *display);
 void intel_display_kbl_init_clock_gating(struct intel_display *display);
+void intel_display_cfl_init_clock_gating(struct intel_display *display);
 #else
 static inline void intel_display_skl_init_clock_gating(struct intel_display *display) {}
 static inline void intel_display_kbl_init_clock_gating(struct intel_display *display) {}
+static inline void intel_display_cfl_init_clock_gating(struct intel_display *display) {}
 #endif
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 5f7910dbe164..b9bd23c2731e 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -307,11 +307,7 @@ static void cfl_init_clock_gating(struct drm_i915_private *i915)
 	/* WAC6entrylatency:cfl */
 	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
 
-	/*
-	 * WaFbcTurnOffFbcWatermark:cfl
-	 * Display WA #0562: cfl
-	 */
-	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+	intel_display_cfl_init_clock_gating(i915->display);
 }
 
 static void kbl_init_clock_gating(struct drm_i915_private *i915)
-- 
2.53.0

[PATCH 4/8] drm/i915/display: move BXT clock gating init to display

[Luca Coelho]

Move the BXT-specific display clock gating programming into display
intel_display_clock_gating.c, to remove more dependencies from i915.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../i915/display/intel_display_clock_gating.c | 25 +++++++++++++++++++
 .../i915/display/intel_display_clock_gating.h |  2 ++
 drivers/gpu/drm/i915/intel_clock_gating.c     | 22 +---------------
 3 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index 82ea21d7377d..59041c807d6d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -35,3 +35,28 @@ void intel_display_cfl_init_clock_gating(struct intel_display *display)
 	 */
 	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
 }
+
+void intel_display_bxt_init_clock_gating(struct intel_display *display)
+{
+	/*
+	 * Wa: Backlight PWM may stop in the asserted state, causing backlight
+	 * to stay fully on.
+	 */
+	intel_de_write(display, GEN9_CLKGATE_DIS_0,
+		       intel_de_read(display, GEN9_CLKGATE_DIS_0) |
+		       PWM1_GATING_DIS | PWM2_GATING_DIS);
+
+	/*
+	 * Lower the display internal timeout.
+	 * This is needed to avoid any hard hangs when DSI port PLL
+	 * is off and a MMIO access is attempted by any privilege
+	 * application, using batch buffers or any other means.
+	 */
+	intel_de_write(display, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
+
+	/*
+	 * WaFbcTurnOffFbcWatermark:bxt
+	 * Display WA #0562: bxt
+	 */
+	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index e0833c5452c5..3512b00b240d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -12,10 +12,12 @@ struct intel_display;
 void intel_display_skl_init_clock_gating(struct intel_display *display);
 void intel_display_kbl_init_clock_gating(struct intel_display *display);
 void intel_display_cfl_init_clock_gating(struct intel_display *display);
+void intel_display_bxt_init_clock_gating(struct intel_display *display);
 #else
 static inline void intel_display_skl_init_clock_gating(struct intel_display *display) {}
 static inline void intel_display_kbl_init_clock_gating(struct intel_display *display) {}
 static inline void intel_display_cfl_init_clock_gating(struct intel_display *display) {}
+static inline void intel_display_bxt_init_clock_gating(struct intel_display *display) {}
 #endif
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index b9bd23c2731e..4c1937d922b2 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -88,27 +88,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *i915)
 	 */
 	intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 
-	/*
-	 * Wa: Backlight PWM may stop in the asserted state, causing backlight
-	 * to stay fully on.
-	 */
-	intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
-			   intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
-			   PWM1_GATING_DIS | PWM2_GATING_DIS);
-
-	/*
-	 * Lower the display internal timeout.
-	 * This is needed to avoid any hard hangs when DSI port PLL
-	 * is off and a MMIO access is attempted by any privilege
-	 * application, using batch buffers or any other means.
-	 */
-	intel_uncore_write(&i915->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
-
-	/*
-	 * WaFbcTurnOffFbcWatermark:bxt
-	 * Display WA #0562: bxt
-	 */
-	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+	intel_display_bxt_init_clock_gating(i915->display);
 }
 
 static void glk_init_clock_gating(struct drm_i915_private *i915)
-- 
2.53.0

[PATCH 5/8] drm/i915/display: move GLK clock gating init to display

[Luca Coelho]

Move the GLK-specific display clock gating programming into display
intel_display_clock_gating.c, to remove more dependencies from i915 to
display registers.

Now that all remaining Gen9-family callers moved into display, we can
move the shared Gen9 display clock gating helper into display and
remove the old local helper from intel_clock_gating.c.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../i915/display/intel_display_clock_gating.c | 63 +++++++++++++++++++
 .../i915/display/intel_display_clock_gating.h |  2 +
 drivers/gpu/drm/i915/intel_clock_gating.c     | 44 +------------
 3 files changed, 66 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index 59041c807d6d..e3b7522b4101 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -6,11 +6,46 @@
 #include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "intel_de.h"
+#include "intel_display.h"
 #include "intel_display_clock_gating.h"
 #include "intel_display_regs.h"
 
+#include "i915_drv.h"
+
+static void intel_display_gen9_init_clock_gating(struct intel_display *display,
+						 bool has_llc)
+{
+	if (has_llc) {
+		/*
+		 * WaCompressedResourceDisplayNewHashMode:skl,kbl
+		 * Display WA #0390: skl,kbl
+		 *
+		 * Must match Sampler, Pixel Back End, and Media. See
+		 * WaCompressedResourceSamplerPbeMediaNewHashMode.
+		 */
+		intel_de_rmw(display, CHICKEN_PAR1_1, 0,
+			     SKL_DE_COMPRESSED_HASH_MODE);
+	}
+
+	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
+	intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
+
+	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
+	intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
+
+	/*
+	 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
+	 * Display WA #0859: skl,bxt,kbl,glk,cfl
+	 */
+	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
+}
+
 void intel_display_skl_init_clock_gating(struct intel_display *display)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
+
+	intel_display_gen9_init_clock_gating(display, HAS_LLC(i915));
+
 	/*
 	 * WaFbcTurnOffFbcWatermark:skl
 	 * Display WA #0562: skl
@@ -20,6 +55,10 @@ void intel_display_skl_init_clock_gating(struct intel_display *display)
 
 void intel_display_kbl_init_clock_gating(struct intel_display *display)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
+
+	intel_display_gen9_init_clock_gating(display, HAS_LLC(i915));
+
 	/*
 	 * WaFbcTurnOffFbcWatermark:kbl
 	 * Display WA #0562: kbl
@@ -29,6 +68,10 @@ void intel_display_kbl_init_clock_gating(struct intel_display *display)
 
 void intel_display_cfl_init_clock_gating(struct intel_display *display)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
+
+	intel_display_gen9_init_clock_gating(display, HAS_LLC(i915));
+
 	/*
 	 * WaFbcTurnOffFbcWatermark:cfl
 	 * Display WA #0562: cfl
@@ -38,6 +81,10 @@ void intel_display_cfl_init_clock_gating(struct intel_display *display)
 
 void intel_display_bxt_init_clock_gating(struct intel_display *display)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
+
+	intel_display_gen9_init_clock_gating(display, HAS_LLC(i915));
+
 	/*
 	 * Wa: Backlight PWM may stop in the asserted state, causing backlight
 	 * to stay fully on.
@@ -60,3 +107,19 @@ void intel_display_bxt_init_clock_gating(struct intel_display *display)
 	 */
 	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
 }
+
+void intel_display_glk_init_clock_gating(struct intel_display *display)
+{
+	struct drm_i915_private *i915 = to_i915(display->drm);
+
+	intel_display_gen9_init_clock_gating(display, HAS_LLC(i915));
+
+	/*
+	 * WaDisablePWMClockGating:glk
+	 * Backlight PWM may stop in the asserted state, causing backlight
+	 * to stay fully on.
+	 */
+	intel_de_write(display, GEN9_CLKGATE_DIS_0,
+		       intel_de_read(display, GEN9_CLKGATE_DIS_0) |
+		       PWM1_GATING_DIS | PWM2_GATING_DIS);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index 3512b00b240d..4abd34fa5832 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -13,11 +13,13 @@ void intel_display_skl_init_clock_gating(struct intel_display *display);
 void intel_display_kbl_init_clock_gating(struct intel_display *display);
 void intel_display_cfl_init_clock_gating(struct intel_display *display);
 void intel_display_bxt_init_clock_gating(struct intel_display *display);
+void intel_display_glk_init_clock_gating(struct intel_display *display);
 #else
 static inline void intel_display_skl_init_clock_gating(struct intel_display *display) {}
 static inline void intel_display_kbl_init_clock_gating(struct intel_display *display) {}
 static inline void intel_display_cfl_init_clock_gating(struct intel_display *display) {}
 static inline void intel_display_bxt_init_clock_gating(struct intel_display *display) {}
+static inline void intel_display_glk_init_clock_gating(struct intel_display *display) {}
 #endif
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 4c1937d922b2..777314e0c75d 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -49,36 +49,8 @@ struct drm_i915_clock_gating_funcs {
 	void (*init_clock_gating)(struct drm_i915_private *i915);
 };
 
-static void gen9_init_clock_gating(struct drm_i915_private *i915)
-{
-	if (HAS_LLC(i915)) {
-		/*
-		 * WaCompressedResourceDisplayNewHashMode:skl,kbl
-		 * Display WA #0390: skl,kbl
-		 *
-		 * Must match Sampler, Pixel Back End, and Media. See
-		 * WaCompressedResourceSamplerPbeMediaNewHashMode.
-		 */
-		intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
-	}
-
-	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
-
-	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
-	intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
-
-	/*
-	 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
-	 * Display WA #0859: skl,bxt,kbl,glk,cfl
-	 */
-	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
-}
-
 static void bxt_init_clock_gating(struct drm_i915_private *i915)
 {
-	gen9_init_clock_gating(i915);
-
 	/* WaDisableSDEUnitClockGating:bxt */
 	intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
@@ -93,16 +65,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *i915)
 
 static void glk_init_clock_gating(struct drm_i915_private *i915)
 {
-	gen9_init_clock_gating(i915);
-
-	/*
-	 * WaDisablePWMClockGating:glk
-	 * Backlight PWM may stop in the asserted state, causing backlight
-	 * to stay fully on.
-	 */
-	intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
-			   intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
-			   PWM1_GATING_DIS | PWM2_GATING_DIS);
+	intel_display_glk_init_clock_gating(i915->display);
 }
 
 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
@@ -282,7 +245,6 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915)
 static void cfl_init_clock_gating(struct drm_i915_private *i915)
 {
 	intel_pch_init_clock_gating(i915->display);
-	gen9_init_clock_gating(i915);
 
 	/* WAC6entrylatency:cfl */
 	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
@@ -292,8 +254,6 @@ static void cfl_init_clock_gating(struct drm_i915_private *i915)
 
 static void kbl_init_clock_gating(struct drm_i915_private *i915)
 {
-	gen9_init_clock_gating(i915);
-
 	/* WAC6entrylatency:kbl */
 	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
 
@@ -312,8 +272,6 @@ static void kbl_init_clock_gating(struct drm_i915_private *i915)
 
 static void skl_init_clock_gating(struct drm_i915_private *i915)
 {
-	gen9_init_clock_gating(i915);
-
 	/* WaDisableDopClockGating:skl */
 	intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,
 			 GEN7_DOP_CLOCK_GATE_ENABLE, 0);
-- 
2.53.0

[PATCH 6/8] drm/i915/display: move HSW and BDW clock gating init to display

[Luca Coelho]

Move the HSW and BDW display clock gating programming into the display
code.  In this case we need two different helpers, because the common
code between these two is split in the middle.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../i915/display/intel_display_clock_gating.c | 33 +++++++++++++++++++
 .../i915/display/intel_display_clock_gating.h |  6 ++++
 drivers/gpu/drm/i915/intel_clock_gating.c     | 31 +++--------------
 3 files changed, 43 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index e3b7522b4101..0b2edf6acb79 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -123,3 +123,36 @@ void intel_display_glk_init_clock_gating(struct intel_display *display)
 		       intel_de_read(display, GEN9_CLKGATE_DIS_0) |
 		       PWM1_GATING_DIS | PWM2_GATING_DIS);
 }
+
+static void
+intel_display_hsw_init_clock_gating_common(struct intel_display *display,
+					   u32 unmask_vbl)
+{
+	enum pipe pipe;
+
+	/* WaPsrDPAMaskVBlankInSRD:hsw */
+	intel_de_rmw(display, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
+
+	for_each_pipe(display, pipe) {
+		/* WaPsrDPRSUnmaskVBlankInSRD:hsw,bdw */
+		intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 0, unmask_vbl);
+	}
+}
+
+void intel_display_bdw_hsw_init_clock_gating(struct intel_display *display)
+{
+	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
+	intel_de_rmw(display, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
+}
+
+void intel_display_bdw_init_clock_gating(struct intel_display *display)
+{
+	intel_display_hsw_init_clock_gating_common(display,
+						   BDW_UNMASK_VBL_TO_REGS_IN_SRD);
+}
+
+void intel_display_hsw_init_clock_gating(struct intel_display *display)
+{
+	intel_display_hsw_init_clock_gating_common(display,
+						   HSW_UNMASK_VBL_TO_REGS_IN_SRD);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index 4abd34fa5832..0eb240f2f69e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -14,12 +14,18 @@ void intel_display_kbl_init_clock_gating(struct intel_display *display);
 void intel_display_cfl_init_clock_gating(struct intel_display *display);
 void intel_display_bxt_init_clock_gating(struct intel_display *display);
 void intel_display_glk_init_clock_gating(struct intel_display *display);
+void intel_display_bdw_hsw_init_clock_gating(struct intel_display *display);
+void intel_display_bdw_init_clock_gating(struct intel_display *display);
+void intel_display_hsw_init_clock_gating(struct intel_display *display);
 #else
 static inline void intel_display_skl_init_clock_gating(struct intel_display *display) {}
 static inline void intel_display_kbl_init_clock_gating(struct intel_display *display) {}
 static inline void intel_display_cfl_init_clock_gating(struct intel_display *display) {}
 static inline void intel_display_bxt_init_clock_gating(struct intel_display *display) {}
 static inline void intel_display_glk_init_clock_gating(struct intel_display *display) {}
+static inline void intel_display_bdw_hsw_init_clock_gating(struct intel_display *display) {}
+static inline void intel_display_bdw_init_clock_gating(struct intel_display *display) {}
+static inline void intel_display_hsw_init_clock_gating(struct intel_display *display) {}
 #endif
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 777314e0c75d..a8e3eb6f06c8 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -284,23 +284,12 @@ static void skl_init_clock_gating(struct drm_i915_private *i915)
 
 static void bdw_init_clock_gating(struct drm_i915_private *i915)
 {
-	struct intel_display *display = i915->display;
-	enum pipe pipe;
-
-	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
+	intel_display_bdw_hsw_init_clock_gating(i915->display);
 
 	/* WaSwitchSolVfFArbitrationPriority:bdw */
 	intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
 
-	/* WaPsrDPAMaskVBlankInSRD:bdw */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
-
-	for_each_pipe(display, pipe) {
-		/* WaPsrDPRSUnmaskVBlankInSRD:bdw */
-		intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
-				 0, BDW_UNMASK_VBL_TO_REGS_IN_SRD);
-	}
+	intel_display_bdw_init_clock_gating(i915->display);
 
 	/* WaVSRefCountFullforceMissDisable:bdw */
 	/* WaDSRefCountFullforceMissDisable:bdw */
@@ -332,20 +321,8 @@ static void bdw_init_clock_gating(struct drm_i915_private *i915)
 
 static void hsw_init_clock_gating(struct drm_i915_private *i915)
 {
-	struct intel_display *display = i915->display;
-	enum pipe pipe;
-
-	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
-
-	/* WaPsrDPAMaskVBlankInSRD:hsw */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
-
-	for_each_pipe(display, pipe) {
-		/* WaPsrDPRSUnmaskVBlankInSRD:hsw */
-		intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
-				 0, HSW_UNMASK_VBL_TO_REGS_IN_SRD);
-	}
+	intel_display_bdw_hsw_init_clock_gating(i915->display);
+	intel_display_hsw_init_clock_gating(i915->display);
 
 	/* This is required by WaCatErrorRejectionIssue:hsw */
 	intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
-- 
2.53.0

[PATCH 7/8] drm/i915/display: move pre-HSW clock gating init to display

[Luca Coelho]

Move the remaining pre-HSW display clock gating programming into
display.

This also drops display register includes from intel_clock_gating.c.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../i915/display/intel_display_clock_gating.c | 100 ++++++++++++++++
 .../i915/display/intel_display_clock_gating.h |  12 ++
 drivers/gpu/drm/i915/intel_clock_gating.c     | 109 +-----------------
 3 files changed, 118 insertions(+), 103 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index 0b2edf6acb79..5809c49dccf0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -6,11 +6,13 @@
 #include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "intel_de.h"
+#include "i9xx_plane_regs.h"
 #include "intel_display.h"
 #include "intel_display_clock_gating.h"
 #include "intel_display_regs.h"
 
 #include "i915_drv.h"
+#include "i915_reg.h"
 
 static void intel_display_gen9_init_clock_gating(struct intel_display *display,
 						 bool has_llc)
@@ -156,3 +158,101 @@ void intel_display_hsw_init_clock_gating(struct intel_display *display)
 	intel_display_hsw_init_clock_gating_common(display,
 						   HSW_UNMASK_VBL_TO_REGS_IN_SRD);
 }
+
+void intel_display_disable_trickle_feed(struct intel_display *display)
+{
+	enum pipe pipe;
+
+	for_each_pipe(display, pipe) {
+		intel_de_rmw(display, DSPCNTR(display, pipe), 0,
+			     DISP_TRICKLE_FEED_DISABLE);
+
+		intel_de_rmw(display, DSPSURF(display, pipe), 0, 0);
+		intel_de_posting_read(display, DSPSURF(display, pipe));
+	}
+}
+
+void intel_display_ilk_init_clock_gating(struct intel_display *display)
+{
+	struct drm_i915_private *i915 = to_i915(display->drm);
+	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
+
+	/*
+	 * Required for FBC
+	 * WaFbcDisableDpfcClockGating:ilk
+	 */
+	dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
+		       ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
+		       ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
+
+	intel_de_write(display, PCH_3DCGDIS0,
+		       MARIUNIT_CLOCK_GATE_DISABLE |
+		       SVSMUNIT_CLOCK_GATE_DISABLE);
+	intel_de_write(display, PCH_3DCGDIS1, VFMUNIT_CLOCK_GATE_DISABLE);
+
+	intel_de_write(display, ILK_DISPLAY_CHICKEN2,
+		       intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
+		       ILK_DPARB_GATE | ILK_VSDPFD_FULL);
+	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
+	intel_de_write(display, DISP_ARB_CTL,
+		       intel_de_read(display, DISP_ARB_CTL) |
+		       DISP_FBC_WM_DIS);
+
+	if (IS_IRONLAKE_M(i915)) {
+		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
+		intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
+		intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
+	}
+
+	intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
+	intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
+
+	intel_display_disable_trickle_feed(display);
+}
+
+void intel_display_gen6_init_clock_gating(struct intel_display *display)
+{
+	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
+
+	intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
+	intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
+
+	intel_de_write(display, ILK_DISPLAY_CHICKEN1,
+		       intel_de_read(display, ILK_DISPLAY_CHICKEN1) |
+		       ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
+	intel_de_write(display, ILK_DISPLAY_CHICKEN2,
+		       intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
+		       ILK_DPARB_GATE | ILK_VSDPFD_FULL);
+	intel_de_write(display, ILK_DSPCLK_GATE_D,
+		       intel_de_read(display, ILK_DSPCLK_GATE_D) |
+		       ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
+		       ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
+
+	intel_display_disable_trickle_feed(display);
+}
+
+void intel_display_ivb_init_clock_gating(struct intel_display *display)
+{
+	intel_de_write(display, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
+	intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
+}
+
+void intel_display_g4x_init_clock_gating(struct intel_display *display)
+{
+	struct drm_i915_private *i915 = to_i915(display->drm);
+	u32 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
+			  OVRUNIT_CLOCK_GATE_DISABLE |
+			  OVCUNIT_CLOCK_GATE_DISABLE;
+
+	if (IS_GM45(i915))
+		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
+
+	intel_de_write(display, DSPCLK_GATE_D, dspclk_gate);
+
+	intel_display_disable_trickle_feed(display);
+}
+
+void intel_display_i965gm_init_clock_gating(struct intel_display *display)
+{
+	intel_de_write(display, DSPCLK_GATE_D, 0);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index 0eb240f2f69e..9eebfc4a6ebe 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -17,6 +17,12 @@ void intel_display_glk_init_clock_gating(struct intel_display *display);
 void intel_display_bdw_hsw_init_clock_gating(struct intel_display *display);
 void intel_display_bdw_init_clock_gating(struct intel_display *display);
 void intel_display_hsw_init_clock_gating(struct intel_display *display);
+void intel_display_disable_trickle_feed(struct intel_display *display);
+void intel_display_ilk_init_clock_gating(struct intel_display *display);
+void intel_display_gen6_init_clock_gating(struct intel_display *display);
+void intel_display_ivb_init_clock_gating(struct intel_display *display);
+void intel_display_g4x_init_clock_gating(struct intel_display *display);
+void intel_display_i965gm_init_clock_gating(struct intel_display *display);
 #else
 static inline void intel_display_skl_init_clock_gating(struct intel_display *display) {}
 static inline void intel_display_kbl_init_clock_gating(struct intel_display *display) {}
@@ -26,6 +32,12 @@ static inline void intel_display_glk_init_clock_gating(struct intel_display *dis
 static inline void intel_display_bdw_hsw_init_clock_gating(struct intel_display *display) {}
 static inline void intel_display_bdw_init_clock_gating(struct intel_display *display) {}
 static inline void intel_display_hsw_init_clock_gating(struct intel_display *display) {}
+static inline void intel_display_disable_trickle_feed(struct intel_display *display) {}
+static inline void intel_display_ilk_init_clock_gating(struct intel_display *display) {}
+static inline void intel_display_gen6_init_clock_gating(struct intel_display *display) {}
+static inline void intel_display_ivb_init_clock_gating(struct intel_display *display) {}
+static inline void intel_display_g4x_init_clock_gating(struct intel_display *display) {}
+static inline void intel_display_i965gm_init_clock_gating(struct intel_display *display) {}
 #endif
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index a8e3eb6f06c8..98c048387a0a 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -29,11 +29,8 @@
 #include <drm/intel/intel_gmd_misc_regs.h>
 #include <drm/intel/intel_gmd_interrupt_regs.h>
 
-#include "display/i9xx_plane_regs.h"
-#include "display/intel_display.h"
 #include "display/intel_display_clock_gating.h"
 #include "display/intel_display_core.h"
-#include "display/intel_display_regs.h"
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_mcr.h"
@@ -68,74 +65,9 @@ static void glk_init_clock_gating(struct drm_i915_private *i915)
 	intel_display_glk_init_clock_gating(i915->display);
 }
 
-static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
-{
-	struct intel_display *display = dev_priv->display;
-	enum pipe pipe;
-
-	for_each_pipe(display, pipe) {
-		intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe),
-				 0, DISP_TRICKLE_FEED_DISABLE);
-
-		intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe),
-				 0, 0);
-		intel_uncore_posting_read(&dev_priv->uncore,
-					  DSPSURF(display, pipe));
-	}
-}
-
 static void ilk_init_clock_gating(struct drm_i915_private *i915)
 {
-	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
-
-	/*
-	 * Required for FBC
-	 * WaFbcDisableDpfcClockGating:ilk
-	 */
-	dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
-		   ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
-		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
-
-	intel_uncore_write(&i915->uncore, PCH_3DCGDIS0,
-			   MARIUNIT_CLOCK_GATE_DISABLE |
-			   SVSMUNIT_CLOCK_GATE_DISABLE);
-	intel_uncore_write(&i915->uncore, PCH_3DCGDIS1,
-			   VFMUNIT_CLOCK_GATE_DISABLE);
-
-	/*
-	 * According to the spec the following bits should be set in
-	 * order to enable memory self-refresh
-	 * The bit 22/21 of 0x42004
-	 * The bit 5 of 0x42020
-	 * The bit 15 of 0x45000
-	 */
-	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
-			   (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
-			    ILK_DPARB_GATE | ILK_VSDPFD_FULL));
-	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
-	intel_uncore_write(&i915->uncore, DISP_ARB_CTL,
-			   (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) |
-			    DISP_FBC_WM_DIS));
-
-	/*
-	 * Based on the document from hardware guys the following bits
-	 * should be set unconditionally in order to enable FBC.
-	 * The bit 22 of 0x42000
-	 * The bit 22 of 0x42004
-	 * The bit 7,8,9 of 0x42020.
-	 */
-	if (IS_IRONLAKE_M(i915)) {
-		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
-		intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
-		intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
-	}
-
-	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
-
-	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
-
-	g4x_disable_trickle_feed(i915);
-
+	intel_display_ilk_init_clock_gating(i915->display);
 	intel_pch_init_clock_gating(i915->display);
 }
 
@@ -152,11 +84,7 @@ static void gen6_check_mch_setup(struct drm_i915_private *i915)
 
 static void gen6_init_clock_gating(struct drm_i915_private *i915)
 {
-	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
-
-	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
-
-	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
+	intel_display_gen6_init_clock_gating(i915->display);
 
 	intel_uncore_write(&i915->uncore, GEN6_UCGCTL1,
 			   intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) |
@@ -191,19 +119,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *i915)
 	 *
 	 * WaFbcAsynchFlipDisableFbcQueue:snb
 	 */
-	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1,
-			   intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) |
-			   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
-	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
-			   intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
-			   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
-	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D,
-			   intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) |
-			   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
-			   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
-
-	g4x_disable_trickle_feed(i915);
-
 	intel_pch_init_clock_gating(i915->display);
 
 	gen6_check_mch_setup(i915);
@@ -338,10 +253,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
 {
 	struct intel_display *display = i915->display;
 
-	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
-
-	/* WaFbcAsynchFlipDisableFbcQueue:ivb */
-	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
+	intel_display_ivb_init_clock_gating(display);
 
 	/* WaDisableBackToBackFlipFix:ivb */
 	intel_uncore_write(&i915->uncore, IVB_CHICKEN3,
@@ -370,7 +282,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
 	intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
 			 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
 
-	g4x_disable_trickle_feed(i915);
+	intel_display_disable_trickle_feed(display);
 
 	intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
 			 GEN6_MBC_SNPCR_MED);
@@ -443,21 +355,12 @@ static void chv_init_clock_gating(struct drm_i915_private *i915)
 
 static void g4x_init_clock_gating(struct drm_i915_private *i915)
 {
-	u32 dspclk_gate;
-
 	intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0);
 	intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
 			   GS_UNIT_CLOCK_GATE_DISABLE |
 			   CL_UNIT_CLOCK_GATE_DISABLE);
 	intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0);
-	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
-		OVRUNIT_CLOCK_GATE_DISABLE |
-		OVCUNIT_CLOCK_GATE_DISABLE;
-	if (IS_GM45(i915))
-		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
-	intel_uncore_write(&i915->uncore, DSPCLK_GATE_D, dspclk_gate);
-
-	g4x_disable_trickle_feed(i915);
+	intel_display_g4x_init_clock_gating(i915->display);
 }
 
 static void i965gm_init_clock_gating(struct drm_i915_private *i915)
@@ -466,7 +369,7 @@ static void i965gm_init_clock_gating(struct drm_i915_private *i915)
 
 	intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
 	intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
-	intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
+	intel_display_i965gm_init_clock_gating(i915->display);
 	intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
 	intel_uncore_write16(uncore, DEUC, 0);
 	intel_uncore_write(uncore,
-- 
2.53.0

[PATCH 8/8] drm/i915: remove HAS_PCH_NOP() dependency from clock gating

[Luca Coelho]

intel_pch_init_clock_gating() already handles unsupported PCH types,
including PCH_NOP, by doing nothing.

Drop the explicit HAS_PCH_NOP() check from the IVB clock gating
path and always call the display helper directly. This removes one
more direct dependency on display-side PCH macros from
intel_clock_gating.c.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 drivers/gpu/drm/i915/intel_clock_gating.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 98c048387a0a..6a5254e02ddf 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -287,8 +287,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
 	intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
 			 GEN6_MBC_SNPCR_MED);
 
-	if (!HAS_PCH_NOP(display))
-		intel_pch_init_clock_gating(display);
+	intel_pch_init_clock_gating(display);
 
 	gen6_check_mch_setup(i915);
 }
-- 
2.53.0

Re: [PATCH 7/8] drm/i915/display: move pre-HSW clock gating init to display

[Ville Syrjälä]

On Tue, Mar 24, 2026 at 04:29:56PM +0200, Luca Coelho wrote:
> Move the remaining pre-HSW display clock gating programming into
> display.
> 
> This also drops display register includes from intel_clock_gating.c.
> 
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> ---
>  .../i915/display/intel_display_clock_gating.c | 100 ++++++++++++++++
>  .../i915/display/intel_display_clock_gating.h |  12 ++
>  drivers/gpu/drm/i915/intel_clock_gating.c     | 109 +-----------------
>  3 files changed, 118 insertions(+), 103 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> index 0b2edf6acb79..5809c49dccf0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> @@ -6,11 +6,13 @@
>  #include <drm/intel/intel_gmd_misc_regs.h>
>  
>  #include "intel_de.h"
> +#include "i9xx_plane_regs.h"
>  #include "intel_display.h"
>  #include "intel_display_clock_gating.h"
>  #include "intel_display_regs.h"
>  
>  #include "i915_drv.h"
> +#include "i915_reg.h"
>  
>  static void intel_display_gen9_init_clock_gating(struct intel_display *display,
>  						 bool has_llc)
> @@ -156,3 +158,101 @@ void intel_display_hsw_init_clock_gating(struct intel_display *display)
>  	intel_display_hsw_init_clock_gating_common(display,
>  						   HSW_UNMASK_VBL_TO_REGS_IN_SRD);
>  }
> +
> +void intel_display_disable_trickle_feed(struct intel_display *display)
> +{
> +	enum pipe pipe;
> +
> +	for_each_pipe(display, pipe) {
> +		intel_de_rmw(display, DSPCNTR(display, pipe), 0,
> +			     DISP_TRICKLE_FEED_DISABLE);
> +
> +		intel_de_rmw(display, DSPSURF(display, pipe), 0, 0);
> +		intel_de_posting_read(display, DSPSURF(display, pipe));
> +	}
> +}
> +
> +void intel_display_ilk_init_clock_gating(struct intel_display *display)
> +{
> +	struct drm_i915_private *i915 = to_i915(display->drm);
> +	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> +
> +	/*
> +	 * Required for FBC
> +	 * WaFbcDisableDpfcClockGating:ilk
> +	 */
> +	dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
> +		       ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> +		       ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
> +
> +	intel_de_write(display, PCH_3DCGDIS0,
> +		       MARIUNIT_CLOCK_GATE_DISABLE |
> +		       SVSMUNIT_CLOCK_GATE_DISABLE);
> +	intel_de_write(display, PCH_3DCGDIS1, VFMUNIT_CLOCK_GATE_DISABLE);

Those two aren't display things.

> +
> +	intel_de_write(display, ILK_DISPLAY_CHICKEN2,
> +		       intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
> +		       ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> +	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
> +	intel_de_write(display, DISP_ARB_CTL,
> +		       intel_de_read(display, DISP_ARB_CTL) |
> +		       DISP_FBC_WM_DIS);
> +
> +	if (IS_IRONLAKE_M(i915)) {
> +		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
> +		intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> +		intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
> +	}
> +
> +	intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
> +	intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> +
> +	intel_display_disable_trickle_feed(display);
> +}
> +
> +void intel_display_gen6_init_clock_gating(struct intel_display *display)
> +{
> +	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> +
> +	intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
> +	intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> +
> +	intel_de_write(display, ILK_DISPLAY_CHICKEN1,
> +		       intel_de_read(display, ILK_DISPLAY_CHICKEN1) |
> +		       ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
> +	intel_de_write(display, ILK_DISPLAY_CHICKEN2,
> +		       intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
> +		       ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> +	intel_de_write(display, ILK_DSPCLK_GATE_D,
> +		       intel_de_read(display, ILK_DSPCLK_GATE_D) |
> +		       ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
> +		       ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
> +
> +	intel_display_disable_trickle_feed(display);
> +}
> +
> +void intel_display_ivb_init_clock_gating(struct intel_display *display)
> +{
> +	intel_de_write(display, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
> +	intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> +}
> +
> +void intel_display_g4x_init_clock_gating(struct intel_display *display)
> +{
> +	struct drm_i915_private *i915 = to_i915(display->drm);
> +	u32 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
> +			  OVRUNIT_CLOCK_GATE_DISABLE |
> +			  OVCUNIT_CLOCK_GATE_DISABLE;
> +
> +	if (IS_GM45(i915))
> +		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
> +
> +	intel_de_write(display, DSPCLK_GATE_D, dspclk_gate);
> +
> +	intel_display_disable_trickle_feed(display);
> +}
> +
> +void intel_display_i965gm_init_clock_gating(struct intel_display *display)
> +{
> +	intel_de_write(display, DSPCLK_GATE_D, 0);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> index 0eb240f2f69e..9eebfc4a6ebe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> @@ -17,6 +17,12 @@ void intel_display_glk_init_clock_gating(struct intel_display *display);
>  void intel_display_bdw_hsw_init_clock_gating(struct intel_display *display);
>  void intel_display_bdw_init_clock_gating(struct intel_display *display);
>  void intel_display_hsw_init_clock_gating(struct intel_display *display);
> +void intel_display_disable_trickle_feed(struct intel_display *display);
> +void intel_display_ilk_init_clock_gating(struct intel_display *display);
> +void intel_display_gen6_init_clock_gating(struct intel_display *display);
> +void intel_display_ivb_init_clock_gating(struct intel_display *display);
> +void intel_display_g4x_init_clock_gating(struct intel_display *display);
> +void intel_display_i965gm_init_clock_gating(struct intel_display *display);
>  #else
>  static inline void intel_display_skl_init_clock_gating(struct intel_display *display) {}
>  static inline void intel_display_kbl_init_clock_gating(struct intel_display *display) {}
> @@ -26,6 +32,12 @@ static inline void intel_display_glk_init_clock_gating(struct intel_display *dis
>  static inline void intel_display_bdw_hsw_init_clock_gating(struct intel_display *display) {}
>  static inline void intel_display_bdw_init_clock_gating(struct intel_display *display) {}
>  static inline void intel_display_hsw_init_clock_gating(struct intel_display *display) {}
> +static inline void intel_display_disable_trickle_feed(struct intel_display *display) {}
> +static inline void intel_display_ilk_init_clock_gating(struct intel_display *display) {}
> +static inline void intel_display_gen6_init_clock_gating(struct intel_display *display) {}
> +static inline void intel_display_ivb_init_clock_gating(struct intel_display *display) {}
> +static inline void intel_display_g4x_init_clock_gating(struct intel_display *display) {}
> +static inline void intel_display_i965gm_init_clock_gating(struct intel_display *display) {}
>  #endif
>  
>  #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index a8e3eb6f06c8..98c048387a0a 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -29,11 +29,8 @@
>  #include <drm/intel/intel_gmd_misc_regs.h>
>  #include <drm/intel/intel_gmd_interrupt_regs.h>
>  
> -#include "display/i9xx_plane_regs.h"
> -#include "display/intel_display.h"
>  #include "display/intel_display_clock_gating.h"
>  #include "display/intel_display_core.h"
> -#include "display/intel_display_regs.h"
>  #include "gt/intel_engine_regs.h"
>  #include "gt/intel_gt.h"
>  #include "gt/intel_gt_mcr.h"
> @@ -68,74 +65,9 @@ static void glk_init_clock_gating(struct drm_i915_private *i915)
>  	intel_display_glk_init_clock_gating(i915->display);
>  }
>  
> -static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
> -{
> -	struct intel_display *display = dev_priv->display;
> -	enum pipe pipe;
> -
> -	for_each_pipe(display, pipe) {
> -		intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe),
> -				 0, DISP_TRICKLE_FEED_DISABLE);
> -
> -		intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe),
> -				 0, 0);
> -		intel_uncore_posting_read(&dev_priv->uncore,
> -					  DSPSURF(display, pipe));
> -	}
> -}
> -
>  static void ilk_init_clock_gating(struct drm_i915_private *i915)
>  {
> -	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> -
> -	/*
> -	 * Required for FBC
> -	 * WaFbcDisableDpfcClockGating:ilk
> -	 */
> -	dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
> -		   ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> -		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
> -
> -	intel_uncore_write(&i915->uncore, PCH_3DCGDIS0,
> -			   MARIUNIT_CLOCK_GATE_DISABLE |
> -			   SVSMUNIT_CLOCK_GATE_DISABLE);
> -	intel_uncore_write(&i915->uncore, PCH_3DCGDIS1,
> -			   VFMUNIT_CLOCK_GATE_DISABLE);
> -
> -	/*
> -	 * According to the spec the following bits should be set in
> -	 * order to enable memory self-refresh
> -	 * The bit 22/21 of 0x42004
> -	 * The bit 5 of 0x42020
> -	 * The bit 15 of 0x45000
> -	 */
> -	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
> -			   (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
> -			    ILK_DPARB_GATE | ILK_VSDPFD_FULL));
> -	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
> -	intel_uncore_write(&i915->uncore, DISP_ARB_CTL,
> -			   (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) |
> -			    DISP_FBC_WM_DIS));
> -
> -	/*
> -	 * Based on the document from hardware guys the following bits
> -	 * should be set unconditionally in order to enable FBC.
> -	 * The bit 22 of 0x42000
> -	 * The bit 22 of 0x42004
> -	 * The bit 7,8,9 of 0x42020.
> -	 */
> -	if (IS_IRONLAKE_M(i915)) {
> -		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
> -		intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> -		intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
> -	}
> -
> -	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
> -
> -	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> -
> -	g4x_disable_trickle_feed(i915);
> -
> +	intel_display_ilk_init_clock_gating(i915->display);
>  	intel_pch_init_clock_gating(i915->display);
>  }
>  
> @@ -152,11 +84,7 @@ static void gen6_check_mch_setup(struct drm_i915_private *i915)
>  
>  static void gen6_init_clock_gating(struct drm_i915_private *i915)
>  {
> -	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> -
> -	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
> -
> -	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> +	intel_display_gen6_init_clock_gating(i915->display);
>  
>  	intel_uncore_write(&i915->uncore, GEN6_UCGCTL1,
>  			   intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) |
> @@ -191,19 +119,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *i915)
>  	 *
>  	 * WaFbcAsynchFlipDisableFbcQueue:snb
>  	 */
> -	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1,
> -			   intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) |
> -			   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
> -	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
> -			   intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
> -			   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> -	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D,
> -			   intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) |
> -			   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
> -			   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
> -
> -	g4x_disable_trickle_feed(i915);
> -
>  	intel_pch_init_clock_gating(i915->display);
>  
>  	gen6_check_mch_setup(i915);
> @@ -338,10 +253,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
>  {
>  	struct intel_display *display = i915->display;
>  
> -	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
> -
> -	/* WaFbcAsynchFlipDisableFbcQueue:ivb */
> -	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> +	intel_display_ivb_init_clock_gating(display);
>  
>  	/* WaDisableBackToBackFlipFix:ivb */
>  	intel_uncore_write(&i915->uncore, IVB_CHICKEN3,
> @@ -370,7 +282,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
>  	intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
>  			 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>  
> -	g4x_disable_trickle_feed(i915);
> +	intel_display_disable_trickle_feed(display);
>  
>  	intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
>  			 GEN6_MBC_SNPCR_MED);
> @@ -443,21 +355,12 @@ static void chv_init_clock_gating(struct drm_i915_private *i915)
>  
>  static void g4x_init_clock_gating(struct drm_i915_private *i915)
>  {
> -	u32 dspclk_gate;
> -
>  	intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0);
>  	intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
>  			   GS_UNIT_CLOCK_GATE_DISABLE |
>  			   CL_UNIT_CLOCK_GATE_DISABLE);
>  	intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0);
> -	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
> -		OVRUNIT_CLOCK_GATE_DISABLE |
> -		OVCUNIT_CLOCK_GATE_DISABLE;
> -	if (IS_GM45(i915))
> -		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
> -	intel_uncore_write(&i915->uncore, DSPCLK_GATE_D, dspclk_gate);
> -
> -	g4x_disable_trickle_feed(i915);
> +	intel_display_g4x_init_clock_gating(i915->display);
>  }
>  
>  static void i965gm_init_clock_gating(struct drm_i915_private *i915)
> @@ -466,7 +369,7 @@ static void i965gm_init_clock_gating(struct drm_i915_private *i915)
>  
>  	intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
>  	intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
> -	intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
> +	intel_display_i965gm_init_clock_gating(i915->display);
>  	intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
>  	intel_uncore_write16(uncore, DEUC, 0);
>  	intel_uncore_write(uncore,
> -- 
> 2.53.0

-- 
Ville Syrjälä
Intel

Re: [PATCH 7/8] drm/i915/display: move pre-HSW clock gating init to display

[Luca Coelho]

On Tue, 2026-03-24 at 17:04 +0200, Ville Syrjälä wrote:
> On Tue, Mar 24, 2026 at 04:29:56PM +0200, Luca Coelho wrote:
> > Move the remaining pre-HSW display clock gating programming into
> > display.
> > 
> > This also drops display register includes from intel_clock_gating.c.
> > 
> > Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> > ---
> >  .../i915/display/intel_display_clock_gating.c | 100 ++++++++++++++++
> >  .../i915/display/intel_display_clock_gating.h |  12 ++
> >  drivers/gpu/drm/i915/intel_clock_gating.c     | 109 +-----------------
> >  3 files changed, 118 insertions(+), 103 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> > index 0b2edf6acb79..5809c49dccf0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> > @@ -6,11 +6,13 @@
> >  #include <drm/intel/intel_gmd_misc_regs.h>
> >  
> >  #include "intel_de.h"
> > +#include "i9xx_plane_regs.h"
> >  #include "intel_display.h"
> >  #include "intel_display_clock_gating.h"
> >  #include "intel_display_regs.h"
> >  
> >  #include "i915_drv.h"
> > +#include "i915_reg.h"
> >  
> >  static void intel_display_gen9_init_clock_gating(struct intel_display *display,
> >  						 bool has_llc)
> > @@ -156,3 +158,101 @@ void intel_display_hsw_init_clock_gating(struct intel_display *display)
> >  	intel_display_hsw_init_clock_gating_common(display,
> >  						   HSW_UNMASK_VBL_TO_REGS_IN_SRD);
> >  }
> > +
> > +void intel_display_disable_trickle_feed(struct intel_display *display)
> > +{
> > +	enum pipe pipe;
> > +
> > +	for_each_pipe(display, pipe) {
> > +		intel_de_rmw(display, DSPCNTR(display, pipe), 0,
> > +			     DISP_TRICKLE_FEED_DISABLE);
> > +
> > +		intel_de_rmw(display, DSPSURF(display, pipe), 0, 0);
> > +		intel_de_posting_read(display, DSPSURF(display, pipe));
> > +	}
> > +}
> > +
> > +void intel_display_ilk_init_clock_gating(struct intel_display *display)
> > +{
> > +	struct drm_i915_private *i915 = to_i915(display->drm);
> > +	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> > +
> > +	/*
> > +	 * Required for FBC
> > +	 * WaFbcDisableDpfcClockGating:ilk
> > +	 */
> > +	dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
> > +		       ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> > +		       ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
> > +
> > +	intel_de_write(display, PCH_3DCGDIS0,
> > +		       MARIUNIT_CLOCK_GATE_DISABLE |
> > +		       SVSMUNIT_CLOCK_GATE_DISABLE);
> > +	intel_de_write(display, PCH_3DCGDIS1, VFMUNIT_CLOCK_GATE_DISABLE);
> 
> Those two aren't display things.

Oops, you're right.  I'll fix it.

--
Cheers,
Luca.


> 
> > +
> > +	intel_de_write(display, ILK_DISPLAY_CHICKEN2,
> > +		       intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
> > +		       ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> > +	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
> > +	intel_de_write(display, DISP_ARB_CTL,
> > +		       intel_de_read(display, DISP_ARB_CTL) |
> > +		       DISP_FBC_WM_DIS);
> > +
> > +	if (IS_IRONLAKE_M(i915)) {
> > +		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
> > +		intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> > +		intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
> > +	}
> > +
> > +	intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
> > +	intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> > +
> > +	intel_display_disable_trickle_feed(display);
> > +}
> > +
> > +void intel_display_gen6_init_clock_gating(struct intel_display *display)
> > +{
> > +	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> > +
> > +	intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
> > +	intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> > +
> > +	intel_de_write(display, ILK_DISPLAY_CHICKEN1,
> > +		       intel_de_read(display, ILK_DISPLAY_CHICKEN1) |
> > +		       ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
> > +	intel_de_write(display, ILK_DISPLAY_CHICKEN2,
> > +		       intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
> > +		       ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> > +	intel_de_write(display, ILK_DSPCLK_GATE_D,
> > +		       intel_de_read(display, ILK_DSPCLK_GATE_D) |
> > +		       ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
> > +		       ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
> > +
> > +	intel_display_disable_trickle_feed(display);
> > +}
> > +
> > +void intel_display_ivb_init_clock_gating(struct intel_display *display)
> > +{
> > +	intel_de_write(display, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
> > +	intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> > +}
> > +
> > +void intel_display_g4x_init_clock_gating(struct intel_display *display)
> > +{
> > +	struct drm_i915_private *i915 = to_i915(display->drm);
> > +	u32 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
> > +			  OVRUNIT_CLOCK_GATE_DISABLE |
> > +			  OVCUNIT_CLOCK_GATE_DISABLE;
> > +
> > +	if (IS_GM45(i915))
> > +		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
> > +
> > +	intel_de_write(display, DSPCLK_GATE_D, dspclk_gate);
> > +
> > +	intel_display_disable_trickle_feed(display);
> > +}
> > +
> > +void intel_display_i965gm_init_clock_gating(struct intel_display *display)
> > +{
> > +	intel_de_write(display, DSPCLK_GATE_D, 0);
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> > index 0eb240f2f69e..9eebfc4a6ebe 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> > @@ -17,6 +17,12 @@ void intel_display_glk_init_clock_gating(struct intel_display *display);
> >  void intel_display_bdw_hsw_init_clock_gating(struct intel_display *display);
> >  void intel_display_bdw_init_clock_gating(struct intel_display *display);
> >  void intel_display_hsw_init_clock_gating(struct intel_display *display);
> > +void intel_display_disable_trickle_feed(struct intel_display *display);
> > +void intel_display_ilk_init_clock_gating(struct intel_display *display);
> > +void intel_display_gen6_init_clock_gating(struct intel_display *display);
> > +void intel_display_ivb_init_clock_gating(struct intel_display *display);
> > +void intel_display_g4x_init_clock_gating(struct intel_display *display);
> > +void intel_display_i965gm_init_clock_gating(struct intel_display *display);
> >  #else
> >  static inline void intel_display_skl_init_clock_gating(struct intel_display *display) {}
> >  static inline void intel_display_kbl_init_clock_gating(struct intel_display *display) {}
> > @@ -26,6 +32,12 @@ static inline void intel_display_glk_init_clock_gating(struct intel_display *dis
> >  static inline void intel_display_bdw_hsw_init_clock_gating(struct intel_display *display) {}
> >  static inline void intel_display_bdw_init_clock_gating(struct intel_display *display) {}
> >  static inline void intel_display_hsw_init_clock_gating(struct intel_display *display) {}
> > +static inline void intel_display_disable_trickle_feed(struct intel_display *display) {}
> > +static inline void intel_display_ilk_init_clock_gating(struct intel_display *display) {}
> > +static inline void intel_display_gen6_init_clock_gating(struct intel_display *display) {}
> > +static inline void intel_display_ivb_init_clock_gating(struct intel_display *display) {}
> > +static inline void intel_display_g4x_init_clock_gating(struct intel_display *display) {}
> > +static inline void intel_display_i965gm_init_clock_gating(struct intel_display *display) {}
> >  #endif
> >  
> >  #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
> > diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> > index a8e3eb6f06c8..98c048387a0a 100644
> > --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> > +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> > @@ -29,11 +29,8 @@
> >  #include <drm/intel/intel_gmd_misc_regs.h>
> >  #include <drm/intel/intel_gmd_interrupt_regs.h>
> >  
> > -#include "display/i9xx_plane_regs.h"
> > -#include "display/intel_display.h"
> >  #include "display/intel_display_clock_gating.h"
> >  #include "display/intel_display_core.h"
> > -#include "display/intel_display_regs.h"
> >  #include "gt/intel_engine_regs.h"
> >  #include "gt/intel_gt.h"
> >  #include "gt/intel_gt_mcr.h"
> > @@ -68,74 +65,9 @@ static void glk_init_clock_gating(struct drm_i915_private *i915)
> >  	intel_display_glk_init_clock_gating(i915->display);
> >  }
> >  
> > -static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
> > -{
> > -	struct intel_display *display = dev_priv->display;
> > -	enum pipe pipe;
> > -
> > -	for_each_pipe(display, pipe) {
> > -		intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe),
> > -				 0, DISP_TRICKLE_FEED_DISABLE);
> > -
> > -		intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe),
> > -				 0, 0);
> > -		intel_uncore_posting_read(&dev_priv->uncore,
> > -					  DSPSURF(display, pipe));
> > -	}
> > -}
> > -
> >  static void ilk_init_clock_gating(struct drm_i915_private *i915)
> >  {
> > -	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> > -
> > -	/*
> > -	 * Required for FBC
> > -	 * WaFbcDisableDpfcClockGating:ilk
> > -	 */
> > -	dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
> > -		   ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> > -		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
> > -
> > -	intel_uncore_write(&i915->uncore, PCH_3DCGDIS0,
> > -			   MARIUNIT_CLOCK_GATE_DISABLE |
> > -			   SVSMUNIT_CLOCK_GATE_DISABLE);
> > -	intel_uncore_write(&i915->uncore, PCH_3DCGDIS1,
> > -			   VFMUNIT_CLOCK_GATE_DISABLE);
> > -
> > -	/*
> > -	 * According to the spec the following bits should be set in
> > -	 * order to enable memory self-refresh
> > -	 * The bit 22/21 of 0x42004
> > -	 * The bit 5 of 0x42020
> > -	 * The bit 15 of 0x45000
> > -	 */
> > -	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
> > -			   (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
> > -			    ILK_DPARB_GATE | ILK_VSDPFD_FULL));
> > -	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
> > -	intel_uncore_write(&i915->uncore, DISP_ARB_CTL,
> > -			   (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) |
> > -			    DISP_FBC_WM_DIS));
> > -
> > -	/*
> > -	 * Based on the document from hardware guys the following bits
> > -	 * should be set unconditionally in order to enable FBC.
> > -	 * The bit 22 of 0x42000
> > -	 * The bit 22 of 0x42004
> > -	 * The bit 7,8,9 of 0x42020.
> > -	 */
> > -	if (IS_IRONLAKE_M(i915)) {
> > -		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
> > -		intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> > -		intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
> > -	}
> > -
> > -	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
> > -
> > -	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> > -
> > -	g4x_disable_trickle_feed(i915);
> > -
> > +	intel_display_ilk_init_clock_gating(i915->display);
> >  	intel_pch_init_clock_gating(i915->display);
> >  }
> >  
> > @@ -152,11 +84,7 @@ static void gen6_check_mch_setup(struct drm_i915_private *i915)
> >  
> >  static void gen6_init_clock_gating(struct drm_i915_private *i915)
> >  {
> > -	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> > -
> > -	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
> > -
> > -	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> > +	intel_display_gen6_init_clock_gating(i915->display);
> >  
> >  	intel_uncore_write(&i915->uncore, GEN6_UCGCTL1,
> >  			   intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) |
> > @@ -191,19 +119,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *i915)
> >  	 *
> >  	 * WaFbcAsynchFlipDisableFbcQueue:snb
> >  	 */
> > -	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1,
> > -			   intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) |
> > -			   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
> > -	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
> > -			   intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
> > -			   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> > -	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D,
> > -			   intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) |
> > -			   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
> > -			   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
> > -
> > -	g4x_disable_trickle_feed(i915);
> > -
> >  	intel_pch_init_clock_gating(i915->display);
> >  
> >  	gen6_check_mch_setup(i915);
> > @@ -338,10 +253,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
> >  {
> >  	struct intel_display *display = i915->display;
> >  
> > -	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
> > -
> > -	/* WaFbcAsynchFlipDisableFbcQueue:ivb */
> > -	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> > +	intel_display_ivb_init_clock_gating(display);
> >  
> >  	/* WaDisableBackToBackFlipFix:ivb */
> >  	intel_uncore_write(&i915->uncore, IVB_CHICKEN3,
> > @@ -370,7 +282,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
> >  	intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> >  			 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
> >  
> > -	g4x_disable_trickle_feed(i915);
> > +	intel_display_disable_trickle_feed(display);
> >  
> >  	intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
> >  			 GEN6_MBC_SNPCR_MED);
> > @@ -443,21 +355,12 @@ static void chv_init_clock_gating(struct drm_i915_private *i915)
> >  
> >  static void g4x_init_clock_gating(struct drm_i915_private *i915)
> >  {
> > -	u32 dspclk_gate;
> > -
> >  	intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0);
> >  	intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
> >  			   GS_UNIT_CLOCK_GATE_DISABLE |
> >  			   CL_UNIT_CLOCK_GATE_DISABLE);
> >  	intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0);
> > -	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
> > -		OVRUNIT_CLOCK_GATE_DISABLE |
> > -		OVCUNIT_CLOCK_GATE_DISABLE;
> > -	if (IS_GM45(i915))
> > -		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
> > -	intel_uncore_write(&i915->uncore, DSPCLK_GATE_D, dspclk_gate);
> > -
> > -	g4x_disable_trickle_feed(i915);
> > +	intel_display_g4x_init_clock_gating(i915->display);
> >  }
> >  
> >  static void i965gm_init_clock_gating(struct drm_i915_private *i915)
> > @@ -466,7 +369,7 @@ static void i965gm_init_clock_gating(struct drm_i915_private *i915)
> >  
> >  	intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
> >  	intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
> > -	intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
> > +	intel_display_i965gm_init_clock_gating(i915->display);
> >  	intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
> >  	intel_uncore_write16(uncore, DEUC, 0);
> >  	intel_uncore_write(uncore,
> > -- 
> > 2.53.0

Re: [PATCH 6/8] drm/i915/display: move HSW and BDW clock gating init to display

[Ville Syrjälä]

On Tue, Mar 24, 2026 at 04:29:55PM +0200, Luca Coelho wrote:
> Move the HSW and BDW display clock gating programming into the display
> code.  In this case we need two different helpers, because the common
> code between these two is split in the middle.
> 
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> ---
>  .../i915/display/intel_display_clock_gating.c | 33 +++++++++++++++++++
>  .../i915/display/intel_display_clock_gating.h |  6 ++++
>  drivers/gpu/drm/i915/intel_clock_gating.c     | 31 +++--------------
>  3 files changed, 43 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> index e3b7522b4101..0b2edf6acb79 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> @@ -123,3 +123,36 @@ void intel_display_glk_init_clock_gating(struct intel_display *display)
>  		       intel_de_read(display, GEN9_CLKGATE_DIS_0) |
>  		       PWM1_GATING_DIS | PWM2_GATING_DIS);
>  }
> +
> +static void
> +intel_display_hsw_init_clock_gating_common(struct intel_display *display,
> +					   u32 unmask_vbl)

Passing that as a parameter feels a bit obfuscated.

> +{
> +	enum pipe pipe;
> +
> +	/* WaPsrDPAMaskVBlankInSRD:hsw */
> +	intel_de_rmw(display, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
> +
> +	for_each_pipe(display, pipe) {
> +		/* WaPsrDPRSUnmaskVBlankInSRD:hsw,bdw */
> +		intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 0, unmask_vbl);

If we want to share the function then I'd probably just do
a platform check here.

> +	}
> +}
> +
> +void intel_display_bdw_hsw_init_clock_gating(struct intel_display *display)
> +{
> +	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
> +	intel_de_rmw(display, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
> +}

Why do we have two different functions that shared by
both platforms?

> +
> +void intel_display_bdw_init_clock_gating(struct intel_display *display)
> +{
> +	intel_display_hsw_init_clock_gating_common(display,
> +						   BDW_UNMASK_VBL_TO_REGS_IN_SRD);
> +}
> +
> +void intel_display_hsw_init_clock_gating(struct intel_display *display)
> +{
> +	intel_display_hsw_init_clock_gating_common(display,
> +						   HSW_UNMASK_VBL_TO_REGS_IN_SRD);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> index 4abd34fa5832..0eb240f2f69e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> @@ -14,12 +14,18 @@ void intel_display_kbl_init_clock_gating(struct intel_display *display);
>  void intel_display_cfl_init_clock_gating(struct intel_display *display);
>  void intel_display_bxt_init_clock_gating(struct intel_display *display);
>  void intel_display_glk_init_clock_gating(struct intel_display *display);
> +void intel_display_bdw_hsw_init_clock_gating(struct intel_display *display);
> +void intel_display_bdw_init_clock_gating(struct intel_display *display);
> +void intel_display_hsw_init_clock_gating(struct intel_display *display);
>  #else
>  static inline void intel_display_skl_init_clock_gating(struct intel_display *display) {}
>  static inline void intel_display_kbl_init_clock_gating(struct intel_display *display) {}
>  static inline void intel_display_cfl_init_clock_gating(struct intel_display *display) {}
>  static inline void intel_display_bxt_init_clock_gating(struct intel_display *display) {}
>  static inline void intel_display_glk_init_clock_gating(struct intel_display *display) {}
> +static inline void intel_display_bdw_hsw_init_clock_gating(struct intel_display *display) {}
> +static inline void intel_display_bdw_init_clock_gating(struct intel_display *display) {}
> +static inline void intel_display_hsw_init_clock_gating(struct intel_display *display) {}
>  #endif
>  
>  #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index 777314e0c75d..a8e3eb6f06c8 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -284,23 +284,12 @@ static void skl_init_clock_gating(struct drm_i915_private *i915)
>  
>  static void bdw_init_clock_gating(struct drm_i915_private *i915)
>  {
> -	struct intel_display *display = i915->display;
> -	enum pipe pipe;
> -
> -	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
> -	intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
> +	intel_display_bdw_hsw_init_clock_gating(i915->display);
>  
>  	/* WaSwitchSolVfFArbitrationPriority:bdw */
>  	intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
>  
> -	/* WaPsrDPAMaskVBlankInSRD:bdw */
> -	intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
> -
> -	for_each_pipe(display, pipe) {
> -		/* WaPsrDPRSUnmaskVBlankInSRD:bdw */
> -		intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
> -				 0, BDW_UNMASK_VBL_TO_REGS_IN_SRD);
> -	}
> +	intel_display_bdw_init_clock_gating(i915->display);
>  
>  	/* WaVSRefCountFullforceMissDisable:bdw */
>  	/* WaDSRefCountFullforceMissDisable:bdw */

...
WaKVMNotificationOnConfigChange:bdw somewhere in here is also a display
thing.

And given that I think sharing anything between the platforms in
this patch is a bit premature. I think it would be better to just
move things as is, and do the code sharing refactoring as a followup
once it's easier to see what's common and what isn't.

> @@ -332,20 +321,8 @@ static void bdw_init_clock_gating(struct drm_i915_private *i915)
>  
>  static void hsw_init_clock_gating(struct drm_i915_private *i915)
>  {
> -	struct intel_display *display = i915->display;
> -	enum pipe pipe;
> -
> -	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
> -	intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
> -
> -	/* WaPsrDPAMaskVBlankInSRD:hsw */
> -	intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
> -
> -	for_each_pipe(display, pipe) {
> -		/* WaPsrDPRSUnmaskVBlankInSRD:hsw */
> -		intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
> -				 0, HSW_UNMASK_VBL_TO_REGS_IN_SRD);
> -	}
> +	intel_display_bdw_hsw_init_clock_gating(i915->display);
> +	intel_display_hsw_init_clock_gating(i915->display);
>  
>  	/* This is required by WaCatErrorRejectionIssue:hsw */
>  	intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> -- 
> 2.53.0

-- 
Ville Syrjälä
Intel

Re: [PATCH 1/8] drm/i915: move SKL clock gating init to display

[Jani Nikula]

On Tue, 24 Mar 2026, Luca Coelho <luciano.coelho@intel.com> wrote:
> Move the SKL-specific display clock gating programming into a new file
> inside display.
>
> This removes dependency from intel_clock_gating.c to the display's
> intel_pch.h file, so we can remove the include statement.
>
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile                 |  1 +
>  .../i915/display/intel_display_clock_gating.c | 19 +++++++++++++++++++
>  .../i915/display/intel_display_clock_gating.h | 17 +++++++++++++++++
>  drivers/gpu/drm/i915/intel_clock_gating.c     |  8 ++------
>  4 files changed, 39 insertions(+), 6 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.c
>  create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index be976a90c5a6..89232873d4b7 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -254,6 +254,7 @@ i915-y += \
>  	display/intel_crtc_state_dump.o \
>  	display/intel_cursor.o \
>  	display/intel_dbuf_bw.o \
> +	display/intel_display_clock_gating.o \
>  	display/intel_display.o \
>  	display/intel_display_conversion.o \
>  	display/intel_display_driver.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> new file mode 100644
> index 000000000000..4a94593335e0
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2026 Intel Corporation
> + */
> +
> +#include <drm/intel/intel_gmd_misc_regs.h>
> +
> +#include "intel_de.h"
> +#include "intel_display_clock_gating.h"
> +#include "intel_display_regs.h"
> +
> +void intel_display_skl_init_clock_gating(struct intel_display *display)
> +{
> +	/*
> +	 * WaFbcTurnOffFbcWatermark:skl
> +	 * Display WA #0562: skl
> +	 */
> +	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> new file mode 100644
> index 000000000000..c93997417dcb
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright 2026 Intel Corporation
> + */
> +
> +#ifndef __INTEL_DISPLAY_CLOCK_GATING_H__
> +#define __INTEL_DISPLAY_CLOCK_GATING_H__
> +
> +struct intel_display;
> +
> +#ifdef I915
> +void intel_display_skl_init_clock_gating(struct intel_display *display);
> +#else
> +static inline void intel_display_skl_init_clock_gating(struct intel_display *display) {}
> +#endif

I don't think we should add any of this #ifdef I915 stuff, because the
next step will be to remove all of them anyway.

Currently they'll only get called for i915, but their existence in xe
doesn't matter. And eventually they'll be part of the display module.

BR,
Jani.


> +
> +#endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index ee2489a2fbe7..454334fef5e7 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -31,9 +31,9 @@
>  
>  #include "display/i9xx_plane_regs.h"
>  #include "display/intel_display.h"
> +#include "display/intel_display_clock_gating.h"
>  #include "display/intel_display_core.h"
>  #include "display/intel_display_regs.h"
> -#include "display/intel_pch.h"
>  #include "gt/intel_engine_regs.h"
>  #include "gt/intel_gt.h"
>  #include "gt/intel_gt_mcr.h"
> @@ -349,11 +349,7 @@ static void skl_init_clock_gating(struct drm_i915_private *i915)
>  	/* WAC6entrylatency:skl */
>  	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
>  
> -	/*
> -	 * WaFbcTurnOffFbcWatermark:skl
> -	 * Display WA #0562: skl
> -	 */
> -	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
> +	intel_display_skl_init_clock_gating(i915->display);
>  }
>  
>  static void bdw_init_clock_gating(struct drm_i915_private *i915)

-- 
Jani Nikula, Intel