[PATCH 09/19] drm/i915/dp: Skip AS SDP for DP branch devices

[PATCH 09/19] drm/i915/dp: Skip AS SDP for DP branch devices

[Ankit Nautiyal]

Currently, VRR is not implmented for DP branch devices.
So skip sending AS SDP for them.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 41908f68ffba..17af68a1a9e5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3130,6 +3130,12 @@ static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
 	if (!intel_dp->as_sdp_supported)
 		return false;
 
+	/*
+	 * #TODO Implement AS SDP for DP branch device.
+	 */
+	if (drm_dp_is_branch(intel_dp->dpcd))
+		return false;
+
 	return crtc_state->vrr.enable;
 }
 
-- 
2.45.2

[PATCH 00/19] Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM

[Ankit Nautiyal]

Enable Adaptive Sync SDP for Panel replay + auxless ALPM.
First few patches are fixes in existing AS SDP enablement.
Later patches add the support to send AS SDP for Panel replay with Link
ON and with auxless ALPM (Link-Off). 

This series is in continuation from discussions in [1] [2] and more
recent [3]:

Apart from few patches from [3] new changes include:
- Some clean up in drm/dp Macros
- Add new DPCD bit to get FAVT PAYLOAD FIELDS PARSING SUPPORT.
- Add AS SDP version and PR and VRR specific bits in drm_dp.h.
- Modify AS SDP compute config to accomodate PR with Link On and Link
  Off.
- Program Downspread Ctrl DPCD bits.
- Make way for T1 and T2 AS SDP transmission timing/position.

[1] https://lore.kernel.org/all/1b8c6c6de1e5fe0db83e6ae942dfee7e6f950767.camel@intel.com/
[2] https://lore.kernel.org/all/aPtqdAxDwiuQZbrn@intel.com/
[3] https://lore.kernel.org/intel-gfx/7c2d6f4e-69e6-452a-89cc-5fd4254430bd@intel.com/T/#m6e8beab2cc3b6ff9d61f740f107d83a2f4e08114

Rev2:
 - Drop the redundant version member for AS SDP, and use the member
   revision
 - Drop member to store AS SDP transmission time, use simple helper
   instead.
 - Use Burst mode to write Panel Replay config DPCDs.
 - Split AS SDP configuration in compute_config() and
   compute_config_late() phase.
 - Always enable AS SDP whenever supported by source + sink.

Rev3:
 - Use ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit also to determine AS
   SDP v2 support.
 - Drop patch to make provision to send AS SDP v1.
 - Add patch to include all relevant AS SDP fields in comparison.
 - Other refactor improvements suggested by Ville.

Ankit Nautiyal (19):
  drm/dp: Rename and relocate AS SDP payload field masks
  drm/dp: Clean up DPRX feature enumeration macros
  drm/dp: Add bits for AS SDP FAVT Payload Fields Parsing support
  drm/dp: Add DPCD for configuring AS SDP for PR + VRR
  drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP
  drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink
  drm/i915/dp: Account for AS_SDP guardband only when enabled
  drm/i915/dp: Add a helper to decide if AS SDP can be used
  drm/i915/dp: Skip AS SDP for DP branch devices
  drm/i915/dp: Use revision field of AS SDP data structure
  drm/i915/dp: Include all relevant AS SDP fields in comparison
  drm/i915/dp: Add member to intel_dp to store AS SDP v2 support
  drm/i915/psr: Write the PR config DPCDs in burst mode
  drm/i915/display: Add helper for AS SDP transmission time selection
  drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission
    time
  drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless
    ALPM
  drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off
  drm/i915/dp: Split AS SDP computation between compute_config and
    compute_config_late
  drm/i915/dp: Always enable AS SDP if supported by source + sink

 drivers/gpu/drm/i915/display/intel_alpm.c     |  20 ++-
 drivers/gpu/drm/i915/display/intel_display.c  |   6 +-
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 147 ++++++++++++++----
 drivers/gpu/drm/i915/display/intel_dp.h       |   2 +
 .../drm/i915/display/intel_dp_link_training.c |  10 +-
 .../drm/i915/display/intel_dp_link_training.h |   3 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  30 ++--
 drivers/gpu/drm/i915/display/intel_vrr.c      |  10 ++
 include/drm/display/drm_dp.h                  |  19 ++-
 11 files changed, 194 insertions(+), 56 deletions(-)

-- 
2.45.2

[PATCH 01/19] drm/dp: Rename and relocate AS SDP payload field masks

[Ankit Nautiyal]

The AS SDP payload field masks were misnamed and placed under the DPRX
feature enumeration list. These are not DPRX capability bits, but are
payload field masks for the Adaptive Sync SDP.

Relocate both masks next to the AS SDP definitions.
Update users to the corrected names. No functional change.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
 include/drm/display/drm_dp.h            | 5 +++--
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4955bd8b11d7..602efaf500bd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5295,8 +5295,8 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	if ((sdp->sdp_header.HB3 & 0x3F) != 9)
 		return -EINVAL;
 
-	as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
-	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
+	as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK;
+	as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
 	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
 	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 8b15d3eeb716..4ea3b5b08a12 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1204,8 +1204,6 @@
 
 #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1         0x2214 /* 2.0 E11 */
 # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED    (1 << 0)
-# define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE		GENMASK(1, 0)
-# define DP_ADAPTIVE_SYNC_SDP_LENGTH				GENMASK(5, 0)
 # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)
 # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED  (1 << 4)
 
@@ -1870,4 +1868,7 @@ enum operation_mode {
 	DP_AS_SDP_FAVT_TRR_REACHED = 0x03
 };
 
+#define DP_AS_SDP_OPERATION_MODE_MASK	GENMASK(1, 0)
+#define DP_AS_SDP_LENGTH_MASK		GENMASK(5, 0)
+
 #endif /* _DRM_DP_H_ */
-- 
2.45.2

[PATCH 02/19] drm/dp: Clean up DPRX feature enumeration macros

[Ankit Nautiyal]

Align the DP_DPRX feature enumeration macros for better readability and
consistency, and use the BIT() macro instead of open-coded shifts.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 include/drm/display/drm_dp.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 4ea3b5b08a12..49f0154eb93c 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1202,10 +1202,10 @@
 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_80_MS	0x04
 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_100_MS	0x05
 
-#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1         0x2214 /* 2.0 E11 */
-# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED    (1 << 0)
-# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)
-# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED  (1 << 4)
+#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1					0x2214 /* 2.0 E11 */
+# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED						BIT(0)
+# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED	BIT(1)
+# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED				BIT(4)
 
 #define DP_128B132B_SUPPORTED_LINK_RATES       0x2215 /* 2.0 */
 # define DP_UHBR10                             (1 << 0)
-- 
2.45.2

[PATCH 03/19] drm/dp: Add bits for AS SDP FAVT Payload Fields Parsing support

[Ankit Nautiyal]

DP v2.1 introduced support for sending AS SDP payload bytes for FAVT.
Add the relavant bits for the same.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 include/drm/display/drm_dp.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 49f0154eb93c..8d172863eba3 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1205,6 +1205,7 @@
 #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1					0x2214 /* 2.0 E11 */
 # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED						BIT(0)
 # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED	BIT(1)
+# define DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED			BIT(2) /* 2.1 */
 # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED				BIT(4)
 
 #define DP_128B132B_SUPPORTED_LINK_RATES       0x2215 /* 2.0 */
-- 
2.45.2

[PATCH 04/19] drm/dp: Add DPCD for configuring AS SDP for PR + VRR

[Ankit Nautiyal]

Add additional DPCDs required to be configured to support VRR with Panel
Replay. These DPCDs are specifically required for configuring Adaptive Sync
SDP and are introduced in DP v2.1.

v2:
 - Correct the shift for the bits. (Ville)
 - Add DP_PR_ prefix for the PR-related fields.
v3:
 - Use macro values in their shifted form to match the convention (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 include/drm/display/drm_dp.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 8d172863eba3..93a188113d36 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -775,6 +775,11 @@
 # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK  (0xf << 3)
 # define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE		 (1 << 7)
 
+#define PANEL_REPLAY_CONFIG3				0x11a /* DP 2.1 */
+# define DP_PR_AS_SDP_SETUP_TIME_T1			(0 << 6)
+# define DP_PR_AS_SDP_SETUP_TIME_DYNAMIC		(1 << 6) /* DP 2.1 Table 2-227 */
+# define DP_PR_AS_SDP_SETUP_TIME_T2			(2 << 6)
+
 #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
-- 
2.45.2

[PATCH 05/19] drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP

[Ankit Nautiyal]

Correct the bit-shift logic to properly readback the 10 bit target_rr from
DB3 and DB4.

v2: Align the style with readback for vtotal. (Ville)

Fixes: 12ea89291603 ("drm/i915/dp: Add Read/Write support for Adaptive Sync SDP")
Cc: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 602efaf500bd..49eeb35973a1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5298,7 +5298,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK;
 	as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
-	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
+	as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
 	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
 
 	return 0;
-- 
2.45.2

[PATCH 06/19] drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink

[Ankit Nautiyal]

Currently we do not support VRR with HDMI so skip vrr compute
config step for all DP branch devices.

v2: Restrict VRR on all DP branch devices instead for checking only for
    HDMI. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 8a957804cb97..160e1c24aa4b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -55,6 +55,16 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
 		if (connector->mst.dp)
 			return false;
 		intel_dp = intel_attached_dp(connector);
+		/*
+		 * Among non-MST DP branch devices, only an HDMI 2.1 sink connected
+		 * via a PCON could support VRR. However, supporting VRR through a
+		 * PCON requires non-trivial changes that are not implemented yet.
+		 * Until that support exists, avoid VRR on all DP branch devices.
+		 *
+		 * TODO: Add support for VRR for DP->HDMI 2.1 PCON.
+		 */
+		if (drm_dp_is_branch(intel_dp->dpcd))
+			return false;
 
 		if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))
 			return false;
-- 
2.45.2

[PATCH 07/19] drm/i915/dp: Account for AS_SDP guardband only when enabled

[Ankit Nautiyal]

Currently the intel_dp_sdp_min_guardband() accounts for AS_SDP for all
platforms that support adaptive sync SDP even for configurations where
it cannot be enabled. Instead account for adaptive sync SDP guardband
only when it is enabled.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 49eeb35973a1..499850c2abcf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7374,7 +7374,6 @@ int intel_dp_get_lines_for_sdp(const struct intel_crtc_state *crtc_state, u32 ty
 int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 			       bool assume_all_enabled)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
 	int sdp_guardband = 0;
 
 	if (assume_all_enabled ||
@@ -7389,8 +7388,8 @@ int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 		sdp_guardband = max(sdp_guardband,
 				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_PPS));
 
-	if ((assume_all_enabled && HAS_AS_SDP(display)) ||
-	    crtc_state->infoframes.enable & intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
+	if (crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
 		sdp_guardband = max(sdp_guardband,
 				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_ADAPTIVE_SYNC));
 
-- 
2.45.2

[PATCH 08/19] drm/i915/dp: Add a helper to decide if AS SDP can be used

[Ankit Nautiyal]

Add a helper that determines whether AS SDP can be used for the
current DP configuration. For now this is true only when the sink
supports AS SDP and VRR is enabled, but more conditions may be added
later.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 499850c2abcf..7ca3f9d583db 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3124,6 +3124,15 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
 	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
 }
 
+static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
+				    struct intel_crtc_state *crtc_state)
+{
+	if (!intel_dp->as_sdp_supported)
+		return false;
+
+	return crtc_state->vrr.enable;
+}
+
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
@@ -3131,7 +3140,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
 
-	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
+	if (!intel_dp_can_use_as_sdp(intel_dp, crtc_state))
 		return;
 
 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
-- 
2.45.2

[PATCH 09/19] drm/i915/dp: Skip AS SDP for DP branch devices

[Ankit Nautiyal]

Currently, VRR is not implmented for DP branch devices.
So skip sending AS SDP for them.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7ca3f9d583db..1a35478411d7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3130,6 +3130,12 @@ static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
 	if (!intel_dp->as_sdp_supported)
 		return false;
 
+	/*
+	 * #TODO Implement AS SDP for DP branch device.
+	 */
+	if (drm_dp_is_branch(intel_dp->dpcd))
+		return false;
+
 	return crtc_state->vrr.enable;
 }
 
-- 
2.45.2

[PATCH 10/19] drm/i915/dp: Use revision field of AS SDP data structure

[Ankit Nautiyal]

Use the revision field of struct drm_dp_as_sdp instead of current
hardcoding for the AS SDP revisions.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
 drivers/gpu/drm/i915/display/intel_dp.c      | 7 +++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 10b6c6fcb03f..57870baebfa5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4906,7 +4906,8 @@ static bool
 intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
 			const struct drm_dp_as_sdp *b)
 {
-	return a->vtotal == b->vtotal &&
+	return a->revision == b->revision &&
+		a->vtotal == b->vtotal &&
 		a->target_rr == b->target_rr &&
 		a->duration_incr_ms == b->duration_incr_ms &&
 		a->duration_decr_ms == b->duration_decr_ms &&
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 1a35478411d7..f9bfb07f0205 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3154,6 +3154,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
 	as_sdp->length = 0x9;
 	as_sdp->duration_incr_ms = 0;
+	as_sdp->revision = 0x2;
 	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
 
 	if (crtc_state->cmrr.enable) {
@@ -5117,7 +5118,7 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
 	/* Prepare AS (Adaptive Sync) SDP Header */
 	sdp->sdp_header.HB0 = 0;
 	sdp->sdp_header.HB1 = as_sdp->sdp_type;
-	sdp->sdp_header.HB2 = 0x02;
+	sdp->sdp_header.HB2 = as_sdp->revision;
 	sdp->sdp_header.HB3 = as_sdp->length;
 
 	/* Fill AS (Adaptive Sync) SDP Payload */
@@ -5304,13 +5305,11 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
 		return -EINVAL;
 
-	if (sdp->sdp_header.HB2 != 0x02)
-		return -EINVAL;
-
 	if ((sdp->sdp_header.HB3 & 0x3F) != 9)
 		return -EINVAL;
 
 	as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK;
+	as_sdp->revision = sdp->sdp_header.HB2;
 	as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
 	as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
-- 
2.45.2

[PATCH 11/19] drm/i915/dp: Include all relevant AS SDP fields in comparison

[Ankit Nautiyal]

Add missing drm_dp_as_sdp header fields to intel_compare_dp_as_sdp()
comparison.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 57870baebfa5..a0e7ef2574b2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4906,11 +4906,14 @@ static bool
 intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
 			const struct drm_dp_as_sdp *b)
 {
-	return a->revision == b->revision &&
+	return a->sdp_type == b->sdp_type &&
+		a->revision == b->revision &&
+		a->length == b->length &&
 		a->vtotal == b->vtotal &&
 		a->target_rr == b->target_rr &&
 		a->duration_incr_ms == b->duration_incr_ms &&
 		a->duration_decr_ms == b->duration_decr_ms &&
+		a->target_rr_divider == b->target_rr_divider &&
 		a->mode == b->mode;
 }
 
-- 
2.45.2

[PATCH 12/19] drm/i915/dp: Add member to intel_dp to store AS SDP v2 support

[Ankit Nautiyal]

DP v2.1 SCR advertises support for FAVT payload fields parsing in DPCD
0x2214 Bit 2. This indicates the support for Adaptive-Sync SDP version 2
(AS SDP v2), which allows the source to set the version in HB2[4:0] and the
payload length in HB3[5:0] of the AS SDP header.

DP v2.1 SCR also adds a bit for Async Video Timing during Panel Replay, in
Panel Replay Capability DPCD 0x00b1 (Bit 3). When this bit is cleared, the
sink supports asynchronous video timing while in a Panel Replay Active
state. The spec mandates that such sinks shall support AS SDP v2.

Infer AS SDP v2 support from these capabilities and store it in
struct intel_dp for use by subsequent feature enablement changes.

v2:
 - Include parsing ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit to
   determine AS SDP v2 support. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 37 +++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e2496db1642a..efc609eef4f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1870,6 +1870,7 @@ struct intel_dp {
 	/* connector directly attached - won't be use for modeset in mst world */
 	struct intel_connector *attached_connector;
 	bool as_sdp_supported;
+	bool as_sdp_v2_supported;
 
 	struct drm_dp_tunnel *tunnel;
 	bool tunnel_suspended:1;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f9bfb07f0205..b2007ffe18bc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6301,6 +6301,40 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
 					       false);
 }
 
+static bool
+intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp)
+{
+	u8 rx_features;
+	u8 pr_caps;
+
+	/*
+	 * The DP spec does not explicitly provide the AS SDP v2 capability.
+	 * So based on the DP v2.1 SCR, we infer it from the following bits:
+	 *
+	 * DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED indicates support for
+	 * FAVT, which is explicitly defined to use AS SDP v2.
+	 *
+	 * DP_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR cleared indicates support
+	 * for Async Video timing in PR active and the spec mandates that such
+	 * sinks shall support AS SDP v2.
+	 */
+	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
+				  DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
+				  &rx_features) == 1) {
+		if (rx_features & DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED)
+			return true;
+	}
+
+	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
+				  DP_PANEL_REPLAY_CAP_CAPABILITY,
+				  &pr_caps) == 1) {
+		if (!(pr_caps & DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))
+			return true;
+	}
+
+	return false;
+}
+
 static void
 intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
 {
@@ -6308,6 +6342,9 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
 
 	intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
 		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
+
+	intel_dp->as_sdp_v2_supported = intel_dp->as_sdp_supported &&
+					intel_dp_sink_supports_as_sdp_v2(intel_dp);
 }
 
 static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)
-- 
2.45.2

[PATCH 13/19] drm/i915/psr: Write the PR config DPCDs in burst mode

[Ankit Nautiyal]

Replace the consecutive single-byte writes to PANEL_REPLAY_CONFIG and
CONFIG2 with one drm_dp_dpcd_write() burst starting at PANEL_REPLAY_CONFIG,
reducing AUX transactions.

v2: Drop extra conditions, and optimize variables. (Ville)

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 29 ++++++++++++++----------
 1 file changed, 17 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2f1b48cd8efd..ca054135ca30 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -782,27 +782,32 @@ static bool psr2_su_region_et_valid(struct intel_connector *connector, bool pane
 static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
 				      const struct intel_crtc_state *crtc_state)
 {
-	u8 val = DP_PANEL_REPLAY_ENABLE |
-		DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
-		DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
-		DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
-		DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
-	u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;
+	struct intel_display *display = to_intel_display(intel_dp);
+	u8 panel_replay_config[2];
+	int ret;
+
+	panel_replay_config[0] = DP_PANEL_REPLAY_ENABLE |
+				 DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
+				 DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
+				 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
+				 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
+	panel_replay_config[1] = DP_PANEL_REPLAY_CRC_VERIFICATION;
 
 	if (crtc_state->has_sel_update)
-		val |= DP_PANEL_REPLAY_SU_ENABLE;
+		panel_replay_config[0] |= DP_PANEL_REPLAY_SU_ENABLE;
 
 	if (crtc_state->enable_psr2_su_region_et)
-		val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
+		panel_replay_config[0] |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
 
 	if (crtc_state->req_psr2_sdp_prior_scanline)
-		panel_replay_config2 |=
+		panel_replay_config[1] |=
 			DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE;
 
-	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val);
+	ret = drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG,
+				panel_replay_config, sizeof(panel_replay_config));
 
-	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,
-			   panel_replay_config2);
+	if (ret != sizeof(panel_replay_config))
+		drm_dbg_kms(display->drm, "Failed to write Panel Replay Configs\n");
 }
 
 static void _psr_enable_sink(struct intel_dp *intel_dp,
-- 
2.45.2

[PATCH 14/19] drm/i915/display: Add helper for AS SDP transmission time selection

[Ankit Nautiyal]

AS SDP may be transmitted at T1 or T2 depending on Panel Replay and
Adaptive Sync SDP configuration as per DP 2.1. Current we are using
T1 only, but future PR/AS SDP modes/features may require T2 or dynamic
selection.

Introduce a helper to return the appropriate AS SDP transmission time so
that a single value is consistently used for programming PR_ALPM.
For now this returns T1.

v2: Avoid adding new member to crtc_state; use a helper. (Ville)
v3: Clarify why AS SDP transmission time is fixed to T1. (Ville)

Bspec: 68920
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 20 +++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.c   | 11 +++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h   |  2 ++
 3 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index a7350ce8e716..76de24a03f61 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -11,6 +11,7 @@
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
+#include "intel_display_utils.h"
 #include "intel_dp.h"
 #include "intel_dp_aux.h"
 #include "intel_psr.h"
@@ -359,6 +360,23 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
 	crtc_state->has_lobf = true;
 }
 
+static u32 get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *crtc_state)
+{
+	int as_sdp_setup_time = intel_dp_as_sdp_transmission_time();
+
+	switch (as_sdp_setup_time) {
+	case DP_PR_AS_SDP_SETUP_TIME_T1:
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
+	case DP_PR_AS_SDP_SETUP_TIME_DYNAMIC:
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2;
+	case DP_PR_AS_SDP_SETUP_TIME_T2:
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2;
+	default:
+		MISSING_CASE(as_sdp_setup_time);
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
+	}
+}
+
 static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state)
 {
@@ -382,7 +400,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
 
 		if (intel_dp->as_sdp_supported) {
-			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
+			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
 
 			if (crtc_state->link_off_after_as_sdp_when_pr_active)
 				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b2007ffe18bc..108e97b26748 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7465,3 +7465,14 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 
 	return true;
 }
+
+int intel_dp_as_sdp_transmission_time(void)
+{
+	/*
+	 * DP allows AS SDP position to move during PR active in some cases, but
+	 * software-controlled refresh rate changes with DC6v / ALPM require the
+	 * AS SDP to remain at T1. Use T1 unconditionally for now.
+	 */
+
+	return DP_PR_AS_SDP_SETUP_TIME_T1;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 2849b9ecdc71..2e4609d9d05c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -238,4 +238,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
 		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
 
+int intel_dp_as_sdp_transmission_time(void);
+
 #endif /* __INTEL_DP_H__ */
-- 
2.45.2

[PATCH 15/19] drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission time

[Ankit Nautiyal]

Panel Replay requires the AS SDP transmission time to be written into
PANEL_REPLAY_CONFIG3. This field was previously not programmed.

Use the AS SDP transmission-time helper to populate CONFIG3.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index ca054135ca30..34b0993d9b1d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -783,7 +783,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
 				      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
-	u8 panel_replay_config[2];
+	u8 panel_replay_config[3];
 	int ret;
 
 	panel_replay_config[0] = DP_PANEL_REPLAY_ENABLE |
@@ -792,6 +792,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
 				 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
 				 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
 	panel_replay_config[1] = DP_PANEL_REPLAY_CRC_VERIFICATION;
+	panel_replay_config[2] = intel_dp_as_sdp_transmission_time();
 
 	if (crtc_state->has_sel_update)
 		panel_replay_config[0] |= DP_PANEL_REPLAY_SU_ENABLE;
-- 
2.45.2

[PATCH 16/19] drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless ALPM

[Ankit Nautiyal]

To support Panel Replay with Auxless-ALPM, the source must transmit
Adaptive-Sync SDPs for video timing synchronization while PR is active.
As per the DP spec v2.1, this requires setting DPCD 0x0107[6]
(FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE). This applies whether VRR is enabled
(AVT/FAVT) or fixed-timing mode is used.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 10 ++++++++--
 drivers/gpu/drm/i915/display/intel_dp_link_training.h |  3 ++-
 drivers/gpu/drm/i915/display/intel_dp_mst.c           |  2 +-
 3 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 54c585c59b90..136cabf06fd9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -27,6 +27,7 @@
 #include <drm/display/drm_dp_helper.h>
 #include <drm/drm_print.h>
 
+#include "intel_alpm.h"
 #include "intel_display_core.h"
 #include "intel_display_jiffies.h"
 #include "intel_display_types.h"
@@ -710,11 +711,14 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
 	return true;
 }
 
-void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)
+void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate,
+				     bool is_vrr,
+				     bool is_pr_with_link_off)
 {
 	u8 link_config[2];
 
 	link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
+	link_config[0] |= is_pr_with_link_off ? DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE : 0;
 	link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
 			 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
 	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
@@ -737,7 +741,9 @@ static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
 	  * especially on the first real commit when clearing the inherited flag.
 	  */
 	intel_dp_link_training_set_mode(intel_dp,
-					crtc_state->port_clock, crtc_state->vrr.in_range);
+					crtc_state->port_clock,
+					crtc_state->vrr.in_range,
+					intel_alpm_is_alpm_aux_less(intel_dp, crtc_state));
 }
 
 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 1ba22ed6db08..3591210f8ee6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -18,7 +18,8 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
 bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp);
 
 void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,
-				     int link_rate, bool is_vrr);
+				     int link_rate, bool is_vrr,
+				     bool is_pr_with_link_off);
 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
 				   int link_bw, int rate_select, int lane_count,
 				   bool enhanced_framing);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 887b6de14e46..2201cf7ce015 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -2142,7 +2142,7 @@ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
 
 	intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);
 
-	intel_dp_link_training_set_mode(intel_dp, link_rate, false);
+	intel_dp_link_training_set_mode(intel_dp, link_rate, false, false);
 	intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
 				      drm_dp_enhanced_frame_cap(intel_dp->dpcd));
 
-- 
2.45.2

[PATCH 17/19] drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off

[Ankit Nautiyal]

For Panel Replay with AUX-less ALPM (link-off PR), the source must send
Adaptive-Sync SDP v2. Program DB[1:0] per DP spec v2.1:
- VRR AVT: 00b (variable VTotal)
- VRR FAVT: 10b/11b (TRR not reached/reached)
- Fixed timing with PR link-off (VRR off): 01b (AS disabled; VTotal fixed)

Also, drop the redundant target_rr assignment.

v2: Fix the else case. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 108e97b26748..343bb2a86675 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3161,9 +3161,10 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
 		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
 		as_sdp->target_rr_divider = true;
-	} else {
+	} else if (crtc_state->vrr.enable) {
 		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
-		as_sdp->target_rr = 0;
+	} else {
+		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
 	}
 }
 
-- 
2.45.2

[PATCH 18/19] drm/i915/dp: Split AS SDP computation between compute_config and compute_config_late

[Ankit Nautiyal]

Currently we enable AS SDP only when VRR is enabled. As we start using
AS SDP for other features, this becomes a problem. The AS SDP
configuration can change dynamically based on VRR, CMRR, PR, ALPM, etc.
Since these features may be enabled or disabled after the initial
configuration, the AS SDP parameters need to be computed later in the
pipeline.

However, not all of the AS SDP logic can be moved to the late stage:
the VRR guardband optimization depends on knowing early whether AS SDP
can be used. Without this, we would end up accounting for AS SDP on all
platforms that support it, even for panels that do not support AS SDP.
Therefore we set the infoframe enable bit for AS SDP during
compute_config(), before the guardband is computed.

To handle these constraints, split the AS SDP programming into two
phases:

 - intel_dp_compute_as_sdp()
   Runs during compute_config().
   Sets only the infoframe enable bit so that the guardband logic can
   account for AS SDP requirements.

 - intel_dp_as_sdp_compute_config_late()
   Runs during compute_config_late().
   Computes all remaining AS SDP fields based on the features that need
   it.

The late-stage computation is called from
intel_dp_sdp_compute_config_late(), before computing the minimum guardband
for SDPs.

This is a preparatory change. A subsequent patch will always enable AS
SDP when the source and sink support it.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 67 ++++++++++++++++---------
 1 file changed, 44 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 343bb2a86675..7da3dee226a0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3142,30 +3142,17 @@ static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
-	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
-
 	if (!intel_dp_can_use_as_sdp(intel_dp, crtc_state))
 		return;
 
+	/*
+	 * Only set the infoframes.enable flag here.
+	 * The remaining AS SDP fields are programmed in the
+	 * compute_config_late() phase. We need this flag early so that the
+	 * VRR guardband calculation can properly account for AS SDP
+	 * requirements.
+	 */
 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
-
-	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
-	as_sdp->length = 0x9;
-	as_sdp->duration_incr_ms = 0;
-	as_sdp->revision = 0x2;
-	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
-
-	if (crtc_state->cmrr.enable) {
-		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
-		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
-		as_sdp->target_rr_divider = true;
-	} else if (crtc_state->vrr.enable) {
-		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
-	} else {
-		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
-	}
 }
 
 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
@@ -7370,11 +7357,45 @@ void intel_dp_mst_resume(struct intel_display *display)
 }
 
 static
-int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
+void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
+					 struct intel_crtc_state *crtc_state)
+{
+	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+
+	if ((crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)) == 0)
+		return;
+
+	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
+	as_sdp->length = 0x9;
+	as_sdp->duration_incr_ms = 0;
+	as_sdp->revision = 0x2;
+	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
+
+	if (crtc_state->cmrr.enable) {
+		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
+		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
+		as_sdp->target_rr_divider = true;
+	} else if (crtc_state->vrr.enable) {
+		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
+	} else {
+		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
+	}
+}
+
+static
+int intel_dp_sdp_compute_config_late(struct intel_dp *intel_dp,
+				     struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	int guardband = intel_crtc_vblank_length(crtc_state);
-	int min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false);
+	int min_sdp_guardband;
+
+	intel_dp_as_sdp_compute_config_late(intel_dp, crtc_state);
+
+	min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false);
 
 	if (guardband < min_sdp_guardband) {
 		drm_dbg_kms(display->drm, "guardband %d < min sdp guardband %d\n",
@@ -7394,7 +7415,7 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
 
 	intel_psr_compute_config_late(intel_dp, crtc_state);
 
-	ret = intel_dp_sdp_compute_config_late(crtc_state);
+	ret = intel_dp_sdp_compute_config_late(intel_dp, crtc_state);
 	if (ret)
 		return ret;
 
-- 
2.45.2

[PATCH 19/19] drm/i915/dp: Always enable AS SDP if supported by source + sink

[Ankit Nautiyal]

Currently AS SDP is only configured when VRR is enabled. However, other
use cases like CMRR, Panel Replay, etc. also send information to the sink
via AS SDPs.

With optimized guardband, we also need to account for wakeup time and other
relevant details that depend on the AS SDP position whenever AS SDP is
enabled. If a feature enabling AS SDP gets turned on later (after modeset),
the guardband might not be sufficient and may need to increase, triggering
a full modeset.

To avoid this, always send AS SDP whenever the source and sink both
support it.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7da3dee226a0..81be0767927e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3136,7 +3136,7 @@ static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
 	if (drm_dp_is_branch(intel_dp->dpcd))
 		return false;
 
-	return crtc_state->vrr.enable;
+	return true;
 }
 
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
-- 
2.45.2

Re: [PATCH 04/19] drm/dp: Add DPCD for configuring AS SDP for PR + VRR

[Ville Syrjälä]

On Mon, Mar 30, 2026 at 09:36:41AM +0530, Ankit Nautiyal wrote:
> Add additional DPCDs required to be configured to support VRR with Panel
> Replay. These DPCDs are specifically required for configuring Adaptive Sync
> SDP and are introduced in DP v2.1.
> 
> v2:
>  - Correct the shift for the bits. (Ville)
>  - Add DP_PR_ prefix for the PR-related fields.
> v3:
>  - Use macro values in their shifted form to match the convention (Ville)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  include/drm/display/drm_dp.h | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 8d172863eba3..93a188113d36 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -775,6 +775,11 @@
>  # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK  (0xf << 3)
>  # define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE		 (1 << 7)
>  
> +#define PANEL_REPLAY_CONFIG3				0x11a /* DP 2.1 */

I would still define a DP_PR_AS_SDP_SETUP_TIME_MASK here, to
make it clear which bits are part of this.

With that
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +# define DP_PR_AS_SDP_SETUP_TIME_T1			(0 << 6)
> +# define DP_PR_AS_SDP_SETUP_TIME_DYNAMIC		(1 << 6) /* DP 2.1 Table 2-227 */
> +# define DP_PR_AS_SDP_SETUP_TIME_T2			(2 << 6)
> +
>  #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
>  #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
>  #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 07/19] drm/i915/dp: Account for AS_SDP guardband only when enabled

[Ville Syrjälä]

On Mon, Mar 30, 2026 at 09:36:44AM +0530, Ankit Nautiyal wrote:
> Currently the intel_dp_sdp_min_guardband() accounts for AS_SDP for all
> platforms that support adaptive sync SDP even for configurations where
> it cannot be enabled. Instead account for adaptive sync SDP guardband
> only when it is enabled.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 49eeb35973a1..499850c2abcf 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7374,7 +7374,6 @@ int intel_dp_get_lines_for_sdp(const struct intel_crtc_state *crtc_state, u32 ty
>  int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
>  			       bool assume_all_enabled)
>  {
> -	struct intel_display *display = to_intel_display(crtc_state);
>  	int sdp_guardband = 0;
>  
>  	if (assume_all_enabled ||
> @@ -7389,8 +7388,8 @@ int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
>  		sdp_guardband = max(sdp_guardband,
>  				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_PPS));
>  
> -	if ((assume_all_enabled && HAS_AS_SDP(display)) ||
> -	    crtc_state->infoframes.enable & intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
> +	if (crtc_state->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
>  		sdp_guardband = max(sdp_guardband,
>  				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_ADAPTIVE_SYNC));
>  
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 08/19] drm/i915/dp: Add a helper to decide if AS SDP can be used

[Ville Syrjälä]

On Mon, Mar 30, 2026 at 09:36:45AM +0530, Ankit Nautiyal wrote:
> Add a helper that determines whether AS SDP can be used for the
> current DP configuration. For now this is true only when the sink
> supports AS SDP and VRR is enabled, but more conditions may be added
> later.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 499850c2abcf..7ca3f9d583db 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3124,6 +3124,15 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
>  	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
>  }
>  
> +static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
> +				    struct intel_crtc_state *crtc_state)
> +{
> +	if (!intel_dp->as_sdp_supported)
> +		return false;
> +

Could have a FIXME here about fastset being borked with this. Didn't
read far enough in the series yet to see if you did anything about that.

Either way
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +	return crtc_state->vrr.enable;
> +}
> +
>  static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>  				    struct intel_crtc_state *crtc_state)
>  {
> @@ -3131,7 +3140,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
>  
> -	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
> +	if (!intel_dp_can_use_as_sdp(intel_dp, crtc_state))
>  		return;
>  
>  	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 09/19] drm/i915/dp: Skip AS SDP for DP branch devices

[Ville Syrjälä]

On Mon, Mar 30, 2026 at 09:36:46AM +0530, Ankit Nautiyal wrote:
> Currently, VRR is not implmented for DP branch devices.
> So skip sending AS SDP for them.

Sure why not.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7ca3f9d583db..1a35478411d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3130,6 +3130,12 @@ static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
>  	if (!intel_dp->as_sdp_supported)
>  		return false;
>  
> +	/*
> +	 * #TODO Implement AS SDP for DP branch device.
> +	 */
> +	if (drm_dp_is_branch(intel_dp->dpcd))
> +		return false;
> +
>  	return crtc_state->vrr.enable;
>  }
>  
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 11/19] drm/i915/dp: Include all relevant AS SDP fields in comparison

[Ville Syrjälä]

On Mon, Mar 30, 2026 at 09:36:48AM +0530, Ankit Nautiyal wrote:
> Add missing drm_dp_as_sdp header fields to intel_compare_dp_as_sdp()
> comparison.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 57870baebfa5..a0e7ef2574b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4906,11 +4906,14 @@ static bool
>  intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
>  			const struct drm_dp_as_sdp *b)
>  {
> -	return a->revision == b->revision &&
> +	return a->sdp_type == b->sdp_type &&
> +		a->revision == b->revision &&
> +		a->length == b->length &&
>  		a->vtotal == b->vtotal &&
>  		a->target_rr == b->target_rr &&
>  		a->duration_incr_ms == b->duration_incr_ms &&
>  		a->duration_decr_ms == b->duration_decr_ms &&
> +		a->target_rr_divider == b->target_rr_divider &&
>  		a->mode == b->mode;

BTW do we know if the hardware actually modifies the AS SDP DIP buffer,
or does it just override some of the values as the SDP is being
transmitted? If the former then I guess we have to keep in mind that
the readout may have to do some sanitizing to avoid mismatches,
if we do anything that require the hardware to dynamically adjust
the AS SDP.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  }
>  
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 12/19] drm/i915/dp: Add member to intel_dp to store AS SDP v2 support

[Ville Syrjälä]

On Mon, Mar 30, 2026 at 09:36:49AM +0530, Ankit Nautiyal wrote:
> DP v2.1 SCR advertises support for FAVT payload fields parsing in DPCD
> 0x2214 Bit 2. This indicates the support for Adaptive-Sync SDP version 2
> (AS SDP v2), which allows the source to set the version in HB2[4:0] and the
> payload length in HB3[5:0] of the AS SDP header.
> 
> DP v2.1 SCR also adds a bit for Async Video Timing during Panel Replay, in
> Panel Replay Capability DPCD 0x00b1 (Bit 3). When this bit is cleared, the
> sink supports asynchronous video timing while in a Panel Replay Active
> state. The spec mandates that such sinks shall support AS SDP v2.
> 
> Infer AS SDP v2 support from these capabilities and store it in
> struct intel_dp for use by subsequent feature enablement changes.
> 
> v2:
>  - Include parsing ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit to
>    determine AS SDP v2 support. (Ville)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 37 +++++++++++++++++++
>  2 files changed, 38 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e2496db1642a..efc609eef4f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1870,6 +1870,7 @@ struct intel_dp {
>  	/* connector directly attached - won't be use for modeset in mst world */
>  	struct intel_connector *attached_connector;
>  	bool as_sdp_supported;
> +	bool as_sdp_v2_supported;
>  
>  	struct drm_dp_tunnel *tunnel;
>  	bool tunnel_suspended:1;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index f9bfb07f0205..b2007ffe18bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6301,6 +6301,40 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
>  					       false);
>  }
>  
> +static bool
> +intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp)
> +{
> +	u8 rx_features;
> +	u8 pr_caps;
> +
> +	/*
> +	 * The DP spec does not explicitly provide the AS SDP v2 capability.
> +	 * So based on the DP v2.1 SCR, we infer it from the following bits:
> +	 *
> +	 * DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED indicates support for
> +	 * FAVT, which is explicitly defined to use AS SDP v2.
> +	 *
> +	 * DP_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR cleared indicates support
> +	 * for Async Video timing in PR active and the spec mandates that such
> +	 * sinks shall support AS SDP v2.
> +	 */
> +	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
> +				  DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
> +				  &rx_features) == 1) {
> +		if (rx_features & DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED)
> +			return true;
> +	}
> +
> +	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
> +				  DP_PANEL_REPLAY_CAP_CAPABILITY,
> +				  &pr_caps) == 1) {
> +		if (!(pr_caps & DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))

That seems to be backwards. If the sink requires AS SDP
then it will set the bit.

> +			return true;
> +	}
> +
> +	return false;
> +}
> +
>  static void
>  intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
>  {
> @@ -6308,6 +6342,9 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
>  
>  	intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
>  		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
> +
> +	intel_dp->as_sdp_v2_supported = intel_dp->as_sdp_supported &&
> +					intel_dp_sink_supports_as_sdp_v2(intel_dp);
>  }
>  
>  static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 13/19] drm/i915/psr: Write the PR config DPCDs in burst mode

[Ville Syrjälä]

On Mon, Mar 30, 2026 at 09:36:50AM +0530, Ankit Nautiyal wrote:
> Replace the consecutive single-byte writes to PANEL_REPLAY_CONFIG and
> CONFIG2 with one drm_dp_dpcd_write() burst starting at PANEL_REPLAY_CONFIG,
> reducing AUX transactions.
> 
> v2: Drop extra conditions, and optimize variables. (Ville)
> 
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 29 ++++++++++++++----------
>  1 file changed, 17 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2f1b48cd8efd..ca054135ca30 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -782,27 +782,32 @@ static bool psr2_su_region_et_valid(struct intel_connector *connector, bool pane
>  static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
>  				      const struct intel_crtc_state *crtc_state)
>  {
> -	u8 val = DP_PANEL_REPLAY_ENABLE |
> -		DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
> -		DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
> -		DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
> -		DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
> -	u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	u8 panel_replay_config[2];
> +	int ret;
> +
> +	panel_replay_config[0] = DP_PANEL_REPLAY_ENABLE |
> +				 DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
> +				 DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
> +				 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
> +				 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
> +	panel_replay_config[1] = DP_PANEL_REPLAY_CRC_VERIFICATION;
>  
>  	if (crtc_state->has_sel_update)
> -		val |= DP_PANEL_REPLAY_SU_ENABLE;
> +		panel_replay_config[0] |= DP_PANEL_REPLAY_SU_ENABLE;
>  
>  	if (crtc_state->enable_psr2_su_region_et)
> -		val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
> +		panel_replay_config[0] |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
>  
>  	if (crtc_state->req_psr2_sdp_prior_scanline)
> -		panel_replay_config2 |=
> +		panel_replay_config[1] |=
>  			DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE;
>  
> -	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val);
> +	ret = drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG,
> +				panel_replay_config, sizeof(panel_replay_config));
>  
> -	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,
> -			   panel_replay_config2);
> +	if (ret != sizeof(panel_replay_config))
> +		drm_dbg_kms(display->drm, "Failed to write Panel Replay Configs\n");

Looks like we don't actually check for errors on any of the
other DPCD accesses here. So I'd probably drop it here as well.

Either way
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  }
>  
>  static void _psr_enable_sink(struct intel_dp *intel_dp,
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 14/19] drm/i915/display: Add helper for AS SDP transmission time selection

[Ville Syrjälä]

On Mon, Mar 30, 2026 at 09:36:51AM +0530, Ankit Nautiyal wrote:
> AS SDP may be transmitted at T1 or T2 depending on Panel Replay and
> Adaptive Sync SDP configuration as per DP 2.1. Current we are using
> T1 only, but future PR/AS SDP modes/features may require T2 or dynamic
> selection.
> 
> Introduce a helper to return the appropriate AS SDP transmission time so
> that a single value is consistently used for programming PR_ALPM.
> For now this returns T1.
> 
> v2: Avoid adding new member to crtc_state; use a helper. (Ville)
> v3: Clarify why AS SDP transmission time is fixed to T1. (Ville)
> 
> Bspec: 68920
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 20 +++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_dp.c   | 11 +++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h   |  2 ++
>  3 files changed, 32 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index a7350ce8e716..76de24a03f61 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -11,6 +11,7 @@
>  #include "intel_crtc.h"
>  #include "intel_de.h"
>  #include "intel_display_types.h"
> +#include "intel_display_utils.h"
>  #include "intel_dp.h"
>  #include "intel_dp_aux.h"
>  #include "intel_psr.h"
> @@ -359,6 +360,23 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
>  	crtc_state->has_lobf = true;
>  }
>  
> +static u32 get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *crtc_state)
> +{
> +	int as_sdp_setup_time = intel_dp_as_sdp_transmission_time();
> +
> +	switch (as_sdp_setup_time) {
> +	case DP_PR_AS_SDP_SETUP_TIME_T1:
> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
> +	case DP_PR_AS_SDP_SETUP_TIME_DYNAMIC:
> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2;
> +	case DP_PR_AS_SDP_SETUP_TIME_T2:
> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2;
> +	default:
> +		MISSING_CASE(as_sdp_setup_time);
> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
> +	}
> +}
> +
>  static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  			       const struct intel_crtc_state *crtc_state)
>  {
> @@ -382,7 +400,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
>  
>  		if (intel_dp->as_sdp_supported) {
> -			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
> +			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
>  
>  			if (crtc_state->link_off_after_as_sdp_when_pr_active)
>  				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index b2007ffe18bc..108e97b26748 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7465,3 +7465,14 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>  
>  	return true;
>  }
> +
> +int intel_dp_as_sdp_transmission_time(void)

This is a DPCD register value, so u8 would seem like the more
appropriate return type.

With that
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +{
> +	/*
> +	 * DP allows AS SDP position to move during PR active in some cases, but
> +	 * software-controlled refresh rate changes with DC6v / ALPM require the
> +	 * AS SDP to remain at T1. Use T1 unconditionally for now.
> +	 */
> +
> +	return DP_PR_AS_SDP_SETUP_TIME_T1;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 2849b9ecdc71..2e4609d9d05c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -238,4 +238,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>  	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>  		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
>  
> +int intel_dp_as_sdp_transmission_time(void);
> +
>  #endif /* __INTEL_DP_H__ */
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 15/19] drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission time

[Ville Syrjälä]

On Mon, Mar 30, 2026 at 09:36:52AM +0530, Ankit Nautiyal wrote:
> Panel Replay requires the AS SDP transmission time to be written into
> PANEL_REPLAY_CONFIG3. This field was previously not programmed.
> 
> Use the AS SDP transmission-time helper to populate CONFIG3.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index ca054135ca30..34b0993d9b1d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -783,7 +783,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
>  				      const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> -	u8 panel_replay_config[2];
> +	u8 panel_replay_config[3];
>  	int ret;
>  
>  	panel_replay_config[0] = DP_PANEL_REPLAY_ENABLE |
> @@ -792,6 +792,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
>  				 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
>  				 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
>  	panel_replay_config[1] = DP_PANEL_REPLAY_CRC_VERIFICATION;
> +	panel_replay_config[2] = intel_dp_as_sdp_transmission_time();

PANEL_REPLAY_CONFIG3 0x11a
...
PANEL_REPLAY_CONFIG1 0x1b0
PANEL_REPLAY_CONFIG2 0x1b1

So apparently we can't do the burst write for all three :/

Looks like 0x1b2 is not used for anything so don't really understand
why it wasn't added there. Oh well.

>  
>  	if (crtc_state->has_sel_update)
>  		panel_replay_config[0] |= DP_PANEL_REPLAY_SU_ENABLE;
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 16/19] drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless ALPM

[Ville Syrjälä]

On Mon, Mar 30, 2026 at 09:36:53AM +0530, Ankit Nautiyal wrote:
> To support Panel Replay with Auxless-ALPM, the source must transmit
> Adaptive-Sync SDPs for video timing synchronization while PR is active.
> As per the DP spec v2.1, this requires setting DPCD 0x0107[6]
> (FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE). This applies whether VRR is enabled
> (AVT/FAVT) or fixed-timing mode is used.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 10 ++++++++--
>  drivers/gpu/drm/i915/display/intel_dp_link_training.h |  3 ++-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c           |  2 +-
>  3 files changed, 11 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 54c585c59b90..136cabf06fd9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -27,6 +27,7 @@
>  #include <drm/display/drm_dp_helper.h>
>  #include <drm/drm_print.h>
>  
> +#include "intel_alpm.h"
>  #include "intel_display_core.h"
>  #include "intel_display_jiffies.h"
>  #include "intel_display_types.h"
> @@ -710,11 +711,14 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
>  	return true;
>  }
>  
> -void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)
> +void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate,
> +				     bool is_vrr,
> +				     bool is_pr_with_link_off)

>  {
>  	u8 link_config[2];
>  
>  	link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> +	link_config[0] |= is_pr_with_link_off ? DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE : 0;

I think we should only set this if we are going to enable the AS SDP.

The bit seems to be perhaps a bit misnamed in the spec because you
apparently you have to set it even if you suspend AS SDP transmission
during PR active (when you have a sink with 
DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR == 0). In that
case it seems to just mean that the sink will grab the coasting vtotal
from the last AS SDP transmitted prior to PR active.

>  	link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
>  			 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
>  	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
> @@ -737,7 +741,9 @@ static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
>  	  * especially on the first real commit when clearing the inherited flag.
>  	  */
>  	intel_dp_link_training_set_mode(intel_dp,
> -					crtc_state->port_clock, crtc_state->vrr.in_range);
> +					crtc_state->port_clock,
> +					crtc_state->vrr.in_range,
> +					intel_alpm_is_alpm_aux_less(intel_dp, crtc_state));
>  }
>  
>  void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> index 1ba22ed6db08..3591210f8ee6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> @@ -18,7 +18,8 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
>  bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp);
>  
>  void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,
> -				     int link_rate, bool is_vrr);
> +				     int link_rate, bool is_vrr,
> +				     bool is_pr_with_link_off);
>  void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
>  				   int link_bw, int rate_select, int lane_count,
>  				   bool enhanced_framing);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 887b6de14e46..2201cf7ce015 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -2142,7 +2142,7 @@ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
>  
>  	intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);
>  
> -	intel_dp_link_training_set_mode(intel_dp, link_rate, false);
> +	intel_dp_link_training_set_mode(intel_dp, link_rate, false, false);
>  	intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
>  				      drm_dp_enhanced_frame_cap(intel_dp->dpcd));
>  
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 18/19] drm/i915/dp: Split AS SDP computation between compute_config and compute_config_late

[Ville Syrjälä]

On Mon, Mar 30, 2026 at 09:36:55AM +0530, Ankit Nautiyal wrote:
> Currently we enable AS SDP only when VRR is enabled. As we start using
> AS SDP for other features, this becomes a problem. The AS SDP
> configuration can change dynamically based on VRR, CMRR, PR, ALPM, etc.
> Since these features may be enabled or disabled after the initial
> configuration, the AS SDP parameters need to be computed later in the
> pipeline.
> 
> However, not all of the AS SDP logic can be moved to the late stage:
> the VRR guardband optimization depends on knowing early whether AS SDP
> can be used. Without this, we would end up accounting for AS SDP on all
> platforms that support it, even for panels that do not support AS SDP.
> Therefore we set the infoframe enable bit for AS SDP during
> compute_config(), before the guardband is computed.
> 
> To handle these constraints, split the AS SDP programming into two
> phases:
> 
>  - intel_dp_compute_as_sdp()
>    Runs during compute_config().
>    Sets only the infoframe enable bit so that the guardband logic can
>    account for AS SDP requirements.
> 
>  - intel_dp_as_sdp_compute_config_late()
>    Runs during compute_config_late().
>    Computes all remaining AS SDP fields based on the features that need
>    it.
> 
> The late-stage computation is called from
> intel_dp_sdp_compute_config_late(), before computing the minimum guardband
> for SDPs.
> 
> This is a preparatory change. A subsequent patch will always enable AS
> SDP when the source and sink support it.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 67 ++++++++++++++++---------
>  1 file changed, 44 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 343bb2a86675..7da3dee226a0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3142,30 +3142,17 @@ static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
>  static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>  				    struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
> -	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->hw.adjusted_mode;
> -
>  	if (!intel_dp_can_use_as_sdp(intel_dp, crtc_state))
>  		return;
>  
> +	/*
> +	 * Only set the infoframes.enable flag here.
> +	 * The remaining AS SDP fields are programmed in the
> +	 * compute_config_late() phase. We need this flag early so that the
> +	 * VRR guardband calculation can properly account for AS SDP
> +	 * requirements.
> +	 */
>  	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
> -
> -	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
> -	as_sdp->length = 0x9;
> -	as_sdp->duration_incr_ms = 0;
> -	as_sdp->revision = 0x2;
> -	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
> -
> -	if (crtc_state->cmrr.enable) {
> -		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
> -		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
> -		as_sdp->target_rr_divider = true;
> -	} else if (crtc_state->vrr.enable) {
> -		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
> -	} else {
> -		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
> -	}
>  }
>  
>  static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
> @@ -7370,11 +7357,45 @@ void intel_dp_mst_resume(struct intel_display *display)
>  }
>  
>  static
> -int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
> +void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
> +					 struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
> +	const struct drm_display_mode *adjusted_mode =
> +		&crtc_state->hw.adjusted_mode;
> +
> +	if ((crtc_state->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)) == 0)
> +		return;
> +
> +	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
> +	as_sdp->length = 0x9;
> +	as_sdp->duration_incr_ms = 0;
> +	as_sdp->revision = 0x2;
> +	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
> +
> +	if (crtc_state->cmrr.enable) {
> +		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
> +		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
> +		as_sdp->target_rr_divider = true;
> +	} else if (crtc_state->vrr.enable) {
> +		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
> +	} else {
> +		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
> +	}

Nothing in here right now depends on anything but
intel_vrr_compute_config(). Was there something specific you will
need to consult here that is computed later?

> +}
> +
> +static
> +int intel_dp_sdp_compute_config_late(struct intel_dp *intel_dp,
> +				     struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	int guardband = intel_crtc_vblank_length(crtc_state);
> -	int min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false);
> +	int min_sdp_guardband;
> +
> +	intel_dp_as_sdp_compute_config_late(intel_dp, crtc_state);
> +
> +	min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false);
>  
>  	if (guardband < min_sdp_guardband) {
>  		drm_dbg_kms(display->drm, "guardband %d < min sdp guardband %d\n",
> @@ -7394,7 +7415,7 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
>  
>  	intel_psr_compute_config_late(intel_dp, crtc_state);
>  
> -	ret = intel_dp_sdp_compute_config_late(crtc_state);
> +	ret = intel_dp_sdp_compute_config_late(intel_dp, crtc_state);
>  	if (ret)
>  		return ret;
>  
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 08/19] drm/i915/dp: Add a helper to decide if AS SDP can be used

[Ville Syrjälä]

On Mon, Mar 30, 2026 at 09:21:42PM +0300, Ville Syrjälä wrote:
> On Mon, Mar 30, 2026 at 09:36:45AM +0530, Ankit Nautiyal wrote:
> > Add a helper that determines whether AS SDP can be used for the
> > current DP configuration. For now this is true only when the sink
> > supports AS SDP and VRR is enabled, but more conditions may be added
> > later.
> > 
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++++-
> >  1 file changed, 10 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 499850c2abcf..7ca3f9d583db 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3124,6 +3124,15 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> >  	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
> >  }
> >  
> > +static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
> > +				    struct intel_crtc_state *crtc_state)

Hmm. Maybe the name should be .._need_as_sdp() or something like that
instead. I can imagine many cases when we could use the AS SDP but don't
have to.

> > +{
> > +	if (!intel_dp->as_sdp_supported)
> > +		return false;
> > +
> 
> Could have a FIXME here about fastset being borked with this. Didn't
> read far enough in the series yet to see if you did anything about that.
> 
> Either way
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> > +	return crtc_state->vrr.enable;
> > +}
> > +
> >  static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> >  				    struct intel_crtc_state *crtc_state)
> >  {
> > @@ -3131,7 +3140,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> >  	const struct drm_display_mode *adjusted_mode =
> >  		&crtc_state->hw.adjusted_mode;
> >  
> > -	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
> > +	if (!intel_dp_can_use_as_sdp(intel_dp, crtc_state))
> >  		return;
> >  
> >  	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
> > -- 
> > 2.45.2
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH 19/19] drm/i915/dp: Always enable AS SDP if supported by source + sink

[Ville Syrjälä]

On Mon, Mar 30, 2026 at 09:36:56AM +0530, Ankit Nautiyal wrote:
> Currently AS SDP is only configured when VRR is enabled. However, other
> use cases like CMRR, Panel Replay, etc. also send information to the sink
> via AS SDPs.
> 
> With optimized guardband, we also need to account for wakeup time and other
> relevant details that depend on the AS SDP position whenever AS SDP is
> enabled. If a feature enabling AS SDP gets turned on later (after modeset),
> the guardband might not be sufficient and may need to increase, triggering
> a full modeset.
> 
> To avoid this, always send AS SDP whenever the source and sink both
> support it.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7da3dee226a0..81be0767927e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3136,7 +3136,7 @@ static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
>  	if (drm_dp_is_branch(intel_dp->dpcd))
>  		return false;
>  
> -	return crtc_state->vrr.enable;
> +	return true;

I think what we actually want is something like

...
	if (pr_auxless_alpm &&
	    DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR)
		return true;
	return intel_vrr_possible();
}

That way non-VRR PR panels that don't need the AS SDP to maintain
the synchronization can avoid the AS SDP, and thus potentially use
a smaller guardband.

>  }
>  
>  static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 04/19] drm/dp: Add DPCD for configuring AS SDP for PR + VRR

[Nautiyal, Ankit K]

On 3/30/2026 11:49 PM, Ville Syrjälä wrote:
> On Mon, Mar 30, 2026 at 09:36:41AM +0530, Ankit Nautiyal wrote:
>> Add additional DPCDs required to be configured to support VRR with Panel
>> Replay. These DPCDs are specifically required for configuring Adaptive Sync
>> SDP and are introduced in DP v2.1.
>>
>> v2:
>>   - Correct the shift for the bits. (Ville)
>>   - Add DP_PR_ prefix for the PR-related fields.
>> v3:
>>   - Use macro values in their shifted form to match the convention (Ville)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   include/drm/display/drm_dp.h | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
>> index 8d172863eba3..93a188113d36 100644
>> --- a/include/drm/display/drm_dp.h
>> +++ b/include/drm/display/drm_dp.h
>> @@ -775,6 +775,11 @@
>>   # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK  (0xf << 3)
>>   # define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE		 (1 << 7)
>>   
>> +#define PANEL_REPLAY_CONFIG3				0x11a /* DP 2.1 */
> I would still define a DP_PR_AS_SDP_SETUP_TIME_MASK here, to
> make it clear which bits are part of this.


  I think I added that in previous implementation, but dropped in this. 
I will add it again.

Regards,

Ankit

>
> With that
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>> +# define DP_PR_AS_SDP_SETUP_TIME_T1			(0 << 6)
>> +# define DP_PR_AS_SDP_SETUP_TIME_DYNAMIC		(1 << 6) /* DP 2.1 Table 2-227 */
>> +# define DP_PR_AS_SDP_SETUP_TIME_T2			(2 << 6)
>> +
>>   #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
>>   #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
>>   #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
>> -- 
>> 2.45.2

Re: [PATCH 08/19] drm/i915/dp: Add a helper to decide if AS SDP can be used

[Nautiyal, Ankit K]

On 3/30/2026 11:51 PM, Ville Syrjälä wrote:
> On Mon, Mar 30, 2026 at 09:36:45AM +0530, Ankit Nautiyal wrote:
>> Add a helper that determines whether AS SDP can be used for the
>> current DP configuration. For now this is true only when the sink
>> supports AS SDP and VRR is enabled, but more conditions may be added
>> later.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++++-
>>   1 file changed, 10 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 499850c2abcf..7ca3f9d583db 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -3124,6 +3124,15 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
>>   	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
>>   }
>>   
>> +static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
>> +				    struct intel_crtc_state *crtc_state)
>> +{
>> +	if (!intel_dp->as_sdp_supported)
>> +		return false;
>> +
> Could have a FIXME here about fastset being borked with this. Didn't
> read far enough in the series yet to see if you did anything about that.

Hmm... let me check if I understand your concern correctly.

When VRR state changes through the fastset path, 
intel_dp_as_sdp_compute_config_late() will compute different AS SDP fields.

We do write the new values to the SDP DIP registers during update_pipe, 
but since AS SDP comparison is skipped during fastset,

we have no way to verify through state readback that the hardware 
actually latched the new values correctly.

Is that what you had in mind?

I'll add a FIXME about this.

Thanks,

Ankit


>
> Either way
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>> +	return crtc_state->vrr.enable;
>> +}
>> +
>>   static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>>   				    struct intel_crtc_state *crtc_state)
>>   {
>> @@ -3131,7 +3140,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>>   	const struct drm_display_mode *adjusted_mode =
>>   		&crtc_state->hw.adjusted_mode;
>>   
>> -	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
>> +	if (!intel_dp_can_use_as_sdp(intel_dp, crtc_state))
>>   		return;
>>   
>>   	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
>> -- 
>> 2.45.2

Re: [PATCH 08/19] drm/i915/dp: Add a helper to decide if AS SDP can be used

[Nautiyal, Ankit K]

On 3/31/2026 1:10 AM, Ville Syrjälä wrote:
> On Mon, Mar 30, 2026 at 09:21:42PM +0300, Ville Syrjälä wrote:
>> On Mon, Mar 30, 2026 at 09:36:45AM +0530, Ankit Nautiyal wrote:
>>> Add a helper that determines whether AS SDP can be used for the
>>> current DP configuration. For now this is true only when the sink
>>> supports AS SDP and VRR is enabled, but more conditions may be added
>>> later.
>>>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++++-
>>>   1 file changed, 10 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index 499850c2abcf..7ca3f9d583db 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -3124,6 +3124,15 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
>>>   	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
>>>   }
>>>   
>>> +static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
>>> +				    struct intel_crtc_state *crtc_state)
> Hmm. Maybe the name should be .._need_as_sdp() or something like that
> instead. I can imagine many cases when we could use the AS SDP but don't
> have to.


Roger that. Will rename this to ..._needs_as_sdp().


Regards,

Ankit


>
>>> +{
>>> +	if (!intel_dp->as_sdp_supported)
>>> +		return false;
>>> +
>> Could have a FIXME here about fastset being borked with this. Didn't
>> read far enough in the series yet to see if you did anything about that.
>>
>> Either way
>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>>> +	return crtc_state->vrr.enable;
>>> +}
>>> +
>>>   static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>>>   				    struct intel_crtc_state *crtc_state)
>>>   {
>>> @@ -3131,7 +3140,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>>>   	const struct drm_display_mode *adjusted_mode =
>>>   		&crtc_state->hw.adjusted_mode;
>>>   
>>> -	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
>>> +	if (!intel_dp_can_use_as_sdp(intel_dp, crtc_state))
>>>   		return;
>>>   
>>>   	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
>>> -- 
>>> 2.45.2
>> -- 
>> Ville Syrjälä
>> Intel

Re: [PATCH 11/19] drm/i915/dp: Include all relevant AS SDP fields in comparison

[Nautiyal, Ankit K]

On 3/30/2026 11:56 PM, Ville Syrjälä wrote:
> On Mon, Mar 30, 2026 at 09:36:48AM +0530, Ankit Nautiyal wrote:
>> Add missing drm_dp_as_sdp header fields to intel_compare_dp_as_sdp()
>> comparison.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
>>   1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 57870baebfa5..a0e7ef2574b2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -4906,11 +4906,14 @@ static bool
>>   intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
>>   			const struct drm_dp_as_sdp *b)
>>   {
>> -	return a->revision == b->revision &&
>> +	return a->sdp_type == b->sdp_type &&
>> +		a->revision == b->revision &&
>> +		a->length == b->length &&
>>   		a->vtotal == b->vtotal &&
>>   		a->target_rr == b->target_rr &&
>>   		a->duration_incr_ms == b->duration_incr_ms &&
>>   		a->duration_decr_ms == b->duration_decr_ms &&
>> +		a->target_rr_divider == b->target_rr_divider &&
>>   		a->mode == b->mode;
> BTW do we know if the hardware actually modifies the AS SDP DIP buffer,
> or does it just override some of the values as the SDP is being
> transmitted? If the former then I guess we have to keep in mind that
> the readout may have to do some sanitizing to avoid mismatches,
> if we do anything that require the hardware to dynamically adjust
> the AS SDP.


There are some things HW sends on its own like bits 2 and 3 of DB0 :
  - Adaptive sync SDP transmission disable Bit 2 and
  - Remote frame buffer update Bit 3

I think it overrides those values instead of modifying the SDP DIP buffer.
That’s what the spec implies I suppose.

"When PR ALPM is Active (AS SDP Version 2), hardware will automatically 
drive DB0[3:2].
Software should always program these bits to zero."

Regards,
Ankit

>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>>   }
>>   
>> -- 
>> 2.45.2

Re: [PATCH 12/19] drm/i915/dp: Add member to intel_dp to store AS SDP v2 support

[Nautiyal, Ankit K]

On 3/30/2026 11:59 PM, Ville Syrjälä wrote:
> On Mon, Mar 30, 2026 at 09:36:49AM +0530, Ankit Nautiyal wrote:
>> DP v2.1 SCR advertises support for FAVT payload fields parsing in DPCD
>> 0x2214 Bit 2. This indicates the support for Adaptive-Sync SDP version 2
>> (AS SDP v2), which allows the source to set the version in HB2[4:0] and the
>> payload length in HB3[5:0] of the AS SDP header.
>>
>> DP v2.1 SCR also adds a bit for Async Video Timing during Panel Replay, in
>> Panel Replay Capability DPCD 0x00b1 (Bit 3). When this bit is cleared, the
>> sink supports asynchronous video timing while in a Panel Replay Active
>> state. The spec mandates that such sinks shall support AS SDP v2.
>>
>> Infer AS SDP v2 support from these capabilities and store it in
>> struct intel_dp for use by subsequent feature enablement changes.
>>
>> v2:
>>   - Include parsing ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit to
>>     determine AS SDP v2 support. (Ville)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   .../drm/i915/display/intel_display_types.h    |  1 +
>>   drivers/gpu/drm/i915/display/intel_dp.c       | 37 +++++++++++++++++++
>>   2 files changed, 38 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index e2496db1642a..efc609eef4f5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1870,6 +1870,7 @@ struct intel_dp {
>>   	/* connector directly attached - won't be use for modeset in mst world */
>>   	struct intel_connector *attached_connector;
>>   	bool as_sdp_supported;
>> +	bool as_sdp_v2_supported;
>>   
>>   	struct drm_dp_tunnel *tunnel;
>>   	bool tunnel_suspended:1;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index f9bfb07f0205..b2007ffe18bc 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -6301,6 +6301,40 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
>>   					       false);
>>   }
>>   
>> +static bool
>> +intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp)
>> +{
>> +	u8 rx_features;
>> +	u8 pr_caps;
>> +
>> +	/*
>> +	 * The DP spec does not explicitly provide the AS SDP v2 capability.
>> +	 * So based on the DP v2.1 SCR, we infer it from the following bits:
>> +	 *
>> +	 * DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED indicates support for
>> +	 * FAVT, which is explicitly defined to use AS SDP v2.
>> +	 *
>> +	 * DP_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR cleared indicates support
>> +	 * for Async Video timing in PR active and the spec mandates that such
>> +	 * sinks shall support AS SDP v2.
>> +	 */
>> +	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
>> +				  DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
>> +				  &rx_features) == 1) {
>> +		if (rx_features & DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED)
>> +			return true;
>> +	}
>> +
>> +	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
>> +				  DP_PANEL_REPLAY_CAP_CAPABILITY,
>> +				  &pr_caps) == 1) {
>> +		if (!(pr_caps & DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))
> That seems to be backwards. If the sink requires AS SDP
> then it will set the bit.


Hmm.. I indeed got it backwards, you are right.

If Async Video timing is supported then re-set the bit. But in that case 
AS SDP is not required.

So reset means AS SDP not required; bit set means it is required.

Thanks, I will correct this in next version.

Regards,

Ankit

>
>> +			return true;
>> +	}
>> +
>> +	return false;
>> +}
>> +
>>   static void
>>   intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
>>   {
>> @@ -6308,6 +6342,9 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
>>   
>>   	intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
>>   		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
>> +
>> +	intel_dp->as_sdp_v2_supported = intel_dp->as_sdp_supported &&
>> +					intel_dp_sink_supports_as_sdp_v2(intel_dp);
>>   }
>>   
>>   static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)
>> -- 
>> 2.45.2

Re: [PATCH 13/19] drm/i915/psr: Write the PR config DPCDs in burst mode

[Nautiyal, Ankit K]

On 3/31/2026 12:14 AM, Ville Syrjälä wrote:
> On Mon, Mar 30, 2026 at 09:36:50AM +0530, Ankit Nautiyal wrote:
>> Replace the consecutive single-byte writes to PANEL_REPLAY_CONFIG and
>> CONFIG2 with one drm_dp_dpcd_write() burst starting at PANEL_REPLAY_CONFIG,
>> reducing AUX transactions.
>>
>> v2: Drop extra conditions, and optimize variables. (Ville)
>>
>> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_psr.c | 29 ++++++++++++++----------
>>   1 file changed, 17 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 2f1b48cd8efd..ca054135ca30 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -782,27 +782,32 @@ static bool psr2_su_region_et_valid(struct intel_connector *connector, bool pane
>>   static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
>>   				      const struct intel_crtc_state *crtc_state)
>>   {
>> -	u8 val = DP_PANEL_REPLAY_ENABLE |
>> -		DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
>> -		DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
>> -		DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
>> -		DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
>> -	u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;
>> +	struct intel_display *display = to_intel_display(intel_dp);
>> +	u8 panel_replay_config[2];
>> +	int ret;
>> +
>> +	panel_replay_config[0] = DP_PANEL_REPLAY_ENABLE |
>> +				 DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
>> +				 DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
>> +				 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
>> +				 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
>> +	panel_replay_config[1] = DP_PANEL_REPLAY_CRC_VERIFICATION;
>>   
>>   	if (crtc_state->has_sel_update)
>> -		val |= DP_PANEL_REPLAY_SU_ENABLE;
>> +		panel_replay_config[0] |= DP_PANEL_REPLAY_SU_ENABLE;
>>   
>>   	if (crtc_state->enable_psr2_su_region_et)
>> -		val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
>> +		panel_replay_config[0] |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
>>   
>>   	if (crtc_state->req_psr2_sdp_prior_scanline)
>> -		panel_replay_config2 |=
>> +		panel_replay_config[1] |=
>>   			DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE;
>>   
>> -	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val);
>> +	ret = drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG,
>> +				panel_replay_config, sizeof(panel_replay_config));
>>   
>> -	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,
>> -			   panel_replay_config2);
>> +	if (ret != sizeof(panel_replay_config))
>> +		drm_dbg_kms(display->drm, "Failed to write Panel Replay Configs\n");
> Looks like we don't actually check for errors on any of the
> other DPCD accesses here. So I'd probably drop it here as well.


Yeah.. will drop the error message.


Thanks,
Ankit
>
> Either way
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>>   }
>>   
>>   static void _psr_enable_sink(struct intel_dp *intel_dp,
>> -- 
>> 2.45.2

Re: [PATCH 15/19] drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission time

[Nautiyal, Ankit K]

On 3/31/2026 12:24 AM, Ville Syrjälä wrote:
> On Mon, Mar 30, 2026 at 09:36:52AM +0530, Ankit Nautiyal wrote:
>> Panel Replay requires the AS SDP transmission time to be written into
>> PANEL_REPLAY_CONFIG3. This field was previously not programmed.
>>
>> Use the AS SDP transmission-time helper to populate CONFIG3.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_psr.c | 3 ++-
>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index ca054135ca30..34b0993d9b1d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -783,7 +783,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
>>   				      const struct intel_crtc_state *crtc_state)
>>   {
>>   	struct intel_display *display = to_intel_display(intel_dp);
>> -	u8 panel_replay_config[2];
>> +	u8 panel_replay_config[3];
>>   	int ret;
>>   
>>   	panel_replay_config[0] = DP_PANEL_REPLAY_ENABLE |
>> @@ -792,6 +792,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
>>   				 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
>>   				 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
>>   	panel_replay_config[1] = DP_PANEL_REPLAY_CRC_VERIFICATION;
>> +	panel_replay_config[2] = intel_dp_as_sdp_transmission_time();
> PANEL_REPLAY_CONFIG3 0x11a
> ...
> PANEL_REPLAY_CONFIG1 0x1b0
> PANEL_REPLAY_CONFIG2 0x1b1
>
> So apparently we can't do the burst write for all three :/
>
> Looks like 0x1b2 is not used for anything so don't really understand
> why it wasn't added there. Oh well.


Oops! My bad. Thanks for catching this blunder.

I would also move the definition of PANEL_REPLAY_CONFIG3 above the 
PANEL_REPLAY_CONFIG.

I guess I didn’t pay any attention on the offset at all, and assumed 
this would follow PANEL_REPLAY_CONFIG2 :(

Will be careful and will not repeat this again.


Thanks,
Ankit

>
>>   
>>   	if (crtc_state->has_sel_update)
>>   		panel_replay_config[0] |= DP_PANEL_REPLAY_SU_ENABLE;
>> -- 
>> 2.45.2

Re: [PATCH 08/19] drm/i915/dp: Add a helper to decide if AS SDP can be used

[Ville Syrjälä]

On Tue, Mar 31, 2026 at 05:12:14PM +0530, Nautiyal, Ankit K wrote:
> 
> On 3/30/2026 11:51 PM, Ville Syrjälä wrote:
> > On Mon, Mar 30, 2026 at 09:36:45AM +0530, Ankit Nautiyal wrote:
> >> Add a helper that determines whether AS SDP can be used for the
> >> current DP configuration. For now this is true only when the sink
> >> supports AS SDP and VRR is enabled, but more conditions may be added
> >> later.
> >>
> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++++-
> >>   1 file changed, 10 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> >> index 499850c2abcf..7ca3f9d583db 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> @@ -3124,6 +3124,15 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> >>   	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
> >>   }
> >>   
> >> +static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
> >> +				    struct intel_crtc_state *crtc_state)
> >> +{
> >> +	if (!intel_dp->as_sdp_supported)
> >> +		return false;
> >> +
> > Could have a FIXME here about fastset being borked with this. Didn't
> > read far enough in the series yet to see if you did anything about that.
> 
> Hmm... let me check if I understand your concern correctly.
> 
> When VRR state changes through the fastset path, 
> intel_dp_as_sdp_compute_config_late() will compute different AS SDP fields.
> 
> We do write the new values to the SDP DIP registers during update_pipe, 
> but since AS SDP comparison is skipped during fastset,

Oh, I thought we didn't have that. If it's there then I guess it's
fine-ish. Although we don't do the infoframe/SDP updates in the
truly proper atomic fashion, nor do we handle the new cdclk->tc clock
crossing thing correctly. So I suspect we might end up sending
a corrupted packet if the update happens to straddle the transmission
line.

> we have no way to verify through state readback that the hardware 
> actually latched the new values correctly.
> 
> Is that what you had in mind?
> 
> I'll add a FIXME about this.
> 
> Thanks,
> 
> Ankit
> 
> 
> >
> > Either way
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >> +	return crtc_state->vrr.enable;
> >> +}
> >> +
> >>   static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> >>   				    struct intel_crtc_state *crtc_state)
> >>   {
> >> @@ -3131,7 +3140,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> >>   	const struct drm_display_mode *adjusted_mode =
> >>   		&crtc_state->hw.adjusted_mode;
> >>   
> >> -	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
> >> +	if (!intel_dp_can_use_as_sdp(intel_dp, crtc_state))
> >>   		return;
> >>   
> >>   	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
> >> -- 
> >> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 16/19] drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless ALPM

[Nautiyal, Ankit K]

On 3/31/2026 12:52 AM, Ville Syrjälä wrote:
> On Mon, Mar 30, 2026 at 09:36:53AM +0530, Ankit Nautiyal wrote:
>> To support Panel Replay with Auxless-ALPM, the source must transmit
>> Adaptive-Sync SDPs for video timing synchronization while PR is active.
>> As per the DP spec v2.1, this requires setting DPCD 0x0107[6]
>> (FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE). This applies whether VRR is enabled
>> (AVT/FAVT) or fixed-timing mode is used.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp_link_training.c | 10 ++++++++--
>>   drivers/gpu/drm/i915/display/intel_dp_link_training.h |  3 ++-
>>   drivers/gpu/drm/i915/display/intel_dp_mst.c           |  2 +-
>>   3 files changed, 11 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index 54c585c59b90..136cabf06fd9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -27,6 +27,7 @@
>>   #include <drm/display/drm_dp_helper.h>
>>   #include <drm/drm_print.h>
>>   
>> +#include "intel_alpm.h"
>>   #include "intel_display_core.h"
>>   #include "intel_display_jiffies.h"
>>   #include "intel_display_types.h"
>> @@ -710,11 +711,14 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
>>   	return true;
>>   }
>>   
>> -void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)
>> +void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate,
>> +				     bool is_vrr,
>> +				     bool is_pr_with_link_off)
>>   {
>>   	u8 link_config[2];
>>   
>>   	link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
>> +	link_config[0] |= is_pr_with_link_off ? DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE : 0;
> I think we should only set this if we are going to enable the AS SDP.
>
> The bit seems to be perhaps a bit misnamed in the spec because you
> apparently you have to set it even if you suspend AS SDP transmission
> during PR active (when you have a sink with
> DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR == 0). In that
> case it seems to just mean that the sink will grab the coasting vtotal
> from the last AS SDP transmitted prior to PR active.

Hmm. Ok then I think will use:
crtc_state->infoframe_enable & 
intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)

Also, I have not yet added fields for coasting vtotal. I am thinking to 
add that support and fill these for:
pr_auxless_alpm && 
DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR case.

Thanks,
Ankit


>
>>   	link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
>>   			 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
>>   	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
>> @@ -737,7 +741,9 @@ static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
>>   	  * especially on the first real commit when clearing the inherited flag.
>>   	  */
>>   	intel_dp_link_training_set_mode(intel_dp,
>> -					crtc_state->port_clock, crtc_state->vrr.in_range);
>> +					crtc_state->port_clock,
>> +					crtc_state->vrr.in_range,
>> +					intel_alpm_is_alpm_aux_less(intel_dp, crtc_state));
>>   }
>>   
>>   void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> index 1ba22ed6db08..3591210f8ee6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> @@ -18,7 +18,8 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
>>   bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp);
>>   
>>   void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,
>> -				     int link_rate, bool is_vrr);
>> +				     int link_rate, bool is_vrr,
>> +				     bool is_pr_with_link_off);
>>   void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
>>   				   int link_bw, int rate_select, int lane_count,
>>   				   bool enhanced_framing);
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> index 887b6de14e46..2201cf7ce015 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> @@ -2142,7 +2142,7 @@ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
>>   
>>   	intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);
>>   
>> -	intel_dp_link_training_set_mode(intel_dp, link_rate, false);
>> +	intel_dp_link_training_set_mode(intel_dp, link_rate, false, false);
>>   	intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
>>   				      drm_dp_enhanced_frame_cap(intel_dp->dpcd));
>>   
>> -- 
>> 2.45.2

Re: [PATCH 15/19] drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission time

[Ville Syrjälä]

On Tue, Mar 31, 2026 at 05:28:51PM +0530, Nautiyal, Ankit K wrote:
> 
> On 3/31/2026 12:24 AM, Ville Syrjälä wrote:
> > On Mon, Mar 30, 2026 at 09:36:52AM +0530, Ankit Nautiyal wrote:
> >> Panel Replay requires the AS SDP transmission time to be written into
> >> PANEL_REPLAY_CONFIG3. This field was previously not programmed.
> >>
> >> Use the AS SDP transmission-time helper to populate CONFIG3.
> >>
> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/display/intel_psr.c | 3 ++-
> >>   1 file changed, 2 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> >> index ca054135ca30..34b0993d9b1d 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> >> @@ -783,7 +783,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
> >>   				      const struct intel_crtc_state *crtc_state)
> >>   {
> >>   	struct intel_display *display = to_intel_display(intel_dp);
> >> -	u8 panel_replay_config[2];
> >> +	u8 panel_replay_config[3];
> >>   	int ret;
> >>   
> >>   	panel_replay_config[0] = DP_PANEL_REPLAY_ENABLE |
> >> @@ -792,6 +792,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
> >>   				 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
> >>   				 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
> >>   	panel_replay_config[1] = DP_PANEL_REPLAY_CRC_VERIFICATION;
> >> +	panel_replay_config[2] = intel_dp_as_sdp_transmission_time();
> > PANEL_REPLAY_CONFIG3 0x11a
> > ...
> > PANEL_REPLAY_CONFIG1 0x1b0
> > PANEL_REPLAY_CONFIG2 0x1b1
> >
> > So apparently we can't do the burst write for all three :/
> >
> > Looks like 0x1b2 is not used for anything so don't really understand
> > why it wasn't added there. Oh well.
> 
> 
> Oops! My bad. Thanks for catching this blunder.
> 
> I would also move the definition of PANEL_REPLAY_CONFIG3 above the 
> PANEL_REPLAY_CONFIG.
> 
> I guess I didn’t pay any attention on the offset at all, and assumed 
> this would follow PANEL_REPLAY_CONFIG2 :(

Yeah, I did the same mistake when reading the previous version and
suggesting the burst write. But at least we can still do the burst
write for PANEL_REPLAY_CONFIG1+PANEL_REPLAY_CONFIG2, so my suggestion
wasn't entirely wrong :)

> 
> Will be careful and will not repeat this again.
> 
> 
> Thanks,
> Ankit
> 
> >
> >>   
> >>   	if (crtc_state->has_sel_update)
> >>   		panel_replay_config[0] |= DP_PANEL_REPLAY_SU_ENABLE;
> >> -- 
> >> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 18/19] drm/i915/dp: Split AS SDP computation between compute_config and compute_config_late

[Nautiyal, Ankit K]

On 3/31/2026 1:08 AM, Ville Syrjälä wrote:
> On Mon, Mar 30, 2026 at 09:36:55AM +0530, Ankit Nautiyal wrote:
>> Currently we enable AS SDP only when VRR is enabled. As we start using
>> AS SDP for other features, this becomes a problem. The AS SDP
>> configuration can change dynamically based on VRR, CMRR, PR, ALPM, etc.
>> Since these features may be enabled or disabled after the initial
>> configuration, the AS SDP parameters need to be computed later in the
>> pipeline.
>>
>> However, not all of the AS SDP logic can be moved to the late stage:
>> the VRR guardband optimization depends on knowing early whether AS SDP
>> can be used. Without this, we would end up accounting for AS SDP on all
>> platforms that support it, even for panels that do not support AS SDP.
>> Therefore we set the infoframe enable bit for AS SDP during
>> compute_config(), before the guardband is computed.
>>
>> To handle these constraints, split the AS SDP programming into two
>> phases:
>>
>>   - intel_dp_compute_as_sdp()
>>     Runs during compute_config().
>>     Sets only the infoframe enable bit so that the guardband logic can
>>     account for AS SDP requirements.
>>
>>   - intel_dp_as_sdp_compute_config_late()
>>     Runs during compute_config_late().
>>     Computes all remaining AS SDP fields based on the features that need
>>     it.
>>
>> The late-stage computation is called from
>> intel_dp_sdp_compute_config_late(), before computing the minimum guardband
>> for SDPs.
>>
>> This is a preparatory change. A subsequent patch will always enable AS
>> SDP when the source and sink support it.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 67 ++++++++++++++++---------
>>   1 file changed, 44 insertions(+), 23 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 343bb2a86675..7da3dee226a0 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -3142,30 +3142,17 @@ static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
>>   static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>>   				    struct intel_crtc_state *crtc_state)
>>   {
>> -	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
>> -	const struct drm_display_mode *adjusted_mode =
>> -		&crtc_state->hw.adjusted_mode;
>> -
>>   	if (!intel_dp_can_use_as_sdp(intel_dp, crtc_state))
>>   		return;
>>   
>> +	/*
>> +	 * Only set the infoframes.enable flag here.
>> +	 * The remaining AS SDP fields are programmed in the
>> +	 * compute_config_late() phase. We need this flag early so that the
>> +	 * VRR guardband calculation can properly account for AS SDP
>> +	 * requirements.
>> +	 */
>>   	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
>> -
>> -	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
>> -	as_sdp->length = 0x9;
>> -	as_sdp->duration_incr_ms = 0;
>> -	as_sdp->revision = 0x2;
>> -	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
>> -
>> -	if (crtc_state->cmrr.enable) {
>> -		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
>> -		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
>> -		as_sdp->target_rr_divider = true;
>> -	} else if (crtc_state->vrr.enable) {
>> -		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
>> -	} else {
>> -		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
>> -	}
>>   }
>>   
>>   static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
>> @@ -7370,11 +7357,45 @@ void intel_dp_mst_resume(struct intel_display *display)
>>   }
>>   
>>   static
>> -int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
>> +void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
>> +					 struct intel_crtc_state *crtc_state)
>> +{
>> +	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
>> +	const struct drm_display_mode *adjusted_mode =
>> +		&crtc_state->hw.adjusted_mode;
>> +
>> +	if ((crtc_state->infoframes.enable &
>> +	    intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)) == 0)
>> +		return;
>> +
>> +	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
>> +	as_sdp->length = 0x9;
>> +	as_sdp->duration_incr_ms = 0;
>> +	as_sdp->revision = 0x2;
>> +	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
>> +
>> +	if (crtc_state->cmrr.enable) {
>> +		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
>> +		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
>> +		as_sdp->target_rr_divider = true;
>> +	} else if (crtc_state->vrr.enable) {
>> +		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
>> +	} else {
>> +		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
>> +	}
> Nothing in here right now depends on anything but
> intel_vrr_compute_config(). Was there something specific you will
> need to consult here that is computed later?


This was required when I was trying to send AS SDP revision 1 based on

PR link ON requirement. Now that it has been nuked so we do not need 
this change yet.

However, when we need to fill coasting Vtotal for Panel replay active 
case, it will need panel replay stuff that is computed late.

So I guess we will need to compute this during ..compute_config_late().


Thanks,
Ankit

>
>> +}
>> +
>> +static
>> +int intel_dp_sdp_compute_config_late(struct intel_dp *intel_dp,
>> +				     struct intel_crtc_state *crtc_state)
>>   {
>>   	struct intel_display *display = to_intel_display(crtc_state);
>>   	int guardband = intel_crtc_vblank_length(crtc_state);
>> -	int min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false);
>> +	int min_sdp_guardband;
>> +
>> +	intel_dp_as_sdp_compute_config_late(intel_dp, crtc_state);
>> +
>> +	min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false);
>>   
>>   	if (guardband < min_sdp_guardband) {
>>   		drm_dbg_kms(display->drm, "guardband %d < min sdp guardband %d\n",
>> @@ -7394,7 +7415,7 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
>>   
>>   	intel_psr_compute_config_late(intel_dp, crtc_state);
>>   
>> -	ret = intel_dp_sdp_compute_config_late(crtc_state);
>> +	ret = intel_dp_sdp_compute_config_late(intel_dp, crtc_state);
>>   	if (ret)
>>   		return ret;
>>   
>> -- 
>> 2.45.2

Re: [PATCH 19/19] drm/i915/dp: Always enable AS SDP if supported by source + sink

[Nautiyal, Ankit K]

On 3/31/2026 1:20 AM, Ville Syrjälä wrote:
> On Mon, Mar 30, 2026 at 09:36:56AM +0530, Ankit Nautiyal wrote:
>> Currently AS SDP is only configured when VRR is enabled. However, other
>> use cases like CMRR, Panel Replay, etc. also send information to the sink
>> via AS SDPs.
>>
>> With optimized guardband, we also need to account for wakeup time and other
>> relevant details that depend on the AS SDP position whenever AS SDP is
>> enabled. If a feature enabling AS SDP gets turned on later (after modeset),
>> the guardband might not be sufficient and may need to increase, triggering
>> a full modeset.
>>
>> To avoid this, always send AS SDP whenever the source and sink both
>> support it.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 7da3dee226a0..81be0767927e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -3136,7 +3136,7 @@ static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
>>   	if (drm_dp_is_branch(intel_dp->dpcd))
>>   		return false;
>>   
>> -	return crtc_state->vrr.enable;
>> +	return true;
> I think what we actually want is something like
>
> ...
> 	if (pr_auxless_alpm &&
> 	    DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR)
> 		return true;
> 	return intel_vrr_possible();
> }
>
> That way non-VRR PR panels that don't need the AS SDP to maintain
> the synchronization can avoid the AS SDP, and thus potentially use
> a smaller guardband.


Hmm.. makes sense. I will change this as suggested.


Thanks,

Ankit


>>   }
>>   
>>   static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>> -- 
>> 2.45.2