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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
	dri-devel@lists.freedesktop.org, jouni.hogander@intel.com,
	animesh.manna@intel.com
Subject: Re: [PATCH 14/19] drm/i915/display: Add helper for AS SDP transmission time selection
Date: Mon, 30 Mar 2026 21:47:08 +0300	[thread overview]
Message-ID: <acrFLD9186X5EOyM@intel.com> (raw)
In-Reply-To: <20260330040656.4116502-15-ankit.k.nautiyal@intel.com>

On Mon, Mar 30, 2026 at 09:36:51AM +0530, Ankit Nautiyal wrote:
> AS SDP may be transmitted at T1 or T2 depending on Panel Replay and
> Adaptive Sync SDP configuration as per DP 2.1. Current we are using
> T1 only, but future PR/AS SDP modes/features may require T2 or dynamic
> selection.
> 
> Introduce a helper to return the appropriate AS SDP transmission time so
> that a single value is consistently used for programming PR_ALPM.
> For now this returns T1.
> 
> v2: Avoid adding new member to crtc_state; use a helper. (Ville)
> v3: Clarify why AS SDP transmission time is fixed to T1. (Ville)
> 
> Bspec: 68920
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 20 +++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_dp.c   | 11 +++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h   |  2 ++
>  3 files changed, 32 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index a7350ce8e716..76de24a03f61 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -11,6 +11,7 @@
>  #include "intel_crtc.h"
>  #include "intel_de.h"
>  #include "intel_display_types.h"
> +#include "intel_display_utils.h"
>  #include "intel_dp.h"
>  #include "intel_dp_aux.h"
>  #include "intel_psr.h"
> @@ -359,6 +360,23 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
>  	crtc_state->has_lobf = true;
>  }
>  
> +static u32 get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *crtc_state)
> +{
> +	int as_sdp_setup_time = intel_dp_as_sdp_transmission_time();
> +
> +	switch (as_sdp_setup_time) {
> +	case DP_PR_AS_SDP_SETUP_TIME_T1:
> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
> +	case DP_PR_AS_SDP_SETUP_TIME_DYNAMIC:
> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2;
> +	case DP_PR_AS_SDP_SETUP_TIME_T2:
> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2;
> +	default:
> +		MISSING_CASE(as_sdp_setup_time);
> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
> +	}
> +}
> +
>  static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  			       const struct intel_crtc_state *crtc_state)
>  {
> @@ -382,7 +400,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
>  
>  		if (intel_dp->as_sdp_supported) {
> -			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
> +			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
>  
>  			if (crtc_state->link_off_after_as_sdp_when_pr_active)
>  				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index b2007ffe18bc..108e97b26748 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7465,3 +7465,14 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>  
>  	return true;
>  }
> +
> +int intel_dp_as_sdp_transmission_time(void)

This is a DPCD register value, so u8 would seem like the more
appropriate return type.

With that
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +{
> +	/*
> +	 * DP allows AS SDP position to move during PR active in some cases, but
> +	 * software-controlled refresh rate changes with DC6v / ALPM require the
> +	 * AS SDP to remain at T1. Use T1 unconditionally for now.
> +	 */
> +
> +	return DP_PR_AS_SDP_SETUP_TIME_T1;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 2849b9ecdc71..2e4609d9d05c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -238,4 +238,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>  	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>  		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
>  
> +int intel_dp_as_sdp_transmission_time(void);
> +
>  #endif /* __INTEL_DP_H__ */
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2026-03-30 18:47 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-30  4:06 [PATCH 00/19] Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM Ankit Nautiyal
2026-03-30  4:06 ` [PATCH 01/19] drm/dp: Rename and relocate AS SDP payload field masks Ankit Nautiyal
2026-03-30  4:06 ` [PATCH 02/19] drm/dp: Clean up DPRX feature enumeration macros Ankit Nautiyal
2026-03-30  4:06 ` [PATCH 03/19] drm/dp: Add bits for AS SDP FAVT Payload Fields Parsing support Ankit Nautiyal
2026-03-30  4:06 ` [PATCH 04/19] drm/dp: Add DPCD for configuring AS SDP for PR + VRR Ankit Nautiyal
2026-03-30 18:19   ` Ville Syrjälä
2026-03-31 11:41     ` Nautiyal, Ankit K
2026-03-30  4:06 ` [PATCH 05/19] drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP Ankit Nautiyal
2026-03-30  4:06 ` [PATCH 06/19] drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink Ankit Nautiyal
2026-03-30  4:06 ` [PATCH 07/19] drm/i915/dp: Account for AS_SDP guardband only when enabled Ankit Nautiyal
2026-03-30 18:20   ` Ville Syrjälä
2026-03-30  4:06 ` [PATCH 08/19] drm/i915/dp: Add a helper to decide if AS SDP can be used Ankit Nautiyal
2026-03-30 18:21   ` Ville Syrjälä
2026-03-30 19:40     ` Ville Syrjälä
2026-03-31 11:44       ` Nautiyal, Ankit K
2026-03-31 11:42     ` Nautiyal, Ankit K
2026-03-31 12:00       ` Ville Syrjälä
2026-03-30  4:06 ` [PATCH 09/19] drm/i915/dp: Skip AS SDP for DP branch devices Ankit Nautiyal
2026-03-30 18:22   ` Ville Syrjälä
2026-03-30  4:06 ` [PATCH 10/19] drm/i915/dp: Use revision field of AS SDP data structure Ankit Nautiyal
2026-03-30  4:06 ` [PATCH 11/19] drm/i915/dp: Include all relevant AS SDP fields in comparison Ankit Nautiyal
2026-03-30 18:26   ` Ville Syrjälä
2026-03-31 11:47     ` Nautiyal, Ankit K
2026-03-30  4:06 ` [PATCH 12/19] drm/i915/dp: Add member to intel_dp to store AS SDP v2 support Ankit Nautiyal
2026-03-30 18:29   ` Ville Syrjälä
2026-03-31 11:49     ` Nautiyal, Ankit K
2026-03-30  4:06 ` [PATCH 13/19] drm/i915/psr: Write the PR config DPCDs in burst mode Ankit Nautiyal
2026-03-30 18:44   ` Ville Syrjälä
2026-03-31 11:51     ` Nautiyal, Ankit K
2026-03-30  4:06 ` [PATCH 14/19] drm/i915/display: Add helper for AS SDP transmission time selection Ankit Nautiyal
2026-03-30 18:47   ` Ville Syrjälä [this message]
2026-03-30  4:06 ` [PATCH 15/19] drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission time Ankit Nautiyal
2026-03-30 18:54   ` Ville Syrjälä
2026-03-31 11:58     ` Nautiyal, Ankit K
2026-03-31 12:04       ` Ville Syrjälä
2026-03-30  4:06 ` [PATCH 16/19] drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless ALPM Ankit Nautiyal
2026-03-30 19:22   ` Ville Syrjälä
2026-03-31 12:01     ` Nautiyal, Ankit K
2026-03-30  4:06 ` [PATCH 17/19] drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off Ankit Nautiyal
2026-03-30  4:06 ` [PATCH 18/19] drm/i915/dp: Split AS SDP computation between compute_config and compute_config_late Ankit Nautiyal
2026-03-30 19:38   ` Ville Syrjälä
2026-03-31 12:05     ` Nautiyal, Ankit K
2026-03-30  4:06 ` [PATCH 19/19] drm/i915/dp: Always enable AS SDP if supported by source + sink Ankit Nautiyal
2026-03-30 19:50   ` Ville Syrjälä
2026-03-31 12:06     ` Nautiyal, Ankit K

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