Re: [PATCH 16/19] drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless ALPM

Nautiyal, Ankit K
2026-03-31T12:01:29Z

On 3/31/2026 12:52 AM, Ville Syrjälä wrote:
> On Mon, Mar 30, 2026 at 09:36:53AM +0530, Ankit Nautiyal wrote:
>> To support Panel Replay with Auxless-ALPM, the source must transmit
>> Adaptive-Sync SDPs for video timing synchronization while PR is active.
>> As per the DP spec v2.1, this requires setting DPCD 0x0107[6]
>> (FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE). This applies whether VRR is enabled
>> (AVT/FAVT) or fixed-timing mode is used.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp_link_training.c | 10 ++++++++--
>> drivers/gpu/drm/i915/display/intel_dp_link_training.h | 3 ++-
>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
>> 3 files changed, 11 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index 54c585c59b90..136cabf06fd9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -27,6 +27,7 @@
>> #include <drm/display/drm_dp_helper.h>
>> #include <drm/drm_print.h>
>>
>> +#include "intel_alpm.h"
>> #include "intel_display_core.h"
>> #include "intel_display_jiffies.h"
>> #include "intel_display_types.h"
>> @@ -710,11 +711,14 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
>> return true;
>> }
>>
>> -void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)
>> +void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate,
>> + bool is_vrr,
>> + bool is_pr_with_link_off)
>> {
>> u8 link_config[2];
>>
>> link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
>> + link_config[0] |= is_pr_with_link_off ? DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE : 0;
> I think we should only set this if we are going to enable the AS SDP.
>
> The bit seems to be perhaps a bit misnamed in the spec because you
> apparently you have to set it even if you suspend AS SDP transmission
> during PR active (when you have a sink with
> DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR == 0). In that
> case it seems to just mean that the sink will grab the coasting vtotal
> from the last AS SDP transmitted prior to PR active.

Hmm. Ok then I think will use:
crtc_state->infoframe_enable &
intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)

Also, I have not yet added fields for coasting vtotal. I am thinking to
add that support and fill these for:
pr_auxless_alpm &&
DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR case.

Thanks,
Ankit

>
>> link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
>> DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
>> drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
>> @@ -737,7 +741,9 @@ static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
>> * especially on the first real commit when clearing the inherited flag.
>> */
>> intel_dp_link_training_set_mode(intel_dp,
>> - crtc_state->port_clock, crtc_state->vrr.in_range);
>> + crtc_state->port_clock,
>> + crtc_state->vrr.in_range,
>> + intel_alpm_is_alpm_aux_less(intel_dp, crtc_state));
>> }
>>
>> void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> index 1ba22ed6db08..3591210f8ee6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> @@ -18,7 +18,8 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
>> bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp);
>>
>> void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,
>> - int link_rate, bool is_vrr);
>> + int link_rate, bool is_vrr,
>> + bool is_pr_with_link_off);
>> void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
>> int link_bw, int rate_select, int lane_count,
>> bool enhanced_framing);
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> index 887b6de14e46..2201cf7ce015 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> @@ -2142,7 +2142,7 @@ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
>>
>> intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);
>>
>> - intel_dp_link_training_set_mode(intel_dp, link_rate, false);
>> + intel_dp_link_training_set_mode(intel_dp, link_rate, false, false);
>> intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
>> drm_dp_enhanced_frame_cap(intel_dp->dpcd));
>>
>> --
>> 2.45.2