[PATCH v3 00/12] CMTG enablement

[PATCH v3 00/12] CMTG enablement

[Animesh Manna]

Common mode timing generator (CMTG) support is added LNL onwards.
Enable CMTG which will be needed by other fearure like dynamic dc
state enablement later.

Testing ongoing, currently counters are incrementing as expected.

Animesh Manna (11):
  drm/i915/cmtg: add is_enable_allowed() for cmtg
  drm/i915/cmtg: set CMTG clock select
  drm/i915/cmtg: set timings for CMTG
  drm/i915/cmtg: program VRR registers of CMTG
  drm/i915/cmtg: set transcoder mn for CMTG
  drm/i915/cmtg: add hook to enable CMTG with sync to port
  drm/i915/cmtg: add a hook to enable ddi for CMTG
  drm/i915/cmtg: Add trigger to enable/disable cmtg
  drm/i915/cmtg: Add CMTG interrupt handling
  drm/i915/cmtg: set dc3co_enable flag for lobf/psr2/pr-alpm
  drm/i915/cmtg: disable CMTG if dc3co entry condition not met

Dibin Moolakadan Subrahmanian (1):
  drm/i915/cmtg: modify existing hook to disable CMTG

 drivers/gpu/drm/i915/display/intel_cmtg.c     | 248 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  14 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  24 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  28 ++
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../gpu/drm/i915/display/intel_display_irq.c  |  12 +
 .../gpu/drm/i915/display/intel_display_regs.h |   6 +
 .../drm/i915/display/intel_display_types.h    |   8 +
 drivers/gpu/drm/i915/display/intel_dp.c       |   8 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |   7 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      |   5 +
 11 files changed, 349 insertions(+), 12 deletions(-)

-- 
2.29.0

[PATCH v3 01/12] drm/i915/cmtg: add is_enable_allowed() for cmtg

[Animesh Manna]

Introduce a flag for DC3co. CMTG will be enabled only with DC3co
so add a separate function is_allowed() for cmtg. DC3co flag
will be enabled in a separate patch.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c          | 14 ++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h          |  2 ++
 .../gpu/drm/i915/display/intel_display_device.h    |  1 +
 drivers/gpu/drm/i915/display/intel_display_types.h |  4 ++++
 4 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index e1fdc6fe9762..024d753eca55 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -16,6 +16,7 @@
 #include "intel_display_device.h"
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
+#include "intel_display_types.h"
 
 /**
  * DOC: Common Primary Timing Generator (CMTG)
@@ -185,3 +186,16 @@ void intel_cmtg_sanitize(struct intel_display *display)
 
 	intel_cmtg_disable(display, &cmtg_config);
 }
+
+bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B) &&
+	    HAS_DC3CO(display) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
+	    crtc_state->dc3co.enable)
+		return true;
+
+	return false;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index ba62199adaa2..7692cc98cf87 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -7,7 +7,9 @@
 #define __INTEL_CMTG_H__
 
 struct intel_display;
+struct intel_crtc_state;
 
 void intel_cmtg_sanitize(struct intel_display *display);
+bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CMTG_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index e84c190dcc4f..35e06fcf794d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -189,6 +189,7 @@ struct intel_display_platforms {
 #define HAS_LRR(__display)		(DISPLAY_VER(__display) >= 12)
 #define HAS_LSPCON(__display)		(IS_DISPLAY_VER(__display, 9, 10))
 #define HAS_LT_PHY(__display)		((__display)->platform.novalake)
+#define HAS_DC3CO(__display)		((__display)->platform.novalake)
 #define HAS_MBUS_JOINING(__display)	((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14)
 #define HAS_MSO(__display)		(DISPLAY_VER(__display) >= 12)
 #define HAS_OVERLAY(__display)		(DISPLAY_INFO(__display)->has_overlay)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e189f8c39ccb..8a92ea4f1438 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1434,6 +1434,10 @@ struct intel_crtc_state {
 
 	/* to track changes in plane color blocks */
 	bool plane_color_changed;
+
+	struct {
+		bool enable;
+	} dc3co;
 };
 
 enum intel_pipe_crc_source {
-- 
2.29.0

[PATCH v3 02/12] drm/i915/cmtg: set CMTG clock select

[Animesh Manna]

Program the CMTG Clock Select register based on the transcoder used.

v2:
- Correct mask for PHY B. [Jani]
- Use REG_FIELD_PREP() for enable value. [Dibin]
- Extend cmtg clock select for xe3plpd. [Dibin]

v3:
- cmtg support removed for old platform.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 24 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  2 ++
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |  7 ++++--
 4 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 024d753eca55..644522b96288 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -199,3 +199,27 @@ bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
 
 	return false;
 }
+
+void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 clk_sel_clr = 0;
+	u32 clk_sel_set = 0;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	if (cpu_transcoder == TRANSCODER_A) {
+		clk_sel_clr = CMTG_CLK_SEL_A_MASK;
+		clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
+	}
+
+	if (cpu_transcoder == TRANSCODER_B) {
+		clk_sel_clr = CMTG_CLK_SEL_B_MASK;
+		clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
+	}
+
+	if (clk_sel_set)
+		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 7692cc98cf87..660ec513626e 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -9,6 +9,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 945a35578284..8a767b659a23 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -10,8 +10,10 @@
 
 #define CMTG_CLK_SEL			_MMIO(0x46160)
 #define CMTG_CLK_SEL_A_MASK		REG_GENMASK(31, 29)
+#define CMTG_CLK_SELECT_PHYA_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
 #define CMTG_CLK_SEL_A_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
 #define CMTG_CLK_SEL_B_MASK		REG_GENMASK(15, 13)
+#define CMTG_CLK_SELECT_PHYB_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x6)
 #define CMTG_CLK_SEL_B_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
 
 #define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index eced8493e566..e78f3a00ea80 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -5,6 +5,7 @@
 
 #include <drm/drm_print.h>
 
+#include "intel_cmtg.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_ddi.h"
@@ -2249,10 +2250,12 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
-	if (intel_tc_port_in_tbt_alt_mode(dig_port))
+	if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
 		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
-	else
+	} else {
 		intel_lt_phy_pll_enable(encoder, crtc_state);
+		intel_cmtg_set_clk_select(crtc_state);
+	}
 }
 
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
-- 
2.29.0

[PATCH v3 03/12] drm/i915/cmtg: set timings for CMTG

[Animesh Manna]

Timing registers are separate for CMTG, read transcoder register
and program cmtg transcoder with those values.

v2:
- Use sw state instead of reading directly from hardware. [Jani]
- Move set_timing later after encoder enable. [Dibin]

v3:
- replace id with trans. [Jani]
- program cmtg set_timing() along with primary transcoder timing.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 48 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  3 ++
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  9 ++++
 drivers/gpu/drm/i915/display/intel_display.c  |  4 ++
 4 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 644522b96288..e0f12925f5c2 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -4,7 +4,6 @@
  */
 
 #include <linux/string_choices.h>
-#include <linux/types.h>
 
 #include <drm/drm_device.h>
 #include <drm/drm_print.h>
@@ -223,3 +222,50 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
 	if (clk_sel_set)
 		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
 }
+
+void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
+	crtc_vtotal = 1;
+	crtc_vblank_start = 1;
+	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
+
+	if (lrr) {
+		intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder),
+			       VACTIVE(crtc_vdisplay - 1) |
+			       VTOTAL(crtc_vtotal - 1));
+		intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder),
+			       VBLANK_START(crtc_vblank_start - 1) |
+			       VBLANK_END(crtc_vblank_end - 1));
+		return;
+	}
+
+	intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder),
+		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
+		       HTOTAL(adjusted_mode->crtc_htotal - 1));
+	intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder),
+		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
+		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
+	intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder),
+		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
+		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
+	intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder),
+		       VACTIVE(crtc_vdisplay - 1) |
+		       VTOTAL(crtc_vtotal - 1));
+	intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder),
+		       VBLANK_START(crtc_vblank_start - 1) |
+		       VBLANK_END(crtc_vblank_end - 1));
+	intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder),
+		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
+		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
+	intel_de_write(display, TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
+		       crtc_state->set_context_latency);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 660ec513626e..53a44f505dd2 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -6,9 +6,12 @@
 #ifndef __INTEL_CMTG_H__
 #define __INTEL_CMTG_H__
 
+#include <linux/types.h>
+
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 8a767b659a23..60714a2080c7 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -20,4 +20,13 @@
 #define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
 #define  CMTG_ENABLE			REG_BIT(31)
 
+#define TRANS_HTOTAL_CMTG(trans)	_MMIO(0x6F000 + (trans) * 0x100)
+#define TRANS_HBLANK_CMTG(trans)	_MMIO(0x6F004 + (trans) * 0x100)
+#define TRANS_HSYNC_CMTG(trans)		_MMIO(0x6F008 + (trans) * 0x100)
+#define TRANS_VTOTAL_CMTG(trans)	_MMIO(0x6F00C + (trans) * 0x100)
+#define TRANS_VBLANK_CMTG(trans)	_MMIO(0x6F010 + (trans) * 0x100)
+#define TRANS_VSYNC_CMTG(trans)		_MMIO(0x6F014 + (trans) * 0x100)
+
+#define TRANS_SET_CTX_LATENCY_CMTG(trans)	_MMIO(0x6F07C + (trans) * 0x100)
+
 #endif /* __INTEL_CMTG_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b18ce0c36a64..82e4d0524d54 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -61,6 +61,7 @@
 #include "intel_casf.h"
 #include "intel_cdclk.h"
 #include "intel_clock_gating.h"
+#include "intel_cmtg.h"
 #include "intel_color.h"
 #include "intel_crt.h"
 #include "intel_crtc.h"
@@ -2775,6 +2776,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 		intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
 			       crtc_state->min_hblank);
 	}
+
+	intel_cmtg_set_timings(crtc_state, false);
 }
 
 static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
@@ -2836,6 +2839,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 		       VACTIVE(crtc_vdisplay - 1) |
 		       VTOTAL(crtc_vtotal - 1));
 
+	intel_cmtg_set_timings(crtc_state, true);
 	intel_vrr_set_fixed_rr_timings(crtc_state);
 	intel_vrr_transcoder_enable(crtc_state);
 }
-- 
2.29.0

[PATCH v3 04/12] drm/i915/cmtg: program VRR registers of CMTG

[Animesh Manna]

Program the VRR registers of CMTG, as the VRR timing generator
will always be enabled for NVL.

v2: Use sw state instead of reading from hardware. [Jani]
v3: Program cmtg vrr control and timing registers along with
vrr transcoder registers.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 33 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  2 ++
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  5 +++
 drivers/gpu/drm/i915/display/intel_vrr.c      |  5 +++
 4 files changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index e0f12925f5c2..038927b8721b 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -16,6 +16,7 @@
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
+#include "intel_vrr_regs.h"
 
 /**
  * DOC: Common Primary Timing Generator (CMTG)
@@ -269,3 +270,35 @@ void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
 	intel_de_write(display, TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
 		       crtc_state->set_context_latency);
 }
+
+void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_de_write(display, TRANS_VRR_VMIN_CMTG(cpu_transcoder), crtc_state->vrr.vmin);
+	intel_de_write(display, TRANS_VRR_VMAX_CMTG(cpu_transcoder), crtc_state->vrr.vmax);
+	intel_de_write(display, TRANS_VRR_FLIPLINE_CMTG(cpu_transcoder), crtc_state->vrr.flipline);
+}
+
+void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 vrr_ctl;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	vrr_ctl = VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN |
+		  XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
+
+	/* TODO: The code below may need to be revisited once CMRR is enabled */
+	if (crtc_state->cmrr.enable)
+		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
+
+	intel_de_write(display, TRANS_VRR_CTL_CMTG(cpu_transcoder), vrr_ctl);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 53a44f505dd2..c92e3a62ff0d 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,8 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 60714a2080c7..3e94151e4daf 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -29,4 +29,9 @@
 
 #define TRANS_SET_CTX_LATENCY_CMTG(trans)	_MMIO(0x6F07C + (trans) * 0x100)
 
+#define TRANS_VRR_CTL_CMTG(trans)	_MMIO(0x6F420 + (trans) * 0x100)
+#define TRANS_VRR_VMAX_CMTG(trans)	_MMIO(0x6F424 + (trans) * 0x100)
+#define TRANS_VRR_VMIN_CMTG(trans)	_MMIO(0x6F434 + (trans) * 0x100)
+#define TRANS_VRR_FLIPLINE_CMTG(trans)	_MMIO(0x6F438 + (trans) * 0x100)
+
 #endif /* __INTEL_CMTG_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 8a957804cb97..0242ff0d04f0 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -7,6 +7,7 @@
 #include <drm/drm_print.h>
 
 #include "intel_alpm.h"
+#include "intel_cmtg.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
@@ -324,6 +325,8 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
 		       intel_vrr_fixed_rr_hw_vmax(crtc_state) - 1);
 	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
 		       intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);
+
+	intel_cmtg_set_vrr_timings(crtc_state);
 }
 
 static
@@ -922,6 +925,8 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
+
+	intel_cmtg_set_vrr_ctl(crtc_state);
 }
 
 static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
-- 
2.29.0

[PATCH v3 05/12] drm/i915/cmtg: set transcoder mn for CMTG

[Animesh Manna]

Program CMTG link M/N.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c      | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h      |  1 +
 drivers/gpu/drm/i915/display/intel_cmtg_regs.h |  3 +++
 drivers/gpu/drm/i915/display/intel_display.c   |  1 +
 4 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 038927b8721b..0d4a8550be24 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -302,3 +302,16 @@ void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
 
 	intel_de_write(display, TRANS_VRR_CTL_CMTG(cpu_transcoder), vrr_ctl);
 }
+
+void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	const struct intel_link_m_n *m_n = &crtc_state->dp_m_n;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_de_write(display, TRANS_LINKM1_CMTG(cpu_transcoder), m_n->link_m);
+	intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder), m_n->link_n);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index c92e3a62ff0d..6796eb727eef 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 3e94151e4daf..b91498ef5274 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -29,6 +29,9 @@
 
 #define TRANS_SET_CTX_LATENCY_CMTG(trans)	_MMIO(0x6F07C + (trans) * 0x100)
 
+#define TRANS_LINKM1_CMTG(trans)	_MMIO(0x6F040 + (trans) * 0x100)
+#define TRANS_LINKN1_CMTG(trans)	_MMIO(0x6F044 + (trans) * 0x100)
+
 #define TRANS_VRR_CTL_CMTG(trans)	_MMIO(0x6F420 + (trans) * 0x100)
 #define TRANS_VRR_VMAX_CMTG(trans)	_MMIO(0x6F424 + (trans) * 0x100)
 #define TRANS_VRR_VMIN_CMTG(trans)	_MMIO(0x6F434 + (trans) * 0x100)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 82e4d0524d54..35f5fd02c815 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1636,6 +1636,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
 					       &crtc_state->dp_m2_n2);
 	}
+	intel_cmtg_set_m_n(crtc_state);
 
 	intel_set_transcoder_timings(crtc_state);
 
-- 
2.29.0

[PATCH v3 06/12] drm/i915/cmtg: add hook to enable CMTG with sync to port

[Animesh Manna]

Add a hook to enable CMTG by programming CMTG CTL with Sync to Port.
When CMTG starts running, the Sync to Port bit will be cleared. Add
a wait to check its running status and trigger WARN_ON() on timeout.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 27 ++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  4 +--
 3 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 0d4a8550be24..a802bf3e52e9 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -104,11 +104,11 @@ static void intel_cmtg_get_config(struct intel_display *display,
 {
 	u32 val;
 
-	val = intel_de_read(display, TRANS_CMTG_CTL_A);
+	val = intel_de_read(display, TRANS_CMTG_CTL(TRANSCODER_A));
 	cmtg_config->cmtg_a_enable = val & CMTG_ENABLE;
 
 	if (intel_cmtg_has_cmtg_b(display)) {
-		val = intel_de_read(display, TRANS_CMTG_CTL_B);
+		val = intel_de_read(display, TRANS_CMTG_CTL(TRANSCODER_B));
 		cmtg_config->cmtg_b_enable = val & CMTG_ENABLE;
 	}
 
@@ -141,14 +141,14 @@ static void intel_cmtg_disable(struct intel_display *display,
 
 	if (cmtg_config->cmtg_a_enable) {
 		drm_dbg_kms(display->drm, "Disabling CMTG A\n");
-		intel_de_rmw(display, TRANS_CMTG_CTL_A, CMTG_ENABLE, 0);
+		intel_de_rmw(display, TRANS_CMTG_CTL(TRANSCODER_A), CMTG_ENABLE, 0);
 		clk_sel_clr |= CMTG_CLK_SEL_A_MASK;
 		clk_sel_set |= CMTG_CLK_SEL_A_DISABLED;
 	}
 
 	if (cmtg_config->cmtg_b_enable) {
 		drm_dbg_kms(display->drm, "Disabling CMTG B\n");
-		intel_de_rmw(display, TRANS_CMTG_CTL_B, CMTG_ENABLE, 0);
+		intel_de_rmw(display, TRANS_CMTG_CTL(TRANSCODER_B), CMTG_ENABLE, 0);
 		clk_sel_clr |= CMTG_CLK_SEL_B_MASK;
 		clk_sel_set |= CMTG_CLK_SEL_B_DISABLED;
 	}
@@ -315,3 +315,22 @@ void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
 	intel_de_write(display, TRANS_LINKM1_CMTG(cpu_transcoder), m_n->link_m);
 	intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder), m_n->link_n);
 }
+
+void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 cmtg_ctl;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	cmtg_ctl = CMTG_SYNC_TO_PORT | CMTG_ENABLE;
+
+	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), 0, cmtg_ctl);
+	if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder),
+				       CMTG_SYNC_TO_PORT, 50)) {
+		drm_WARN(display->drm, 1, "CMTG: %s enable timeout\n",
+			 transcoder_name(cpu_transcoder));
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 6796eb727eef..64ff6a19948a 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index b91498ef5274..93bdf8e23546 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -16,9 +16,9 @@
 #define CMTG_CLK_SELECT_PHYB_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x6)
 #define CMTG_CLK_SEL_B_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
 
-#define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
-#define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
+#define TRANS_CMTG_CTL(trans)		_MMIO(0x6fa88 + (trans) * 0x100)
 #define  CMTG_ENABLE			REG_BIT(31)
+#define  CMTG_SYNC_TO_PORT		REG_BIT(29)
 
 #define TRANS_HTOTAL_CMTG(trans)	_MMIO(0x6F000 + (trans) * 0x100)
 #define TRANS_HBLANK_CMTG(trans)	_MMIO(0x6F004 + (trans) * 0x100)
-- 
2.29.0

[PATCH v3 07/12] drm/i915/cmtg: add a hook to enable ddi for CMTG

[Animesh Manna]

Program DDI_FUNC_CTL2 to configure the eDP transcoder as secondary
to the CMTG transcoder.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h |  1 +
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index a802bf3e52e9..703828339d4d 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -334,3 +334,16 @@ void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
 			 transcoder_name(cpu_transcoder));
 	}
 }
+
+void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
+
+	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 64ff6a19948a..12abbafa7d08 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
-- 
2.29.0

[PATCH v3 08/12] drm/i915/cmtg: modify existing hook to disable CMTG

[Animesh Manna]

From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>

Earlier cmtg_disable() used to disable all instances of CMTG
which cannot handle individual request for specific CMTG instance.
Introduce cmtg_disable_all() which will disable all cmtg instances
and cmtg_disable() only disable specific instance.

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 36 +++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  1 +
 3 files changed, 35 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 703828339d4d..a6ac87fd552e 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -125,8 +125,8 @@ static bool intel_cmtg_disable_requires_modeset(struct intel_display *display,
 	return cmtg_config->trans_a_secondary || cmtg_config->trans_b_secondary;
 }
 
-static void intel_cmtg_disable(struct intel_display *display,
-			       struct intel_cmtg_config *cmtg_config)
+static void intel_cmtg_disable_all(struct intel_display *display,
+				   struct intel_cmtg_config *cmtg_config)
 {
 	u32 clk_sel_clr = 0;
 	u32 clk_sel_set = 0;
@@ -157,6 +157,36 @@ static void intel_cmtg_disable(struct intel_display *display,
 		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
 }
 
+void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 val;
+
+	if (!HAS_DC3CO(display))
+		return;
+
+	if (cpu_transcoder != TRANSCODER_A && cpu_transcoder != TRANSCODER_B)
+		return;
+
+	val = intel_de_read(display, TRANS_VRR_CTL_CMTG(cpu_transcoder));
+	val &= ~VRR_CTL_VRR_ENABLE;
+	val &= ~VRR_CTL_FLIP_LINE_EN;
+	intel_de_write(display, TRANS_VRR_CTL_CMTG(cpu_transcoder), val);
+
+	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
+		     PORT_SYNC_MODE_ENABLE, 0);
+
+	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_ENABLE, 0);
+
+	if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_STATE, 50)) {
+		drm_WARN(display->drm, 1, "CMTG: %s disable timeout\n",
+			 transcoder_name(cpu_transcoder));
+		return;
+	}
+
+	drm_dbg_kms(display->drm, "CMTG: %s disabled\n", transcoder_name(cpu_transcoder));
+}
 /*
  * Read out CMTG configuration and, on platforms that allow disabling it without
  * a modeset, do it.
@@ -184,7 +214,7 @@ void intel_cmtg_sanitize(struct intel_display *display)
 	if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))
 		return;
 
-	intel_cmtg_disable(display, &cmtg_config);
+	intel_cmtg_disable_all(display, &cmtg_config);
 }
 
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 12abbafa7d08..79785afccc51 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_disable(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 93bdf8e23546..d53891f3e3c3 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -19,6 +19,7 @@
 #define TRANS_CMTG_CTL(trans)		_MMIO(0x6fa88 + (trans) * 0x100)
 #define  CMTG_ENABLE			REG_BIT(31)
 #define  CMTG_SYNC_TO_PORT		REG_BIT(29)
+#define  CMTG_STATE			REG_BIT(23)
 
 #define TRANS_HTOTAL_CMTG(trans)	_MMIO(0x6F000 + (trans) * 0x100)
 #define TRANS_HBLANK_CMTG(trans)	_MMIO(0x6F004 + (trans) * 0x100)
-- 
2.29.0

[PATCH v3 09/12] drm/i915/cmtg: Add trigger to enable/disable cmtg

[Animesh Manna]

Enable CMTG with fixed refresh rate mode and with dynamic
dc state enabled.

Disable CMTG with transcoder disable or if there is a transition
to vrr mode from fixed refresh rate mode.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c          |  5 ++++-
 drivers/gpu/drm/i915/display/intel_display.c       | 10 ++++++++++
 drivers/gpu/drm/i915/display/intel_display_types.h |  4 ++++
 3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index a6ac87fd552e..fff299e1acfb 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -160,6 +160,7 @@ static void intel_cmtg_disable_all(struct intel_display *display,
 void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 val;
 
@@ -184,7 +185,7 @@ void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
 			 transcoder_name(cpu_transcoder));
 		return;
 	}
-
+	crtc->cmtg.enabled = false;
 	drm_dbg_kms(display->drm, "CMTG: %s disabled\n", transcoder_name(cpu_transcoder));
 }
 /*
@@ -368,6 +369,7 @@ void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
 void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	if (!intel_cmtg_is_allowed(crtc_state))
@@ -375,5 +377,6 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 
 	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
 
+	crtc->cmtg.enabled = true;
 	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 35f5fd02c815..baf4d640bfbf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1080,6 +1080,11 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
 		intel_alpm_lobf_enable(new_crtc_state);
 
 	intel_psr_post_plane_update(state, crtc);
+
+	if (!crtc->cmtg.enabled && intel_vrr_is_fixed_rr(new_crtc_state)) {
+		intel_cmtg_enable_sync(new_crtc_state);
+		intel_cmtg_enable_ddi(new_crtc_state);
+	}
 }
 
 static void intel_post_plane_update_after_readout(struct intel_atomic_state *state,
@@ -1793,6 +1798,8 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
 	struct intel_crtc *pipe_crtc;
 	int i;
 
+	if (crtc->cmtg.enabled)
+		intel_cmtg_disable(old_crtc_state);
 	/*
 	 * FIXME collapse everything to one hook.
 	 * Need care with mst->ddi interactions.
@@ -6917,6 +6924,9 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	if (intel_crtc_needs_fastset(new_crtc_state) &&
 	    old_crtc_state->inherited)
 		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
+
+	if (crtc->cmtg.enabled && intel_crtc_vrr_enabling(state, crtc))
+		intel_cmtg_disable(new_crtc_state);
 }
 
 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8a92ea4f1438..b4c3d8537a99 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1574,6 +1574,10 @@ struct intel_crtc {
 #endif
 
 	bool vblank_psr_notify;
+
+	struct {
+		bool enabled;
+	} cmtg;
 };
 
 struct intel_plane_error {
-- 
2.29.0

[PATCH v3 10/12] drm/i915/cmtg: Add CMTG interrupt handling

[Animesh Manna]

Add support fot vsync, vblank, and delayed vlank interrupts of
CMTG which are part of DE port interrupt.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 37 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  2 +
 drivers/gpu/drm/i915/display/intel_display.c  |  5 ++-
 .../gpu/drm/i915/display/intel_display_irq.c  | 12 ++++++
 .../gpu/drm/i915/display/intel_display_regs.h |  6 +++
 5 files changed, 61 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index fff299e1acfb..35d39f2fb86b 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -13,6 +13,7 @@
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_device.h"
+#include "intel_display_irq.h"
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
@@ -380,3 +381,39 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 	crtc->cmtg.enabled = true;
 	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
 }
+
+void intel_cmtg_mask_interrupt(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 interrupt_mask = 0;
+
+	if (!HAS_DC3CO(display))
+		return;
+
+	if (cpu_transcoder == TRANSCODER_A)
+		interrupt_mask = CMTG_VBLANK_A | CMTG_DELAYED_VBLANK_A | CMTG_VSYNC_A;
+
+	if (cpu_transcoder == TRANSCODER_B)
+		interrupt_mask = CMTG_VBLANK_B | CMTG_DELAYED_VBLANK_B | CMTG_VSYNC_B;
+
+	bdw_update_port_irq(display, interrupt_mask, 0);
+}
+
+void intel_cmtg_unmask_interrupt(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 enabled_irq_mask = 0;
+
+	if (!HAS_DC3CO(display))
+		return;
+
+	if (cpu_transcoder == TRANSCODER_A)
+		enabled_irq_mask = CMTG_VBLANK_A | CMTG_DELAYED_VBLANK_A | CMTG_VSYNC_A;
+
+	if (cpu_transcoder == TRANSCODER_B)
+		enabled_irq_mask = CMTG_VBLANK_B | CMTG_DELAYED_VBLANK_B | CMTG_VSYNC_B;
+
+	bdw_update_port_irq(display, 0, enabled_irq_mask);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 79785afccc51..0a6fad9635ab 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -21,5 +21,7 @@ void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_mask_interrupt(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_unmask_interrupt(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CMTG_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index baf4d640bfbf..6febf569889f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1084,6 +1084,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
 	if (!crtc->cmtg.enabled && intel_vrr_is_fixed_rr(new_crtc_state)) {
 		intel_cmtg_enable_sync(new_crtc_state);
 		intel_cmtg_enable_ddi(new_crtc_state);
+		intel_cmtg_unmask_interrupt(new_crtc_state);
 	}
 }
 
@@ -6925,8 +6926,10 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	    old_crtc_state->inherited)
 		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
 
-	if (crtc->cmtg.enabled && intel_crtc_vrr_enabling(state, crtc))
+	if (crtc->cmtg.enabled && intel_crtc_vrr_enabling(state, crtc)) {
 		intel_cmtg_disable(new_crtc_state);
+		intel_cmtg_mask_interrupt(new_crtc_state);
+	}
 }
 
 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 70c1bba7c0a8..95e6523b32d9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1467,6 +1467,18 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
 				found = true;
 			}
 
+			if (DISPLAY_VER(display) > 30) {
+				if (iir & (CMTG_VBLANK_A | CMTG_VSYNC_A | CMTG_DELAYED_VBLANK_A)) {
+					intel_handle_vblank(display, PIPE_A);
+					found = true;
+				}
+
+				if (iir & (CMTG_VBLANK_B | CMTG_VSYNC_B | CMTG_DELAYED_VBLANK_B)) {
+					intel_handle_vblank(display, PIPE_B);
+					found = true;
+				}
+			}
+
 			if (DISPLAY_VER(display) >= 11) {
 				u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 4746e9ebd920..5838338f495a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1427,6 +1427,12 @@
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
 #define  DSI1_TE			(1 << 24)
 #define  DSI0_TE			(1 << 23)
+#define  CMTG_VSYNC_B			(1 << 19)
+#define  CMTG_DELAYED_VBLANK_B		(1 << 18)
+#define  CMTG_VBLANK_B			(1 << 17)
+#define  CMTG_VSYNC_A			(1 << 16)
+#define  CMTG_DELAYED_VBLANK_A		(1 << 15)
+#define  CMTG_VBLANK_A			(1 << 14)
 #define  GEN8_DE_PORT_HOTPLUG(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
 #define  BXT_DE_PORT_HOTPLUG_MASK	(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
 					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
-- 
2.29.0

[PATCH v3 11/12] drm/i915/cmtg: set dc3co_enable flag for lobf/psr2/pr-alpm

[Animesh Manna]

Set the flag in specific scenarios such as LOBF/PSR2/PR-ALPM,
where DC3CO enablement will be targeted, allowing CMTG to be programmed.
DC3CO enablement will be implemented in a separate patch series.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fbb5e2f9c241..53982d1e39dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7327,6 +7327,7 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
 				 struct intel_crtc_state *crtc_state,
 				 struct drm_connector_state *conn_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	int ret;
 
@@ -7338,6 +7339,13 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
 
 	intel_alpm_lobf_compute_config_late(intel_dp, crtc_state);
 
+	if (HAS_DC3CO(display) && intel_dp_is_edp(intel_dp) &&
+	    (crtc_state->has_lobf || crtc_state->has_sel_update ||
+	     crtc_state->has_panel_replay))
+		crtc_state->dc3co.enable = true;
+	else
+		crtc_state->dc3co.enable = false;
+
 	return 0;
 }
 
-- 
2.29.0

[PATCH v3 12/12] drm/i915/cmtg: disable CMTG if dc3co entry condition not met

[Animesh Manna]

DC3co entry condition can change dymamically and disable
CMTG if entry condition is not met for DC3co.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6febf569889f..f20d5ebe06ed 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1029,6 +1029,15 @@ static bool intel_crtc_lobf_disabling(const struct intel_crtc_state *old_crtc_st
 		 (new_crtc_state->update_lrr || new_crtc_state->update_m_n));
 }
 
+static bool intel_crtc_dc3co_disabling(const struct intel_crtc_state *old_crtc_state,
+				       const struct intel_crtc_state *new_crtc_state)
+{
+	if (!old_crtc_state->hw.active)
+		return false;
+
+	return is_disabling(dc3co.enable, old_crtc_state, new_crtc_state);
+}
+
 #undef is_disabling
 #undef is_enabling
 
@@ -6926,7 +6935,8 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	    old_crtc_state->inherited)
 		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
 
-	if (crtc->cmtg.enabled && intel_crtc_vrr_enabling(state, crtc)) {
+	if (crtc->cmtg.enabled && (intel_crtc_vrr_enabling(state, crtc) ||
+				   intel_crtc_dc3co_disabling(old_crtc_state, new_crtc_state))) {
 		intel_cmtg_disable(new_crtc_state);
 		intel_cmtg_mask_interrupt(new_crtc_state);
 	}
-- 
2.29.0

✓ CI.KUnit: success for CMTG enablement (rev4)

[Patchwork]

== Series Details ==

Series: CMTG enablement (rev4)
URL   : https://patchwork.freedesktop.org/series/157663/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[16:09:27] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:09:31] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[16:10:09] Starting KUnit Kernel (1/1)...
[16:10:09] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:10:09] ================== guc_buf (11 subtests) ===================
[16:10:09] [PASSED] test_smallest
[16:10:09] [PASSED] test_largest
[16:10:09] [PASSED] test_granular
[16:10:09] [PASSED] test_unique
[16:10:09] [PASSED] test_overlap
[16:10:09] [PASSED] test_reusable
[16:10:09] [PASSED] test_too_big
[16:10:09] [PASSED] test_flush
[16:10:09] [PASSED] test_lookup
[16:10:09] [PASSED] test_data
[16:10:09] [PASSED] test_class
[16:10:09] ===================== [PASSED] guc_buf =====================
[16:10:09] =================== guc_dbm (7 subtests) ===================
[16:10:09] [PASSED] test_empty
[16:10:09] [PASSED] test_default
[16:10:09] ======================== test_size  ========================
[16:10:09] [PASSED] 4
[16:10:09] [PASSED] 8
[16:10:09] [PASSED] 32
[16:10:09] [PASSED] 256
[16:10:09] ==================== [PASSED] test_size ====================
[16:10:09] ======================= test_reuse  ========================
[16:10:09] [PASSED] 4
[16:10:09] [PASSED] 8
[16:10:09] [PASSED] 32
[16:10:09] [PASSED] 256
[16:10:09] =================== [PASSED] test_reuse ====================
[16:10:09] =================== test_range_overlap  ====================
[16:10:09] [PASSED] 4
[16:10:09] [PASSED] 8
[16:10:09] [PASSED] 32
[16:10:09] [PASSED] 256
[16:10:09] =============== [PASSED] test_range_overlap ================
[16:10:09] =================== test_range_compact  ====================
[16:10:09] [PASSED] 4
[16:10:09] [PASSED] 8
[16:10:09] [PASSED] 32
[16:10:09] [PASSED] 256
[16:10:09] =============== [PASSED] test_range_compact ================
[16:10:09] ==================== test_range_spare  =====================
[16:10:09] [PASSED] 4
[16:10:09] [PASSED] 8
[16:10:09] [PASSED] 32
[16:10:09] [PASSED] 256
[16:10:09] ================ [PASSED] test_range_spare =================
[16:10:09] ===================== [PASSED] guc_dbm =====================
[16:10:09] =================== guc_idm (6 subtests) ===================
[16:10:09] [PASSED] bad_init
[16:10:09] [PASSED] no_init
[16:10:09] [PASSED] init_fini
[16:10:09] [PASSED] check_used
[16:10:09] [PASSED] check_quota
[16:10:09] [PASSED] check_all
[16:10:09] ===================== [PASSED] guc_idm =====================
[16:10:09] ================== no_relay (3 subtests) ===================
[16:10:09] [PASSED] xe_drops_guc2pf_if_not_ready
[16:10:09] [PASSED] xe_drops_guc2vf_if_not_ready
[16:10:09] [PASSED] xe_rejects_send_if_not_ready
[16:10:09] ==================== [PASSED] no_relay =====================
[16:10:09] ================== pf_relay (14 subtests) ==================
[16:10:09] [PASSED] pf_rejects_guc2pf_too_short
[16:10:09] [PASSED] pf_rejects_guc2pf_too_long
[16:10:09] [PASSED] pf_rejects_guc2pf_no_payload
[16:10:09] [PASSED] pf_fails_no_payload
[16:10:09] [PASSED] pf_fails_bad_origin
[16:10:09] [PASSED] pf_fails_bad_type
[16:10:09] [PASSED] pf_txn_reports_error
[16:10:09] [PASSED] pf_txn_sends_pf2guc
[16:10:09] [PASSED] pf_sends_pf2guc
[16:10:09] [SKIPPED] pf_loopback_nop
[16:10:09] [SKIPPED] pf_loopback_echo
[16:10:09] [SKIPPED] pf_loopback_fail
[16:10:09] [SKIPPED] pf_loopback_busy
[16:10:09] [SKIPPED] pf_loopback_retry
[16:10:09] ==================== [PASSED] pf_relay =====================
[16:10:09] ================== vf_relay (3 subtests) ===================
[16:10:09] [PASSED] vf_rejects_guc2vf_too_short
[16:10:09] [PASSED] vf_rejects_guc2vf_too_long
[16:10:09] [PASSED] vf_rejects_guc2vf_no_payload
[16:10:09] ==================== [PASSED] vf_relay =====================
[16:10:09] ================ pf_gt_config (9 subtests) =================
[16:10:09] [PASSED] fair_contexts_1vf
[16:10:09] [PASSED] fair_doorbells_1vf
[16:10:09] [PASSED] fair_ggtt_1vf
[16:10:09] ====================== fair_vram_1vf  ======================
[16:10:09] [PASSED] 3.50 GiB
[16:10:09] [PASSED] 11.5 GiB
[16:10:09] [PASSED] 15.5 GiB
[16:10:09] [PASSED] 31.5 GiB
[16:10:09] [PASSED] 63.5 GiB
[16:10:09] [PASSED] 1.91 GiB
[16:10:09] ================== [PASSED] fair_vram_1vf ==================
[16:10:09] ================ fair_vram_1vf_admin_only  =================
[16:10:09] [PASSED] 3.50 GiB
[16:10:09] [PASSED] 11.5 GiB
[16:10:09] [PASSED] 15.5 GiB
[16:10:09] [PASSED] 31.5 GiB
[16:10:09] [PASSED] 63.5 GiB
[16:10:09] [PASSED] 1.91 GiB
[16:10:09] ============ [PASSED] fair_vram_1vf_admin_only =============
[16:10:09] ====================== fair_contexts  ======================
[16:10:09] [PASSED] 1 VF
[16:10:09] [PASSED] 2 VFs
[16:10:09] [PASSED] 3 VFs
[16:10:09] [PASSED] 4 VFs
[16:10:09] [PASSED] 5 VFs
[16:10:09] [PASSED] 6 VFs
[16:10:09] [PASSED] 7 VFs
[16:10:09] [PASSED] 8 VFs
[16:10:09] [PASSED] 9 VFs
[16:10:09] [PASSED] 10 VFs
[16:10:09] [PASSED] 11 VFs
[16:10:09] [PASSED] 12 VFs
[16:10:09] [PASSED] 13 VFs
[16:10:09] [PASSED] 14 VFs
[16:10:09] [PASSED] 15 VFs
[16:10:09] [PASSED] 16 VFs
[16:10:09] [PASSED] 17 VFs
[16:10:09] [PASSED] 18 VFs
[16:10:09] [PASSED] 19 VFs
[16:10:09] [PASSED] 20 VFs
[16:10:09] [PASSED] 21 VFs
[16:10:09] [PASSED] 22 VFs
[16:10:09] [PASSED] 23 VFs
[16:10:09] [PASSED] 24 VFs
[16:10:09] [PASSED] 25 VFs
[16:10:09] [PASSED] 26 VFs
[16:10:09] [PASSED] 27 VFs
[16:10:09] [PASSED] 28 VFs
[16:10:09] [PASSED] 29 VFs
[16:10:09] [PASSED] 30 VFs
[16:10:09] [PASSED] 31 VFs
[16:10:09] [PASSED] 32 VFs
[16:10:09] [PASSED] 33 VFs
[16:10:09] [PASSED] 34 VFs
[16:10:09] [PASSED] 35 VFs
[16:10:09] [PASSED] 36 VFs
[16:10:09] [PASSED] 37 VFs
[16:10:09] [PASSED] 38 VFs
[16:10:09] [PASSED] 39 VFs
[16:10:09] [PASSED] 40 VFs
[16:10:09] [PASSED] 41 VFs
[16:10:09] [PASSED] 42 VFs
[16:10:09] [PASSED] 43 VFs
[16:10:09] [PASSED] 44 VFs
[16:10:09] [PASSED] 45 VFs
[16:10:09] [PASSED] 46 VFs
[16:10:09] [PASSED] 47 VFs
[16:10:09] [PASSED] 48 VFs
[16:10:09] [PASSED] 49 VFs
[16:10:09] [PASSED] 50 VFs
[16:10:09] [PASSED] 51 VFs
[16:10:09] [PASSED] 52 VFs
[16:10:09] [PASSED] 53 VFs
[16:10:09] [PASSED] 54 VFs
[16:10:09] [PASSED] 55 VFs
[16:10:09] [PASSED] 56 VFs
[16:10:09] [PASSED] 57 VFs
[16:10:09] [PASSED] 58 VFs
[16:10:09] [PASSED] 59 VFs
[16:10:09] [PASSED] 60 VFs
[16:10:09] [PASSED] 61 VFs
[16:10:09] [PASSED] 62 VFs
[16:10:09] [PASSED] 63 VFs
[16:10:09] ================== [PASSED] fair_contexts ==================
[16:10:09] ===================== fair_doorbells  ======================
[16:10:09] [PASSED] 1 VF
[16:10:09] [PASSED] 2 VFs
[16:10:09] [PASSED] 3 VFs
[16:10:09] [PASSED] 4 VFs
[16:10:09] [PASSED] 5 VFs
[16:10:09] [PASSED] 6 VFs
[16:10:09] [PASSED] 7 VFs
[16:10:09] [PASSED] 8 VFs
[16:10:09] [PASSED] 9 VFs
[16:10:09] [PASSED] 10 VFs
[16:10:09] [PASSED] 11 VFs
[16:10:09] [PASSED] 12 VFs
[16:10:09] [PASSED] 13 VFs
[16:10:09] [PASSED] 14 VFs
[16:10:09] [PASSED] 15 VFs
[16:10:09] [PASSED] 16 VFs
[16:10:09] [PASSED] 17 VFs
[16:10:09] [PASSED] 18 VFs
[16:10:09] [PASSED] 19 VFs
[16:10:09] [PASSED] 20 VFs
[16:10:09] [PASSED] 21 VFs
[16:10:09] [PASSED] 22 VFs
[16:10:09] [PASSED] 23 VFs
[16:10:09] [PASSED] 24 VFs
[16:10:09] [PASSED] 25 VFs
[16:10:09] [PASSED] 26 VFs
[16:10:09] [PASSED] 27 VFs
[16:10:09] [PASSED] 28 VFs
[16:10:09] [PASSED] 29 VFs
[16:10:09] [PASSED] 30 VFs
[16:10:09] [PASSED] 31 VFs
[16:10:09] [PASSED] 32 VFs
[16:10:09] [PASSED] 33 VFs
[16:10:09] [PASSED] 34 VFs
[16:10:09] [PASSED] 35 VFs
[16:10:09] [PASSED] 36 VFs
[16:10:09] [PASSED] 37 VFs
[16:10:09] [PASSED] 38 VFs
[16:10:09] [PASSED] 39 VFs
[16:10:09] [PASSED] 40 VFs
[16:10:09] [PASSED] 41 VFs
[16:10:09] [PASSED] 42 VFs
[16:10:09] [PASSED] 43 VFs
[16:10:09] [PASSED] 44 VFs
[16:10:09] [PASSED] 45 VFs
[16:10:09] [PASSED] 46 VFs
[16:10:09] [PASSED] 47 VFs
[16:10:09] [PASSED] 48 VFs
[16:10:09] [PASSED] 49 VFs
[16:10:09] [PASSED] 50 VFs
[16:10:09] [PASSED] 51 VFs
[16:10:09] [PASSED] 52 VFs
[16:10:09] [PASSED] 53 VFs
[16:10:09] [PASSED] 54 VFs
[16:10:09] [PASSED] 55 VFs
[16:10:09] [PASSED] 56 VFs
[16:10:09] [PASSED] 57 VFs
[16:10:09] [PASSED] 58 VFs
[16:10:09] [PASSED] 59 VFs
[16:10:09] [PASSED] 60 VFs
[16:10:09] [PASSED] 61 VFs
[16:10:09] [PASSED] 62 VFs
[16:10:09] [PASSED] 63 VFs
[16:10:09] ================= [PASSED] fair_doorbells ==================
[16:10:09] ======================== fair_ggtt  ========================
[16:10:09] [PASSED] 1 VF
[16:10:09] [PASSED] 2 VFs
[16:10:09] [PASSED] 3 VFs
[16:10:09] [PASSED] 4 VFs
[16:10:09] [PASSED] 5 VFs
[16:10:09] [PASSED] 6 VFs
[16:10:09] [PASSED] 7 VFs
[16:10:09] [PASSED] 8 VFs
[16:10:09] [PASSED] 9 VFs
[16:10:09] [PASSED] 10 VFs
[16:10:09] [PASSED] 11 VFs
[16:10:09] [PASSED] 12 VFs
[16:10:09] [PASSED] 13 VFs
[16:10:09] [PASSED] 14 VFs
[16:10:09] [PASSED] 15 VFs
[16:10:09] [PASSED] 16 VFs
[16:10:09] [PASSED] 17 VFs
[16:10:09] [PASSED] 18 VFs
[16:10:09] [PASSED] 19 VFs
[16:10:09] [PASSED] 20 VFs
[16:10:09] [PASSED] 21 VFs
[16:10:09] [PASSED] 22 VFs
[16:10:09] [PASSED] 23 VFs
[16:10:09] [PASSED] 24 VFs
[16:10:09] [PASSED] 25 VFs
[16:10:09] [PASSED] 26 VFs
[16:10:09] [PASSED] 27 VFs
[16:10:09] [PASSED] 28 VFs
[16:10:09] [PASSED] 29 VFs
[16:10:09] [PASSED] 30 VFs
[16:10:09] [PASSED] 31 VFs
[16:10:09] [PASSED] 32 VFs
[16:10:09] [PASSED] 33 VFs
[16:10:09] [PASSED] 34 VFs
[16:10:09] [PASSED] 35 VFs
[16:10:09] [PASSED] 36 VFs
[16:10:09] [PASSED] 37 VFs
[16:10:09] [PASSED] 38 VFs
[16:10:09] [PASSED] 39 VFs
[16:10:09] [PASSED] 40 VFs
[16:10:09] [PASSED] 41 VFs
[16:10:09] [PASSED] 42 VFs
[16:10:09] [PASSED] 43 VFs
[16:10:09] [PASSED] 44 VFs
[16:10:09] [PASSED] 45 VFs
[16:10:09] [PASSED] 46 VFs
[16:10:09] [PASSED] 47 VFs
[16:10:09] [PASSED] 48 VFs
[16:10:09] [PASSED] 49 VFs
[16:10:09] [PASSED] 50 VFs
[16:10:09] [PASSED] 51 VFs
[16:10:09] [PASSED] 52 VFs
[16:10:09] [PASSED] 53 VFs
[16:10:09] [PASSED] 54 VFs
[16:10:09] [PASSED] 55 VFs
[16:10:09] [PASSED] 56 VFs
[16:10:09] [PASSED] 57 VFs
[16:10:09] [PASSED] 58 VFs
[16:10:09] [PASSED] 59 VFs
[16:10:09] [PASSED] 60 VFs
[16:10:09] [PASSED] 61 VFs
[16:10:09] [PASSED] 62 VFs
[16:10:09] [PASSED] 63 VFs
[16:10:09] ==================== [PASSED] fair_ggtt ====================
[16:10:09] ======================== fair_vram  ========================
[16:10:09] [PASSED] 1 VF
[16:10:09] [PASSED] 2 VFs
[16:10:09] [PASSED] 3 VFs
[16:10:09] [PASSED] 4 VFs
[16:10:09] [PASSED] 5 VFs
[16:10:09] [PASSED] 6 VFs
[16:10:09] [PASSED] 7 VFs
[16:10:09] [PASSED] 8 VFs
[16:10:09] [PASSED] 9 VFs
[16:10:09] [PASSED] 10 VFs
[16:10:09] [PASSED] 11 VFs
[16:10:09] [PASSED] 12 VFs
[16:10:09] [PASSED] 13 VFs
[16:10:09] [PASSED] 14 VFs
[16:10:09] [PASSED] 15 VFs
[16:10:09] [PASSED] 16 VFs
[16:10:09] [PASSED] 17 VFs
[16:10:09] [PASSED] 18 VFs
[16:10:09] [PASSED] 19 VFs
[16:10:09] [PASSED] 20 VFs
[16:10:09] [PASSED] 21 VFs
[16:10:09] [PASSED] 22 VFs
[16:10:09] [PASSED] 23 VFs
[16:10:09] [PASSED] 24 VFs
[16:10:09] [PASSED] 25 VFs
[16:10:09] [PASSED] 26 VFs
[16:10:09] [PASSED] 27 VFs
[16:10:09] [PASSED] 28 VFs
[16:10:09] [PASSED] 29 VFs
[16:10:09] [PASSED] 30 VFs
[16:10:09] [PASSED] 31 VFs
[16:10:09] [PASSED] 32 VFs
[16:10:09] [PASSED] 33 VFs
[16:10:09] [PASSED] 34 VFs
[16:10:09] [PASSED] 35 VFs
[16:10:09] [PASSED] 36 VFs
[16:10:09] [PASSED] 37 VFs
[16:10:09] [PASSED] 38 VFs
[16:10:09] [PASSED] 39 VFs
[16:10:09] [PASSED] 40 VFs
[16:10:09] [PASSED] 41 VFs
[16:10:09] [PASSED] 42 VFs
[16:10:09] [PASSED] 43 VFs
[16:10:09] [PASSED] 44 VFs
[16:10:09] [PASSED] 45 VFs
[16:10:09] [PASSED] 46 VFs
[16:10:09] [PASSED] 47 VFs
[16:10:09] [PASSED] 48 VFs
[16:10:09] [PASSED] 49 VFs
[16:10:09] [PASSED] 50 VFs
[16:10:09] [PASSED] 51 VFs
[16:10:09] [PASSED] 52 VFs
[16:10:09] [PASSED] 53 VFs
[16:10:09] [PASSED] 54 VFs
[16:10:09] [PASSED] 55 VFs
[16:10:09] [PASSED] 56 VFs
[16:10:09] [PASSED] 57 VFs
[16:10:09] [PASSED] 58 VFs
[16:10:09] [PASSED] 59 VFs
[16:10:09] [PASSED] 60 VFs
[16:10:09] [PASSED] 61 VFs
[16:10:09] [PASSED] 62 VFs
[16:10:09] [PASSED] 63 VFs
[16:10:09] ==================== [PASSED] fair_vram ====================
[16:10:09] ================== [PASSED] pf_gt_config ===================
[16:10:09] ===================== lmtt (1 subtest) =====================
[16:10:09] ======================== test_ops  =========================
[16:10:09] [PASSED] 2-level
[16:10:09] [PASSED] multi-level
[16:10:09] ==================== [PASSED] test_ops =====================
[16:10:09] ====================== [PASSED] lmtt =======================
[16:10:09] ================= pf_service (11 subtests) =================
[16:10:09] [PASSED] pf_negotiate_any
[16:10:09] [PASSED] pf_negotiate_base_match
[16:10:09] [PASSED] pf_negotiate_base_newer
[16:10:09] [PASSED] pf_negotiate_base_next
[16:10:09] [SKIPPED] pf_negotiate_base_older
[16:10:09] [PASSED] pf_negotiate_base_prev
[16:10:09] [PASSED] pf_negotiate_latest_match
[16:10:09] [PASSED] pf_negotiate_latest_newer
[16:10:09] [PASSED] pf_negotiate_latest_next
[16:10:09] [SKIPPED] pf_negotiate_latest_older
[16:10:09] [SKIPPED] pf_negotiate_latest_prev
[16:10:09] =================== [PASSED] pf_service ====================
[16:10:09] ================= xe_guc_g2g (2 subtests) ==================
[16:10:09] ============== xe_live_guc_g2g_kunit_default  ==============
[16:10:09] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[16:10:09] ============== xe_live_guc_g2g_kunit_allmem  ===============
[16:10:09] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[16:10:09] =================== [SKIPPED] xe_guc_g2g ===================
[16:10:09] =================== xe_mocs (2 subtests) ===================
[16:10:09] ================ xe_live_mocs_kernel_kunit  ================
[16:10:09] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[16:10:09] ================ xe_live_mocs_reset_kunit  =================
[16:10:09] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[16:10:09] ==================== [SKIPPED] xe_mocs =====================
[16:10:09] ================= xe_migrate (2 subtests) ==================
[16:10:09] ================= xe_migrate_sanity_kunit  =================
[16:10:09] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[16:10:09] ================== xe_validate_ccs_kunit  ==================
[16:10:09] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[16:10:09] =================== [SKIPPED] xe_migrate ===================
[16:10:09] ================== xe_dma_buf (1 subtest) ==================
[16:10:09] ==================== xe_dma_buf_kunit  =====================
[16:10:09] ================ [SKIPPED] xe_dma_buf_kunit ================
[16:10:09] =================== [SKIPPED] xe_dma_buf ===================
[16:10:09] ================= xe_bo_shrink (1 subtest) =================
[16:10:09] =================== xe_bo_shrink_kunit  ====================
[16:10:09] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[16:10:09] ================== [SKIPPED] xe_bo_shrink ==================
[16:10:09] ==================== xe_bo (2 subtests) ====================
[16:10:09] ================== xe_ccs_migrate_kunit  ===================
[16:10:09] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[16:10:09] ==================== xe_bo_evict_kunit  ====================
[16:10:09] =============== [SKIPPED] xe_bo_evict_kunit ================
[16:10:09] ===================== [SKIPPED] xe_bo ======================
[16:10:09] ==================== args (13 subtests) ====================
[16:10:09] [PASSED] count_args_test
[16:10:09] [PASSED] call_args_example
[16:10:09] [PASSED] call_args_test
[16:10:09] [PASSED] drop_first_arg_example
[16:10:09] [PASSED] drop_first_arg_test
[16:10:09] [PASSED] first_arg_example
[16:10:09] [PASSED] first_arg_test
[16:10:09] [PASSED] last_arg_example
[16:10:09] [PASSED] last_arg_test
[16:10:09] [PASSED] pick_arg_example
[16:10:09] [PASSED] if_args_example
[16:10:09] [PASSED] if_args_test
[16:10:09] [PASSED] sep_comma_example
[16:10:09] ====================== [PASSED] args =======================
[16:10:09] =================== xe_pci (3 subtests) ====================
[16:10:09] ==================== check_graphics_ip  ====================
[16:10:09] [PASSED] 12.00 Xe_LP
[16:10:09] [PASSED] 12.10 Xe_LP+
[16:10:09] [PASSED] 12.55 Xe_HPG
[16:10:09] [PASSED] 12.60 Xe_HPC
[16:10:09] [PASSED] 12.70 Xe_LPG
[16:10:09] [PASSED] 12.71 Xe_LPG
[16:10:09] [PASSED] 12.74 Xe_LPG+
[16:10:09] [PASSED] 20.01 Xe2_HPG
[16:10:09] [PASSED] 20.02 Xe2_HPG
[16:10:09] [PASSED] 20.04 Xe2_LPG
[16:10:09] [PASSED] 30.00 Xe3_LPG
[16:10:09] [PASSED] 30.01 Xe3_LPG
[16:10:09] [PASSED] 30.03 Xe3_LPG
[16:10:09] [PASSED] 30.04 Xe3_LPG
[16:10:09] [PASSED] 30.05 Xe3_LPG
[16:10:09] [PASSED] 35.10 Xe3p_LPG
[16:10:09] [PASSED] 35.11 Xe3p_XPC
[16:10:09] ================ [PASSED] check_graphics_ip ================
[16:10:09] ===================== check_media_ip  ======================
[16:10:09] [PASSED] 12.00 Xe_M
[16:10:09] [PASSED] 12.55 Xe_HPM
[16:10:09] [PASSED] 13.00 Xe_LPM+
[16:10:09] [PASSED] 13.01 Xe2_HPM
[16:10:09] [PASSED] 20.00 Xe2_LPM
[16:10:09] [PASSED] 30.00 Xe3_LPM
[16:10:09] [PASSED] 30.02 Xe3_LPM
[16:10:09] [PASSED] 35.00 Xe3p_LPM
[16:10:09] [PASSED] 35.03 Xe3p_HPM
[16:10:09] ================= [PASSED] check_media_ip ==================
[16:10:09] =================== check_platform_desc  ===================
[16:10:09] [PASSED] 0x9A60 (TIGERLAKE)
[16:10:09] [PASSED] 0x9A68 (TIGERLAKE)
[16:10:09] [PASSED] 0x9A70 (TIGERLAKE)
[16:10:09] [PASSED] 0x9A40 (TIGERLAKE)
[16:10:09] [PASSED] 0x9A49 (TIGERLAKE)
[16:10:09] [PASSED] 0x9A59 (TIGERLAKE)
[16:10:09] [PASSED] 0x9A78 (TIGERLAKE)
[16:10:09] [PASSED] 0x9AC0 (TIGERLAKE)
[16:10:09] [PASSED] 0x9AC9 (TIGERLAKE)
[16:10:09] [PASSED] 0x9AD9 (TIGERLAKE)
[16:10:09] [PASSED] 0x9AF8 (TIGERLAKE)
[16:10:09] [PASSED] 0x4C80 (ROCKETLAKE)
[16:10:09] [PASSED] 0x4C8A (ROCKETLAKE)
[16:10:09] [PASSED] 0x4C8B (ROCKETLAKE)
[16:10:09] [PASSED] 0x4C8C (ROCKETLAKE)
[16:10:09] [PASSED] 0x4C90 (ROCKETLAKE)
[16:10:09] [PASSED] 0x4C9A (ROCKETLAKE)
[16:10:09] [PASSED] 0x4680 (ALDERLAKE_S)
[16:10:09] [PASSED] 0x4682 (ALDERLAKE_S)
[16:10:09] [PASSED] 0x4688 (ALDERLAKE_S)
[16:10:09] [PASSED] 0x468A (ALDERLAKE_S)
[16:10:09] [PASSED] 0x468B (ALDERLAKE_S)
[16:10:09] [PASSED] 0x4690 (ALDERLAKE_S)
[16:10:09] [PASSED] 0x4692 (ALDERLAKE_S)
[16:10:09] [PASSED] 0x4693 (ALDERLAKE_S)
[16:10:09] [PASSED] 0x46A0 (ALDERLAKE_P)
[16:10:09] [PASSED] 0x46A1 (ALDERLAKE_P)
[16:10:09] [PASSED] 0x46A2 (ALDERLAKE_P)
[16:10:09] [PASSED] 0x46A3 (ALDERLAKE_P)
[16:10:09] [PASSED] 0x46A6 (ALDERLAKE_P)
[16:10:09] [PASSED] 0x46A8 (ALDERLAKE_P)
[16:10:09] [PASSED] 0x46AA (ALDERLAKE_P)
[16:10:09] [PASSED] 0x462A (ALDERLAKE_P)
[16:10:09] [PASSED] 0x4626 (ALDERLAKE_P)
[16:10:09] [PASSED] 0x4628 (ALDERLAKE_P)
[16:10:09] [PASSED] 0x46B0 (ALDERLAKE_P)
[16:10:09] [PASSED] 0x46B1 (ALDERLAKE_P)
[16:10:09] [PASSED] 0x46B2 (ALDERLAKE_P)
[16:10:09] [PASSED] 0x46B3 (ALDERLAKE_P)
[16:10:09] [PASSED] 0x46C0 (ALDERLAKE_P)
[16:10:09] [PASSED] 0x46C1 (ALDERLAKE_P)
[16:10:09] [PASSED] 0x46C2 (ALDERLAKE_P)
[16:10:09] [PASSED] 0x46C3 (ALDERLAKE_P)
[16:10:09] [PASSED] 0x46D0 (ALDERLAKE_N)
[16:10:09] [PASSED] 0x46D1 (ALDERLAKE_N)
[16:10:09] [PASSED] 0x46D2 (ALDERLAKE_N)
[16:10:09] [PASSED] 0x46D3 (ALDERLAKE_N)
[16:10:09] [PASSED] 0x46D4 (ALDERLAKE_N)
[16:10:09] [PASSED] 0xA721 (ALDERLAKE_P)
[16:10:09] [PASSED] 0xA7A1 (ALDERLAKE_P)
[16:10:09] [PASSED] 0xA7A9 (ALDERLAKE_P)
[16:10:09] [PASSED] 0xA7AC (ALDERLAKE_P)
[16:10:09] [PASSED] 0xA7AD (ALDERLAKE_P)
[16:10:09] [PASSED] 0xA720 (ALDERLAKE_P)
[16:10:09] [PASSED] 0xA7A0 (ALDERLAKE_P)
[16:10:09] [PASSED] 0xA7A8 (ALDERLAKE_P)
[16:10:09] [PASSED] 0xA7AA (ALDERLAKE_P)
[16:10:09] [PASSED] 0xA7AB (ALDERLAKE_P)
[16:10:09] [PASSED] 0xA780 (ALDERLAKE_S)
[16:10:09] [PASSED] 0xA781 (ALDERLAKE_S)
[16:10:09] [PASSED] 0xA782 (ALDERLAKE_S)
[16:10:09] [PASSED] 0xA783 (ALDERLAKE_S)
[16:10:09] [PASSED] 0xA788 (ALDERLAKE_S)
[16:10:09] [PASSED] 0xA789 (ALDERLAKE_S)
[16:10:09] [PASSED] 0xA78A (ALDERLAKE_S)
[16:10:09] [PASSED] 0xA78B (ALDERLAKE_S)
[16:10:09] [PASSED] 0x4905 (DG1)
[16:10:09] [PASSED] 0x4906 (DG1)
[16:10:09] [PASSED] 0x4907 (DG1)
[16:10:09] [PASSED] 0x4908 (DG1)
[16:10:09] [PASSED] 0x4909 (DG1)
[16:10:09] [PASSED] 0x56C0 (DG2)
[16:10:09] [PASSED] 0x56C2 (DG2)
[16:10:09] [PASSED] 0x56C1 (DG2)
[16:10:09] [PASSED] 0x7D51 (METEORLAKE)
[16:10:09] [PASSED] 0x7DD1 (METEORLAKE)
[16:10:09] [PASSED] 0x7D41 (METEORLAKE)
[16:10:09] [PASSED] 0x7D67 (METEORLAKE)
[16:10:09] [PASSED] 0xB640 (METEORLAKE)
[16:10:09] [PASSED] 0x56A0 (DG2)
[16:10:09] [PASSED] 0x56A1 (DG2)
[16:10:09] [PASSED] 0x56A2 (DG2)
[16:10:09] [PASSED] 0x56BE (DG2)
[16:10:09] [PASSED] 0x56BF (DG2)
[16:10:09] [PASSED] 0x5690 (DG2)
[16:10:09] [PASSED] 0x5691 (DG2)
[16:10:09] [PASSED] 0x5692 (DG2)
[16:10:09] [PASSED] 0x56A5 (DG2)
[16:10:09] [PASSED] 0x56A6 (DG2)
[16:10:09] [PASSED] 0x56B0 (DG2)
[16:10:09] [PASSED] 0x56B1 (DG2)
[16:10:09] [PASSED] 0x56BA (DG2)
[16:10:09] [PASSED] 0x56BB (DG2)
[16:10:09] [PASSED] 0x56BC (DG2)
[16:10:09] [PASSED] 0x56BD (DG2)
[16:10:09] [PASSED] 0x5693 (DG2)
[16:10:09] [PASSED] 0x5694 (DG2)
[16:10:09] [PASSED] 0x5695 (DG2)
[16:10:09] [PASSED] 0x56A3 (DG2)
[16:10:09] [PASSED] 0x56A4 (DG2)
[16:10:09] [PASSED] 0x56B2 (DG2)
[16:10:09] [PASSED] 0x56B3 (DG2)
[16:10:09] [PASSED] 0x5696 (DG2)
[16:10:09] [PASSED] 0x5697 (DG2)
[16:10:09] [PASSED] 0xB69 (PVC)
[16:10:09] [PASSED] 0xB6E (PVC)
[16:10:09] [PASSED] 0xBD4 (PVC)
[16:10:09] [PASSED] 0xBD5 (PVC)
[16:10:09] [PASSED] 0xBD6 (PVC)
[16:10:09] [PASSED] 0xBD7 (PVC)
[16:10:09] [PASSED] 0xBD8 (PVC)
[16:10:09] [PASSED] 0xBD9 (PVC)
[16:10:09] [PASSED] 0xBDA (PVC)
[16:10:09] [PASSED] 0xBDB (PVC)
[16:10:09] [PASSED] 0xBE0 (PVC)
[16:10:09] [PASSED] 0xBE1 (PVC)
[16:10:09] [PASSED] 0xBE5 (PVC)
[16:10:09] [PASSED] 0x7D40 (METEORLAKE)
[16:10:09] [PASSED] 0x7D45 (METEORLAKE)
[16:10:09] [PASSED] 0x7D55 (METEORLAKE)
[16:10:09] [PASSED] 0x7D60 (METEORLAKE)
[16:10:09] [PASSED] 0x7DD5 (METEORLAKE)
[16:10:09] [PASSED] 0x6420 (LUNARLAKE)
[16:10:09] [PASSED] 0x64A0 (LUNARLAKE)
[16:10:09] [PASSED] 0x64B0 (LUNARLAKE)
[16:10:09] [PASSED] 0xE202 (BATTLEMAGE)
[16:10:09] [PASSED] 0xE209 (BATTLEMAGE)
[16:10:09] [PASSED] 0xE20B (BATTLEMAGE)
[16:10:09] [PASSED] 0xE20C (BATTLEMAGE)
[16:10:09] [PASSED] 0xE20D (BATTLEMAGE)
[16:10:09] [PASSED] 0xE210 (BATTLEMAGE)
[16:10:09] [PASSED] 0xE211 (BATTLEMAGE)
[16:10:09] [PASSED] 0xE212 (BATTLEMAGE)
[16:10:09] [PASSED] 0xE216 (BATTLEMAGE)
[16:10:09] [PASSED] 0xE220 (BATTLEMAGE)
[16:10:09] [PASSED] 0xE221 (BATTLEMAGE)
[16:10:09] [PASSED] 0xE222 (BATTLEMAGE)
[16:10:09] [PASSED] 0xE223 (BATTLEMAGE)
[16:10:09] [PASSED] 0xB080 (PANTHERLAKE)
[16:10:09] [PASSED] 0xB081 (PANTHERLAKE)
[16:10:09] [PASSED] 0xB082 (PANTHERLAKE)
[16:10:09] [PASSED] 0xB083 (PANTHERLAKE)
[16:10:09] [PASSED] 0xB084 (PANTHERLAKE)
[16:10:09] [PASSED] 0xB085 (PANTHERLAKE)
[16:10:09] [PASSED] 0xB086 (PANTHERLAKE)
[16:10:09] [PASSED] 0xB087 (PANTHERLAKE)
[16:10:09] [PASSED] 0xB08F (PANTHERLAKE)
[16:10:09] [PASSED] 0xB090 (PANTHERLAKE)
[16:10:09] [PASSED] 0xB0A0 (PANTHERLAKE)
[16:10:09] [PASSED] 0xB0B0 (PANTHERLAKE)
[16:10:09] [PASSED] 0xFD80 (PANTHERLAKE)
[16:10:09] [PASSED] 0xFD81 (PANTHERLAKE)
[16:10:09] [PASSED] 0xD740 (NOVALAKE_S)
[16:10:09] [PASSED] 0xD741 (NOVALAKE_S)
[16:10:09] [PASSED] 0xD742 (NOVALAKE_S)
[16:10:09] [PASSED] 0xD743 (NOVALAKE_S)
[16:10:09] [PASSED] 0xD744 (NOVALAKE_S)
[16:10:09] [PASSED] 0xD745 (NOVALAKE_S)
[16:10:09] [PASSED] 0x674C (CRESCENTISLAND)
[16:10:09] [PASSED] 0xD750 (NOVALAKE_P)
[16:10:09] [PASSED] 0xD751 (NOVALAKE_P)
[16:10:09] [PASSED] 0xD752 (NOVALAKE_P)
[16:10:09] [PASSED] 0xD753 (NOVALAKE_P)
[16:10:09] [PASSED] 0xD754 (NOVALAKE_P)
[16:10:09] [PASSED] 0xD755 (NOVALAKE_P)
[16:10:09] [PASSED] 0xD756 (NOVALAKE_P)
[16:10:09] [PASSED] 0xD757 (NOVALAKE_P)
[16:10:09] [PASSED] 0xD75F (NOVALAKE_P)
[16:10:09] =============== [PASSED] check_platform_desc ===============
[16:10:09] ===================== [PASSED] xe_pci ======================
[16:10:09] =================== xe_rtp (2 subtests) ====================
[16:10:09] =============== xe_rtp_process_to_sr_tests  ================
[16:10:09] [PASSED] coalesce-same-reg
[16:10:09] [PASSED] no-match-no-add
[16:10:09] [PASSED] match-or
[16:10:09] [PASSED] match-or-xfail
[16:10:09] [PASSED] no-match-no-add-multiple-rules
[16:10:09] [PASSED] two-regs-two-entries
[16:10:09] [PASSED] clr-one-set-other
[16:10:09] [PASSED] set-field
[16:10:09] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[16:10:09] [PASSED] conflict-not-disjoint
[16:10:09] [PASSED] conflict-reg-type
[16:10:09] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[16:10:09] ================== xe_rtp_process_tests  ===================
[16:10:09] [PASSED] active1
[16:10:09] [PASSED] active2
[16:10:09] [PASSED] active-inactive
[16:10:09] [PASSED] inactive-active
[16:10:09] [PASSED] inactive-1st_or_active-inactive
[16:10:09] [PASSED] inactive-2nd_or_active-inactive
[16:10:09] [PASSED] inactive-last_or_active-inactive
[16:10:09] [PASSED] inactive-no_or_active-inactive
[16:10:09] ============== [PASSED] xe_rtp_process_tests ===============
[16:10:09] ===================== [PASSED] xe_rtp ======================
[16:10:09] ==================== xe_wa (1 subtest) =====================
[16:10:09] ======================== xe_wa_gt  =========================
[16:10:09] [PASSED] TIGERLAKE B0
[16:10:09] [PASSED] DG1 A0
[16:10:09] [PASSED] DG1 B0
[16:10:09] [PASSED] ALDERLAKE_S A0
[16:10:09] [PASSED] ALDERLAKE_S B0
[16:10:09] [PASSED] ALDERLAKE_S C0
[16:10:09] [PASSED] ALDERLAKE_S D0
[16:10:09] [PASSED] ALDERLAKE_P A0
[16:10:09] [PASSED] ALDERLAKE_P B0
[16:10:09] [PASSED] ALDERLAKE_P C0
[16:10:09] [PASSED] ALDERLAKE_S RPLS D0
[16:10:09] [PASSED] ALDERLAKE_P RPLU E0
[16:10:09] [PASSED] DG2 G10 C0
[16:10:09] [PASSED] DG2 G11 B1
[16:10:09] [PASSED] DG2 G12 A1
[16:10:09] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[16:10:09] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[16:10:09] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[16:10:09] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[16:10:09] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[16:10:09] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[16:10:09] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[16:10:09] ==================== [PASSED] xe_wa_gt =====================
[16:10:09] ====================== [PASSED] xe_wa ======================
[16:10:09] ============================================================
[16:10:09] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[16:10:09] Elapsed time: 42.406s total, 4.340s configuring, 37.398s building, 0.628s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[16:10:09] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:10:11] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[16:10:40] Starting KUnit Kernel (1/1)...
[16:10:40] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:10:40] ============ drm_test_pick_cmdline (2 subtests) ============
[16:10:40] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[16:10:40] =============== drm_test_pick_cmdline_named  ===============
[16:10:40] [PASSED] NTSC
[16:10:40] [PASSED] NTSC-J
[16:10:40] [PASSED] PAL
[16:10:40] [PASSED] PAL-M
[16:10:40] =========== [PASSED] drm_test_pick_cmdline_named ===========
[16:10:40] ============== [PASSED] drm_test_pick_cmdline ==============
[16:10:40] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[16:10:40] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[16:10:40] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[16:10:40] =========== drm_validate_clone_mode (2 subtests) ===========
[16:10:40] ============== drm_test_check_in_clone_mode  ===============
[16:10:40] [PASSED] in_clone_mode
[16:10:40] [PASSED] not_in_clone_mode
[16:10:40] ========== [PASSED] drm_test_check_in_clone_mode ===========
[16:10:40] =============== drm_test_check_valid_clones  ===============
[16:10:40] [PASSED] not_in_clone_mode
[16:10:40] [PASSED] valid_clone
[16:10:40] [PASSED] invalid_clone
[16:10:40] =========== [PASSED] drm_test_check_valid_clones ===========
[16:10:40] ============= [PASSED] drm_validate_clone_mode =============
[16:10:40] ============= drm_validate_modeset (1 subtest) =============
[16:10:40] [PASSED] drm_test_check_connector_changed_modeset
[16:10:40] ============== [PASSED] drm_validate_modeset ===============
[16:10:40] ====== drm_test_bridge_get_current_state (2 subtests) ======
[16:10:40] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[16:10:40] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[16:10:40] ======== [PASSED] drm_test_bridge_get_current_state ========
[16:10:40] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[16:10:40] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[16:10:40] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[16:10:40] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[16:10:40] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[16:10:40] ============== drm_bridge_alloc (2 subtests) ===============
[16:10:40] [PASSED] drm_test_drm_bridge_alloc_basic
[16:10:40] [PASSED] drm_test_drm_bridge_alloc_get_put
[16:10:40] ================ [PASSED] drm_bridge_alloc =================
[16:10:40] ============= drm_cmdline_parser (40 subtests) =============
[16:10:40] [PASSED] drm_test_cmdline_force_d_only
[16:10:40] [PASSED] drm_test_cmdline_force_D_only_dvi
[16:10:40] [PASSED] drm_test_cmdline_force_D_only_hdmi
[16:10:40] [PASSED] drm_test_cmdline_force_D_only_not_digital
[16:10:40] [PASSED] drm_test_cmdline_force_e_only
[16:10:40] [PASSED] drm_test_cmdline_res
[16:10:40] [PASSED] drm_test_cmdline_res_vesa
[16:10:40] [PASSED] drm_test_cmdline_res_vesa_rblank
[16:10:40] [PASSED] drm_test_cmdline_res_rblank
[16:10:40] [PASSED] drm_test_cmdline_res_bpp
[16:10:40] [PASSED] drm_test_cmdline_res_refresh
[16:10:40] [PASSED] drm_test_cmdline_res_bpp_refresh
[16:10:40] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[16:10:40] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[16:10:40] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[16:10:40] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[16:10:40] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[16:10:40] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[16:10:40] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[16:10:40] [PASSED] drm_test_cmdline_res_margins_force_on
[16:10:40] [PASSED] drm_test_cmdline_res_vesa_margins
[16:10:40] [PASSED] drm_test_cmdline_name
[16:10:40] [PASSED] drm_test_cmdline_name_bpp
[16:10:40] [PASSED] drm_test_cmdline_name_option
[16:10:40] [PASSED] drm_test_cmdline_name_bpp_option
[16:10:40] [PASSED] drm_test_cmdline_rotate_0
[16:10:40] [PASSED] drm_test_cmdline_rotate_90
[16:10:40] [PASSED] drm_test_cmdline_rotate_180
[16:10:40] [PASSED] drm_test_cmdline_rotate_270
[16:10:40] [PASSED] drm_test_cmdline_hmirror
[16:10:40] [PASSED] drm_test_cmdline_vmirror
[16:10:40] [PASSED] drm_test_cmdline_margin_options
[16:10:40] [PASSED] drm_test_cmdline_multiple_options
[16:10:40] [PASSED] drm_test_cmdline_bpp_extra_and_option
[16:10:40] [PASSED] drm_test_cmdline_extra_and_option
[16:10:40] [PASSED] drm_test_cmdline_freestanding_options
[16:10:40] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[16:10:40] [PASSED] drm_test_cmdline_panel_orientation
[16:10:40] ================ drm_test_cmdline_invalid  =================
[16:10:40] [PASSED] margin_only
[16:10:40] [PASSED] interlace_only
[16:10:40] [PASSED] res_missing_x
[16:10:40] [PASSED] res_missing_y
[16:10:40] [PASSED] res_bad_y
[16:10:40] [PASSED] res_missing_y_bpp
[16:10:40] [PASSED] res_bad_bpp
[16:10:40] [PASSED] res_bad_refresh
[16:10:40] [PASSED] res_bpp_refresh_force_on_off
[16:10:40] [PASSED] res_invalid_mode
[16:10:40] [PASSED] res_bpp_wrong_place_mode
[16:10:40] [PASSED] name_bpp_refresh
[16:10:40] [PASSED] name_refresh
[16:10:40] [PASSED] name_refresh_wrong_mode
[16:10:40] [PASSED] name_refresh_invalid_mode
[16:10:40] [PASSED] rotate_multiple
[16:10:40] [PASSED] rotate_invalid_val
[16:10:40] [PASSED] rotate_truncated
[16:10:40] [PASSED] invalid_option
[16:10:40] [PASSED] invalid_tv_option
[16:10:40] [PASSED] truncated_tv_option
[16:10:40] ============ [PASSED] drm_test_cmdline_invalid =============
[16:10:40] =============== drm_test_cmdline_tv_options  ===============
[16:10:40] [PASSED] NTSC
[16:10:40] [PASSED] NTSC_443
[16:10:40] [PASSED] NTSC_J
[16:10:40] [PASSED] PAL
[16:10:40] [PASSED] PAL_M
[16:10:40] [PASSED] PAL_N
[16:10:40] [PASSED] SECAM
[16:10:40] [PASSED] MONO_525
[16:10:40] [PASSED] MONO_625
[16:10:40] =========== [PASSED] drm_test_cmdline_tv_options ===========
[16:10:40] =============== [PASSED] drm_cmdline_parser ================
[16:10:40] ========== drmm_connector_hdmi_init (20 subtests) ==========
[16:10:40] [PASSED] drm_test_connector_hdmi_init_valid
[16:10:40] [PASSED] drm_test_connector_hdmi_init_bpc_8
[16:10:40] [PASSED] drm_test_connector_hdmi_init_bpc_10
[16:10:40] [PASSED] drm_test_connector_hdmi_init_bpc_12
[16:10:40] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[16:10:40] [PASSED] drm_test_connector_hdmi_init_bpc_null
[16:10:40] [PASSED] drm_test_connector_hdmi_init_formats_empty
[16:10:40] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[16:10:40] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[16:10:40] [PASSED] supported_formats=0x9 yuv420_allowed=1
[16:10:40] [PASSED] supported_formats=0x9 yuv420_allowed=0
[16:10:40] [PASSED] supported_formats=0x3 yuv420_allowed=1
[16:10:40] [PASSED] supported_formats=0x3 yuv420_allowed=0
[16:10:40] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[16:10:40] [PASSED] drm_test_connector_hdmi_init_null_ddc
[16:10:40] [PASSED] drm_test_connector_hdmi_init_null_product
[16:10:40] [PASSED] drm_test_connector_hdmi_init_null_vendor
[16:10:40] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[16:10:40] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[16:10:40] [PASSED] drm_test_connector_hdmi_init_product_valid
[16:10:40] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[16:10:40] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[16:10:40] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[16:10:40] ========= drm_test_connector_hdmi_init_type_valid  =========
[16:10:40] [PASSED] HDMI-A
[16:10:40] [PASSED] HDMI-B
[16:10:40] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[16:10:40] ======== drm_test_connector_hdmi_init_type_invalid  ========
[16:10:40] [PASSED] Unknown
[16:10:40] [PASSED] VGA
[16:10:40] [PASSED] DVI-I
[16:10:40] [PASSED] DVI-D
[16:10:40] [PASSED] DVI-A
[16:10:40] [PASSED] Composite
[16:10:40] [PASSED] SVIDEO
[16:10:40] [PASSED] LVDS
[16:10:40] [PASSED] Component
[16:10:40] [PASSED] DIN
[16:10:40] [PASSED] DP
[16:10:40] [PASSED] TV
[16:10:40] [PASSED] eDP
[16:10:40] [PASSED] Virtual
[16:10:40] [PASSED] DSI
[16:10:40] [PASSED] DPI
[16:10:40] [PASSED] Writeback
[16:10:40] [PASSED] SPI
[16:10:40] [PASSED] USB
[16:10:40] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[16:10:40] ============ [PASSED] drmm_connector_hdmi_init =============
[16:10:40] ============= drmm_connector_init (3 subtests) =============
[16:10:40] [PASSED] drm_test_drmm_connector_init
[16:10:40] [PASSED] drm_test_drmm_connector_init_null_ddc
[16:10:40] ========= drm_test_drmm_connector_init_type_valid  =========
[16:10:40] [PASSED] Unknown
[16:10:40] [PASSED] VGA
[16:10:40] [PASSED] DVI-I
[16:10:40] [PASSED] DVI-D
[16:10:40] [PASSED] DVI-A
[16:10:40] [PASSED] Composite
[16:10:40] [PASSED] SVIDEO
[16:10:40] [PASSED] LVDS
[16:10:40] [PASSED] Component
[16:10:40] [PASSED] DIN
[16:10:40] [PASSED] DP
[16:10:40] [PASSED] HDMI-A
[16:10:40] [PASSED] HDMI-B
[16:10:40] [PASSED] TV
[16:10:40] [PASSED] eDP
[16:10:40] [PASSED] Virtual
[16:10:40] [PASSED] DSI
[16:10:40] [PASSED] DPI
[16:10:40] [PASSED] Writeback
[16:10:40] [PASSED] SPI
[16:10:40] [PASSED] USB
[16:10:40] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[16:10:40] =============== [PASSED] drmm_connector_init ===============
[16:10:40] ========= drm_connector_dynamic_init (6 subtests) ==========
[16:10:40] [PASSED] drm_test_drm_connector_dynamic_init
[16:10:40] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[16:10:40] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[16:10:40] [PASSED] drm_test_drm_connector_dynamic_init_properties
[16:10:40] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[16:10:40] [PASSED] Unknown
[16:10:40] [PASSED] VGA
[16:10:40] [PASSED] DVI-I
[16:10:40] [PASSED] DVI-D
[16:10:40] [PASSED] DVI-A
[16:10:40] [PASSED] Composite
[16:10:40] [PASSED] SVIDEO
[16:10:40] [PASSED] LVDS
[16:10:40] [PASSED] Component
[16:10:40] [PASSED] DIN
[16:10:40] [PASSED] DP
[16:10:40] [PASSED] HDMI-A
[16:10:40] [PASSED] HDMI-B
[16:10:40] [PASSED] TV
[16:10:40] [PASSED] eDP
[16:10:40] [PASSED] Virtual
[16:10:40] [PASSED] DSI
[16:10:40] [PASSED] DPI
[16:10:40] [PASSED] Writeback
[16:10:40] [PASSED] SPI
[16:10:40] [PASSED] USB
[16:10:40] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[16:10:40] ======== drm_test_drm_connector_dynamic_init_name  =========
[16:10:40] [PASSED] Unknown
[16:10:40] [PASSED] VGA
[16:10:40] [PASSED] DVI-I
[16:10:40] [PASSED] DVI-D
[16:10:40] [PASSED] DVI-A
[16:10:40] [PASSED] Composite
[16:10:40] [PASSED] SVIDEO
[16:10:40] [PASSED] LVDS
[16:10:40] [PASSED] Component
[16:10:40] [PASSED] DIN
[16:10:40] [PASSED] DP
[16:10:40] [PASSED] HDMI-A
[16:10:40] [PASSED] HDMI-B
[16:10:40] [PASSED] TV
[16:10:40] [PASSED] eDP
[16:10:40] [PASSED] Virtual
[16:10:40] [PASSED] DSI
[16:10:40] [PASSED] DPI
[16:10:40] [PASSED] Writeback
[16:10:40] [PASSED] SPI
[16:10:40] [PASSED] USB
[16:10:40] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[16:10:40] =========== [PASSED] drm_connector_dynamic_init ============
[16:10:40] ==== drm_connector_dynamic_register_early (4 subtests) =====
[16:10:40] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[16:10:40] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[16:10:40] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[16:10:40] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[16:10:40] ====== [PASSED] drm_connector_dynamic_register_early =======
[16:10:40] ======= drm_connector_dynamic_register (7 subtests) ========
[16:10:40] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[16:10:40] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[16:10:40] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[16:10:40] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[16:10:40] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[16:10:40] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[16:10:40] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[16:10:40] ========= [PASSED] drm_connector_dynamic_register ==========
[16:10:40] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[16:10:40] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[16:10:40] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[16:10:40] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[16:10:40] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[16:10:40] ========== drm_test_get_tv_mode_from_name_valid  ===========
[16:10:40] [PASSED] NTSC
[16:10:40] [PASSED] NTSC-443
[16:10:40] [PASSED] NTSC-J
[16:10:40] [PASSED] PAL
[16:10:40] [PASSED] PAL-M
[16:10:40] [PASSED] PAL-N
[16:10:40] [PASSED] SECAM
[16:10:40] [PASSED] Mono
[16:10:40] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[16:10:40] [PASSED] drm_test_get_tv_mode_from_name_truncated
[16:10:40] ============ [PASSED] drm_get_tv_mode_from_name ============
[16:10:40] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[16:10:40] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[16:10:40] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[16:10:40] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[16:10:40] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[16:10:40] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[16:10:40] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[16:10:40] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[16:10:40] [PASSED] VIC 96
[16:10:40] [PASSED] VIC 97
[16:10:40] [PASSED] VIC 101
[16:10:40] [PASSED] VIC 102
[16:10:40] [PASSED] VIC 106
[16:10:40] [PASSED] VIC 107
[16:10:40] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[16:10:40] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[16:10:40] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[16:10:40] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[16:10:40] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[16:10:40] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[16:10:40] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[16:10:40] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[16:10:40] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[16:10:40] [PASSED] Automatic
[16:10:40] [PASSED] Full
[16:10:40] [PASSED] Limited 16:235
[16:10:40] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[16:10:40] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[16:10:40] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[16:10:40] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[16:10:40] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[16:10:40] [PASSED] RGB
[16:10:40] [PASSED] YUV 4:2:0
[16:10:40] [PASSED] YUV 4:2:2
[16:10:40] [PASSED] YUV 4:4:4
[16:10:40] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[16:10:40] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[16:10:40] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[16:10:40] ============= drm_damage_helper (21 subtests) ==============
[16:10:40] [PASSED] drm_test_damage_iter_no_damage
[16:10:40] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[16:10:40] [PASSED] drm_test_damage_iter_no_damage_src_moved
[16:10:40] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[16:10:40] [PASSED] drm_test_damage_iter_no_damage_not_visible
[16:10:40] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[16:10:40] [PASSED] drm_test_damage_iter_no_damage_no_fb
[16:10:40] [PASSED] drm_test_damage_iter_simple_damage
[16:10:40] [PASSED] drm_test_damage_iter_single_damage
[16:10:40] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[16:10:40] [PASSED] drm_test_damage_iter_single_damage_outside_src
[16:10:40] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[16:10:40] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[16:10:40] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[16:10:40] [PASSED] drm_test_damage_iter_single_damage_src_moved
[16:10:40] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[16:10:40] [PASSED] drm_test_damage_iter_damage
[16:10:40] [PASSED] drm_test_damage_iter_damage_one_intersect
[16:10:40] [PASSED] drm_test_damage_iter_damage_one_outside
[16:10:40] [PASSED] drm_test_damage_iter_damage_src_moved
[16:10:40] [PASSED] drm_test_damage_iter_damage_not_visible
[16:10:40] ================ [PASSED] drm_damage_helper ================
[16:10:40] ============== drm_dp_mst_helper (3 subtests) ==============
[16:10:40] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[16:10:40] [PASSED] Clock 154000 BPP 30 DSC disabled
[16:10:40] [PASSED] Clock 234000 BPP 30 DSC disabled
[16:10:40] [PASSED] Clock 297000 BPP 24 DSC disabled
[16:10:40] [PASSED] Clock 332880 BPP 24 DSC enabled
[16:10:40] [PASSED] Clock 324540 BPP 24 DSC enabled
[16:10:40] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[16:10:40] ============== drm_test_dp_mst_calc_pbn_div  ===============
[16:10:40] [PASSED] Link rate 2000000 lane count 4
[16:10:40] [PASSED] Link rate 2000000 lane count 2
[16:10:40] [PASSED] Link rate 2000000 lane count 1
[16:10:40] [PASSED] Link rate 1350000 lane count 4
[16:10:40] [PASSED] Link rate 1350000 lane count 2
[16:10:40] [PASSED] Link rate 1350000 lane count 1
[16:10:40] [PASSED] Link rate 1000000 lane count 4
[16:10:40] [PASSED] Link rate 1000000 lane count 2
[16:10:40] [PASSED] Link rate 1000000 lane count 1
[16:10:40] [PASSED] Link rate 810000 lane count 4
[16:10:40] [PASSED] Link rate 810000 lane count 2
[16:10:40] [PASSED] Link rate 810000 lane count 1
[16:10:40] [PASSED] Link rate 540000 lane count 4
[16:10:40] [PASSED] Link rate 540000 lane count 2
[16:10:40] [PASSED] Link rate 540000 lane count 1
[16:10:40] [PASSED] Link rate 270000 lane count 4
[16:10:40] [PASSED] Link rate 270000 lane count 2
[16:10:40] [PASSED] Link rate 270000 lane count 1
[16:10:40] [PASSED] Link rate 162000 lane count 4
[16:10:40] [PASSED] Link rate 162000 lane count 2
[16:10:40] [PASSED] Link rate 162000 lane count 1
[16:10:40] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[16:10:40] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[16:10:40] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[16:10:40] [PASSED] DP_POWER_UP_PHY with port number
[16:10:40] [PASSED] DP_POWER_DOWN_PHY with port number
[16:10:40] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[16:10:40] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[16:10:40] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[16:10:40] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[16:10:40] [PASSED] DP_QUERY_PAYLOAD with port number
[16:10:40] [PASSED] DP_QUERY_PAYLOAD with VCPI
[16:10:40] [PASSED] DP_REMOTE_DPCD_READ with port number
[16:10:40] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[16:10:40] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[16:10:40] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[16:10:40] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[16:10:40] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[16:10:40] [PASSED] DP_REMOTE_I2C_READ with port number
[16:10:40] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[16:10:40] [PASSED] DP_REMOTE_I2C_READ with transactions array
[16:10:40] [PASSED] DP_REMOTE_I2C_WRITE with port number
[16:10:40] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[16:10:40] [PASSED] DP_REMOTE_I2C_WRITE with data array
[16:10:40] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[16:10:40] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[16:10:40] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[16:10:40] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[16:10:40] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[16:10:40] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[16:10:40] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[16:10:40] ================ [PASSED] drm_dp_mst_helper ================
[16:10:40] ================== drm_exec (7 subtests) ===================
[16:10:40] [PASSED] sanitycheck
[16:10:40] [PASSED] test_lock
[16:10:40] [PASSED] test_lock_unlock
[16:10:40] [PASSED] test_duplicates
[16:10:40] [PASSED] test_prepare
[16:10:40] [PASSED] test_prepare_array
[16:10:40] [PASSED] test_multiple_loops
[16:10:40] ==================== [PASSED] drm_exec =====================
[16:10:40] =========== drm_format_helper_test (17 subtests) ===========
[16:10:40] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[16:10:40] [PASSED] single_pixel_source_buffer
[16:10:40] [PASSED] single_pixel_clip_rectangle
[16:10:40] [PASSED] well_known_colors
[16:10:40] [PASSED] destination_pitch
[16:10:40] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[16:10:40] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[16:10:40] [PASSED] single_pixel_source_buffer
[16:10:40] [PASSED] single_pixel_clip_rectangle
[16:10:40] [PASSED] well_known_colors
[16:10:40] [PASSED] destination_pitch
[16:10:40] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[16:10:40] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[16:10:40] [PASSED] single_pixel_source_buffer
[16:10:40] [PASSED] single_pixel_clip_rectangle
[16:10:40] [PASSED] well_known_colors
[16:10:40] [PASSED] destination_pitch
[16:10:40] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[16:10:40] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[16:10:40] [PASSED] single_pixel_source_buffer
[16:10:40] [PASSED] single_pixel_clip_rectangle
[16:10:40] [PASSED] well_known_colors
[16:10:40] [PASSED] destination_pitch
[16:10:40] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[16:10:40] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[16:10:40] [PASSED] single_pixel_source_buffer
[16:10:40] [PASSED] single_pixel_clip_rectangle
[16:10:40] [PASSED] well_known_colors
[16:10:40] [PASSED] destination_pitch
[16:10:40] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[16:10:40] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[16:10:40] [PASSED] single_pixel_source_buffer
[16:10:40] [PASSED] single_pixel_clip_rectangle
[16:10:40] [PASSED] well_known_colors
[16:10:40] [PASSED] destination_pitch
[16:10:40] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[16:10:40] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[16:10:40] [PASSED] single_pixel_source_buffer
[16:10:40] [PASSED] single_pixel_clip_rectangle
[16:10:40] [PASSED] well_known_colors
[16:10:40] [PASSED] destination_pitch
[16:10:40] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[16:10:40] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[16:10:40] [PASSED] single_pixel_source_buffer
[16:10:40] [PASSED] single_pixel_clip_rectangle
[16:10:40] [PASSED] well_known_colors
[16:10:40] [PASSED] destination_pitch
[16:10:40] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[16:10:40] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[16:10:40] [PASSED] single_pixel_source_buffer
[16:10:40] [PASSED] single_pixel_clip_rectangle
[16:10:40] [PASSED] well_known_colors
[16:10:40] [PASSED] destination_pitch
[16:10:40] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[16:10:40] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[16:10:40] [PASSED] single_pixel_source_buffer
[16:10:40] [PASSED] single_pixel_clip_rectangle
[16:10:40] [PASSED] well_known_colors
[16:10:40] [PASSED] destination_pitch
[16:10:40] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[16:10:40] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[16:10:40] [PASSED] single_pixel_source_buffer
[16:10:40] [PASSED] single_pixel_clip_rectangle
[16:10:40] [PASSED] well_known_colors
[16:10:40] [PASSED] destination_pitch
[16:10:40] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[16:10:40] ============== drm_test_fb_xrgb8888_to_mono  ===============
[16:10:40] [PASSED] single_pixel_source_buffer
[16:10:40] [PASSED] single_pixel_clip_rectangle
[16:10:40] [PASSED] well_known_colors
[16:10:40] [PASSED] destination_pitch
[16:10:40] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[16:10:40] ==================== drm_test_fb_swab  =====================
[16:10:40] [PASSED] single_pixel_source_buffer
[16:10:40] [PASSED] single_pixel_clip_rectangle
[16:10:40] [PASSED] well_known_colors
[16:10:40] [PASSED] destination_pitch
[16:10:40] ================ [PASSED] drm_test_fb_swab =================
[16:10:40] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[16:10:40] [PASSED] single_pixel_source_buffer
[16:10:40] [PASSED] single_pixel_clip_rectangle
[16:10:40] [PASSED] well_known_colors
[16:10:40] [PASSED] destination_pitch
[16:10:40] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[16:10:40] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[16:10:40] [PASSED] single_pixel_source_buffer
[16:10:40] [PASSED] single_pixel_clip_rectangle
[16:10:40] [PASSED] well_known_colors
[16:10:40] [PASSED] destination_pitch
[16:10:40] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[16:10:40] ================= drm_test_fb_clip_offset  =================
[16:10:40] [PASSED] pass through
[16:10:40] [PASSED] horizontal offset
[16:10:40] [PASSED] vertical offset
[16:10:40] [PASSED] horizontal and vertical offset
[16:10:40] [PASSED] horizontal offset (custom pitch)
[16:10:40] [PASSED] vertical offset (custom pitch)
[16:10:40] [PASSED] horizontal and vertical offset (custom pitch)
[16:10:40] ============= [PASSED] drm_test_fb_clip_offset =============
[16:10:40] =================== drm_test_fb_memcpy  ====================
[16:10:40] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[16:10:40] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[16:10:40] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[16:10:40] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[16:10:40] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[16:10:40] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[16:10:40] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[16:10:40] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[16:10:40] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[16:10:40] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[16:10:40] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[16:10:40] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[16:10:40] =============== [PASSED] drm_test_fb_memcpy ================
[16:10:40] ============= [PASSED] drm_format_helper_test ==============
[16:10:40] ================= drm_format (18 subtests) =================
[16:10:40] [PASSED] drm_test_format_block_width_invalid
[16:10:40] [PASSED] drm_test_format_block_width_one_plane
[16:10:40] [PASSED] drm_test_format_block_width_two_plane
[16:10:40] [PASSED] drm_test_format_block_width_three_plane
[16:10:40] [PASSED] drm_test_format_block_width_tiled
[16:10:40] [PASSED] drm_test_format_block_height_invalid
[16:10:40] [PASSED] drm_test_format_block_height_one_plane
[16:10:40] [PASSED] drm_test_format_block_height_two_plane
[16:10:40] [PASSED] drm_test_format_block_height_three_plane
[16:10:40] [PASSED] drm_test_format_block_height_tiled
[16:10:40] [PASSED] drm_test_format_min_pitch_invalid
[16:10:40] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[16:10:40] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[16:10:40] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[16:10:40] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[16:10:40] [PASSED] drm_test_format_min_pitch_two_plane
[16:10:40] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[16:10:40] [PASSED] drm_test_format_min_pitch_tiled
[16:10:40] =================== [PASSED] drm_format ====================
[16:10:40] ============== drm_framebuffer (10 subtests) ===============
[16:10:40] ========== drm_test_framebuffer_check_src_coords  ==========
[16:10:40] [PASSED] Success: source fits into fb
[16:10:40] [PASSED] Fail: overflowing fb with x-axis coordinate
[16:10:40] [PASSED] Fail: overflowing fb with y-axis coordinate
[16:10:40] [PASSED] Fail: overflowing fb with source width
[16:10:40] [PASSED] Fail: overflowing fb with source height
[16:10:40] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[16:10:40] [PASSED] drm_test_framebuffer_cleanup
[16:10:40] =============== drm_test_framebuffer_create  ===============
[16:10:40] [PASSED] ABGR8888 normal sizes
[16:10:40] [PASSED] ABGR8888 max sizes
[16:10:40] [PASSED] ABGR8888 pitch greater than min required
[16:10:40] [PASSED] ABGR8888 pitch less than min required
[16:10:40] [PASSED] ABGR8888 Invalid width
[16:10:40] [PASSED] ABGR8888 Invalid buffer handle
[16:10:40] [PASSED] No pixel format
[16:10:40] [PASSED] ABGR8888 Width 0
[16:10:40] [PASSED] ABGR8888 Height 0
[16:10:40] [PASSED] ABGR8888 Out of bound height * pitch combination
[16:10:40] [PASSED] ABGR8888 Large buffer offset
[16:10:40] [PASSED] ABGR8888 Buffer offset for inexistent plane
[16:10:40] [PASSED] ABGR8888 Invalid flag
[16:10:40] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[16:10:40] [PASSED] ABGR8888 Valid buffer modifier
[16:10:40] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[16:10:40] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[16:10:40] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[16:10:40] [PASSED] NV12 Normal sizes
[16:10:40] [PASSED] NV12 Max sizes
[16:10:40] [PASSED] NV12 Invalid pitch
[16:10:40] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[16:10:40] [PASSED] NV12 different  modifier per-plane
[16:10:40] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[16:10:40] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[16:10:40] [PASSED] NV12 Modifier for inexistent plane
[16:10:40] [PASSED] NV12 Handle for inexistent plane
[16:10:40] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[16:10:40] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[16:10:40] [PASSED] YVU420 Normal sizes
[16:10:40] [PASSED] YVU420 Max sizes
[16:10:40] [PASSED] YVU420 Invalid pitch
[16:10:40] [PASSED] YVU420 Different pitches
[16:10:40] [PASSED] YVU420 Different buffer offsets/pitches
[16:10:40] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[16:10:40] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[16:10:40] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[16:10:40] [PASSED] YVU420 Valid modifier
[16:10:40] [PASSED] YVU420 Different modifiers per plane
[16:10:40] [PASSED] YVU420 Modifier for inexistent plane
[16:10:40] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[16:10:40] [PASSED] X0L2 Normal sizes
[16:10:40] [PASSED] X0L2 Max sizes
[16:10:40] [PASSED] X0L2 Invalid pitch
[16:10:40] [PASSED] X0L2 Pitch greater than minimum required
[16:10:40] [PASSED] X0L2 Handle for inexistent plane
[16:10:40] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[16:10:40] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[16:10:40] [PASSED] X0L2 Valid modifier
[16:10:40] [PASSED] X0L2 Modifier for inexistent plane
[16:10:40] =========== [PASSED] drm_test_framebuffer_create ===========
[16:10:40] [PASSED] drm_test_framebuffer_free
[16:10:40] [PASSED] drm_test_framebuffer_init
[16:10:40] [PASSED] drm_test_framebuffer_init_bad_format
[16:10:40] [PASSED] drm_test_framebuffer_init_dev_mismatch
[16:10:40] [PASSED] drm_test_framebuffer_lookup
[16:10:40] [PASSED] drm_test_framebuffer_lookup_inexistent
[16:10:40] [PASSED] drm_test_framebuffer_modifiers_not_supported
[16:10:40] ================= [PASSED] drm_framebuffer =================
[16:10:40] ================ drm_gem_shmem (8 subtests) ================
[16:10:40] [PASSED] drm_gem_shmem_test_obj_create
[16:10:40] [PASSED] drm_gem_shmem_test_obj_create_private
[16:10:40] [PASSED] drm_gem_shmem_test_pin_pages
[16:10:40] [PASSED] drm_gem_shmem_test_vmap
[16:10:40] [PASSED] drm_gem_shmem_test_get_sg_table
[16:10:40] [PASSED] drm_gem_shmem_test_get_pages_sgt
[16:10:40] [PASSED] drm_gem_shmem_test_madvise
[16:10:40] [PASSED] drm_gem_shmem_test_purge
[16:10:40] ================== [PASSED] drm_gem_shmem ==================
[16:10:40] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[16:10:40] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[16:10:40] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[16:10:40] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[16:10:40] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[16:10:40] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[16:10:40] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[16:10:40] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[16:10:40] [PASSED] Automatic
[16:10:40] [PASSED] Full
[16:10:40] [PASSED] Limited 16:235
[16:10:40] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[16:10:40] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[16:10:40] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[16:10:40] [PASSED] drm_test_check_disable_connector
[16:10:40] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[16:10:40] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[16:10:40] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[16:10:40] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[16:10:40] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[16:10:40] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[16:10:40] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[16:10:40] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[16:10:40] [PASSED] drm_test_check_output_bpc_dvi
[16:10:40] [PASSED] drm_test_check_output_bpc_format_vic_1
[16:10:40] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[16:10:40] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[16:10:40] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[16:10:40] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[16:10:40] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[16:10:40] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[16:10:40] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[16:10:40] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[16:10:40] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[16:10:40] [PASSED] drm_test_check_broadcast_rgb_value
[16:10:40] [PASSED] drm_test_check_bpc_8_value
[16:10:40] [PASSED] drm_test_check_bpc_10_value
[16:10:40] [PASSED] drm_test_check_bpc_12_value
[16:10:40] [PASSED] drm_test_check_format_value
[16:10:40] [PASSED] drm_test_check_tmds_char_value
[16:10:40] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[16:10:40] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[16:10:40] [PASSED] drm_test_check_mode_valid
[16:10:40] [PASSED] drm_test_check_mode_valid_reject
[16:10:40] [PASSED] drm_test_check_mode_valid_reject_rate
[16:10:40] [PASSED] drm_test_check_mode_valid_reject_max_clock
[16:10:40] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[16:10:40] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[16:10:40] [PASSED] drm_test_check_infoframes
[16:10:40] [PASSED] drm_test_check_reject_avi_infoframe
[16:10:40] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[16:10:40] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[16:10:40] [PASSED] drm_test_check_reject_audio_infoframe
[16:10:40] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[16:10:40] ================= drm_managed (2 subtests) =================
[16:10:40] [PASSED] drm_test_managed_release_action
[16:10:40] [PASSED] drm_test_managed_run_action
[16:10:40] =================== [PASSED] drm_managed ===================
[16:10:40] =================== drm_mm (6 subtests) ====================
[16:10:40] [PASSED] drm_test_mm_init
[16:10:40] [PASSED] drm_test_mm_debug
[16:10:40] [PASSED] drm_test_mm_align32
[16:10:40] [PASSED] drm_test_mm_align64
[16:10:40] [PASSED] drm_test_mm_lowest
[16:10:40] [PASSED] drm_test_mm_highest
[16:10:40] ===================== [PASSED] drm_mm ======================
[16:10:40] ============= drm_modes_analog_tv (5 subtests) =============
[16:10:40] [PASSED] drm_test_modes_analog_tv_mono_576i
[16:10:40] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[16:10:40] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[16:10:40] [PASSED] drm_test_modes_analog_tv_pal_576i
[16:10:40] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[16:10:40] =============== [PASSED] drm_modes_analog_tv ===============
[16:10:40] ============== drm_plane_helper (2 subtests) ===============
[16:10:40] =============== drm_test_check_plane_state  ================
[16:10:40] [PASSED] clipping_simple
[16:10:40] [PASSED] clipping_rotate_reflect
[16:10:40] [PASSED] positioning_simple
[16:10:40] [PASSED] upscaling
[16:10:40] [PASSED] downscaling
[16:10:40] [PASSED] rounding1
[16:10:40] [PASSED] rounding2
[16:10:40] [PASSED] rounding3
[16:10:40] [PASSED] rounding4
[16:10:40] =========== [PASSED] drm_test_check_plane_state ============
[16:10:40] =========== drm_test_check_invalid_plane_state  ============
[16:10:40] [PASSED] positioning_invalid
[16:10:40] [PASSED] upscaling_invalid
[16:10:40] [PASSED] downscaling_invalid
[16:10:40] ======= [PASSED] drm_test_check_invalid_plane_state ========
[16:10:40] ================ [PASSED] drm_plane_helper =================
[16:10:40] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[16:10:40] ====== drm_test_connector_helper_tv_get_modes_check  =======
[16:10:40] [PASSED] None
[16:10:40] [PASSED] PAL
[16:10:40] [PASSED] NTSC
[16:10:40] [PASSED] Both, NTSC Default
[16:10:40] [PASSED] Both, PAL Default
[16:10:40] [PASSED] Both, NTSC Default, with PAL on command-line
[16:10:40] [PASSED] Both, PAL Default, with NTSC on command-line
[16:10:40] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[16:10:40] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[16:10:40] ================== drm_rect (9 subtests) ===================
[16:10:40] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[16:10:40] [PASSED] drm_test_rect_clip_scaled_not_clipped
[16:10:40] [PASSED] drm_test_rect_clip_scaled_clipped
[16:10:40] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[16:10:40] ================= drm_test_rect_intersect  =================
[16:10:40] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[16:10:40] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[16:10:40] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[16:10:40] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[16:10:40] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[16:10:40] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[16:10:40] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[16:10:40] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[16:10:40] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[16:10:40] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[16:10:40] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[16:10:40] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[16:10:40] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[16:10:40] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[16:10:40] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[16:10:40] ============= [PASSED] drm_test_rect_intersect =============
[16:10:40] ================ drm_test_rect_calc_hscale  ================
[16:10:40] [PASSED] normal use
[16:10:40] [PASSED] out of max range
[16:10:40] [PASSED] out of min range
[16:10:40] [PASSED] zero dst
[16:10:40] [PASSED] negative src
[16:10:40] [PASSED] negative dst
[16:10:40] ============ [PASSED] drm_test_rect_calc_hscale ============
[16:10:40] ================ drm_test_rect_calc_vscale  ================
[16:10:40] [PASSED] normal use
[16:10:40] [PASSED] out of max range
[16:10:40] [PASSED] out of min range
[16:10:40] [PASSED] zero dst
[16:10:40] [PASSED] negative src
[16:10:40] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[16:10:40] ============ [PASSED] drm_test_rect_calc_vscale ============
[16:10:40] ================== drm_test_rect_rotate  ===================
[16:10:40] [PASSED] reflect-x
[16:10:40] [PASSED] reflect-y
[16:10:40] [PASSED] rotate-0
[16:10:40] [PASSED] rotate-90
[16:10:40] [PASSED] rotate-180
[16:10:40] [PASSED] rotate-270
[16:10:40] ============== [PASSED] drm_test_rect_rotate ===============
[16:10:40] ================ drm_test_rect_rotate_inv  =================
[16:10:40] [PASSED] reflect-x
[16:10:40] [PASSED] reflect-y
[16:10:40] [PASSED] rotate-0
[16:10:40] [PASSED] rotate-90
[16:10:40] [PASSED] rotate-180
[16:10:40] [PASSED] rotate-270
[16:10:40] ============ [PASSED] drm_test_rect_rotate_inv =============
[16:10:40] ==================== [PASSED] drm_rect =====================
[16:10:40] ============ drm_sysfb_modeset_test (1 subtest) ============
[16:10:40] ============ drm_test_sysfb_build_fourcc_list  =============
[16:10:40] [PASSED] no native formats
[16:10:40] [PASSED] XRGB8888 as native format
[16:10:40] [PASSED] remove duplicates
[16:10:40] [PASSED] convert alpha formats
[16:10:40] [PASSED] random formats
[16:10:40] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[16:10:40] ============= [PASSED] drm_sysfb_modeset_test ==============
[16:10:40] ================== drm_fixp (2 subtests) ===================
[16:10:40] [PASSED] drm_test_int2fixp
[16:10:40] [PASSED] drm_test_sm2fixp
[16:10:40] ==================== [PASSED] drm_fixp =====================
[16:10:40] ============================================================
[16:10:40] Testing complete. Ran 621 tests: passed: 621
[16:10:40] Elapsed time: 30.966s total, 1.646s configuring, 29.104s building, 0.170s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[16:10:40] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:10:42] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[16:10:52] Starting KUnit Kernel (1/1)...
[16:10:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:10:52] ================= ttm_device (5 subtests) ==================
[16:10:52] [PASSED] ttm_device_init_basic
[16:10:52] [PASSED] ttm_device_init_multiple
[16:10:52] [PASSED] ttm_device_fini_basic
[16:10:52] [PASSED] ttm_device_init_no_vma_man
[16:10:52] ================== ttm_device_init_pools  ==================
[16:10:52] [PASSED] No DMA allocations, no DMA32 required
[16:10:52] [PASSED] DMA allocations, DMA32 required
[16:10:52] [PASSED] No DMA allocations, DMA32 required
[16:10:52] [PASSED] DMA allocations, no DMA32 required
[16:10:52] ============== [PASSED] ttm_device_init_pools ==============
[16:10:52] =================== [PASSED] ttm_device ====================
[16:10:52] ================== ttm_pool (8 subtests) ===================
[16:10:52] ================== ttm_pool_alloc_basic  ===================
[16:10:52] [PASSED] One page
[16:10:52] [PASSED] More than one page
[16:10:52] [PASSED] Above the allocation limit
[16:10:52] [PASSED] One page, with coherent DMA mappings enabled
[16:10:52] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[16:10:52] ============== [PASSED] ttm_pool_alloc_basic ===============
[16:10:52] ============== ttm_pool_alloc_basic_dma_addr  ==============
[16:10:52] [PASSED] One page
[16:10:52] [PASSED] More than one page
[16:10:52] [PASSED] Above the allocation limit
[16:10:52] [PASSED] One page, with coherent DMA mappings enabled
[16:10:52] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[16:10:52] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[16:10:52] [PASSED] ttm_pool_alloc_order_caching_match
[16:10:52] [PASSED] ttm_pool_alloc_caching_mismatch
[16:10:52] [PASSED] ttm_pool_alloc_order_mismatch
[16:10:52] [PASSED] ttm_pool_free_dma_alloc
[16:10:52] [PASSED] ttm_pool_free_no_dma_alloc
[16:10:52] [PASSED] ttm_pool_fini_basic
[16:10:52] ==================== [PASSED] ttm_pool =====================
[16:10:52] ================ ttm_resource (8 subtests) =================
[16:10:52] ================= ttm_resource_init_basic  =================
[16:10:52] [PASSED] Init resource in TTM_PL_SYSTEM
[16:10:52] [PASSED] Init resource in TTM_PL_VRAM
[16:10:52] [PASSED] Init resource in a private placement
[16:10:52] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[16:10:52] ============= [PASSED] ttm_resource_init_basic =============
[16:10:52] [PASSED] ttm_resource_init_pinned
[16:10:52] [PASSED] ttm_resource_fini_basic
[16:10:52] [PASSED] ttm_resource_manager_init_basic
[16:10:52] [PASSED] ttm_resource_manager_usage_basic
[16:10:52] [PASSED] ttm_resource_manager_set_used_basic
[16:10:52] [PASSED] ttm_sys_man_alloc_basic
[16:10:52] [PASSED] ttm_sys_man_free_basic
[16:10:52] ================== [PASSED] ttm_resource ===================
[16:10:52] =================== ttm_tt (15 subtests) ===================
[16:10:52] ==================== ttm_tt_init_basic  ====================
[16:10:52] [PASSED] Page-aligned size
[16:10:52] [PASSED] Extra pages requested
[16:10:52] ================ [PASSED] ttm_tt_init_basic ================
[16:10:52] [PASSED] ttm_tt_init_misaligned
[16:10:52] [PASSED] ttm_tt_fini_basic
[16:10:52] [PASSED] ttm_tt_fini_sg
[16:10:52] [PASSED] ttm_tt_fini_shmem
[16:10:52] [PASSED] ttm_tt_create_basic
[16:10:52] [PASSED] ttm_tt_create_invalid_bo_type
[16:10:52] [PASSED] ttm_tt_create_ttm_exists
[16:10:52] [PASSED] ttm_tt_create_failed
[16:10:52] [PASSED] ttm_tt_destroy_basic
[16:10:52] [PASSED] ttm_tt_populate_null_ttm
[16:10:52] [PASSED] ttm_tt_populate_populated_ttm
[16:10:52] [PASSED] ttm_tt_unpopulate_basic
[16:10:52] [PASSED] ttm_tt_unpopulate_empty_ttm
[16:10:52] [PASSED] ttm_tt_swapin_basic
[16:10:52] ===================== [PASSED] ttm_tt ======================
[16:10:52] =================== ttm_bo (14 subtests) ===================
[16:10:52] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[16:10:52] [PASSED] Cannot be interrupted and sleeps
[16:10:52] [PASSED] Cannot be interrupted, locks straight away
[16:10:52] [PASSED] Can be interrupted, sleeps
[16:10:52] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[16:10:52] [PASSED] ttm_bo_reserve_locked_no_sleep
[16:10:52] [PASSED] ttm_bo_reserve_no_wait_ticket
[16:10:52] [PASSED] ttm_bo_reserve_double_resv
[16:10:52] [PASSED] ttm_bo_reserve_interrupted
[16:10:52] [PASSED] ttm_bo_reserve_deadlock
[16:10:52] [PASSED] ttm_bo_unreserve_basic
[16:10:52] [PASSED] ttm_bo_unreserve_pinned
[16:10:52] [PASSED] ttm_bo_unreserve_bulk
[16:10:52] [PASSED] ttm_bo_fini_basic
[16:10:52] [PASSED] ttm_bo_fini_shared_resv
[16:10:52] [PASSED] ttm_bo_pin_basic
[16:10:52] [PASSED] ttm_bo_pin_unpin_resource
[16:10:52] [PASSED] ttm_bo_multiple_pin_one_unpin
[16:10:52] ===================== [PASSED] ttm_bo ======================
[16:10:52] ============== ttm_bo_validate (22 subtests) ===============
[16:10:52] ============== ttm_bo_init_reserved_sys_man  ===============
[16:10:52] [PASSED] Buffer object for userspace
[16:10:52] [PASSED] Kernel buffer object
[16:10:52] [PASSED] Shared buffer object
[16:10:52] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[16:10:52] ============== ttm_bo_init_reserved_mock_man  ==============
[16:10:52] [PASSED] Buffer object for userspace
[16:10:52] [PASSED] Kernel buffer object
[16:10:52] [PASSED] Shared buffer object
[16:10:52] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[16:10:52] [PASSED] ttm_bo_init_reserved_resv
[16:10:52] ================== ttm_bo_validate_basic  ==================
[16:10:52] [PASSED] Buffer object for userspace
[16:10:52] [PASSED] Kernel buffer object
[16:10:52] [PASSED] Shared buffer object
[16:10:52] ============== [PASSED] ttm_bo_validate_basic ==============
[16:10:52] [PASSED] ttm_bo_validate_invalid_placement
[16:10:52] ============= ttm_bo_validate_same_placement  ==============
[16:10:52] [PASSED] System manager
[16:10:52] [PASSED] VRAM manager
[16:10:52] ========= [PASSED] ttm_bo_validate_same_placement ==========
[16:10:52] [PASSED] ttm_bo_validate_failed_alloc
[16:10:52] [PASSED] ttm_bo_validate_pinned
[16:10:52] [PASSED] ttm_bo_validate_busy_placement
[16:10:52] ================ ttm_bo_validate_multihop  =================
[16:10:52] [PASSED] Buffer object for userspace
[16:10:52] [PASSED] Kernel buffer object
[16:10:52] [PASSED] Shared buffer object
[16:10:52] ============ [PASSED] ttm_bo_validate_multihop =============
[16:10:52] ========== ttm_bo_validate_no_placement_signaled  ==========
[16:10:52] [PASSED] Buffer object in system domain, no page vector
[16:10:52] [PASSED] Buffer object in system domain with an existing page vector
[16:10:52] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[16:10:52] ======== ttm_bo_validate_no_placement_not_signaled  ========
[16:10:52] [PASSED] Buffer object for userspace
[16:10:52] [PASSED] Kernel buffer object
[16:10:52] [PASSED] Shared buffer object
[16:10:52] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[16:10:52] [PASSED] ttm_bo_validate_move_fence_signaled
[16:10:52] ========= ttm_bo_validate_move_fence_not_signaled  =========
[16:10:52] [PASSED] Waits for GPU
[16:10:52] [PASSED] Tries to lock straight away
[16:10:52] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[16:10:52] [PASSED] ttm_bo_validate_swapout
[16:10:52] [PASSED] ttm_bo_validate_happy_evict
[16:10:52] [PASSED] ttm_bo_validate_all_pinned_evict
[16:10:52] [PASSED] ttm_bo_validate_allowed_only_evict
[16:10:52] [PASSED] ttm_bo_validate_deleted_evict
[16:10:52] [PASSED] ttm_bo_validate_busy_domain_evict
[16:10:52] [PASSED] ttm_bo_validate_evict_gutting
[16:10:52] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[16:10:52] ================= [PASSED] ttm_bo_validate =================
[16:10:52] ============================================================
[16:10:52] Testing complete. Ran 102 tests: passed: 102
[16:10:52] Elapsed time: 11.544s total, 1.806s configuring, 9.521s building, 0.181s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for CMTG enablement (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2401 bytes --]

== Series Details ==

Series: CMTG enablement (rev4)
URL   : https://patchwork.freedesktop.org/series/157663/
State : success

== Summary ==

CI Bug Log - changes from xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132_BAT -> xe-pw-157663v4_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-157663v4_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@reltime:
    - bat-dg2-oem2:       [PASS][1] -> [FAIL][2] ([Intel XE#6520])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/bat-dg2-oem2/igt@xe_waitfence@reltime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/bat-dg2-oem2/igt@xe_waitfence@reltime.html

  
#### Possible fixes ####

  * igt@xe_waitfence@abstime:
    - bat-dg2-oem2:       [TIMEOUT][3] ([Intel XE#6506]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/bat-dg2-oem2/igt@xe_waitfence@abstime.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/bat-dg2-oem2/igt@xe_waitfence@abstime.html

  * igt@xe_waitfence@engine:
    - bat-dg2-oem2:       [FAIL][5] ([Intel XE#6519]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/bat-dg2-oem2/igt@xe_waitfence@engine.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/bat-dg2-oem2/igt@xe_waitfence@engine.html

  
  [Intel XE#6506]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6506
  [Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519
  [Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520


Build changes
-------------

  * IGT: IGT_8801 -> IGT_8802
  * Linux: xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132 -> xe-pw-157663v4

  IGT_8801: 246d93c1df887e151d038cee9eb0fc31650c4fb0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8802: 8802
  xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132: 45618ec6cfed86e72cf6c2325c8f947bfbe7c132
  xe-pw-157663v4: 157663v4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/index.html

[-- Attachment #2: Type: text/html, Size: 3036 bytes --]

✓ Xe.CI.FULL: success for CMTG enablement (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 56897 bytes --]

== Series Details ==

Series: CMTG enablement (rev4)
URL   : https://patchwork.freedesktop.org/series/157663/
State : success

== Summary ==

CI Bug Log - changes from xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132_FULL -> xe-pw-157663v4_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-157663v4_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@x-tiled-16bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][1] ([Intel XE#2327])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-4/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][2] ([Intel XE#1124])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          [PASS][3] -> [SKIP][4] ([Intel XE#2314] / [Intel XE#2894] / [Intel XE#7373])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-3/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-1-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#367] / [Intel XE#7354])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#2887]) +1 other test skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@kms_ccs@bad-rotation-90-y-tiled-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-a-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2652]) +7 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_chamelium_audio@dp-audio:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2252]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@kms_chamelium_audio@dp-audio.html

  * igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][9] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-offscreen-32x32:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2320]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-9/igt@kms_cursor_crc@cursor-offscreen-32x32.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2321] / [Intel XE#7355])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][12] -> [SKIP][13] ([Intel XE#2291]) +2 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#309] / [Intel XE#7343])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-2/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
    - shard-bmg:          [PASS][15] -> [SKIP][16] ([Intel XE#2291] / [Intel XE#7343])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-3/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#4210] / [Intel XE#7467])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-10/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-bmg:          [PASS][18] -> [SKIP][19] ([Intel XE#4294])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-4/igt@kms_dp_linktrain_fallback@dp-fallback.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
    - shard-bmg:          [PASS][20] -> [SKIP][21] ([Intel XE#2316]) +3 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-4/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [PASS][22] -> [FAIL][23] ([Intel XE#301]) +1 other test fail
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [PASS][24] -> [FAIL][25] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-bmg:          [PASS][26] -> [INCOMPLETE][27] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-8/igt@kms_flip@flip-vs-suspend-interruptible.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-9/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@wf_vblank-ts-check@a-edp1:
    - shard-lnl:          [PASS][28] -> [FAIL][29] ([Intel XE#3098]) +1 other test fail
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-4/igt@kms_flip@wf_vblank-ts-check@a-edp1.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-7/igt@kms_flip@wf_vblank-ts-check@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#7178] / [Intel XE#7349])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#7178] / [Intel XE#7349])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-7/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#7178] / [Intel XE#7351])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#4141]) +4 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#6312] / [Intel XE#651])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2311]) +12 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#7061] / [Intel XE#7356])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#2313]) +7 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#1469] / [Intel XE#7399])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#2352] / [Intel XE#7399])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@plane-fbc-rte:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#2350] / [Intel XE#7503])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-6/igt@kms_frontbuffer_tracking@plane-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#2312]) +1 other test skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#5021] / [Intel XE#7377])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-10/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-bmg:          [PASS][43] -> [SKIP][44] ([Intel XE#2685] / [Intel XE#3307])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-9/igt@kms_plane_scaling@intel-max-src-size.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-3/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_psr2_sf@psr2-cursor-plane-update-sf:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#1489]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-7/igt@kms_psr2_sf@psr2-cursor-plane-update-sf.html

  * igt@kms_psr@psr-no-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@kms_psr@psr-no-drrs.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-lnl:          [PASS][47] -> [SKIP][48] ([Intel XE#4692] / [Intel XE#7508])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_sharpness_filter@filter-modifiers:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#6503]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@kms_sharpness_filter@filter-modifiers.html

  * igt@xe_eudebug@vm-bind-clear-faultable:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#4837]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-6/igt@xe_eudebug@vm-bind-clear-faultable.html

  * igt@xe_eudebug_online@breakpoint-many-sessions-single-tile:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#4837] / [Intel XE#6665])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-10/igt@xe_eudebug_online@breakpoint-many-sessions-single-tile.html

  * igt@xe_evict@evict-small-external-multi-queue-cm:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#7140])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-9/igt@xe_evict@evict-small-external-multi-queue-cm.html
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#6540] / [Intel XE#688])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-5/igt@xe_evict@evict-small-external-multi-queue-cm.html

  * igt@xe_exec_balancer@twice-cm-virtual-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#7482]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-8/igt@xe_exec_balancer@twice-cm-virtual-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#2322] / [Intel XE#7372]) +2 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue.html

  * igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-imm:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#7136]) +1 other test skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-4/igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-imm.html

  * igt@xe_exec_multi_queue@two-queues-priority:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#6874]) +10 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-7/igt@xe_exec_multi_queue@two-queues-priority.html
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#6874])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-2/igt@xe_exec_multi_queue@two-queues-priority.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#7138]) +4 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#2236])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-4/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_pm_residency@cpg-basic:
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#584] / [Intel XE#7369])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-1/igt@xe_pm_residency@cpg-basic.html

  * igt@xe_pxp@pxp-optout:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#4733] / [Intel XE#7417]) +1 other test skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@xe_pxp@pxp-optout.html

  
#### Possible fixes ####

  * igt@fbdev@read:
    - shard-bmg:          [FAIL][64] -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@fbdev@read.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@fbdev@read.html

  * igt@kms_cursor_crc@cursor-sliding-256x256:
    - shard-bmg:          [FAIL][66] ([Intel XE#6747]) -> [PASS][67] +1 other test pass
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@kms_cursor_crc@cursor-sliding-256x256.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-4/igt@kms_cursor_crc@cursor-sliding-256x256.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
    - shard-bmg:          [SKIP][68] ([Intel XE#2316]) -> [PASS][69] +7 other tests pass
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-bmg:          [SKIP][70] ([Intel XE#7086]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-5/igt@kms_joiner@basic-force-big-joiner.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-3/igt@kms_joiner@basic-force-big-joiner.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][72] ([Intel XE#6321]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-10/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-4/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_exec_fault_mode@twice-userptr-rebind:
    - shard-bmg:          [SKIP][74] ([Intel XE#6703]) -> [PASS][75] +82 other tests pass
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@xe_exec_fault_mode@twice-userptr-rebind.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-10/igt@xe_exec_fault_mode@twice-userptr-rebind.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma:
    - shard-lnl:          [FAIL][76] ([Intel XE#5625]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-4/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-5/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html

  * igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-free-race-nomemset:
    - shard-bmg:          [INCOMPLETE][78] -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-9/igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-free-race-nomemset.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-10/igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-free-race-nomemset.html

  * igt@xe_exec_system_allocator@twice-large-malloc-multi-fault:
    - shard-bmg:          [DMESG-FAIL][80] ([Intel XE#5545] / [Intel XE#6652]) -> [PASS][81]
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@xe_exec_system_allocator@twice-large-malloc-multi-fault.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-9/igt@xe_exec_system_allocator@twice-large-malloc-multi-fault.html

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [SKIP][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107]) ([Intel XE#378] / [Intel XE#7405]) -> ([PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-1/igt@xe_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-2/igt@xe_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-2/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-1/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-6/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-6/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-6/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-5/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-6/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-8/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-5/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-5/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-3/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-3/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-3/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-8/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-8/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-8/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-7/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-7/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-7/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-4/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-4/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-4/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-1/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-lnl-2/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-7/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-2/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-4/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-8/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-4/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-6/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-6/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-5/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-5/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-5/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-1/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-3/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-3/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-4/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-3/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-3/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-1/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-2/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-8/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-2/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-8/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-7/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-6/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-1/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-lnl-7/igt@xe_module_load@load.html
    - shard-bmg:          ([PASS][133], [SKIP][134], [PASS][135], [PASS][136], [PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [PASS][145], [PASS][146], [PASS][147], [PASS][148], [PASS][149], [PASS][150], [PASS][151], [PASS][152], [PASS][153], [PASS][154], [PASS][155], [PASS][156], [PASS][157], [PASS][158]) ([Intel XE#2457] / [Intel XE#7405]) -> ([PASS][159], [PASS][160], [PASS][161], [PASS][162], [PASS][163], [PASS][164], [PASS][165], [PASS][166], [PASS][167], [PASS][168], [PASS][169], [PASS][170], [PASS][171], [PASS][172], [PASS][173], [PASS][174], [PASS][175], [PASS][176], [PASS][177], [PASS][178], [PASS][179], [PASS][180], [PASS][181], [PASS][182], [PASS][183])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-10/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-3/igt@xe_module_load@load.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-5/igt@xe_module_load@load.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-4/igt@xe_module_load@load.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-4/igt@xe_module_load@load.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-9/igt@xe_module_load@load.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-9/igt@xe_module_load@load.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-3/igt@xe_module_load@load.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-3/igt@xe_module_load@load.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-3/igt@xe_module_load@load.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@xe_module_load@load.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-5/igt@xe_module_load@load.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-5/igt@xe_module_load@load.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-7/igt@xe_module_load@load.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-8/igt@xe_module_load@load.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-6/igt@xe_module_load@load.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-6/igt@xe_module_load@load.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-6/igt@xe_module_load@load.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-10/igt@xe_module_load@load.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-7/igt@xe_module_load@load.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-10/igt@xe_module_load@load.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-7/igt@xe_module_load@load.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-4/igt@xe_module_load@load.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@xe_module_load@load.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@xe_module_load@load.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-8/igt@xe_module_load@load.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-3/igt@xe_module_load@load.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-2/igt@xe_module_load@load.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@xe_module_load@load.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@xe_module_load@load.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-2/igt@xe_module_load@load.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@xe_module_load@load.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-2/igt@xe_module_load@load.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@xe_module_load@load.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-9/igt@xe_module_load@load.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-6/igt@xe_module_load@load.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-7/igt@xe_module_load@load.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-7/igt@xe_module_load@load.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-10/igt@xe_module_load@load.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-9/igt@xe_module_load@load.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-10/igt@xe_module_load@load.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-3/igt@xe_module_load@load.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-6/igt@xe_module_load@load.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@xe_module_load@load.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@xe_module_load@load.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-4/igt@xe_module_load@load.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-4/igt@xe_module_load@load.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-4/igt@xe_module_load@load.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-9/igt@xe_module_load@load.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-10/igt@xe_module_load@load.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-7/igt@xe_module_load@load.html

  * igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling@numvfs-random:
    - shard-bmg:          [FAIL][184] ([Intel XE#5937]) -> [PASS][185] +1 other test pass
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-4/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling@numvfs-random.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-4/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling@numvfs-random.html

  
#### Warnings ####

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
    - shard-bmg:          [SKIP][186] ([Intel XE#6703]) -> [SKIP][187] ([Intel XE#1124])
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-6/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs:
    - shard-bmg:          [SKIP][188] ([Intel XE#6703]) -> [SKIP][189] ([Intel XE#2887]) +1 other test skip
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-3/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-bmg:          [SKIP][190] ([Intel XE#6703]) -> [SKIP][191] ([Intel XE#2652])
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
    - shard-bmg:          [SKIP][192] ([Intel XE#6703]) -> [SKIP][193] ([Intel XE#2252]) +1 other test skip
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-2/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html

  * igt@kms_content_protection@legacy:
    - shard-bmg:          [FAIL][194] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) -> [SKIP][195] ([Intel XE#2341])
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-9/igt@kms_content_protection@legacy.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@lic-type-0-hdcp14:
    - shard-bmg:          [SKIP][196] ([Intel XE#7194]) -> [FAIL][197] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-5/igt@kms_content_protection@lic-type-0-hdcp14.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@kms_content_protection@lic-type-0-hdcp14.html

  * igt@kms_cursor_crc@cursor-sliding-64x21:
    - shard-bmg:          [SKIP][198] ([Intel XE#6703]) -> [SKIP][199] ([Intel XE#2320])
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@kms_cursor_crc@cursor-sliding-64x21.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-2/igt@kms_cursor_crc@cursor-sliding-64x21.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
    - shard-bmg:          [SKIP][200] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][201] ([Intel XE#7178] / [Intel XE#7351])
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][202] ([Intel XE#2312]) -> [SKIP][203] ([Intel XE#2311]) +9 other tests skip
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt:
    - shard-bmg:          [SKIP][204] ([Intel XE#6703]) -> [SKIP][205] ([Intel XE#4141]) +1 other test skip
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][206] ([Intel XE#4141]) -> [SKIP][207] ([Intel XE#2312]) +2 other tests skip
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][208] ([Intel XE#6703]) -> [SKIP][209] ([Intel XE#2312])
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          [SKIP][210] ([Intel XE#2312]) -> [SKIP][211] ([Intel XE#4141]) +2 other tests skip
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][212] ([Intel XE#6703]) -> [SKIP][213] ([Intel XE#2311]) +2 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-msflip-blt.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][214] ([Intel XE#2311]) -> [SKIP][215] ([Intel XE#2312]) +6 other tests skip
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][216] ([Intel XE#2313]) -> [SKIP][217] ([Intel XE#2312]) +9 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][218] ([Intel XE#6703]) -> [SKIP][219] ([Intel XE#2313]) +3 other tests skip
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-onoff:
    - shard-bmg:          [SKIP][220] ([Intel XE#2312]) -> [SKIP][221] ([Intel XE#2313]) +8 other tests skip
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-onoff.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-blt:
    - shard-bmg:          [SKIP][222] ([Intel XE#6703]) -> [SKIP][223] ([Intel XE#7061] / [Intel XE#7356])
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-blt.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-9/igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-blt.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf:
    - shard-bmg:          [SKIP][224] ([Intel XE#6703]) -> [SKIP][225] ([Intel XE#1489])
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-9/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html

  * igt@kms_psr@psr2-sprite-plane-onoff:
    - shard-bmg:          [SKIP][226] ([Intel XE#6703]) -> [SKIP][227] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@kms_psr@psr2-sprite-plane-onoff.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-2/igt@kms_psr@psr2-sprite-plane-onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-bmg:          [SKIP][228] ([Intel XE#6703]) -> [SKIP][229] ([Intel XE#1435])
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@kms_setmode@basic-clone-single-crtc.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-7/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@xe_eudebug_online@stopped-thread:
    - shard-bmg:          [SKIP][230] ([Intel XE#6703]) -> [SKIP][231] ([Intel XE#4837] / [Intel XE#6665]) +2 other tests skip
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@xe_eudebug_online@stopped-thread.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-9/igt@xe_eudebug_online@stopped-thread.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate:
    - shard-bmg:          [SKIP][232] ([Intel XE#6703]) -> [SKIP][233] ([Intel XE#2322] / [Intel XE#7372])
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-prefetch:
    - shard-bmg:          [SKIP][234] ([Intel XE#6703]) -> [SKIP][235] ([Intel XE#7136])
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@xe_exec_fault_mode@twice-multi-queue-userptr-prefetch.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@xe_exec_fault_mode@twice-multi-queue-userptr-prefetch.html

  * igt@xe_exec_multi_queue@two-queues-priority-smem:
    - shard-bmg:          [SKIP][236] ([Intel XE#6703]) -> [SKIP][237] ([Intel XE#6874]) +3 other tests skip
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@xe_exec_multi_queue@two-queues-priority-smem.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-5/igt@xe_exec_multi_queue@two-queues-priority-smem.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-fd-rebind:
    - shard-bmg:          [SKIP][238] ([Intel XE#6703]) -> [SKIP][239] ([Intel XE#7138]) +1 other test skip
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-mixed-fd-rebind.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@xe_exec_threads@threads-multi-queue-mixed-fd-rebind.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-bmg:          [ABORT][240] ([Intel XE#5466] / [Intel XE#6652] / [Intel XE#7577]) -> [ABORT][241] ([Intel XE#5466] / [Intel XE#7577])
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-4/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-10/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  * igt@xe_pxp@pxp-stale-queue-post-termination-irq:
    - shard-bmg:          [SKIP][242] ([Intel XE#6703]) -> [SKIP][243] ([Intel XE#4733] / [Intel XE#7417])
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@xe_pxp@pxp-stale-queue-post-termination-irq.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-9/igt@xe_pxp@pxp-stale-queue-post-termination-irq.html

  * igt@xe_query@multigpu-query-invalid-size:
    - shard-bmg:          [SKIP][244] ([Intel XE#6703]) -> [SKIP][245] ([Intel XE#944])
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132/shard-bmg-2/igt@xe_query@multigpu-query-invalid-size.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/shard-bmg-8/igt@xe_query@multigpu-query-invalid-size.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1469]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1469
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2236]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2236
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2350
  [Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2685]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2685
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3307
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4210]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4210
  [Intel XE#4294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4294
  [Intel XE#4692]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4692
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5937
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
  [Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6747]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6747
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7086]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7086
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7194]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7194
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7354
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7373
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7377]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7377
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7467]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7467
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7503
  [Intel XE#7508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7508
  [Intel XE#7577]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7577
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_8801 -> IGT_8802
  * Linux: xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132 -> xe-pw-157663v4

  IGT_8801: 246d93c1df887e151d038cee9eb0fc31650c4fb0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8802: 8802
  xe-4713-45618ec6cfed86e72cf6c2325c8f947bfbe7c132: 45618ec6cfed86e72cf6c2325c8f947bfbe7c132
  xe-pw-157663v4: 157663v4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v4/index.html

[-- Attachment #2: Type: text/html, Size: 64998 bytes --]

RE: [PATCH v3 01/12] drm/i915/cmtg: add is_enable_allowed() for cmtg

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Friday, March 13, 2026 9:03 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v3 01/12] drm/i915/cmtg: add is_enable_allowed() for cmtg

Nit: Name here in subject doesn't match the actual function. Better to use exact same name.

> Introduce a flag for DC3co. CMTG will be enabled only with DC3co so add a
> separate function is_allowed() for cmtg. DC3co flag will be enabled in a separate
> patch.
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c          | 14 ++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h          |  2 ++
>  .../gpu/drm/i915/display/intel_display_device.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_display_types.h |  4 ++++
>  4 files changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index e1fdc6fe9762..024d753eca55 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -16,6 +16,7 @@
>  #include "intel_display_device.h"
>  #include "intel_display_power.h"
>  #include "intel_display_regs.h"
> +#include "intel_display_types.h"
> 
>  /**
>   * DOC: Common Primary Timing Generator (CMTG) @@ -185,3 +186,16 @@
> void intel_cmtg_sanitize(struct intel_display *display)
> 
>  	intel_cmtg_disable(display, &cmtg_config);  }
> +
> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder ==
> TRANSCODER_B) &&
> +	    HAS_DC3CO(display) && intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_EDP) &&
> +	    crtc_state->dc3co.enable)

Don't think we need both HAS_DC3CO and dc3co.enable here. Later should never be set if HAS_DC3CO
not true.

> +		return true;
> +
> +	return false;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index ba62199adaa2..7692cc98cf87 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -7,7 +7,9 @@
>  #define __INTEL_CMTG_H__
> 
>  struct intel_display;
> +struct intel_crtc_state;
> 
>  void intel_cmtg_sanitize(struct intel_display *display);
> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
> 
>  #endif /* __INTEL_CMTG_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> b/drivers/gpu/drm/i915/display/intel_display_device.h
> index e84c190dcc4f..35e06fcf794d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -189,6 +189,7 @@ struct intel_display_platforms {
>  #define HAS_LRR(__display)		(DISPLAY_VER(__display) >= 12)
>  #define HAS_LSPCON(__display)		(IS_DISPLAY_VER(__display, 9,
> 10))
>  #define HAS_LT_PHY(__display)		((__display)->platform.novalake)
> +#define HAS_DC3CO(__display)		((__display)->platform.novalake)
>  #define HAS_MBUS_JOINING(__display)	((__display)->platform.alderlake_p
> || DISPLAY_VER(__display) >= 14)
>  #define HAS_MSO(__display)		(DISPLAY_VER(__display) >= 12)
>  #define HAS_OVERLAY(__display)		(DISPLAY_INFO(__display)-
> >has_overlay)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e189f8c39ccb..8a92ea4f1438 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1434,6 +1434,10 @@ struct intel_crtc_state {
> 
>  	/* to track changes in plane color blocks */
>  	bool plane_color_changed;
> +
> +	struct {
> +		bool enable;
> +	} dc3co;
>  };
> 
>  enum intel_pipe_crc_source {
> --
> 2.29.0

RE: [PATCH v3 02/12] drm/i915/cmtg: set CMTG clock select

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Friday, March 13, 2026 9:03 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v3 02/12] drm/i915/cmtg: set CMTG clock select
> 
> Program the CMTG Clock Select register based on the transcoder used.
> 
> v2:
> - Correct mask for PHY B. [Jani]
> - Use REG_FIELD_PREP() for enable value. [Dibin]
> - Extend cmtg clock select for xe3plpd. [Dibin]
> 
> v3:
> - cmtg support removed for old platform.
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 24 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
>  .../gpu/drm/i915/display/intel_cmtg_regs.h    |  2 ++
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   |  7 ++++--
>  4 files changed, 32 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 024d753eca55..644522b96288 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -199,3 +199,27 @@ bool intel_cmtg_is_allowed(const struct intel_crtc_state
> *crtc_state)
> 
>  	return false;
>  }
> +
> +void intel_cmtg_set_clk_select(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 clk_sel_clr = 0;
> +	u32 clk_sel_set = 0;
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	if (cpu_transcoder == TRANSCODER_A) {
> +		clk_sel_clr = CMTG_CLK_SEL_A_MASK;
> +		clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
> +	}
> +

Use else if instead of a separate if block, that will be cleaner.

> +	if (cpu_transcoder == TRANSCODER_B) {
> +		clk_sel_clr = CMTG_CLK_SEL_B_MASK;
> +		clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
> +	}
> +
> +	if (clk_sel_set)
> +		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 7692cc98cf87..660ec513626e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -9,6 +9,7 @@
>  struct intel_display;
>  struct intel_crtc_state;
> 
> +void intel_cmtg_set_clk_select(const struct intel_crtc_state
> +*crtc_state);
>  void intel_cmtg_sanitize(struct intel_display *display);  bool
> intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 945a35578284..8a767b659a23 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -10,8 +10,10 @@
> 
>  #define CMTG_CLK_SEL			_MMIO(0x46160)
>  #define CMTG_CLK_SEL_A_MASK		REG_GENMASK(31, 29)
> +#define CMTG_CLK_SELECT_PHYA_ENABLE
> 	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
>  #define CMTG_CLK_SEL_A_DISABLED
> 	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
>  #define CMTG_CLK_SEL_B_MASK		REG_GENMASK(15, 13)
> +#define CMTG_CLK_SELECT_PHYB_ENABLE
> 	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x6)

Mask is not correct, use B.

>  #define CMTG_CLK_SEL_B_DISABLED
> 	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
> 
>  #define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index eced8493e566..e78f3a00ea80 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -5,6 +5,7 @@
> 
>  #include <drm/drm_print.h>
> 
> +#include "intel_cmtg.h"
>  #include "intel_cx0_phy.h"
>  #include "intel_cx0_phy_regs.h"
>  #include "intel_ddi.h"
> @@ -2249,10 +2250,12 @@ void intel_xe3plpd_pll_enable(struct intel_encoder
> *encoder,  {
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> 
> -	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> +	if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
>  		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
> -	else
> +	} else {
>  		intel_lt_phy_pll_enable(encoder, crtc_state);
> +		intel_cmtg_set_clk_select(crtc_state);
> +	}
>  }
> 
>  void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
> --
> 2.29.0

RE: [PATCH v3 03/12] drm/i915/cmtg: set timings for CMTG

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Friday, March 13, 2026 9:03 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v3 03/12] drm/i915/cmtg: set timings for CMTG
> 
> Timing registers are separate for CMTG, read transcoder register and program
> cmtg transcoder with those values.
> 
> v2:
> - Use sw state instead of reading directly from hardware. [Jani]
> - Move set_timing later after encoder enable. [Dibin]
> 
> v3:
> - replace id with trans. [Jani]
> - program cmtg set_timing() along with primary transcoder timing.
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 48 ++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  3 ++
>  .../gpu/drm/i915/display/intel_cmtg_regs.h    |  9 ++++
>  drivers/gpu/drm/i915/display/intel_display.c  |  4 ++
>  4 files changed, 63 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 644522b96288..e0f12925f5c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -4,7 +4,6 @@
>   */
> 
>  #include <linux/string_choices.h>
> -#include <linux/types.h>
> 
>  #include <drm/drm_device.h>
>  #include <drm/drm_print.h>
> @@ -223,3 +222,50 @@ void intel_cmtg_set_clk_select(const struct
> intel_crtc_state *crtc_state)
>  	if (clk_sel_set)
>  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
> }
> +
> +void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state,
> +bool lrr) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> +	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> +	crtc_vtotal = 1;
> +	crtc_vblank_start = 1;

Why 1 ?

> +	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> +
> +	if (lrr) {
> +		intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder),
> +			       VACTIVE(crtc_vdisplay - 1) |
> +			       VTOTAL(crtc_vtotal - 1));
> +		intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder),
> +			       VBLANK_START(crtc_vblank_start - 1) |
> +			       VBLANK_END(crtc_vblank_end - 1));

We will end up programming vtotal and vblank_start as 0, check and fix.

> +		return;
> +	}
> +
> +	intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder),
> +		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> +		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> +	intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder),
> +		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> +		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> +	intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder),
> +		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> +		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> +	intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder),
> +		       VACTIVE(crtc_vdisplay - 1) |
> +		       VTOTAL(crtc_vtotal - 1));
> +	intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder),
> +		       VBLANK_START(crtc_vblank_start - 1) |
> +		       VBLANK_END(crtc_vblank_end - 1));
> +	intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder),
> +		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> +		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> +	intel_de_write(display,
> TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
> +		       crtc_state->set_context_latency); }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 660ec513626e..53a44f505dd2 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -6,9 +6,12 @@
>  #ifndef __INTEL_CMTG_H__
>  #define __INTEL_CMTG_H__
> 
> +#include <linux/types.h>
> +
>  struct intel_display;
>  struct intel_crtc_state;
> 
> +void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state,
> +bool lrr);
>  void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_sanitize(struct intel_display *display);  bool
> intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state); diff --git
> a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 8a767b659a23..60714a2080c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -20,4 +20,13 @@
>  #define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
>  #define  CMTG_ENABLE			REG_BIT(31)
> 
> +#define TRANS_HTOTAL_CMTG(trans)	_MMIO(0x6F000 + (trans) *
> 0x100)
> +#define TRANS_HBLANK_CMTG(trans)	_MMIO(0x6F004 + (trans) *
> 0x100)
> +#define TRANS_HSYNC_CMTG(trans)		_MMIO(0x6F008 + (trans)
> * 0x100)
> +#define TRANS_VTOTAL_CMTG(trans)	_MMIO(0x6F00C + (trans) *
> 0x100)
> +#define TRANS_VBLANK_CMTG(trans)	_MMIO(0x6F010 + (trans) *
> 0x100)
> +#define TRANS_VSYNC_CMTG(trans)		_MMIO(0x6F014 + (trans)
> * 0x100)
> +
> +#define TRANS_SET_CTX_LATENCY_CMTG(trans)	_MMIO(0x6F07C +
> (trans) * 0x100)
> +
>  #endif /* __INTEL_CMTG_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b18ce0c36a64..82e4d0524d54 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -61,6 +61,7 @@
>  #include "intel_casf.h"
>  #include "intel_cdclk.h"
>  #include "intel_clock_gating.h"
> +#include "intel_cmtg.h"
>  #include "intel_color.h"
>  #include "intel_crt.h"
>  #include "intel_crtc.h"
> @@ -2775,6 +2776,8 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
>  		intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
>  			       crtc_state->min_hblank);
>  	}
> +
> +	intel_cmtg_set_timings(crtc_state, false);
>  }
> 
>  static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state
> *crtc_state) @@ -2836,6 +2839,7 @@ static void
> intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
>  		       VACTIVE(crtc_vdisplay - 1) |
>  		       VTOTAL(crtc_vtotal - 1));
> 
> +	intel_cmtg_set_timings(crtc_state, true);
>  	intel_vrr_set_fixed_rr_timings(crtc_state);
>  	intel_vrr_transcoder_enable(crtc_state);
>  }
> --
> 2.29.0

RE: [PATCH v3 04/12] drm/i915/cmtg: program VRR registers of CMTG

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Friday, March 13, 2026 9:03 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v3 04/12] drm/i915/cmtg: program VRR registers of CMTG
> 
> Program the VRR registers of CMTG, as the VRR timing generator will always be
> enabled for NVL.
> 
> v2: Use sw state instead of reading from hardware. [Jani]
> v3: Program cmtg vrr control and timing registers along with vrr transcoder
> registers.

Change Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 33 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  2 ++
>  .../gpu/drm/i915/display/intel_cmtg_regs.h    |  5 +++
>  drivers/gpu/drm/i915/display/intel_vrr.c      |  5 +++
>  4 files changed, 45 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index e0f12925f5c2..038927b8721b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -16,6 +16,7 @@
>  #include "intel_display_power.h"
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
> +#include "intel_vrr_regs.h"
> 
>  /**
>   * DOC: Common Primary Timing Generator (CMTG) @@ -269,3 +270,35 @@
> void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
>  	intel_de_write(display,
> TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
>  		       crtc_state->set_context_latency);  }
> +
> +void intel_cmtg_set_vrr_timings(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	intel_de_write(display, TRANS_VRR_VMIN_CMTG(cpu_transcoder),
> crtc_state->vrr.vmin);
> +	intel_de_write(display, TRANS_VRR_VMAX_CMTG(cpu_transcoder),
> crtc_state->vrr.vmax);
> +	intel_de_write(display, TRANS_VRR_FLIPLINE_CMTG(cpu_transcoder),
> +crtc_state->vrr.flipline); }
> +
> +void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 vrr_ctl;
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	vrr_ctl = VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN |
> +		  XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state-
> >vrr.guardband);
> +
> +	/* TODO: The code below may need to be revisited once CMRR is
> enabled */
> +	if (crtc_state->cmrr.enable)
> +		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
> +
> +	intel_de_write(display, TRANS_VRR_CTL_CMTG(cpu_transcoder),
> vrr_ctl);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 53a44f505dd2..c92e3a62ff0d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -11,6 +11,8 @@
>  struct intel_display;
>  struct intel_crtc_state;
> 
> +void intel_cmtg_set_vrr_timings(const struct intel_crtc_state
> +*crtc_state); void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state
> +*crtc_state);
>  void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
> void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_sanitize(struct intel_display *display); diff --git
> a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 60714a2080c7..3e94151e4daf 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -29,4 +29,9 @@
> 
>  #define TRANS_SET_CTX_LATENCY_CMTG(trans)	_MMIO(0x6F07C +
> (trans) * 0x100)
> 
> +#define TRANS_VRR_CTL_CMTG(trans)	_MMIO(0x6F420 + (trans) *
> 0x100)
> +#define TRANS_VRR_VMAX_CMTG(trans)	_MMIO(0x6F424 + (trans) *
> 0x100)
> +#define TRANS_VRR_VMIN_CMTG(trans)	_MMIO(0x6F434 + (trans) *
> 0x100)
> +#define TRANS_VRR_FLIPLINE_CMTG(trans)	_MMIO(0x6F438 + (trans) *
> 0x100)
> +
>  #endif /* __INTEL_CMTG_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 8a957804cb97..0242ff0d04f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -7,6 +7,7 @@
>  #include <drm/drm_print.h>
> 
>  #include "intel_alpm.h"
> +#include "intel_cmtg.h"
>  #include "intel_crtc.h"
>  #include "intel_de.h"
>  #include "intel_display_regs.h"
> @@ -324,6 +325,8 @@ void intel_vrr_set_fixed_rr_timings(const struct
> intel_crtc_state *crtc_state)
>  		       intel_vrr_fixed_rr_hw_vmax(crtc_state) - 1);
>  	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
>  		       intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);
> +
> +	intel_cmtg_set_vrr_timings(crtc_state);
>  }
> 
>  static
> @@ -922,6 +925,8 @@ static void intel_vrr_tg_enable(const struct
> intel_crtc_state *crtc_state,
>  		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
> 
>  	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> vrr_ctl);
> +
> +	intel_cmtg_set_vrr_ctl(crtc_state);
>  }
> 
>  static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
> --
> 2.29.0

RE: [PATCH v3 05/12] drm/i915/cmtg: set transcoder mn for CMTG

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Friday, March 13, 2026 9:03 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v3 05/12] drm/i915/cmtg: set transcoder mn for CMTG
> 
> Program CMTG link M/N.
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c      | 13 +++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h      |  1 +
>  drivers/gpu/drm/i915/display/intel_cmtg_regs.h |  3 +++
>  drivers/gpu/drm/i915/display/intel_display.c   |  1 +
>  4 files changed, 18 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 038927b8721b..0d4a8550be24 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -302,3 +302,16 @@ void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state
> *crtc_state)
> 
>  	intel_de_write(display, TRANS_VRR_CTL_CMTG(cpu_transcoder),
> vrr_ctl);  }
> +
> +void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	const struct intel_link_m_n *m_n = &crtc_state->dp_m_n;
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	intel_de_write(display, TRANS_LINKM1_CMTG(cpu_transcoder), m_n-
> >link_m);
> +	intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder),
> +m_n->link_n); }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index c92e3a62ff0d..6796eb727eef 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -11,6 +11,7 @@
>  struct intel_display;
>  struct intel_crtc_state;
> 
> +void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr); diff --git
> a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 3e94151e4daf..b91498ef5274 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -29,6 +29,9 @@
> 
>  #define TRANS_SET_CTX_LATENCY_CMTG(trans)	_MMIO(0x6F07C +
> (trans) * 0x100)
> 
> +#define TRANS_LINKM1_CMTG(trans)	_MMIO(0x6F040 + (trans) *
> 0x100)
> +#define TRANS_LINKN1_CMTG(trans)	_MMIO(0x6F044 + (trans) *
> 0x100)
> +
>  #define TRANS_VRR_CTL_CMTG(trans)	_MMIO(0x6F420 + (trans) *
> 0x100)
>  #define TRANS_VRR_VMAX_CMTG(trans)	_MMIO(0x6F424 + (trans) *
> 0x100)
>  #define TRANS_VRR_VMIN_CMTG(trans)	_MMIO(0x6F434 + (trans) *
> 0x100)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 82e4d0524d54..35f5fd02c815 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1636,6 +1636,7 @@ static void hsw_configure_cpu_transcoder(const struct
> intel_crtc_state *crtc_sta
>  		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
>  					       &crtc_state->dp_m2_n2);
>  	}

Leave a blank line

> +	intel_cmtg_set_m_n(crtc_state);

Drop blank line and keep them together.

Change Looks Good to me. With above fixed,
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>  	intel_set_transcoder_timings(crtc_state);
> 
> --
> 2.29.0

RE: [PATCH v3 06/12] drm/i915/cmtg: add hook to enable CMTG with sync to port

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Friday, March 13, 2026 9:03 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v3 06/12] drm/i915/cmtg: add hook to enable CMTG with sync to
> port
> 
> Add a hook to enable CMTG by programming CMTG CTL with Sync to Port.
> When CMTG starts running, the Sync to Port bit will be cleared. Add a wait to
> check its running status and trigger WARN_ON() on timeout.
> 

Change Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 27 ++++++++++++++++---
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
>  .../gpu/drm/i915/display/intel_cmtg_regs.h    |  4 +--
>  3 files changed, 26 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 0d4a8550be24..a802bf3e52e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -104,11 +104,11 @@ static void intel_cmtg_get_config(struct intel_display
> *display,  {
>  	u32 val;
> 
> -	val = intel_de_read(display, TRANS_CMTG_CTL_A);
> +	val = intel_de_read(display, TRANS_CMTG_CTL(TRANSCODER_A));
>  	cmtg_config->cmtg_a_enable = val & CMTG_ENABLE;
> 
>  	if (intel_cmtg_has_cmtg_b(display)) {
> -		val = intel_de_read(display, TRANS_CMTG_CTL_B);
> +		val = intel_de_read(display,
> TRANS_CMTG_CTL(TRANSCODER_B));
>  		cmtg_config->cmtg_b_enable = val & CMTG_ENABLE;
>  	}
> 
> @@ -141,14 +141,14 @@ static void intel_cmtg_disable(struct intel_display
> *display,
> 
>  	if (cmtg_config->cmtg_a_enable) {
>  		drm_dbg_kms(display->drm, "Disabling CMTG A\n");
> -		intel_de_rmw(display, TRANS_CMTG_CTL_A, CMTG_ENABLE,
> 0);
> +		intel_de_rmw(display, TRANS_CMTG_CTL(TRANSCODER_A),
> CMTG_ENABLE, 0);
>  		clk_sel_clr |= CMTG_CLK_SEL_A_MASK;
>  		clk_sel_set |= CMTG_CLK_SEL_A_DISABLED;
>  	}
> 
>  	if (cmtg_config->cmtg_b_enable) {
>  		drm_dbg_kms(display->drm, "Disabling CMTG B\n");
> -		intel_de_rmw(display, TRANS_CMTG_CTL_B, CMTG_ENABLE,
> 0);
> +		intel_de_rmw(display, TRANS_CMTG_CTL(TRANSCODER_B),
> CMTG_ENABLE, 0);
>  		clk_sel_clr |= CMTG_CLK_SEL_B_MASK;
>  		clk_sel_set |= CMTG_CLK_SEL_B_DISABLED;
>  	}
> @@ -315,3 +315,22 @@ void intel_cmtg_set_m_n(const struct intel_crtc_state
> *crtc_state)
>  	intel_de_write(display, TRANS_LINKM1_CMTG(cpu_transcoder), m_n-
> >link_m);
>  	intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder), m_n-
> >link_n);  }
> +
> +void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 cmtg_ctl;
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	cmtg_ctl = CMTG_SYNC_TO_PORT | CMTG_ENABLE;
> +
> +	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), 0, cmtg_ctl);
> +	if (intel_de_wait_for_clear_ms(display,
> TRANS_CMTG_CTL(cpu_transcoder),
> +				       CMTG_SYNC_TO_PORT, 50)) {
> +		drm_WARN(display->drm, 1, "CMTG: %s enable timeout\n",
> +			 transcoder_name(cpu_transcoder));
> +	}
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 6796eb727eef..64ff6a19948a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -11,6 +11,7 @@
>  struct intel_display;
>  struct intel_crtc_state;
> 
> +void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state); diff --git
> a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index b91498ef5274..93bdf8e23546 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -16,9 +16,9 @@
>  #define CMTG_CLK_SELECT_PHYB_ENABLE
> 	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x6)
>  #define CMTG_CLK_SEL_B_DISABLED
> 	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
> 
> -#define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
> -#define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
> +#define TRANS_CMTG_CTL(trans)		_MMIO(0x6fa88 + (trans) *
> 0x100)
>  #define  CMTG_ENABLE			REG_BIT(31)
> +#define  CMTG_SYNC_TO_PORT		REG_BIT(29)
> 
>  #define TRANS_HTOTAL_CMTG(trans)	_MMIO(0x6F000 + (trans) *
> 0x100)
>  #define TRANS_HBLANK_CMTG(trans)	_MMIO(0x6F004 + (trans) *
> 0x100)
> --
> 2.29.0

RE: [PATCH v3 07/12] drm/i915/cmtg: add a hook to enable ddi for CMTG

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Friday, March 13, 2026 9:03 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v3 07/12] drm/i915/cmtg: add a hook to enable ddi for CMTG

Commit header can be updated, this is not enabling DDI bit making it secondary.

With above fixed,
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Program DDI_FUNC_CTL2 to configure the eDP transcoder as secondary to the
> CMTG transcoder.
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c | 13 +++++++++++++
> drivers/gpu/drm/i915/display/intel_cmtg.h |  1 +
>  2 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index a802bf3e52e9..703828339d4d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -334,3 +334,16 @@ void intel_cmtg_enable_sync(const struct
> intel_crtc_state *crtc_state)
>  			 transcoder_name(cpu_transcoder));
>  	}
>  }
> +
> +void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder), 0,
> +CMTG_SECONDARY_MODE);
> +
> +	drm_dbg_kms(display->drm, "CMTG: %s enabled\n",
> +transcoder_name(cpu_transcoder)); }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 64ff6a19948a..12abbafa7d08 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -11,6 +11,7 @@
>  struct intel_display;
>  struct intel_crtc_state;
> 
> +void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
> --
> 2.29.0

RE: [PATCH v3 08/12] drm/i915/cmtg: modify existing hook to disable CMTG

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Friday, March 13, 2026 9:03 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v3 08/12] drm/i915/cmtg: modify existing hook to disable CMTG
> 
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> 
> Earlier cmtg_disable() used to disable all instances of CMTG which cannot handle
> individual request for specific CMTG instance.
> Introduce cmtg_disable_all() which will disable all cmtg instances and
> cmtg_disable() only disable specific instance.
> 
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 36 +++++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
>  .../gpu/drm/i915/display/intel_cmtg_regs.h    |  1 +
>  3 files changed, 35 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 703828339d4d..a6ac87fd552e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -125,8 +125,8 @@ static bool intel_cmtg_disable_requires_modeset(struct
> intel_display *display,
>  	return cmtg_config->trans_a_secondary || cmtg_config-
> >trans_b_secondary;  }
> 
> -static void intel_cmtg_disable(struct intel_display *display,
> -			       struct intel_cmtg_config *cmtg_config)
> +static void intel_cmtg_disable_all(struct intel_display *display,
> +				   struct intel_cmtg_config *cmtg_config)
>  {
>  	u32 clk_sel_clr = 0;
>  	u32 clk_sel_set = 0;
> @@ -157,6 +157,36 @@ static void intel_cmtg_disable(struct intel_display
> *display,
>  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
> }
> 
> +void intel_cmtg_disable(const struct intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 val;
> +
> +	if (!HAS_DC3CO(display))
> +		return;
> +
> +	if (cpu_transcoder != TRANSCODER_A && cpu_transcoder !=
> TRANSCODER_B)
> +		return;

Maybe just use intel_cmtg_is_allowed which is used throughout for CMTG.

> +
> +	val = intel_de_read(display, TRANS_VRR_CTL_CMTG(cpu_transcoder));
> +	val &= ~VRR_CTL_VRR_ENABLE;
> +	val &= ~VRR_CTL_FLIP_LINE_EN;
> +	intel_de_write(display, TRANS_VRR_CTL_CMTG(cpu_transcoder), val);

Use intel_de_rmw instead of manually doing it.

> +
> +	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder),
> +		     PORT_SYNC_MODE_ENABLE, 0);
> +
> +	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder),
> CMTG_ENABLE, 0);
> +
> +	if (intel_de_wait_for_clear_ms(display,
> TRANS_CMTG_CTL(cpu_transcoder), CMTG_STATE, 50)) {
> +		drm_WARN(display->drm, 1, "CMTG: %s disable timeout\n",
> +			 transcoder_name(cpu_transcoder));
> +		return;
> +	}
> +
> +	drm_dbg_kms(display->drm, "CMTG: %s disabled\n",
> +transcoder_name(cpu_transcoder)); }
>  /*
>   * Read out CMTG configuration and, on platforms that allow disabling it without
>   * a modeset, do it.
> @@ -184,7 +214,7 @@ void intel_cmtg_sanitize(struct intel_display *display)
>  	if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))
>  		return;
> 
> -	intel_cmtg_disable(display, &cmtg_config);
> +	intel_cmtg_disable_all(display, &cmtg_config);
>  }
> 
>  bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state) diff --git
> a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 12abbafa7d08..79785afccc51 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -11,6 +11,7 @@
>  struct intel_display;
>  struct intel_crtc_state;
> 
> +void intel_cmtg_disable(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state); diff --git
> a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 93bdf8e23546..d53891f3e3c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -19,6 +19,7 @@
>  #define TRANS_CMTG_CTL(trans)		_MMIO(0x6fa88 + (trans) *
> 0x100)
>  #define  CMTG_ENABLE			REG_BIT(31)
>  #define  CMTG_SYNC_TO_PORT		REG_BIT(29)
> +#define  CMTG_STATE			REG_BIT(23)
> 
>  #define TRANS_HTOTAL_CMTG(trans)	_MMIO(0x6F000 + (trans) *
> 0x100)
>  #define TRANS_HBLANK_CMTG(trans)	_MMIO(0x6F004 + (trans) *
> 0x100)
> --
> 2.29.0

RE: [PATCH v3 09/12] drm/i915/cmtg: Add trigger to enable/disable cmtg

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Friday, March 13, 2026 9:03 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v3 09/12] drm/i915/cmtg: Add trigger to enable/disable cmtg
> 
> Enable CMTG with fixed refresh rate mode and with dynamic dc state enabled.
> 
> Disable CMTG with transcoder disable or if there is a transition to vrr mode from
> fixed refresh rate mode.
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c          |  5 ++++-
>  drivers/gpu/drm/i915/display/intel_display.c       | 10 ++++++++++
>  drivers/gpu/drm/i915/display/intel_display_types.h |  4 ++++
>  3 files changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index a6ac87fd552e..fff299e1acfb 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -160,6 +160,7 @@ static void intel_cmtg_disable_all(struct intel_display
> *display,  void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	u32 val;
> 
> @@ -184,7 +185,7 @@ void intel_cmtg_disable(const struct intel_crtc_state
> *crtc_state)
>  			 transcoder_name(cpu_transcoder));
>  		return;

This return without setting flag to false can be an issue. Please check once.

>  	}
> -
> +	crtc->cmtg.enabled = false;

>  	drm_dbg_kms(display->drm, "CMTG: %s disabled\n",
> transcoder_name(cpu_transcoder));  }
>  /*
> @@ -368,6 +369,7 @@ void intel_cmtg_enable_sync(const struct intel_crtc_state
> *crtc_state)  void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
> {
>  	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> 
>  	if (!intel_cmtg_is_allowed(crtc_state))
> @@ -375,5 +377,6 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state
> *crtc_state)
> 
>  	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder), 0, CMTG_SECONDARY_MODE);
> 
> +	crtc->cmtg.enabled = true;
>  	drm_dbg_kms(display->drm, "CMTG: %s enabled\n",
> transcoder_name(cpu_transcoder));  } diff --git
> a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 35f5fd02c815..baf4d640bfbf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1080,6 +1080,11 @@ static void intel_post_plane_update(struct
> intel_atomic_state *state,
>  		intel_alpm_lobf_enable(new_crtc_state);
> 
>  	intel_psr_post_plane_update(state, crtc);
> +
> +	if (!crtc->cmtg.enabled && intel_vrr_is_fixed_rr(new_crtc_state)) {
> +		intel_cmtg_enable_sync(new_crtc_state);
> +		intel_cmtg_enable_ddi(new_crtc_state);
> +	}
>  }
> 
>  static void intel_post_plane_update_after_readout(struct intel_atomic_state
> *state, @@ -1793,6 +1798,8 @@ static void hsw_crtc_disable(struct
> intel_atomic_state *state,
>  	struct intel_crtc *pipe_crtc;
>  	int i;
> 
> +	if (crtc->cmtg.enabled)
> +		intel_cmtg_disable(old_crtc_state);
>  	/*
>  	 * FIXME collapse everything to one hook.
>  	 * Need care with mst->ddi interactions.
> @@ -6917,6 +6924,9 @@ static void intel_update_crtc(struct intel_atomic_state
> *state,
>  	if (intel_crtc_needs_fastset(new_crtc_state) &&
>  	    old_crtc_state->inherited)
>  		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
> +
> +	if (crtc->cmtg.enabled && intel_crtc_vrr_enabling(state, crtc))
> +		intel_cmtg_disable(new_crtc_state);
>  }
> 
>  static void intel_old_crtc_state_disables(struct intel_atomic_state *state, diff --git
> a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8a92ea4f1438..b4c3d8537a99 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1574,6 +1574,10 @@ struct intel_crtc {  #endif
> 
>  	bool vblank_psr_notify;
> +
> +	struct {
> +		bool enabled;
> +	} cmtg;
>  };
> 
>  struct intel_plane_error {
> --
> 2.29.0

RE: [PATCH v3 10/12] drm/i915/cmtg: Add CMTG interrupt handling

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Friday, March 13, 2026 9:03 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v3 10/12] drm/i915/cmtg: Add CMTG interrupt handling
> 
> Add support fot vsync, vblank, and delayed vlank interrupts of CMTG which are
> part of DE port interrupt.

Nit: Typo in for

> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 37 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  2 +
>  drivers/gpu/drm/i915/display/intel_display.c  |  5 ++-
> .../gpu/drm/i915/display/intel_display_irq.c  | 12 ++++++
> .../gpu/drm/i915/display/intel_display_regs.h |  6 +++
>  5 files changed, 61 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index fff299e1acfb..35d39f2fb86b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -13,6 +13,7 @@
>  #include "intel_crtc.h"
>  #include "intel_de.h"
>  #include "intel_display_device.h"
> +#include "intel_display_irq.h"
>  #include "intel_display_power.h"
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
> @@ -380,3 +381,39 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state
> *crtc_state)
>  	crtc->cmtg.enabled = true;
>  	drm_dbg_kms(display->drm, "CMTG: %s enabled\n",
> transcoder_name(cpu_transcoder));  }
> +
> +void intel_cmtg_mask_interrupt(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 interrupt_mask = 0;
> +
> +	if (!HAS_DC3CO(display))

Use consistent DC3co check as used in earlier patches.

> +		return;
> +
> +	if (cpu_transcoder == TRANSCODER_A)
> +		interrupt_mask = CMTG_VBLANK_A |
> CMTG_DELAYED_VBLANK_A |
> +CMTG_VSYNC_A;
> +
 
Better to use if else if instead of separate if block.

> +	if (cpu_transcoder == TRANSCODER_B)
> +		interrupt_mask = CMTG_VBLANK_B |
> CMTG_DELAYED_VBLANK_B |
> +CMTG_VSYNC_B;
> +
> +	bdw_update_port_irq(display, interrupt_mask, 0); }
> +
> +void intel_cmtg_unmask_interrupt(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 enabled_irq_mask = 0;
> +
> +	if (!HAS_DC3CO(display))
> +		return;
> +
> +	if (cpu_transcoder == TRANSCODER_A)
> +		enabled_irq_mask = CMTG_VBLANK_A |
> CMTG_DELAYED_VBLANK_A |
> +CMTG_VSYNC_A;
> +
> +	if (cpu_transcoder == TRANSCODER_B)
> +		enabled_irq_mask = CMTG_VBLANK_B |
> CMTG_DELAYED_VBLANK_B |
> +CMTG_VSYNC_B;

Logic for mask and unmask function is similar, this can be merged and managed with one function.

> +
> +	bdw_update_port_irq(display, 0, enabled_irq_mask); }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 79785afccc51..0a6fad9635ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -21,5 +21,7 @@ void intel_cmtg_set_timings(const struct intel_crtc_state
> *crtc_state, bool lrr)  void intel_cmtg_set_clk_select(const struct intel_crtc_state
> *crtc_state);  void intel_cmtg_sanitize(struct intel_display *display);  bool
> intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
> +void intel_cmtg_mask_interrupt(const struct intel_crtc_state
> +*crtc_state); void intel_cmtg_unmask_interrupt(const struct
> +intel_crtc_state *crtc_state);
> 
>  #endif /* __INTEL_CMTG_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index baf4d640bfbf..6febf569889f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1084,6 +1084,7 @@ static void intel_post_plane_update(struct
> intel_atomic_state *state,
>  	if (!crtc->cmtg.enabled && intel_vrr_is_fixed_rr(new_crtc_state)) {
>  		intel_cmtg_enable_sync(new_crtc_state);
>  		intel_cmtg_enable_ddi(new_crtc_state);
> +		intel_cmtg_unmask_interrupt(new_crtc_state);
>  	}
>  }
> 
> @@ -6925,8 +6926,10 @@ static void intel_update_crtc(struct intel_atomic_state
> *state,
>  	    old_crtc_state->inherited)
>  		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
> 
> -	if (crtc->cmtg.enabled && intel_crtc_vrr_enabling(state, crtc))
> +	if (crtc->cmtg.enabled && intel_crtc_vrr_enabling(state, crtc)) {
>  		intel_cmtg_disable(new_crtc_state);
> +		intel_cmtg_mask_interrupt(new_crtc_state);
> +	}
>  }
> 
>  static void intel_old_crtc_state_disables(struct intel_atomic_state *state, diff --git
> a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 70c1bba7c0a8..95e6523b32d9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -1467,6 +1467,18 @@ void gen8_de_irq_handler(struct intel_display
> *display, u32 master_ctl)
>  				found = true;
>  			}
> 
> +			if (DISPLAY_VER(display) > 30) {

I think better to start with >=35, I mean do from where it starts the support.

> +				if (iir & (CMTG_VBLANK_A | CMTG_VSYNC_A |
> CMTG_DELAYED_VBLANK_A)) {
> +					intel_handle_vblank(display, PIPE_A);
> +					found = true;
> +				}
> +
> +				if (iir & (CMTG_VBLANK_B | CMTG_VSYNC_B |
> CMTG_DELAYED_VBLANK_B)) {
> +					intel_handle_vblank(display, PIPE_B);
> +					found = true;
> +				}
> +			}
> +
>  			if (DISPLAY_VER(display) >= 11) {
>  				u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 4746e9ebd920..5838338f495a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -1427,6 +1427,12 @@
>  #define  GEN9_AUX_CHANNEL_B		(1 << 25)
>  #define  DSI1_TE			(1 << 24)
>  #define  DSI0_TE			(1 << 23)
> +#define  CMTG_VSYNC_B			(1 << 19)
> +#define  CMTG_DELAYED_VBLANK_B		(1 << 18)
> +#define  CMTG_VBLANK_B			(1 << 17)
> +#define  CMTG_VSYNC_A			(1 << 16)
> +#define  CMTG_DELAYED_VBLANK_A		(1 << 15)
> +#define  CMTG_VBLANK_A			(1 << 14)
>  #define  GEN8_DE_PORT_HOTPLUG(hpd_pin)	REG_BIT(3 +
> _HPD_PIN_DDI(hpd_pin))
>  #define  BXT_DE_PORT_HOTPLUG_MASK
> 	(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
> 
> GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
> --
> 2.29.0

RE: [PATCH v3 11/12] drm/i915/cmtg: set dc3co_enable flag for lobf/psr2/pr-alpm

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Friday, March 13, 2026 9:03 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v3 11/12] drm/i915/cmtg: set dc3co_enable flag for lobf/psr2/pr-
> alpm
> 
> Set the flag in specific scenarios such as LOBF/PSR2/PR-ALPM, where DC3CO
> enablement will be targeted, allowing CMTG to be programmed.
> DC3CO enablement will be implemented in a separate patch series.

Yeah, this should be done once DC3Co changes are also in place.
Plan merge accordingly.

> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index fbb5e2f9c241..53982d1e39dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7327,6 +7327,7 @@ int intel_dp_compute_config_late(struct intel_encoder
> *encoder,
>  				 struct intel_crtc_state *crtc_state,
>  				 struct drm_connector_state *conn_state)  {
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	int ret;
> 
> @@ -7338,6 +7339,13 @@ int intel_dp_compute_config_late(struct intel_encoder
> *encoder,
> 
>  	intel_alpm_lobf_compute_config_late(intel_dp, crtc_state);
> 
> +	if (HAS_DC3CO(display) && intel_dp_is_edp(intel_dp) &&
> +	    (crtc_state->has_lobf || crtc_state->has_sel_update ||
> +	     crtc_state->has_panel_replay))
> +		crtc_state->dc3co.enable = true;
> +	else
> +		crtc_state->dc3co.enable = false;
> +
>  	return 0;
>  }
> 
> --
> 2.29.0

RE: [PATCH v3 12/12] drm/i915/cmtg: disable CMTG if dc3co entry condition not met

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Friday, March 13, 2026 9:03 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v3 12/12] drm/i915/cmtg: disable CMTG if dc3co entry condition
> not met
> 
> DC3co entry condition can change dymamically and disable CMTG if entry
> condition is not met for DC3co.

Its not entry condition, but when DC3Co is disabled due to relevant reasons.
Update the commit message accordingly.

> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 6febf569889f..f20d5ebe06ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1029,6 +1029,15 @@ static bool intel_crtc_lobf_disabling(const struct
> intel_crtc_state *old_crtc_st
>  		 (new_crtc_state->update_lrr || new_crtc_state->update_m_n));  }
> 
> +static bool intel_crtc_dc3co_disabling(const struct intel_crtc_state
> *old_crtc_state,
> +				       const struct intel_crtc_state *new_crtc_state)
> {
> +	if (!old_crtc_state->hw.active)
> +		return false;
> +
> +	return is_disabling(dc3co.enable, old_crtc_state, new_crtc_state); }
> +
>  #undef is_disabling
>  #undef is_enabling
> 
> @@ -6926,7 +6935,8 @@ static void intel_update_crtc(struct intel_atomic_state
> *state,
>  	    old_crtc_state->inherited)
>  		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
> 
> -	if (crtc->cmtg.enabled && intel_crtc_vrr_enabling(state, crtc)) {
> +	if (crtc->cmtg.enabled && (intel_crtc_vrr_enabling(state, crtc) ||
> +				   intel_crtc_dc3co_disabling(old_crtc_state,
> new_crtc_state))) {
>  		intel_cmtg_disable(new_crtc_state);
>  		intel_cmtg_mask_interrupt(new_crtc_state);
>  	}
> --
> 2.29.0

Re: [PATCH v3 03/12] drm/i915/cmtg: set timings for CMTG

[Jani Nikula]

On Fri, 13 Mar 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> +#define TRANS_HTOTAL_CMTG(trans)	_MMIO(0x6F000 + (trans) * 0x100)
> +#define TRANS_HBLANK_CMTG(trans)	_MMIO(0x6F004 + (trans) * 0x100)
> +#define TRANS_HSYNC_CMTG(trans)		_MMIO(0x6F008 + (trans) * 0x100)
> +#define TRANS_VTOTAL_CMTG(trans)	_MMIO(0x6F00C + (trans) * 0x100)
> +#define TRANS_VBLANK_CMTG(trans)	_MMIO(0x6F010 + (trans) * 0x100)
> +#define TRANS_VSYNC_CMTG(trans)		_MMIO(0x6F014 + (trans) * 0x100)
> +
> +#define TRANS_SET_CTX_LATENCY_CMTG(trans)	_MMIO(0x6F07C + (trans) * 0x100)

We have a bunch of helpers to avoid doing the manual multiplication
here.

BR,
Jani.


-- 
Jani Nikula, Intel

Re: [PATCH v3 01/12] drm/i915/cmtg: add is_enable_allowed() for cmtg

[Dibin Moolakadan Subrahmanian]

On 07-04-2026 00:18, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: Manna, Animesh <animesh.manna@intel.com>
>> Sent: Friday, March 13, 2026 9:03 PM
>> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
>> <animesh.manna@intel.com>
>> Subject: [PATCH v3 01/12] drm/i915/cmtg: add is_enable_allowed() for cmtg
> Nit: Name here in subject doesn't match the actual function. Better to use exact same name.
>
>> Introduce a flag for DC3co. CMTG will be enabled only with DC3co so add a
>> separate function is_allowed() for cmtg. DC3co flag will be enabled in a separate
>> patch.
>>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_cmtg.c          | 14 ++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_cmtg.h          |  2 ++
>>   .../gpu/drm/i915/display/intel_display_device.h    |  1 +
>>   drivers/gpu/drm/i915/display/intel_display_types.h |  4 ++++
>>   4 files changed, 21 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
>> b/drivers/gpu/drm/i915/display/intel_cmtg.c
>> index e1fdc6fe9762..024d753eca55 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
>> @@ -16,6 +16,7 @@
>>   #include "intel_display_device.h"
>>   #include "intel_display_power.h"
>>   #include "intel_display_regs.h"
>> +#include "intel_display_types.h"
>>
>>   /**
>>    * DOC: Common Primary Timing Generator (CMTG) @@ -185,3 +186,16 @@
>> void intel_cmtg_sanitize(struct intel_display *display)
>>
>>   	intel_cmtg_disable(display, &cmtg_config);  }
>> +
>> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state) {
>> +	struct intel_display *display = to_intel_display(crtc_state);
>> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> +
>> +	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder ==
>> TRANSCODER_B) &&
>> +	    HAS_DC3CO(display) && intel_crtc_has_type(crtc_state,
>> INTEL_OUTPUT_EDP) &&
>> +	    crtc_state->dc3co.enable)
> Don't think we need both HAS_DC3CO and dc3co.enable here. Later should never be set if HAS_DC3CO
> not true.
>
>> +		return true;
>> +
>> +	return false;
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
>> b/drivers/gpu/drm/i915/display/intel_cmtg.h
>> index ba62199adaa2..7692cc98cf87 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
>> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
>> @@ -7,7 +7,9 @@
>>   #define __INTEL_CMTG_H__
>>
>>   struct intel_display;
>> +struct intel_crtc_state;
>>
>>   void intel_cmtg_sanitize(struct intel_display *display);
>> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
>>
>>   #endif /* __INTEL_CMTG_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
>> b/drivers/gpu/drm/i915/display/intel_display_device.h
>> index e84c190dcc4f..35e06fcf794d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
>> @@ -189,6 +189,7 @@ struct intel_display_platforms {
>>   #define HAS_LRR(__display)		(DISPLAY_VER(__display) >= 12)
>>   #define HAS_LSPCON(__display)		(IS_DISPLAY_VER(__display, 9,
>> 10))
>>   #define HAS_LT_PHY(__display)		((__display)->platform.novalake)
>> +#define HAS_DC3CO(__display)		((__display)->platform.novalake)
>>   #define HAS_MBUS_JOINING(__display)	((__display)->platform.alderlake_p
>> || DISPLAY_VER(__display) >= 14)
>>   #define HAS_MSO(__display)		(DISPLAY_VER(__display) >= 12)
>>   #define HAS_OVERLAY(__display)		(DISPLAY_INFO(__display)-
>>> has_overlay)
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index e189f8c39ccb..8a92ea4f1438 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1434,6 +1434,10 @@ struct intel_crtc_state {
>>
>>   	/* to track changes in plane color blocks */
>>   	bool plane_color_changed;
>> +
>> +	struct {
>> +		bool enable;
>> +	} dc3co;
>>   };

DC3CO shouldn’t be part of struct intel_crtc_state.
It’s a global display power feature, not per-CRTC state.
struct intel_atomic_state would be a more appropriate place to track this.

>>   enum intel_pipe_crc_source {
>> --
>> 2.29.0

Re: [PATCH v3 03/12] drm/i915/cmtg: set timings for CMTG

[Ville Syrjälä]

On Tue, Apr 07, 2026 at 11:03:37AM +0300, Jani Nikula wrote:
> On Fri, 13 Mar 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> > +#define TRANS_HTOTAL_CMTG(trans)	_MMIO(0x6F000 + (trans) * 0x100)
> > +#define TRANS_HBLANK_CMTG(trans)	_MMIO(0x6F004 + (trans) * 0x100)
> > +#define TRANS_HSYNC_CMTG(trans)		_MMIO(0x6F008 + (trans) * 0x100)
> > +#define TRANS_VTOTAL_CMTG(trans)	_MMIO(0x6F00C + (trans) * 0x100)
> > +#define TRANS_VBLANK_CMTG(trans)	_MMIO(0x6F010 + (trans) * 0x100)
> > +#define TRANS_VSYNC_CMTG(trans)		_MMIO(0x6F014 + (trans) * 0x100)
> > +
> > +#define TRANS_SET_CTX_LATENCY_CMTG(trans)	_MMIO(0x6F07C + (trans) * 0x100)

These are all just normal transcoder registers, so no new definitions
should be necessary at all.

> 
> We have a bunch of helpers to avoid doing the manual multiplication
> here.
> 
> BR,
> Jani.
> 
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH v3 01/12] drm/i915/cmtg: add is_enable_allowed() for cmtg

[Ville Syrjälä]

On Tue, Apr 07, 2026 at 02:29:46PM +0530, Dibin Moolakadan Subrahmanian wrote:
> On 07-04-2026 00:18, Shankar, Uma wrote:
> >
> >> -----Original Message-----
> >> From: Manna, Animesh <animesh.manna@intel.com>
> >> Sent: Friday, March 13, 2026 9:03 PM
> >> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> >> Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> >> <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> >> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> >> <animesh.manna@intel.com>
> >> Subject: [PATCH v3 01/12] drm/i915/cmtg: add is_enable_allowed() for cmtg
> > Nit: Name here in subject doesn't match the actual function. Better to use exact same name.
> >
> >> Introduce a flag for DC3co. CMTG will be enabled only with DC3co so add a
> >> separate function is_allowed() for cmtg. DC3co flag will be enabled in a separate
> >> patch.
> >>
> >> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/display/intel_cmtg.c          | 14 ++++++++++++++
> >>   drivers/gpu/drm/i915/display/intel_cmtg.h          |  2 ++
> >>   .../gpu/drm/i915/display/intel_display_device.h    |  1 +
> >>   drivers/gpu/drm/i915/display/intel_display_types.h |  4 ++++
> >>   4 files changed, 21 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> >> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> >> index e1fdc6fe9762..024d753eca55 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> >> @@ -16,6 +16,7 @@
> >>   #include "intel_display_device.h"
> >>   #include "intel_display_power.h"
> >>   #include "intel_display_regs.h"
> >> +#include "intel_display_types.h"
> >>
> >>   /**
> >>    * DOC: Common Primary Timing Generator (CMTG) @@ -185,3 +186,16 @@
> >> void intel_cmtg_sanitize(struct intel_display *display)
> >>
> >>   	intel_cmtg_disable(display, &cmtg_config);  }
> >> +
> >> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state) {
> >> +	struct intel_display *display = to_intel_display(crtc_state);
> >> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >> +
> >> +	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder ==
> >> TRANSCODER_B) &&
> >> +	    HAS_DC3CO(display) && intel_crtc_has_type(crtc_state,
> >> INTEL_OUTPUT_EDP) &&
> >> +	    crtc_state->dc3co.enable)
> > Don't think we need both HAS_DC3CO and dc3co.enable here. Later should never be set if HAS_DC3CO
> > not true.
> >
> >> +		return true;
> >> +
> >> +	return false;
> >> +}
> >> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> >> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> >> index ba62199adaa2..7692cc98cf87 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> >> @@ -7,7 +7,9 @@
> >>   #define __INTEL_CMTG_H__
> >>
> >>   struct intel_display;
> >> +struct intel_crtc_state;
> >>
> >>   void intel_cmtg_sanitize(struct intel_display *display);
> >> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
> >>
> >>   #endif /* __INTEL_CMTG_H__ */
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> >> b/drivers/gpu/drm/i915/display/intel_display_device.h
> >> index e84c190dcc4f..35e06fcf794d 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> >> @@ -189,6 +189,7 @@ struct intel_display_platforms {
> >>   #define HAS_LRR(__display)		(DISPLAY_VER(__display) >= 12)
> >>   #define HAS_LSPCON(__display)		(IS_DISPLAY_VER(__display, 9,
> >> 10))
> >>   #define HAS_LT_PHY(__display)		((__display)->platform.novalake)
> >> +#define HAS_DC3CO(__display)		((__display)->platform.novalake)
> >>   #define HAS_MBUS_JOINING(__display)	((__display)->platform.alderlake_p
> >> || DISPLAY_VER(__display) >= 14)
> >>   #define HAS_MSO(__display)		(DISPLAY_VER(__display) >= 12)
> >>   #define HAS_OVERLAY(__display)		(DISPLAY_INFO(__display)-
> >>> has_overlay)
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> >> b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> index e189f8c39ccb..8a92ea4f1438 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> @@ -1434,6 +1434,10 @@ struct intel_crtc_state {
> >>
> >>   	/* to track changes in plane color blocks */
> >>   	bool plane_color_changed;
> >> +
> >> +	struct {
> >> +		bool enable;
> >> +	} dc3co;
> >>   };
> 
> DC3CO shouldn’t be part of struct intel_crtc_state.
> It’s a global display power feature, not per-CRTC state.
> struct intel_atomic_state would be a more appropriate place to track this.

intel_atomic_state isn't actually a state, and so should not be used
to track anything. To better reflect its role drm_atomic_state will
soon be renamed to drm_atomic_commit, and we need to follow up with
the corresponding intel_atomic_* rename.

-- 
Ville Syrjälä
Intel

Re: [PATCH v3 03/12] drm/i915/cmtg: set timings for CMTG

[Jani Nikula]

On Tue, 07 Apr 2026, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Apr 07, 2026 at 11:03:37AM +0300, Jani Nikula wrote:
>> On Fri, 13 Mar 2026, Animesh Manna <animesh.manna@intel.com> wrote:
>> > +#define TRANS_HTOTAL_CMTG(trans)	_MMIO(0x6F000 + (trans) * 0x100)
>> > +#define TRANS_HBLANK_CMTG(trans)	_MMIO(0x6F004 + (trans) * 0x100)
>> > +#define TRANS_HSYNC_CMTG(trans)		_MMIO(0x6F008 + (trans) * 0x100)
>> > +#define TRANS_VTOTAL_CMTG(trans)	_MMIO(0x6F00C + (trans) * 0x100)
>> > +#define TRANS_VBLANK_CMTG(trans)	_MMIO(0x6F010 + (trans) * 0x100)
>> > +#define TRANS_VSYNC_CMTG(trans)		_MMIO(0x6F014 + (trans) * 0x100)
>> > +
>> > +#define TRANS_SET_CTX_LATENCY_CMTG(trans)	_MMIO(0x6F07C + (trans) * 0x100)
>
> These are all just normal transcoder registers, so no new definitions
> should be necessary at all.

Right, so the question becomes why are their writes duplicated, and
what's with the whole "Timing registers are separate for CMTG" part in
the commit message???

BR,
Jani.

>
>> 
>> We have a bunch of helpers to avoid doing the manual multiplication
>> here.
>> 
>> BR,
>> Jani.
>> 
>> 
>> -- 
>> Jani Nikula, Intel

-- 
Jani Nikula, Intel

RE: [PATCH v3 03/12] drm/i915/cmtg: set timings for CMTG

[Manna, Animesh]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, April 7, 2026 4:33 PM
> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; Shankar, Uma
> <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Subject: Re: [PATCH v3 03/12] drm/i915/cmtg: set timings for CMTG
> 
> On Tue, 07 Apr 2026, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Tue, Apr 07, 2026 at 11:03:37AM +0300, Jani Nikula wrote:
> >> On Fri, 13 Mar 2026, Animesh Manna <animesh.manna@intel.com>
> wrote:
> >> > +#define TRANS_HTOTAL_CMTG(trans)	_MMIO(0x6F000 + (trans) *
> 0x100)
> >> > +#define TRANS_HBLANK_CMTG(trans)	_MMIO(0x6F004 + (trans) *
> 0x100)
> >> > +#define TRANS_HSYNC_CMTG(trans)		_MMIO(0x6F008 +
> (trans) * 0x100)
> >> > +#define TRANS_VTOTAL_CMTG(trans)	_MMIO(0x6F00C + (trans) *
> 0x100)
> >> > +#define TRANS_VBLANK_CMTG(trans)	_MMIO(0x6F010 + (trans) *
> 0x100)
> >> > +#define TRANS_VSYNC_CMTG(trans)		_MMIO(0x6F014 +
> (trans) * 0x100)
> >> > +
> >> > +#define TRANS_SET_CTX_LATENCY_CMTG(trans)	_MMIO(0x6F07C +
> (trans) * 0x100)
> >
> > These are all just normal transcoder registers, so no new definitions
> > should be necessary at all.
> 
> Right, so the question becomes why are their writes duplicated, and what's
> with the whole "Timing registers are separate for CMTG" part in the commit
> message???

As per my understanding CMTG will be used with dynamic dc-state enabled which means normal transcoder along with pipe can go to low power state.
So, write is duplicated and completely dependent on h/w design.
The offset difference between two CMTG transcoder registers is also different compared to normal transcoder registers.
I have used _MMIO_TRANS() in latest version instead of manual multiplication. Good to know any further feedback.

Regards,
Animesh
> 
> BR,
> Jani.
> 
> >
> >>
> >> We have a bunch of helpers to avoid doing the manual multiplication
> >> here.
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >> --
> >> Jani Nikula, Intel
> 
> --
> Jani Nikula, Intel