From: Riana Tauro <riana.tauro@intel.com>
To: Raag Jadav <raag.jadav@intel.com>
Cc: <intel-xe@lists.freedesktop.org>, <anshuman.gupta@intel.com>,
<rodrigo.vivi@intel.com>, <aravind.iddamsetty@linux.intel.com>,
<badal.nilawar@intel.com>, <ravi.kishore.koppuravuri@intel.com>,
<mallesh.koujalagi@intel.com>
Subject: Re: [PATCH 7/8] drm/xe/xe_ras: Add support for Uncorrectable Core-Compute errors
Date: Mon, 23 Feb 2026 19:40:08 +0530 [thread overview]
Message-ID: <ade5dea5-07b6-4334-922b-57fc8b00a178@intel.com> (raw)
In-Reply-To: <aZR1ARo309W6gMxX@black.igk.intel.com>
On 2/17/2026 7:32 PM, Raag Jadav wrote:
> On Thu, Jan 22, 2026 at 03:36:19PM +0530, Riana Tauro wrote:
>> Uncorrectable Core-Compute errors are classified into Global and Local
>> errors.
>>
>> Global error is an error that affects the entire device requiring a
>> reset. This type of error is not isolated. When an AER is reported and
>> error_detected is invoked return PCI_ERS_RESULT_NEED_RESET.
>>
>> A Local error is confined to a specific component or context like a
>> engine. These errors can be contained and recovered by resetting
>> only the affected part without distrupting the rest of the device.
>>
>> Upon detection of an Uncorrectable Local Core-Compute error, an AER is
>> generated and GuC is notified of the error. The KMD then sets
>> the context as non-runnable and initiates an engine reset.
>> (TODO: GuC <->KMD communication for the error).
>> Since the error is contained and recovered, PCI error handling
>> callback returns PCI_ERS_RESULT_RECOVERED.
>
> ...
>
>> +/**
>> + * xe_ras_process_errors - Process and contain hardware errors
>> + * @xe: xe device instance
>> + *
>> + * Get error details from system controller and return recovery
>> + * method. Called only from PCI error handling.
>> + *
>> + * Returns: PCI_ERS_RESULT_RECOVERED if recovered or if no recovery needed,
>> + * PCI_ERS_RESULT_NEED_RESET otherwise.
>
> PCI error codes are unrelated to xe_ras. IMO let's use standard error
> codes here and translate them to PCI ones in the callbacks.
Yeah agreed. I had originally implemented RAS specific enums but then
removed it since it was same as PCI enums.
We can't use normal error codes here and map. We could have XE RAS
specific enum and then map in callbacks
Thanks
Riana
>
> Raag
>
>> + */
next prev parent reply other threads:[~2026-02-23 14:10 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-22 10:06 [PATCH 0/8] Introduce Xe Uncorrectable Error Handling Riana Tauro
2026-01-22 9:42 ` ✗ CI.checkpatch: warning for " Patchwork
2026-01-22 9:43 ` ✓ CI.KUnit: success " Patchwork
2026-01-22 10:06 ` [PATCH 1/8] drm/xe/xe_sysctrl: Add System controller patch Riana Tauro
2026-01-22 10:06 ` [PATCH 2/8] drm/xe/xe_pci_error: Implement PCI error recovery callbacks Riana Tauro
2026-01-27 22:49 ` Michal Wajdeczko
2026-02-02 9:45 ` Riana Tauro
2026-01-29 9:09 ` Nilawar, Badal
2026-02-02 13:19 ` Nilawar, Badal
2026-02-03 3:46 ` Riana Tauro
2026-02-03 3:41 ` Riana Tauro
2026-02-08 8:02 ` Raag Jadav
2026-02-24 3:23 ` Riana Tauro
2026-02-24 5:33 ` Raag Jadav
2026-02-16 8:53 ` Mallesh, Koujalagi
2026-02-24 3:26 ` Riana Tauro
2026-01-22 10:06 ` [PATCH 3/8] drm/xe/xe_pci_error: Group all devres to release them on PCIe slot reset Riana Tauro
2026-01-27 11:23 ` Mallesh, Koujalagi
2026-02-02 8:46 ` Riana Tauro
2026-01-22 10:06 ` [PATCH 4/8] drm/xe: Skip device access during PCI error recovery Riana Tauro
2026-01-22 10:06 ` [PATCH 5/8] drm/xe/xe_ras: Initialize Uncorrectable AER Registers Riana Tauro
2026-01-27 12:41 ` Mallesh, Koujalagi
2026-02-02 9:34 ` Riana Tauro
2026-02-04 8:38 ` Aravind Iddamsetty
2026-02-16 12:27 ` Mallesh, Koujalagi
2026-02-18 14:48 ` Riana Tauro
2026-01-22 10:06 ` [PATCH 6/8] drm/xe/xe_ras: Add structures and commands for Uncorrectable Core Compute Errors Riana Tauro
2026-02-23 14:19 ` Mallesh, Koujalagi
2026-02-23 14:30 ` Riana Tauro
2026-01-22 10:06 ` [PATCH 7/8] drm/xe/xe_ras: Add support for Uncorrectable Core-Compute errors Riana Tauro
2026-01-27 11:44 ` Mallesh, Koujalagi
2026-02-02 8:38 ` Riana Tauro
2026-01-27 14:03 ` Mallesh, Koujalagi
2026-02-02 8:54 ` Riana Tauro
2026-02-24 12:17 ` Mallesh, Koujalagi
2026-02-17 14:02 ` Raag Jadav
2026-02-23 14:10 ` Riana Tauro [this message]
2026-01-22 10:06 ` [PATCH 8/8] drm/xe/xe_pci_error: Process errors in mmio_enabled Riana Tauro
2026-02-24 12:46 ` Mallesh, Koujalagi
2026-01-22 10:21 ` ✓ Xe.CI.BAT: success for Introduce Xe Uncorrectable Error Handling Patchwork
2026-01-22 20:28 ` ✗ Xe.CI.Full: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ade5dea5-07b6-4334-922b-57fc8b00a178@intel.com \
--to=riana.tauro@intel.com \
--cc=anshuman.gupta@intel.com \
--cc=aravind.iddamsetty@linux.intel.com \
--cc=badal.nilawar@intel.com \
--cc=intel-xe@lists.freedesktop.org \
--cc=mallesh.koujalagi@intel.com \
--cc=raag.jadav@intel.com \
--cc=ravi.kishore.koppuravuri@intel.com \
--cc=rodrigo.vivi@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox