[PATCH v4 0/2] USE drm mm instead of drm SA for CCS read/write

[PATCH v4 0/2] USE drm mm instead of drm SA for CCS read/write

[Satyanarayana K V P]

The suballocator algorithm tracks a hole cursor at the last allocation
and tries to allocate after it. This is optimized for fence-ordered
progress, where older allocations are expected to become reusable first.

In fence-enabled mode, that ordering assumption holds. In fence-disabled
mode, allocations may be freed in arbitrary order, so limiting allocation
to the current hole window can miss valid free space and fail allocations
despite sufficient total space.

Use DRM memory manager instead of sub-allocator to get rid of this issue
as CCS read/write operations do not use fences.

Used drm mm instead of drm sa based on comments from
https://lore.kernel.org/all/bbf0d48d-a95a-46e1-ac8f-e8a0daa81365@amd.com/

---
V3 -> V4:
- Cleaned documentation.
- Squashed chnages from xe_bb.c to xe_mem_pool.c
- Made xe_mem_pool_shadow_init() local.
- Renamed the xe_mem_pool_manager to xe_mem_pool.
- Fixed some other review comments.
- Cached iomem status in mem_pool, as the pool->cpu_addr need to be freed
in xe_mem_pool_fini() which is part of drm cleanup, but the BO is part of
devm cleanup.

V2 -> V3:
- Used xe_mem_pool_init() and xe_mem_pool_shadow_init() to allocate BB
pools.
- Renamed xe_mm_suballoc to xe_mem_pool_manager
- Splitted xe_mm_suballoc_manager_init() into xe_mem_pool_init() and
xe_mem_pool_shadow_init() (Michal)
- Made xe_mm_sa_manager structure private. (Matt)
- Introduced init flags to initialize allocated pools.

V1 -> V2:
- Renamed xe_drm_mm to xe_mm_suballoc (Thomas)
- Removed memset from xe_drm_mm_bb_insert() (Matt).
- Removed memset during manager init and insert (Matt)

Satyanarayana K V P (2):
  drm/xe: Add memory pool with shadow support
  drm/xe/vf: Use drm mm instead of drm sa for CCS read/write

 drivers/gpu/drm/xe/Makefile                |   1 +
 drivers/gpu/drm/xe/xe_bo_types.h           |   3 +-
 drivers/gpu/drm/xe/xe_mem_pool.c           | 403 +++++++++++++++++++++
 drivers/gpu/drm/xe/xe_mem_pool.h           |  35 ++
 drivers/gpu/drm/xe/xe_mem_pool_types.h     |  21 ++
 drivers/gpu/drm/xe/xe_migrate.c            |  56 +--
 drivers/gpu/drm/xe/xe_sriov_vf_ccs.c       |  54 +--
 drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h |   5 +-
 8 files changed, 523 insertions(+), 55 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/xe_mem_pool.c
 create mode 100644 drivers/gpu/drm/xe/xe_mem_pool.h
 create mode 100644 drivers/gpu/drm/xe/xe_mem_pool_types.h

-- 
2.43.0

[PATCH v4 1/2] drm/xe: Add memory pool with shadow support

[Satyanarayana K V P]

Add a memory pool to allocate sub-ranges from a BO-backed pool
using drm_mm.

Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Maarten Lankhorst <dev@lankhorst.se>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>

---
V3 -> V4:
- Cleaned documentation.
- Squashed chnages from xe_bb.c to xe_mem_pool.c
- Made xe_mem_pool_shadow_init() local.
- Renamed the xe_mem_pool_manager to xe_mem_pool.
- Fixed some other review comments.
- Cached iomem status in mem_pool, as the pool->cpu_addr need to be freed
in xe_mem_pool_fini() which is part of drm cleanup, but the BO is part of
devm cleanup.

V2 -> V3:
- Renamed xe_mm_suballoc to xe_mem_pool_manager.
- Splitted xe_mm_suballoc_manager_init() into xe_mem_pool_init() and
xe_mem_pool_shadow_init() (Michal)
- Made xe_mm_sa_manager structure private. (Matt)
- Introduced init flags to initialize allocated pools.

V1 -> V2:
- Renamed xe_drm_mm to xe_mm_suballoc (Thomas)
- Removed memset during manager init and insert (Matt)
---
 drivers/gpu/drm/xe/Makefile            |   1 +
 drivers/gpu/drm/xe/xe_mem_pool.c       | 403 +++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_mem_pool.h       |  35 +++
 drivers/gpu/drm/xe/xe_mem_pool_types.h |  21 ++
 4 files changed, 460 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/xe_mem_pool.c
 create mode 100644 drivers/gpu/drm/xe/xe_mem_pool.h
 create mode 100644 drivers/gpu/drm/xe/xe_mem_pool_types.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 110fef511fe2..e42e582aca5c 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -88,6 +88,7 @@ xe-y += xe_bb.o \
 	xe_irq.o \
 	xe_late_bind_fw.o \
 	xe_lrc.o \
+	xe_mem_pool.o \
 	xe_migrate.o \
 	xe_mmio.o \
 	xe_mmio_gem.o \
diff --git a/drivers/gpu/drm/xe/xe_mem_pool.c b/drivers/gpu/drm/xe/xe_mem_pool.c
new file mode 100644
index 000000000000..d5e24d6aa88d
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_mem_pool.c
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <linux/kernel.h>
+
+#include <drm/drm_managed.h>
+
+#include "instructions/xe_mi_commands.h"
+#include "xe_bo.h"
+#include "xe_device_types.h"
+#include "xe_map.h"
+#include "xe_mem_pool.h"
+#include "xe_mem_pool_types.h"
+#include "xe_tile_printk.h"
+
+/**
+ * struct xe_mem_pool - DRM MM pool for sub-allocating memory from a BO on an
+ * XE tile.
+ *
+ * The XE memory pool is a DRM MM manager that provides sub-allocation of memory
+ * from a backing buffer object (BO) on a specific XE tile. It is designed to
+ * manage memory for GPU workloads, allowing for efficient allocation and
+ * deallocation of memory regions within the BO.
+ *
+ * The memory pool maintains a primary BO that is pinned in the GGTT and mapped
+ * into the CPU address space for direct access. Optionally, it can also maintain
+ * a shadow BO that can be used for atomic updates to the primary BO's contents.
+ *
+ * The API provided by the memory pool allows clients to allocate and free memory
+ * regions, retrieve GPU and CPU addresses, and synchronize data between the
+ * primary and shadow BOs as needed.
+ */
+struct xe_mem_pool {
+	/** @base: Range allocator over [0, @size) in bytes */
+	struct drm_mm base;
+	/** @bo: Active pool BO (GGTT-pinned, CPU-mapped). */
+	struct xe_bo *bo;
+	/** @shadow: Shadow BO for atomic command updates. */
+	struct xe_bo *shadow;
+	/** @swap_guard: Timeline guard updating @bo and @shadow */
+	struct mutex swap_guard;
+	/** @cpu_addr: CPU virtual address of the active BO. */
+	void *cpu_addr;
+	/** @is_iomem: Indicates if the BO mapping is I/O memory. */
+	bool is_iomem;
+};
+
+static struct xe_mem_pool *node_to_pool(struct xe_mem_pool_node *node)
+{
+	return container_of(node->sa_node.mm, struct xe_mem_pool, base);
+}
+
+static struct xe_tile *pool_to_tile(struct xe_mem_pool *pool)
+{
+	return pool->bo->tile;
+}
+
+static void fini_pool_action(struct drm_device *drm, void *arg)
+{
+	struct xe_mem_pool *pool = arg;
+
+	if (pool->is_iomem)
+		kvfree(pool->cpu_addr);
+
+	drm_mm_takedown(&pool->base);
+}
+
+static int pool_shadow_init(struct xe_mem_pool *pool)
+{
+	struct xe_tile *tile = pool->bo->tile;
+	struct xe_device *xe = tile_to_xe(tile);
+	struct xe_bo *shadow;
+	int ret;
+
+	xe_assert(xe, !pool->shadow);
+
+	ret = drmm_mutex_init(&xe->drm, &pool->swap_guard);
+	if (ret)
+		return ret;
+
+	if (IS_ENABLED(CONFIG_PROVE_LOCKING)) {
+		fs_reclaim_acquire(GFP_KERNEL);
+		might_lock(&pool->swap_guard);
+		fs_reclaim_release(GFP_KERNEL);
+	}
+	shadow = xe_managed_bo_create_pin_map(xe, tile,
+					      xe_bo_size(pool->bo),
+					      XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+					      XE_BO_FLAG_GGTT |
+					      XE_BO_FLAG_GGTT_INVALIDATE |
+					      XE_BO_FLAG_PINNED_NORESTORE);
+	if (IS_ERR(shadow))
+		return PTR_ERR(shadow);
+
+	pool->shadow = shadow;
+
+	return 0;
+}
+
+/**
+ * xe_mem_pool_init() - Initialize memory pool.
+ * @tile: the &xe_tile where allocate.
+ * @size: number of bytes to allocate.
+ * @guard: the size of the guard region at the end of the BO that is not
+ * sub-allocated, in bytes.
+ * @flags: flags to use to create shadow pool.
+ *
+ * Initializes a memory pool for sub-allocating memory from a backing BO on the
+ * specified XE tile. The backing BO is pinned in the GGTT and mapped into
+ * the CPU address space for direct access. Optionally, a shadow BO can also be
+ * initialized for atomic updates to the primary BO's contents.
+ *
+ * Returns: a pointer to the &xe_mem_pool, or an error pointer on failure.
+ */
+struct xe_mem_pool *xe_mem_pool_init(struct xe_tile *tile, u32 size,
+				     u32 guard, int flags)
+{
+	struct xe_device *xe = tile_to_xe(tile);
+	struct xe_mem_pool *pool;
+	struct xe_bo *bo;
+	u32 managed_size;
+	int ret;
+
+	xe_tile_assert(tile, size > guard);
+	managed_size = size - guard;
+
+	pool = drmm_kzalloc(&xe->drm, sizeof(*pool), GFP_KERNEL);
+	if (!pool)
+		return ERR_PTR(-ENOMEM);
+
+	bo = xe_managed_bo_create_pin_map(xe, tile, size,
+					  XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+					  XE_BO_FLAG_GGTT |
+					  XE_BO_FLAG_GGTT_INVALIDATE |
+					  XE_BO_FLAG_PINNED_NORESTORE);
+	if (IS_ERR(bo)) {
+		xe_tile_err(tile, "Failed to prepare %uKiB BO for mem pool (%pe)\n",
+			    size / SZ_1K, bo);
+		return ERR_CAST(bo);
+	}
+	pool->bo = bo;
+	pool->is_iomem = bo->vmap.is_iomem;
+
+	if (pool->is_iomem) {
+		pool->cpu_addr = kvzalloc(size, GFP_KERNEL);
+		if (!pool->cpu_addr)
+			return ERR_PTR(-ENOMEM);
+	} else {
+		pool->cpu_addr = bo->vmap.vaddr;
+	}
+
+	if (flags & XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY) {
+		ret = pool_shadow_init(pool);
+
+		if (ret)
+			goto out_err;
+	}
+
+	drm_mm_init(&pool->base, 0, managed_size);
+	ret = drmm_add_action_or_reset(&xe->drm, fini_pool_action, pool);
+	if (ret)
+		return ERR_PTR(ret);
+
+	return pool;
+
+out_err:
+	if (flags & XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY)
+		xe_tile_err(tile,
+			    "Failed to initialize shadow BO for mem pool (%d)\n", ret);
+	if (bo->vmap.is_iomem)
+		kvfree(pool->cpu_addr);
+	return ERR_PTR(ret);
+}
+
+/**
+ * xe_mem_pool_sync() - Copy the entire contents of the main pool to shadow pool.
+ * @pool: the memory pool containing the primary and shadow BOs.
+ *
+ * Copies the entire contents of the primary pool to the shadow pool. This must
+ * be done after xe_mem_pool_init() with the XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY
+ * flag to ensure that the shadow pool has the same initial contents as the primary
+ * pool. After this initial synchronization, clients can choose to synchronize the
+ * shadow pool with the primary pool on a node  basis using
+ * xe_mem_pool_sync_shadow_locked() as needed.
+ *
+ * Return: None.
+ */
+void xe_mem_pool_sync(struct xe_mem_pool *pool)
+{
+	struct xe_tile *tile = pool_to_tile(pool);
+	struct xe_device *xe = tile_to_xe(tile);
+
+	xe_tile_assert(tile, pool->shadow);
+
+	xe_map_memcpy_to(xe, &pool->shadow->vmap, 0,
+			 pool->cpu_addr, xe_bo_size(pool->bo));
+}
+
+/**
+ * xe_mem_pool_swap_shadow_locked() - Swap the primary BO with the shadow BO.
+ * @pool: the memory pool containing the primary and shadow BOs.
+ *
+ * Swaps the primary buffer object with the shadow buffer object in the mem
+ * pool. This allows for atomic updates to the contents of the primary BO
+ * by first writing to the shadow BO and then swapping it with the primary BO.
+ * Swap_guard must be held to ensure synchronization with any concurrent swap
+ * operations.
+ *
+ * Return: None.
+ */
+void xe_mem_pool_swap_shadow_locked(struct xe_mem_pool *pool)
+{
+	struct xe_tile *tile = pool_to_tile(pool);
+
+	xe_tile_assert(tile, pool->shadow);
+	lockdep_assert_held(&pool->swap_guard);
+
+	swap(pool->bo, pool->shadow);
+	if (!pool->bo->vmap.is_iomem)
+		pool->cpu_addr = pool->bo->vmap.vaddr;
+}
+
+/**
+ * xe_mem_pool_sync_shadow_locked() - Copy node from primary pool to shadow pool.
+ * @node: the node allocated in the memory pool.
+ *
+ * Copies the specified batch buffer from the primary pool to the shadow pool.
+ * Swap_guard must be held to ensure synchronization with any concurrent swap
+ * operations.
+ *
+ * Return: None.
+ */
+void xe_mem_pool_sync_shadow_locked(struct xe_mem_pool_node *node)
+{
+	struct xe_mem_pool *pool = node_to_pool(node);
+	struct xe_tile *tile = pool_to_tile(pool);
+	struct xe_device *xe = tile_to_xe(tile);
+	struct drm_mm_node *sa_node = &node->sa_node;
+
+	xe_tile_assert(tile, pool->shadow);
+	lockdep_assert_held(&pool->swap_guard);
+
+	xe_map_memcpy_to(xe, &pool->shadow->vmap,
+			 sa_node->start,
+			 pool->cpu_addr + sa_node->start,
+			 sa_node->size);
+}
+
+/**
+ * xe_mem_pool_gpu_addr() - Retrieve GPU address of memory pool.
+ * @pool: the memory pool
+ *
+ * Returns: GGTT address of the memory pool.
+ */
+u64 xe_mem_pool_gpu_addr(struct xe_mem_pool *pool)
+{
+	return xe_bo_ggtt_addr(pool->bo);
+}
+
+/**
+ * xe_mem_pool_cpu_addr() - Retrieve CPU address of manager pool.
+ * @pool: the memory pool
+ *
+ * Returns: CPU virtual address of memory pool.
+ */
+void *xe_mem_pool_cpu_addr(struct xe_mem_pool *pool)
+{
+	return pool->cpu_addr;
+}
+
+/**
+ * xe_mem_pool_bo_swap_guard() - Retrieve the mutex used to guard swap
+ * operations on a memory pool.
+ * @pool: the memory pool
+ *
+ * Returns: Swap guard mutex or NULL if shadow pool is not created.
+ */
+struct mutex *xe_mem_pool_bo_swap_guard(struct xe_mem_pool *pool)
+{
+	if (!pool->shadow)
+		return NULL;
+
+	return &pool->swap_guard;
+}
+
+/**
+ * xe_mem_pool_bo_flush_write() - Copy the data from the sub-allocation
+ * to the GPU memory.
+ * @node: the node allocated in the memory pool to flush.
+ */
+void xe_mem_pool_bo_flush_write(struct xe_mem_pool_node *node)
+{
+	struct xe_mem_pool *pool = node_to_pool(node);
+	struct xe_tile *tile = pool_to_tile(pool);
+	struct xe_device *xe = tile_to_xe(tile);
+	struct drm_mm_node *sa_node = &node->sa_node;
+
+	if (!pool->bo->vmap.is_iomem)
+		return;
+
+	xe_map_memcpy_to(xe, &pool->bo->vmap, sa_node->start,
+			 pool->cpu_addr + sa_node->start,
+			 sa_node->size);
+}
+
+/**
+ * xe_mem_pool_bo_sync_read() - Copy the data from GPU memory to the
+ * sub-allocation.
+ * @node: the node allocated in the memory pool to read back.
+ */
+void xe_mem_pool_bo_sync_read(struct xe_mem_pool_node *node)
+{
+	struct xe_mem_pool *pool = node_to_pool(node);
+	struct xe_tile *tile = pool_to_tile(pool);
+	struct xe_device *xe = tile_to_xe(tile);
+	struct drm_mm_node *sa_node = &node->sa_node;
+
+	if (!pool->bo->vmap.is_iomem)
+		return;
+
+	xe_map_memcpy_from(xe, pool->cpu_addr + sa_node->start,
+			   &pool->bo->vmap, sa_node->start, sa_node->size);
+}
+
+/**
+ * xe_mem_pool_alloc_node() - Allocate a new node for use with xe_mem_pool.
+ *
+ * Returns: node structure or an ERR_PTR(-ENOMEM).
+ */
+struct xe_mem_pool_node *xe_mem_pool_alloc_node(void)
+{
+	struct xe_mem_pool_node *node = kzalloc_obj(*node);
+
+	if (!node)
+		return ERR_PTR(-ENOMEM);
+
+	return node;
+}
+
+/**
+ * xe_mem_pool_insert_node() - Insert a node into the memory pool.
+ * @pool: the memory pool to insert into
+ * @node: the node to insert
+ * @size: the size of the node to be allocated in bytes.
+ *
+ * Inserts a node into the specified memory pool using drm_mm for
+ * allocation.
+ *
+ * Returns: 0 on success or a negative error code on failure.
+ */
+int xe_mem_pool_insert_node(struct xe_mem_pool *pool,
+			    struct xe_mem_pool_node *node, u32 size)
+{
+	if (!pool)
+		return -EINVAL;
+
+	return drm_mm_insert_node(&pool->base, &node->sa_node, size);
+}
+
+/**
+ * xe_mem_pool_free_node() - Free a node allocated from the memory pool.
+ * @node: the node to free
+ *
+ * Returns: None.
+ */
+void xe_mem_pool_free_node(struct xe_mem_pool_node *node)
+{
+	if (!node)
+		return;
+
+	drm_mm_remove_node(&node->sa_node);
+	kfree(node);
+}
+
+/**
+ * xe_mem_pool_node_cpu_addr() - Retrieve CPU address of the node.
+ * @node: the node allocated in the memory pool
+ *
+ * Returns: CPU virtual address of the node.
+ */
+void *xe_mem_pool_node_cpu_addr(struct xe_mem_pool_node *node)
+{
+	struct xe_mem_pool *pool = node_to_pool(node);
+
+	return xe_mem_pool_cpu_addr(pool) + node->sa_node.start;
+}
+
+/**
+ * xe_mem_pool_dump() - Dump the state of the DRM MM manager for debugging.
+ * @pool: the memory pool info be dumped.
+ * @p: The DRM printer to use for output.
+ *
+ * Only the drm managed region is dumped, not the state of the BOs or any other
+ * pool information.
+ *
+ * Returns: None.
+ */
+void xe_mem_pool_dump(struct xe_mem_pool *pool, struct drm_printer *p)
+{
+	drm_mm_print(&pool->base, p);
+}
diff --git a/drivers/gpu/drm/xe/xe_mem_pool.h b/drivers/gpu/drm/xe/xe_mem_pool.h
new file mode 100644
index 000000000000..89cd2555fe91
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_mem_pool.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+#ifndef _XE_MEM_POOL_H_
+#define _XE_MEM_POOL_H_
+
+#include <linux/sizes.h>
+#include <linux/types.h>
+
+#include <drm/drm_mm.h>
+#include "xe_mem_pool_types.h"
+
+struct drm_printer;
+struct xe_mem_pool;
+struct xe_tile;
+
+struct xe_mem_pool *xe_mem_pool_init(struct xe_tile *tile, u32 size,
+				     u32 guard, int flags);
+void xe_mem_pool_sync(struct xe_mem_pool *pool);
+void xe_mem_pool_swap_shadow_locked(struct xe_mem_pool *pool);
+void xe_mem_pool_sync_shadow_locked(struct xe_mem_pool_node *node);
+u64 xe_mem_pool_gpu_addr(struct xe_mem_pool *pool);
+void *xe_mem_pool_cpu_addr(struct xe_mem_pool *pool);
+struct mutex *xe_mem_pool_bo_swap_guard(struct xe_mem_pool *pool);
+void xe_mem_pool_bo_flush_write(struct xe_mem_pool_node *node);
+void xe_mem_pool_bo_sync_read(struct xe_mem_pool_node *node);
+struct xe_mem_pool_node *xe_mem_pool_alloc_node(void);
+int xe_mem_pool_insert_node(struct xe_mem_pool *pool,
+			    struct xe_mem_pool_node *node, u32 size);
+void xe_mem_pool_free_node(struct xe_mem_pool_node *node);
+void *xe_mem_pool_node_cpu_addr(struct xe_mem_pool_node *node);
+void xe_mem_pool_dump(struct xe_mem_pool *pool, struct drm_printer *p);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_mem_pool_types.h b/drivers/gpu/drm/xe/xe_mem_pool_types.h
new file mode 100644
index 000000000000..d5e926c93351
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_mem_pool_types.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_MEM_POOL_TYPES_H_
+#define _XE_MEM_POOL_TYPES_H_
+
+#include <drm/drm_mm.h>
+
+#define XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY			BIT(0)
+
+/**
+ * struct xe_mem_pool_node - Sub-range allocations from mem pool.
+ */
+struct xe_mem_pool_node {
+	/** @sa_node: drm_mm_node for this allocation. */
+	struct drm_mm_node sa_node;
+};
+
+#endif
-- 
2.43.0

[PATCH v4 2/2] drm/xe/vf: Use drm mm instead of drm sa for CCS read/write

[Satyanarayana K V P]

The suballocator algorithm tracks a hole cursor at the last allocation
and tries to allocate after it. This is optimized for fence-ordered
progress, where older allocations are expected to become reusable first.

In fence-enabled mode, that ordering assumption holds. In fence-disabled
mode, allocations may be freed in arbitrary order, so limiting allocation
to the current hole window can miss valid free space and fail allocations
despite sufficient total space.

Use DRM memory manager instead of sub-allocator to get rid of this issue
as CCS read/write operations do not use fences.

Fixes: 864690cf4dd6 ("drm/xe/vf: Attach and detach CCS copy commands with BO")
Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Maarten Lankhorst <dev@lankhorst.se>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>

---
V3 -> V4:
- Updated changes as per xe_mem_pool.
- Updated Fixes: field (Thomas)

V2 -> V3:
- Used xe_mem_pool_init() and xe_mem_pool_shadow_init() to allocate BB
pools.

V1 -> V2:
- Renamed xe_drm_mm to xe_mm_suballoc (Thomas)
---
 drivers/gpu/drm/xe/xe_bo_types.h           |  3 +-
 drivers/gpu/drm/xe/xe_migrate.c            | 56 ++++++++++++----------
 drivers/gpu/drm/xe/xe_sriov_vf_ccs.c       | 54 +++++++++++----------
 drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h |  5 +-
 4 files changed, 63 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h
index ff8317bfc1ae..9d19940b8fc0 100644
--- a/drivers/gpu/drm/xe/xe_bo_types.h
+++ b/drivers/gpu/drm/xe/xe_bo_types.h
@@ -18,6 +18,7 @@
 #include "xe_ggtt_types.h"
 
 struct xe_device;
+struct xe_mem_pool_node;
 struct xe_vm;
 
 #define XE_BO_MAX_PLACEMENTS	3
@@ -88,7 +89,7 @@ struct xe_bo {
 	bool ccs_cleared;
 
 	/** @bb_ccs: BB instructions of CCS read/write. Valid only for VF */
-	struct xe_bb *bb_ccs[XE_SRIOV_VF_CCS_CTX_COUNT];
+	struct xe_mem_pool_node *bb_ccs[XE_SRIOV_VF_CCS_CTX_COUNT];
 
 	/**
 	 * @cpu_caching: CPU caching mode. Currently only used for userspace
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index fc918b4fba54..5fdc89ed5256 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -29,6 +29,7 @@
 #include "xe_hw_engine.h"
 #include "xe_lrc.h"
 #include "xe_map.h"
+#include "xe_mem_pool.h"
 #include "xe_mocs.h"
 #include "xe_printk.h"
 #include "xe_pt.h"
@@ -1166,11 +1167,12 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
 	u32 batch_size, batch_size_allocated;
 	struct xe_device *xe = gt_to_xe(gt);
 	struct xe_res_cursor src_it, ccs_it;
+	struct xe_mem_pool *bb_pool;
 	struct xe_sriov_vf_ccs_ctx *ctx;
-	struct xe_sa_manager *bb_pool;
 	u64 size = xe_bo_size(src_bo);
-	struct xe_bb *bb = NULL;
+	struct xe_mem_pool_node *bb;
 	u64 src_L0, src_L0_ofs;
+	struct xe_bb xe_bb_tmp;
 	u32 src_L0_pt;
 	int err;
 
@@ -1208,18 +1210,18 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
 		size -= src_L0;
 	}
 
-	bb = xe_bb_alloc(gt);
+	bb = xe_mem_pool_alloc_node();
 	if (IS_ERR(bb))
 		return PTR_ERR(bb);
 
 	bb_pool = ctx->mem.ccs_bb_pool;
-	scoped_guard(mutex, xe_sa_bo_swap_guard(bb_pool)) {
-		xe_sa_bo_swap_shadow(bb_pool);
+	scoped_guard(mutex, xe_mem_pool_bo_swap_guard(bb_pool)) {
+		xe_mem_pool_swap_shadow_locked(bb_pool);
 
-		err = xe_bb_init(bb, bb_pool, batch_size);
+		err = xe_mem_pool_insert_node(bb_pool, bb, batch_size * sizeof(u32));
 		if (err) {
 			xe_gt_err(gt, "BB allocation failed.\n");
-			xe_bb_free(bb, NULL);
+			kfree(bb);
 			return err;
 		}
 
@@ -1227,6 +1229,7 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
 		size = xe_bo_size(src_bo);
 		batch_size = 0;
 
+		xe_bb_tmp = (struct xe_bb){ .cs = xe_mem_pool_node_cpu_addr(bb), .len = 0 };
 		/*
 		 * Emit PTE and copy commands here.
 		 * The CCS copy command can only support limited size. If the size to be
@@ -1255,24 +1258,27 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
 			xe_assert(xe, IS_ALIGNED(ccs_it.start, PAGE_SIZE));
 			batch_size += EMIT_COPY_CCS_DW;
 
-			emit_pte(m, bb, src_L0_pt, false, true, &src_it, src_L0, src);
+			emit_pte(m, &xe_bb_tmp, src_L0_pt, false, true, &src_it, src_L0, src);
 
-			emit_pte(m, bb, ccs_pt, false, false, &ccs_it, ccs_size, src);
+			emit_pte(m, &xe_bb_tmp, ccs_pt, false, false, &ccs_it, ccs_size, src);
 
-			bb->len = emit_flush_invalidate(bb->cs, bb->len, flush_flags);
-			flush_flags = xe_migrate_ccs_copy(m, bb, src_L0_ofs, src_is_pltt,
+			xe_bb_tmp.len = emit_flush_invalidate(xe_bb_tmp.cs, xe_bb_tmp.len,
+							      flush_flags);
+			flush_flags = xe_migrate_ccs_copy(m, &xe_bb_tmp, src_L0_ofs, src_is_pltt,
 							  src_L0_ofs, dst_is_pltt,
 							  src_L0, ccs_ofs, true);
-			bb->len = emit_flush_invalidate(bb->cs, bb->len, flush_flags);
+			xe_bb_tmp.len = emit_flush_invalidate(xe_bb_tmp.cs, xe_bb_tmp.len,
+							      flush_flags);
 
 			size -= src_L0;
 		}
 
-		xe_assert(xe, (batch_size_allocated == bb->len));
+		xe_assert(xe, (batch_size_allocated == xe_bb_tmp.len));
+		xe_assert(xe, bb->sa_node.size == xe_bb_tmp.len * sizeof(u32));
 		src_bo->bb_ccs[read_write] = bb;
 
 		xe_sriov_vf_ccs_rw_update_bb_addr(ctx);
-		xe_sa_bo_sync_shadow(bb->bo);
+		xe_mem_pool_sync_shadow_locked(bb);
 	}
 
 	return 0;
@@ -1297,10 +1303,10 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
 void xe_migrate_ccs_rw_copy_clear(struct xe_bo *src_bo,
 				  enum xe_sriov_vf_ccs_rw_ctxs read_write)
 {
-	struct xe_bb *bb = src_bo->bb_ccs[read_write];
+	struct xe_mem_pool_node *bb = src_bo->bb_ccs[read_write];
 	struct xe_device *xe = xe_bo_device(src_bo);
+	struct xe_mem_pool *bb_pool;
 	struct xe_sriov_vf_ccs_ctx *ctx;
-	struct xe_sa_manager *bb_pool;
 	u32 *cs;
 
 	xe_assert(xe, IS_SRIOV_VF(xe));
@@ -1308,17 +1314,17 @@ void xe_migrate_ccs_rw_copy_clear(struct xe_bo *src_bo,
 	ctx = &xe->sriov.vf.ccs.contexts[read_write];
 	bb_pool = ctx->mem.ccs_bb_pool;
 
-	guard(mutex) (xe_sa_bo_swap_guard(bb_pool));
-	xe_sa_bo_swap_shadow(bb_pool);
-
-	cs = xe_sa_bo_cpu_addr(bb->bo);
-	memset(cs, MI_NOOP, bb->len * sizeof(u32));
-	xe_sriov_vf_ccs_rw_update_bb_addr(ctx);
+	scoped_guard(mutex, xe_mem_pool_bo_swap_guard(bb_pool)) {
+		xe_mem_pool_swap_shadow_locked(bb_pool);
 
-	xe_sa_bo_sync_shadow(bb->bo);
+		cs = xe_mem_pool_node_cpu_addr(bb);
+		memset(cs, MI_NOOP, bb->sa_node.size);
+		xe_sriov_vf_ccs_rw_update_bb_addr(ctx);
 
-	xe_bb_free(bb, NULL);
-	src_bo->bb_ccs[read_write] = NULL;
+		xe_mem_pool_sync_shadow_locked(bb);
+		xe_mem_pool_free_node(bb);
+		src_bo->bb_ccs[read_write] = NULL;
+	}
 }
 
 /**
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
index db023fb66a27..09b99fb2608b 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
@@ -14,9 +14,9 @@
 #include "xe_guc.h"
 #include "xe_guc_submit.h"
 #include "xe_lrc.h"
+#include "xe_mem_pool.h"
 #include "xe_migrate.h"
 #include "xe_pm.h"
-#include "xe_sa.h"
 #include "xe_sriov_printk.h"
 #include "xe_sriov_vf.h"
 #include "xe_sriov_vf_ccs.h"
@@ -141,43 +141,47 @@ static u64 get_ccs_bb_pool_size(struct xe_device *xe)
 
 static int alloc_bb_pool(struct xe_tile *tile, struct xe_sriov_vf_ccs_ctx *ctx)
 {
+	struct xe_mem_pool *pool;
 	struct xe_device *xe = tile_to_xe(tile);
-	struct xe_sa_manager *sa_manager;
+	u32 *pool_cpu_addr, *last_dw_addr;
 	u64 bb_pool_size;
-	int offset, err;
+	int err;
 
 	bb_pool_size = get_ccs_bb_pool_size(xe);
 	xe_sriov_info(xe, "Allocating %s CCS BB pool size = %lldMB\n",
 		      ctx->ctx_id ? "Restore" : "Save", bb_pool_size / SZ_1M);
 
-	sa_manager = __xe_sa_bo_manager_init(tile, bb_pool_size, SZ_4K, SZ_16,
-					     XE_SA_BO_MANAGER_FLAG_SHADOW);
-
-	if (IS_ERR(sa_manager)) {
-		xe_sriov_err(xe, "Suballocator init failed with error: %pe\n",
-			     sa_manager);
-		err = PTR_ERR(sa_manager);
+	pool = xe_mem_pool_init(tile, bb_pool_size, sizeof(u32),
+				XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY);
+	if (IS_ERR(pool)) {
+		xe_sriov_err(xe, "xe_mem_pool_init failed with error: %pe\n",
+			     pool);
+		err = PTR_ERR(pool);
 		return err;
 	}
 
-	offset = 0;
-	xe_map_memset(xe, &sa_manager->bo->vmap, offset, MI_NOOP,
-		      bb_pool_size);
-	xe_map_memset(xe, &sa_manager->shadow->vmap, offset, MI_NOOP,
-		      bb_pool_size);
+	pool_cpu_addr = xe_mem_pool_cpu_addr(pool);
+	memset(pool_cpu_addr, 0, bb_pool_size);
 
-	offset = bb_pool_size - sizeof(u32);
-	xe_map_wr(xe, &sa_manager->bo->vmap, offset, u32, MI_BATCH_BUFFER_END);
-	xe_map_wr(xe, &sa_manager->shadow->vmap, offset, u32, MI_BATCH_BUFFER_END);
+	last_dw_addr = pool_cpu_addr + (bb_pool_size / sizeof(u32)) - 1;
+	*last_dw_addr = MI_BATCH_BUFFER_END;
 
-	ctx->mem.ccs_bb_pool = sa_manager;
+	/**
+	 * Sync the main copy and shadow copy so that the shadow copy is
+	 * replica of main copy. We sync only BBs after init part. So, we
+	 * need to make sure the main pool and shadow copy are in sync after
+	 * this point. This is needed as GuC may read the BB commands from
+	 * shadow copy.
+	 */
+	xe_mem_pool_sync(pool);
 
+	ctx->mem.ccs_bb_pool = pool;
 	return 0;
 }
 
 static void ccs_rw_update_ring(struct xe_sriov_vf_ccs_ctx *ctx)
 {
-	u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool);
+	u64 addr = xe_mem_pool_gpu_addr(ctx->mem.ccs_bb_pool);
 	struct xe_lrc *lrc = xe_exec_queue_lrc(ctx->mig_q);
 	u32 dw[10], i = 0;
 
@@ -388,7 +392,7 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe)
 #define XE_SRIOV_VF_CCS_RW_BB_ADDR_OFFSET	(2 * sizeof(u32))
 void xe_sriov_vf_ccs_rw_update_bb_addr(struct xe_sriov_vf_ccs_ctx *ctx)
 {
-	u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool);
+	u64 addr = xe_mem_pool_gpu_addr(ctx->mem.ccs_bb_pool);
 	struct xe_lrc *lrc = xe_exec_queue_lrc(ctx->mig_q);
 	struct xe_device *xe = gt_to_xe(ctx->mig_q->gt);
 
@@ -412,8 +416,8 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo)
 	struct xe_device *xe = xe_bo_device(bo);
 	enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
 	struct xe_sriov_vf_ccs_ctx *ctx;
+	struct xe_mem_pool_node *bb;
 	struct xe_tile *tile;
-	struct xe_bb *bb;
 	int err = 0;
 
 	xe_assert(xe, IS_VF_CCS_READY(xe));
@@ -445,7 +449,7 @@ int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo)
 {
 	struct xe_device *xe = xe_bo_device(bo);
 	enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
-	struct xe_bb *bb;
+	struct xe_mem_pool_node *bb;
 
 	xe_assert(xe, IS_VF_CCS_READY(xe));
 
@@ -471,8 +475,8 @@ int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo)
  */
 void xe_sriov_vf_ccs_print(struct xe_device *xe, struct drm_printer *p)
 {
-	struct xe_sa_manager *bb_pool;
 	enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
+	struct xe_mem_pool *bb_pool;
 
 	if (!IS_VF_CCS_READY(xe))
 		return;
@@ -485,7 +489,7 @@ void xe_sriov_vf_ccs_print(struct xe_device *xe, struct drm_printer *p)
 
 		drm_printf(p, "ccs %s bb suballoc info\n", ctx_id ? "write" : "read");
 		drm_printf(p, "-------------------------\n");
-		drm_suballoc_dump_debug_info(&bb_pool->base, p, xe_sa_manager_gpu_addr(bb_pool));
+		xe_mem_pool_dump(bb_pool, p);
 		drm_puts(p, "\n");
 	}
 }
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
index 22c499943d2a..6fc8f97ef3f4 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
@@ -17,9 +17,6 @@ enum xe_sriov_vf_ccs_rw_ctxs {
 	XE_SRIOV_VF_CCS_CTX_COUNT
 };
 
-struct xe_migrate;
-struct xe_sa_manager;
-
 /**
  * struct xe_sriov_vf_ccs_ctx - VF CCS migration context data.
  */
@@ -33,7 +30,7 @@ struct xe_sriov_vf_ccs_ctx {
 	/** @mem: memory data */
 	struct {
 		/** @mem.ccs_bb_pool: Pool from which batch buffers are allocated. */
-		struct xe_sa_manager *ccs_bb_pool;
+		struct xe_mem_pool *ccs_bb_pool;
 	} mem;
 };
 
-- 
2.43.0

✗ CI.checkpatch: warning for USE drm mm instead of drm SA for CCS read/write (rev4)

[Patchwork]

== Series Details ==

Series: USE drm mm instead of drm SA for CCS read/write (rev4)
URL   : https://patchwork.freedesktop.org/series/163588/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 0d93d3585aa5595b1cf95a25fb62efb00f045c4f
Author: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Date:   Wed Apr 8 11:01:48 2026 +0000

    drm/xe/vf: Use drm mm instead of drm sa for CCS read/write
    
    The suballocator algorithm tracks a hole cursor at the last allocation
    and tries to allocate after it. This is optimized for fence-ordered
    progress, where older allocations are expected to become reusable first.
    
    In fence-enabled mode, that ordering assumption holds. In fence-disabled
    mode, allocations may be freed in arbitrary order, so limiting allocation
    to the current hole window can miss valid free space and fail allocations
    despite sufficient total space.
    
    Use DRM memory manager instead of sub-allocator to get rid of this issue
    as CCS read/write operations do not use fences.
    
    Fixes: 864690cf4dd6 ("drm/xe/vf: Attach and detach CCS copy commands with BO")
    Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
    Cc: Matthew Brost <matthew.brost@intel.com>
    Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
    Cc: Maarten Lankhorst <dev@lankhorst.se>
    Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
+ /mt/dim checkpatch 1debea0fa06176e70720a9c53b23c398b971fa5b drm-intel
46ac0bbf1186 drm/xe: Add memory pool with shadow support
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#31: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 466 lines checked
0d93d3585aa5 drm/xe/vf: Use drm mm instead of drm sa for CCS read/write

✗ CI.KUnit: failure for USE drm mm instead of drm SA for CCS read/write (rev4)

[Patchwork]

== Series Details ==

Series: USE drm mm instead of drm SA for CCS read/write (rev4)
URL   : https://patchwork.freedesktop.org/series/163588/
State : failure

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[11:08:03] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:08:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:08:38] Starting KUnit Kernel (1/1)...
[11:08:38] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:08:39] ================== guc_buf (11 subtests) ===================
[11:08:39] [PASSED] test_smallest
[11:08:39] [PASSED] test_largest
[11:08:39] [PASSED] test_granular
[11:08:39] [PASSED] test_unique
[11:08:39] [PASSED] test_overlap
[11:08:39] [PASSED] test_reusable
[11:08:39] [PASSED] test_too_big
[11:08:39] [PASSED] test_flush
[11:08:39] [PASSED] test_lookup
[11:08:39] [PASSED] test_data
[11:08:39] [PASSED] test_class
[11:08:39] ===================== [PASSED] guc_buf =====================
[11:08:39] =================== guc_dbm (7 subtests) ===================
[11:08:39] [PASSED] test_empty
[11:08:39] [PASSED] test_default
[11:08:39] ======================== test_size  ========================
[11:08:39] [PASSED] 4
[11:08:39] [PASSED] 8
[11:08:39] [PASSED] 32
[11:08:39] [PASSED] 256
[11:08:39] ==================== [PASSED] test_size ====================
[11:08:39] ======================= test_reuse  ========================
[11:08:39] [PASSED] 4
[11:08:39] [PASSED] 8
[11:08:39] [PASSED] 32
[11:08:39] [PASSED] 256
[11:08:39] =================== [PASSED] test_reuse ====================
[11:08:39] =================== test_range_overlap  ====================
[11:08:39] [PASSED] 4
[11:08:39] [PASSED] 8
[11:08:39] [PASSED] 32
[11:08:39] [PASSED] 256
[11:08:39] =============== [PASSED] test_range_overlap ================
[11:08:39] =================== test_range_compact  ====================
[11:08:39] [PASSED] 4
[11:08:39] [PASSED] 8
[11:08:39] [PASSED] 32
[11:08:39] [PASSED] 256
[11:08:39] =============== [PASSED] test_range_compact ================
[11:08:39] ==================== test_range_spare  =====================
[11:08:39] [PASSED] 4
[11:08:39] [PASSED] 8
[11:08:39] [PASSED] 32
[11:08:39] [PASSED] 256
[11:08:39] ================ [PASSED] test_range_spare =================
[11:08:39] ===================== [PASSED] guc_dbm =====================
[11:08:39] =================== guc_idm (6 subtests) ===================
[11:08:39] [PASSED] bad_init
[11:08:39] [PASSED] no_init
[11:08:39] [PASSED] init_fini
[11:08:39] [PASSED] check_used
[11:08:39] [PASSED] check_quota
[11:08:39] [PASSED] check_all
[11:08:39] ===================== [PASSED] guc_idm =====================
[11:08:39] ================== no_relay (3 subtests) ===================
[11:08:39] [PASSED] xe_drops_guc2pf_if_not_ready
[11:08:39] [PASSED] xe_drops_guc2vf_if_not_ready
[11:08:39] [PASSED] xe_rejects_send_if_not_ready
[11:08:39] ==================== [PASSED] no_relay =====================
[11:08:39] ================== pf_relay (14 subtests) ==================
[11:08:39] [PASSED] pf_rejects_guc2pf_too_short
[11:08:39] [PASSED] pf_rejects_guc2pf_too_long
[11:08:39] [PASSED] pf_rejects_guc2pf_no_payload
[11:08:39] [PASSED] pf_fails_no_payload
[11:08:39] [PASSED] pf_fails_bad_origin
[11:08:39] [PASSED] pf_fails_bad_type
[11:08:39] [PASSED] pf_txn_reports_error
[11:08:39] [PASSED] pf_txn_sends_pf2guc
[11:08:39] [PASSED] pf_sends_pf2guc
[11:08:39] [SKIPPED] pf_loopback_nop
[11:08:39] [SKIPPED] pf_loopback_echo
[11:08:39] [SKIPPED] pf_loopback_fail
[11:08:39] [SKIPPED] pf_loopback_busy
[11:08:39] [SKIPPED] pf_loopback_retry
[11:08:39] ==================== [PASSED] pf_relay =====================
[11:08:39] ================== vf_relay (3 subtests) ===================
[11:08:39] [PASSED] vf_rejects_guc2vf_too_short
[11:08:39] [PASSED] vf_rejects_guc2vf_too_long
[11:08:39] [PASSED] vf_rejects_guc2vf_no_payload
[11:08:39] ==================== [PASSED] vf_relay =====================
[11:08:39] ================ pf_gt_config (9 subtests) =================
[11:08:39] [PASSED] fair_contexts_1vf
[11:08:39] [PASSED] fair_doorbells_1vf
[11:08:39] [PASSED] fair_ggtt_1vf
[11:08:39] ====================== fair_vram_1vf  ======================
[11:08:39] [PASSED] 3.50 GiB
[11:08:39] [PASSED] 11.5 GiB
[11:08:39] [PASSED] 15.5 GiB
[11:08:39] [PASSED] 31.5 GiB
[11:08:39] [PASSED] 63.5 GiB
[11:08:39] [PASSED] 1.91 GiB
[11:08:39] ================== [PASSED] fair_vram_1vf ==================
[11:08:39] ================ fair_vram_1vf_admin_only  =================
[11:08:39] [PASSED] 3.50 GiB
[11:08:39] [PASSED] 11.5 GiB
[11:08:39] [PASSED] 15.5 GiB
[11:08:39] [PASSED] 31.5 GiB
[11:08:39] [PASSED] 63.5 GiB
[11:08:39] [PASSED] 1.91 GiB
[11:08:39] ============ [PASSED] fair_vram_1vf_admin_only =============
[11:08:39] ====================== fair_contexts  ======================
[11:08:39] [PASSED] 1 VF
[11:08:39] [PASSED] 2 VFs
[11:08:39] [PASSED] 3 VFs
[11:08:39] [PASSED] 4 VFs
[11:08:39] [PASSED] 5 VFs
[11:08:39] [PASSED] 6 VFs
[11:08:39] [PASSED] 7 VFs
[11:08:39] [PASSED] 8 VFs
[11:08:39] [PASSED] 9 VFs
[11:08:39] [PASSED] 10 VFs
[11:08:39] [PASSED] 11 VFs
[11:08:39] [PASSED] 12 VFs
[11:08:39] [PASSED] 13 VFs
[11:08:39] [PASSED] 14 VFs
[11:08:39] [PASSED] 15 VFs
[11:08:39] [PASSED] 16 VFs
[11:08:39] [PASSED] 17 VFs
[11:08:39] [PASSED] 18 VFs
[11:08:39] [PASSED] 19 VFs
[11:08:39] [PASSED] 20 VFs
[11:08:39] [PASSED] 21 VFs
[11:08:39] [PASSED] 22 VFs
[11:08:39] [PASSED] 23 VFs
[11:08:39] [PASSED] 24 VFs
[11:08:39] [PASSED] 25 VFs
[11:08:39] [PASSED] 26 VFs
[11:08:39] [PASSED] 27 VFs
[11:08:39] [PASSED] 28 VFs
[11:08:39] [PASSED] 29 VFs
[11:08:39] [PASSED] 30 VFs
[11:08:39] [PASSED] 31 VFs
[11:08:39] [PASSED] 32 VFs
[11:08:39] [PASSED] 33 VFs
[11:08:39] [PASSED] 34 VFs
[11:08:39] [PASSED] 35 VFs
[11:08:39] [PASSED] 36 VFs
[11:08:39] [PASSED] 37 VFs
[11:08:39] [PASSED] 38 VFs
[11:08:39] [PASSED] 39 VFs
[11:08:39] [PASSED] 40 VFs
[11:08:39] [PASSED] 41 VFs
[11:08:39] [PASSED] 42 VFs
[11:08:39] [PASSED] 43 VFs
[11:08:39] [PASSED] 44 VFs
[11:08:39] [PASSED] 45 VFs
[11:08:39] [PASSED] 46 VFs
[11:08:39] [PASSED] 47 VFs
[11:08:39] [PASSED] 48 VFs
[11:08:39] [PASSED] 49 VFs
[11:08:39] [PASSED] 50 VFs
[11:08:39] [PASSED] 51 VFs
[11:08:39] [PASSED] 52 VFs
[11:08:39] [PASSED] 53 VFs
[11:08:39] [PASSED] 54 VFs
[11:08:39] [PASSED] 55 VFs
[11:08:39] [PASSED] 56 VFs
[11:08:39] [PASSED] 57 VFs
[11:08:39] [PASSED] 58 VFs
[11:08:39] [PASSED] 59 VFs
[11:08:39] [PASSED] 60 VFs
[11:08:39] [PASSED] 61 VFs
[11:08:39] [PASSED] 62 VFs
[11:08:39] [PASSED] 63 VFs
[11:08:39] ================== [PASSED] fair_contexts ==================
[11:08:39] ===================== fair_doorbells  ======================
[11:08:39] [PASSED] 1 VF
[11:08:39] [PASSED] 2 VFs
[11:08:39] [PASSED] 3 VFs
[11:08:39] [PASSED] 4 VFs
[11:08:39] [PASSED] 5 VFs
[11:08:39] [PASSED] 6 VFs
[11:08:39] [PASSED] 7 VFs
[11:08:39] [PASSED] 8 VFs
[11:08:39] [PASSED] 9 VFs
[11:08:39] [PASSED] 10 VFs
[11:08:39] [PASSED] 11 VFs
[11:08:39] [PASSED] 12 VFs
[11:08:39] [PASSED] 13 VFs
[11:08:39] [PASSED] 14 VFs
[11:08:39] [PASSED] 15 VFs
[11:08:39] [PASSED] 16 VFs
[11:08:39] [PASSED] 17 VFs
[11:08:39] [PASSED] 18 VFs
[11:08:39] [PASSED] 19 VFs
[11:08:39] [PASSED] 20 VFs
[11:08:39] [PASSED] 21 VFs
[11:08:39] [PASSED] 22 VFs
[11:08:39] [PASSED] 23 VFs
[11:08:39] [PASSED] 24 VFs
[11:08:39] [PASSED] 25 VFs
[11:08:39] [PASSED] 26 VFs
[11:08:39] [PASSED] 27 VFs
[11:08:39] [PASSED] 28 VFs
[11:08:39] [PASSED] 29 VFs
[11:08:39] [PASSED] 30 VFs
[11:08:39] [PASSED] 31 VFs
[11:08:39] [PASSED] 32 VFs
[11:08:39] [PASSED] 33 VFs
[11:08:39] [PASSED] 34 VFs
[11:08:39] [PASSED] 35 VFs
[11:08:39] [PASSED] 36 VFs
[11:08:39] [PASSED] 37 VFs
[11:08:39] [PASSED] 38 VFs
[11:08:39] [PASSED] 39 VFs
[11:08:39] [PASSED] 40 VFs
[11:08:39] [PASSED] 41 VFs
[11:08:39] [PASSED] 42 VFs
[11:08:39] [PASSED] 43 VFs
[11:08:39] [PASSED] 44 VFs
[11:08:39] [PASSED] 45 VFs
[11:08:39] [PASSED] 46 VFs
[11:08:39] [PASSED] 47 VFs
[11:08:39] [PASSED] 48 VFs
[11:08:39] [PASSED] 49 VFs
[11:08:39] [PASSED] 50 VFs
[11:08:39] [PASSED] 51 VFs
[11:08:39] [PASSED] 52 VFs
[11:08:39] [PASSED] 53 VFs
[11:08:39] [PASSED] 54 VFs
[11:08:39] [PASSED] 55 VFs
[11:08:39] [PASSED] 56 VFs
[11:08:39] [PASSED] 57 VFs
[11:08:39] [PASSED] 58 VFs
[11:08:39] [PASSED] 59 VFs
[11:08:39] [PASSED] 60 VFs
[11:08:39] [PASSED] 61 VFs
[11:08:39] [PASSED] 62 VFs
[11:08:39] [PASSED] 63 VFs
[11:08:39] ================= [PASSED] fair_doorbells ==================
[11:08:39] ======================== fair_ggtt  ========================
[11:08:39] [PASSED] 1 VF
[11:08:39] [PASSED] 2 VFs
[11:08:39] [PASSED] 3 VFs
[11:08:39] [PASSED] 4 VFs
[11:08:39] [PASSED] 5 VFs
[11:08:39] [PASSED] 6 VFs
[11:08:39] [PASSED] 7 VFs
[11:08:39] [PASSED] 8 VFs
[11:08:39] [PASSED] 9 VFs
[11:08:39] [PASSED] 10 VFs
[11:08:39] [PASSED] 11 VFs
[11:08:39] [PASSED] 12 VFs
[11:08:39] [PASSED] 13 VFs
[11:08:39] [PASSED] 14 VFs
[11:08:39] [PASSED] 15 VFs
[11:08:39] [PASSED] 16 VFs
[11:08:39] [PASSED] 17 VFs
[11:08:39] [PASSED] 18 VFs
[11:08:39] [PASSED] 19 VFs
[11:08:39] [PASSED] 20 VFs
[11:08:39] [PASSED] 21 VFs
[11:08:39] [PASSED] 22 VFs
[11:08:39] [PASSED] 23 VFs
[11:08:39] [PASSED] 24 VFs
[11:08:39] [PASSED] 25 VFs
[11:08:39] [PASSED] 26 VFs
[11:08:39] [PASSED] 27 VFs
[11:08:39] [PASSED] 28 VFs
[11:08:39] [PASSED] 29 VFs
[11:08:39] [PASSED] 30 VFs
[11:08:39] [PASSED] 31 VFs
[11:08:39] [PASSED] 32 VFs
[11:08:39] [PASSED] 33 VFs
[11:08:39] [PASSED] 34 VFs
[11:08:39] [PASSED] 35 VFs
[11:08:39] [PASSED] 36 VFs
[11:08:39] [PASSED] 37 VFs
[11:08:39] [PASSED] 38 VFs
[11:08:39] [PASSED] 39 VFs
[11:08:39] [PASSED] 40 VFs
[11:08:39] [PASSED] 41 VFs
[11:08:39] [PASSED] 42 VFs
[11:08:39] [PASSED] 43 VFs
[11:08:39] [PASSED] 44 VFs
[11:08:39] [PASSED] 45 VFs
[11:08:39] [PASSED] 46 VFs
[11:08:39] [PASSED] 47 VFs
[11:08:39] [PASSED] 48 VFs
[11:08:39] [PASSED] 49 VFs
[11:08:39] [PASSED] 50 VFs
[11:08:39] [PASSED] 51 VFs
[11:08:39] [PASSED] 52 VFs
[11:08:39] [PASSED] 53 VFs
[11:08:39] [PASSED] 54 VFs
[11:08:39] [PASSED] 55 VFs
[11:08:39] [PASSED] 56 VFs
[11:08:39] [PASSED] 57 VFs
[11:08:39] [PASSED] 58 VFs
[11:08:39] [PASSED] 59 VFs
[11:08:39] [PASSED] 60 VFs
[11:08:39] [PASSED] 61 VFs
[11:08:39] [PASSED] 62 VFs
[11:08:39] [PASSED] 63 VFs
[11:08:39] ==================== [PASSED] fair_ggtt ====================
[11:08:39] ======================== fair_vram  ========================
[11:08:39] [PASSED] 1 VF
[11:08:39] [PASSED] 2 VFs
[11:08:39] [PASSED] 3 VFs
[11:08:39] [PASSED] 4 VFs
[11:08:39] [PASSED] 5 VFs
[11:08:39] [PASSED] 6 VFs
[11:08:39] [PASSED] 7 VFs
[11:08:39] [PASSED] 8 VFs
[11:08:39] [PASSED] 9 VFs
[11:08:39] [PASSED] 10 VFs
[11:08:39] [PASSED] 11 VFs
[11:08:39] [PASSED] 12 VFs
[11:08:39] [PASSED] 13 VFs
[11:08:39] [PASSED] 14 VFs
[11:08:39] [PASSED] 15 VFs
[11:08:39] [PASSED] 16 VFs
[11:08:39] [PASSED] 17 VFs
[11:08:39] [PASSED] 18 VFs
[11:08:39] [PASSED] 19 VFs
[11:08:39] [PASSED] 20 VFs
[11:08:39] [PASSED] 21 VFs
[11:08:39] [PASSED] 22 VFs
[11:08:39] [PASSED] 23 VFs
[11:08:39] [PASSED] 24 VFs
[11:08:39] [PASSED] 25 VFs
[11:08:39] [PASSED] 26 VFs
[11:08:39] [PASSED] 27 VFs
[11:08:39] [PASSED] 28 VFs
[11:08:39] [PASSED] 29 VFs
[11:08:39] [PASSED] 30 VFs
[11:08:39] [PASSED] 31 VFs
[11:08:39] [PASSED] 32 VFs
[11:08:39] [PASSED] 33 VFs
[11:08:39] [PASSED] 34 VFs
[11:08:39] [PASSED] 35 VFs
[11:08:39] [PASSED] 36 VFs
[11:08:39] [PASSED] 37 VFs
[11:08:39] [PASSED] 38 VFs
[11:08:39] [PASSED] 39 VFs
[11:08:39] [PASSED] 40 VFs
[11:08:39] [PASSED] 41 VFs
[11:08:39] [PASSED] 42 VFs
[11:08:39] [PASSED] 43 VFs
[11:08:39] [PASSED] 44 VFs
[11:08:39] [PASSED] 45 VFs
[11:08:39] [PASSED] 46 VFs
[11:08:39] [PASSED] 47 VFs
[11:08:39] [PASSED] 48 VFs
[11:08:39] [PASSED] 49 VFs
[11:08:39] [PASSED] 50 VFs
[11:08:39] [PASSED] 51 VFs
[11:08:39] [PASSED] 52 VFs
[11:08:39] [PASSED] 53 VFs
[11:08:39] [PASSED] 54 VFs
[11:08:39] [PASSED] 55 VFs
[11:08:39] [PASSED] 56 VFs
[11:08:39] [PASSED] 57 VFs
[11:08:39] [PASSED] 58 VFs
[11:08:39] [PASSED] 59 VFs
[11:08:39] [PASSED] 60 VFs
[11:08:39] [PASSED] 61 VFs
[11:08:39] [PASSED] 62 VFs
[11:08:39] [PASSED] 63 VFs
[11:08:39] ==================== [PASSED] fair_vram ====================
[11:08:39] ================== [PASSED] pf_gt_config ===================
[11:08:39] ===================== lmtt (1 subtest) =====================
[11:08:39] ======================== test_ops  =========================
[11:08:39] [PASSED] 2-level
[11:08:39] [PASSED] multi-level
[11:08:39] ==================== [PASSED] test_ops =====================
[11:08:39] ====================== [PASSED] lmtt =======================
[11:08:39] ================= pf_service (11 subtests) =================
[11:08:39] [PASSED] pf_negotiate_any
[11:08:39] [PASSED] pf_negotiate_base_match
[11:08:39] [PASSED] pf_negotiate_base_newer
[11:08:39] [PASSED] pf_negotiate_base_next
[11:08:39] [SKIPPED] pf_negotiate_base_older
[11:08:39] [PASSED] pf_negotiate_base_prev
[11:08:39] [PASSED] pf_negotiate_latest_match
[11:08:39] [PASSED] pf_negotiate_latest_newer
[11:08:39] [PASSED] pf_negotiate_latest_next
[11:08:39] [SKIPPED] pf_negotiate_latest_older
[11:08:39] [SKIPPED] pf_negotiate_latest_prev
[11:08:39] =================== [PASSED] pf_service ====================
[11:08:39] ================= xe_guc_g2g (2 subtests) ==================
[11:08:39] ============== xe_live_guc_g2g_kunit_default  ==============
[11:08:39] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[11:08:39] ============== xe_live_guc_g2g_kunit_allmem  ===============
[11:08:39] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[11:08:39] =================== [SKIPPED] xe_guc_g2g ===================
[11:08:39] =================== xe_mocs (2 subtests) ===================
[11:08:39] ================ xe_live_mocs_kernel_kunit  ================
[11:08:39] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[11:08:39] ================ xe_live_mocs_reset_kunit  =================
[11:08:39] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[11:08:39] ==================== [SKIPPED] xe_mocs =====================
[11:08:39] ================= xe_migrate (2 subtests) ==================
[11:08:39] ================= xe_migrate_sanity_kunit  =================
[11:08:39] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[11:08:39] ================== xe_validate_ccs_kunit  ==================
[11:08:39] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[11:08:39] =================== [SKIPPED] xe_migrate ===================
[11:08:39] ================== xe_dma_buf (1 subtest) ==================
[11:08:39] ==================== xe_dma_buf_kunit  =====================
[11:08:39] ================ [SKIPPED] xe_dma_buf_kunit ================
[11:08:39] =================== [SKIPPED] xe_dma_buf ===================
[11:08:39] ================= xe_bo_shrink (1 subtest) =================
[11:08:39] =================== xe_bo_shrink_kunit  ====================
[11:08:39] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[11:08:39] ================== [SKIPPED] xe_bo_shrink ==================
[11:08:39] ==================== xe_bo (2 subtests) ====================
[11:08:39] ================== xe_ccs_migrate_kunit  ===================
[11:08:39] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[11:08:39] ==================== xe_bo_evict_kunit  ====================
[11:08:39] =============== [SKIPPED] xe_bo_evict_kunit ================
[11:08:39] ===================== [SKIPPED] xe_bo ======================
[11:08:39] ==================== args (13 subtests) ====================
[11:08:39] [PASSED] count_args_test
[11:08:39] [PASSED] call_args_example
[11:08:39] [PASSED] call_args_test
[11:08:39] [PASSED] drop_first_arg_example
[11:08:39] [PASSED] drop_first_arg_test
[11:08:39] [PASSED] first_arg_example
[11:08:39] [PASSED] first_arg_test
[11:08:39] [PASSED] last_arg_example
[11:08:39] [PASSED] last_arg_test
[11:08:39] [PASSED] pick_arg_example
[11:08:39] [PASSED] if_args_example
[11:08:39] [PASSED] if_args_test
[11:08:39] [PASSED] sep_comma_example
[11:08:39] ====================== [PASSED] args =======================
[11:08:39] =================== xe_pci (3 subtests) ====================
[11:08:39] ==================== check_graphics_ip  ====================
[11:08:39] [PASSED] 12.00 Xe_LP
[11:08:39] [PASSED] 12.10 Xe_LP+
[11:08:39] [PASSED] 12.55 Xe_HPG
[11:08:39] [PASSED] 12.60 Xe_HPC
[11:08:39] [PASSED] 12.70 Xe_LPG
[11:08:39] [PASSED] 12.71 Xe_LPG
[11:08:39] [PASSED] 12.74 Xe_LPG+
[11:08:39] [PASSED] 20.01 Xe2_HPG
[11:08:39] [PASSED] 20.02 Xe2_HPG
[11:08:39] [PASSED] 20.04 Xe2_LPG
[11:08:39] [PASSED] 30.00 Xe3_LPG
[11:08:39] [PASSED] 30.01 Xe3_LPG
[11:08:39] [PASSED] 30.03 Xe3_LPG
[11:08:39] [PASSED] 30.04 Xe3_LPG
[11:08:39] [PASSED] 30.05 Xe3_LPG
[11:08:39] [PASSED] 35.10 Xe3p_LPG
[11:08:39] [PASSED] 35.11 Xe3p_XPC
[11:08:39] ================ [PASSED] check_graphics_ip ================
[11:08:39] ===================== check_media_ip  ======================
[11:08:39] [PASSED] 12.00 Xe_M
[11:08:39] [PASSED] 12.55 Xe_HPM
[11:08:39] [PASSED] 13.00 Xe_LPM+
[11:08:39] [PASSED] 13.01 Xe2_HPM
[11:08:39] [PASSED] 20.00 Xe2_LPM
[11:08:39] [PASSED] 30.00 Xe3_LPM
[11:08:39] [PASSED] 30.02 Xe3_LPM
[11:08:39] [PASSED] 35.00 Xe3p_LPM
[11:08:39] [PASSED] 35.03 Xe3p_HPM
[11:08:39] ================= [PASSED] check_media_ip ==================
[11:08:39] =================== check_platform_desc  ===================
[11:08:39] [PASSED] 0x9A60 (TIGERLAKE)
[11:08:39] [PASSED] 0x9A68 (TIGERLAKE)
[11:08:39] [PASSED] 0x9A70 (TIGERLAKE)
[11:08:39] [PASSED] 0x9A40 (TIGERLAKE)
[11:08:39] [PASSED] 0x9A49 (TIGERLAKE)
[11:08:39] [PASSED] 0x9A59 (TIGERLAKE)
[11:08:39] [PASSED] 0x9A78 (TIGERLAKE)
[11:08:39] [PASSED] 0x9AC0 (TIGERLAKE)
[11:08:39] [PASSED] 0x9AC9 (TIGERLAKE)
[11:08:39] [PASSED] 0x9AD9 (TIGERLAKE)
[11:08:39] [PASSED] 0x9AF8 (TIGERLAKE)
[11:08:39] [PASSED] 0x4C80 (ROCKETLAKE)
[11:08:39] [PASSED] 0x4C8A (ROCKETLAKE)
[11:08:39] [PASSED] 0x4C8B (ROCKETLAKE)
[11:08:39] [PASSED] 0x4C8C (ROCKETLAKE)
[11:08:39] [PASSED] 0x4C90 (ROCKETLAKE)
[11:08:39] [PASSED] 0x4C9A (ROCKETLAKE)
[11:08:39] [PASSED] 0x4680 (ALDERLAKE_S)
[11:08:39] [PASSED] 0x4682 (ALDERLAKE_S)
[11:08:39] [PASSED] 0x4688 (ALDERLAKE_S)
[11:08:39] [PASSED] 0x468A (ALDERLAKE_S)
[11:08:39] [PASSED] 0x468B (ALDERLAKE_S)
[11:08:39] [PASSED] 0x4690 (ALDERLAKE_S)
[11:08:39] [PASSED] 0x4692 (ALDERLAKE_S)
[11:08:39] [PASSED] 0x4693 (ALDERLAKE_S)
[11:08:39] [PASSED] 0x46A0 (ALDERLAKE_P)
[11:08:39] [PASSED] 0x46A1 (ALDERLAKE_P)
[11:08:39] [PASSED] 0x46A2 (ALDERLAKE_P)
[11:08:39] [PASSED] 0x46A3 (ALDERLAKE_P)
[11:08:39] [PASSED] 0x46A6 (ALDERLAKE_P)
[11:08:39] [PASSED] 0x46A8 (ALDERLAKE_P)
[11:08:39] [PASSED] 0x46AA (ALDERLAKE_P)
[11:08:39] [PASSED] 0x462A (ALDERLAKE_P)
[11:08:39] [PASSED] 0x4626 (ALDERLAKE_P)
[11:08:39] [PASSED] 0x4628 (ALDERLAKE_P)
[11:08:39] [PASSED] 0x46B0 (ALDERLAKE_P)
[11:08:39] [PASSED] 0x46B1 (ALDERLAKE_P)
[11:08:39] [PASSED] 0x46B2 (ALDERLAKE_P)
[11:08:39] [PASSED] 0x46B3 (ALDERLAKE_P)
[11:08:39] [PASSED] 0x46C0 (ALDERLAKE_P)
[11:08:39] [PASSED] 0x46C1 (ALDERLAKE_P)
[11:08:39] [PASSED] 0x46C2 (ALDERLAKE_P)
[11:08:39] [PASSED] 0x46C3 (ALDERLAKE_P)
[11:08:39] [PASSED] 0x46D0 (ALDERLAKE_N)
[11:08:39] [PASSED] 0x46D1 (ALDERLAKE_N)
[11:08:39] [PASSED] 0x46D2 (ALDERLAKE_N)
[11:08:39] [PASSED] 0x46D3 (ALDERLAKE_N)
[11:08:39] [PASSED] 0x46D4 (ALDERLAKE_N)
[11:08:39] [PASSED] 0xA721 (ALDERLAKE_P)
[11:08:39] [PASSED] 0xA7A1 (ALDERLAKE_P)
[11:08:39] [PASSED] 0xA7A9 (ALDERLAKE_P)
[11:08:39] [PASSED] 0xA7AC (ALDERLAKE_P)
[11:08:39] [PASSED] 0xA7AD (ALDERLAKE_P)
[11:08:39] [PASSED] 0xA720 (ALDERLAKE_P)
[11:08:39] [PASSED] 0xA7A0 (ALDERLAKE_P)
[11:08:39] [PASSED] 0xA7A8 (ALDERLAKE_P)
[11:08:39] [PASSED] 0xA7AA (ALDERLAKE_P)
[11:08:39] [PASSED] 0xA7AB (ALDERLAKE_P)
[11:08:39] [PASSED] 0xA780 (ALDERLAKE_S)
[11:08:39] [PASSED] 0xA781 (ALDERLAKE_S)
[11:08:39] [PASSED] 0xA782 (ALDERLAKE_S)
[11:08:39] [PASSED] 0xA783 (ALDERLAKE_S)
[11:08:39] [PASSED] 0xA788 (ALDERLAKE_S)
[11:08:39] [PASSED] 0xA789 (ALDERLAKE_S)
[11:08:39] [PASSED] 0xA78A (ALDERLAKE_S)
[11:08:39] [PASSED] 0xA78B (ALDERLAKE_S)
[11:08:39] [PASSED] 0x4905 (DG1)
[11:08:39] [PASSED] 0x4906 (DG1)
[11:08:39] [PASSED] 0x4907 (DG1)
[11:08:39] [PASSED] 0x4908 (DG1)
[11:08:39] [PASSED] 0x4909 (DG1)
[11:08:39] [PASSED] 0x56C0 (DG2)
[11:08:39] [PASSED] 0x56C2 (DG2)
[11:08:39] [PASSED] 0x56C1 (DG2)
[11:08:39] [PASSED] 0x7D51 (METEORLAKE)
[11:08:39] [PASSED] 0x7DD1 (METEORLAKE)
[11:08:39] [PASSED] 0x7D41 (METEORLAKE)
[11:08:39] [PASSED] 0x7D67 (METEORLAKE)
[11:08:39] [PASSED] 0xB640 (METEORLAKE)
[11:08:39] [PASSED] 0x56A0 (DG2)
[11:08:39] [PASSED] 0x56A1 (DG2)
[11:08:39] [PASSED] 0x56A2 (DG2)
[11:08:39] [PASSED] 0x56BE (DG2)
[11:08:39] [PASSED] 0x56BF (DG2)
[11:08:39] [PASSED] 0x5690 (DG2)
[11:08:39] [PASSED] 0x5691 (DG2)
[11:08:39] [PASSED] 0x5692 (DG2)
[11:08:39] [PASSED] 0x56A5 (DG2)
[11:08:39] [PASSED] 0x56A6 (DG2)
[11:08:39] [PASSED] 0x56B0 (DG2)
[11:08:39] [PASSED] 0x56B1 (DG2)
[11:08:39] [PASSED] 0x56BA (DG2)
[11:08:39] [PASSED] 0x56BB (DG2)
[11:08:39] [PASSED] 0x56BC (DG2)
[11:08:39] [PASSED] 0x56BD (DG2)
[11:08:39] [PASSED] 0x5693 (DG2)
[11:08:39] [PASSED] 0x5694 (DG2)
[11:08:39] [PASSED] 0x5695 (DG2)
[11:08:39] [PASSED] 0x56A3 (DG2)
[11:08:39] [PASSED] 0x56A4 (DG2)
[11:08:39] [PASSED] 0x56B2 (DG2)
[11:08:39] [PASSED] 0x56B3 (DG2)
[11:08:39] [PASSED] 0x5696 (DG2)
[11:08:39] [PASSED] 0x5697 (DG2)
[11:08:39] [PASSED] 0xB69 (PVC)
[11:08:39] [PASSED] 0xB6E (PVC)
[11:08:39] [PASSED] 0xBD4 (PVC)
[11:08:39] [PASSED] 0xBD5 (PVC)
[11:08:39] [PASSED] 0xBD6 (PVC)
[11:08:39] [PASSED] 0xBD7 (PVC)
[11:08:39] [PASSED] 0xBD8 (PVC)
[11:08:39] [PASSED] 0xBD9 (PVC)
[11:08:39] [PASSED] 0xBDA (PVC)
[11:08:39] [PASSED] 0xBDB (PVC)
[11:08:39] [PASSED] 0xBE0 (PVC)
[11:08:39] [PASSED] 0xBE1 (PVC)
[11:08:39] [PASSED] 0xBE5 (PVC)
[11:08:39] [PASSED] 0x7D40 (METEORLAKE)
[11:08:39] [PASSED] 0x7D45 (METEORLAKE)
[11:08:39] [PASSED] 0x7D55 (METEORLAKE)
[11:08:39] [PASSED] 0x7D60 (METEORLAKE)
[11:08:39] [PASSED] 0x7DD5 (METEORLAKE)
[11:08:39] [PASSED] 0x6420 (LUNARLAKE)
[11:08:39] [PASSED] 0x64A0 (LUNARLAKE)
[11:08:39] [PASSED] 0x64B0 (LUNARLAKE)
[11:08:39] [PASSED] 0xE202 (BATTLEMAGE)
[11:08:39] [PASSED] 0xE209 (BATTLEMAGE)
[11:08:39] [PASSED] 0xE20B (BATTLEMAGE)
[11:08:39] [PASSED] 0xE20C (BATTLEMAGE)
[11:08:39] [PASSED] 0xE20D (BATTLEMAGE)
[11:08:39] [PASSED] 0xE210 (BATTLEMAGE)
[11:08:39] [PASSED] 0xE211 (BATTLEMAGE)
[11:08:39] [PASSED] 0xE212 (BATTLEMAGE)
[11:08:39] [PASSED] 0xE216 (BATTLEMAGE)
[11:08:39] [PASSED] 0xE220 (BATTLEMAGE)
[11:08:39] [PASSED] 0xE221 (BATTLEMAGE)
[11:08:39] [PASSED] 0xE222 (BATTLEMAGE)
[11:08:39] [PASSED] 0xE223 (BATTLEMAGE)
[11:08:39] [PASSED] 0xB080 (PANTHERLAKE)
[11:08:39] [PASSED] 0xB081 (PANTHERLAKE)
[11:08:39] [PASSED] 0xB082 (PANTHERLAKE)
[11:08:39] [PASSED] 0xB083 (PANTHERLAKE)
[11:08:39] [PASSED] 0xB084 (PANTHERLAKE)
[11:08:39] [PASSED] 0xB085 (PANTHERLAKE)
[11:08:39] [PASSED] 0xB086 (PANTHERLAKE)
[11:08:39] [PASSED] 0xB087 (PANTHERLAKE)
[11:08:39] [PASSED] 0xB08F (PANTHERLAKE)
[11:08:39] [PASSED] 0xB090 (PANTHERLAKE)
[11:08:39] [PASSED] 0xB0A0 (PANTHERLAKE)
[11:08:39] [PASSED] 0xB0B0 (PANTHERLAKE)
[11:08:39] [PASSED] 0xFD80 (PANTHERLAKE)
[11:08:39] [PASSED] 0xFD81 (PANTHERLAKE)
[11:08:39] [PASSED] 0xD740 (NOVALAKE_S)
[11:08:39] [PASSED] 0xD741 (NOVALAKE_S)
[11:08:39] [PASSED] 0xD742 (NOVALAKE_S)
[11:08:39] [PASSED] 0xD743 (NOVALAKE_S)
[11:08:39] [PASSED] 0xD744 (NOVALAKE_S)
[11:08:39] [PASSED] 0xD745 (NOVALAKE_S)
[11:08:39] [PASSED] 0x674C (CRESCENTISLAND)
[11:08:39] [PASSED] 0xD750 (NOVALAKE_P)
[11:08:39] [PASSED] 0xD751 (NOVALAKE_P)
[11:08:39] [PASSED] 0xD752 (NOVALAKE_P)
[11:08:39] [PASSED] 0xD753 (NOVALAKE_P)
[11:08:39] [PASSED] 0xD754 (NOVALAKE_P)
[11:08:39] [PASSED] 0xD755 (NOVALAKE_P)
[11:08:39] [PASSED] 0xD756 (NOVALAKE_P)
[11:08:39] [PASSED] 0xD757 (NOVALAKE_P)
[11:08:39] [PASSED] 0xD75F (NOVALAKE_P)
[11:08:39] =============== [PASSED] check_platform_desc ===============
[11:08:39] ===================== [PASSED] xe_pci ======================
[11:08:39] =================== xe_rtp (2 subtests) ====================
[11:08:39] =============== xe_rtp_process_to_sr_tests  ================
[11:08:39] [PASSED] coalesce-same-reg
[11:08:39] [PASSED] no-match-no-add
[11:08:39] [PASSED] match-or
[11:08:39] [PASSED] match-or-xfail
[11:08:39] [PASSED] no-match-no-add-multiple-rules
[11:08:39] [PASSED] two-regs-two-entries
[11:08:39] [PASSED] clr-one-set-other
[11:08:39] [PASSED] set-field
[11:08:39] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[11:08:39] [PASSED] conflict-not-disjoint
[11:08:39] [PASSED] conflict-reg-type
[11:08:39] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[11:08:39] ================== xe_rtp_process_tests  ===================
[11:08:39] [PASSED] active1
[11:08:39] [PASSED] active2
[11:08:39] [PASSED] active-inactive
[11:08:39] [PASSED] inactive-active
[11:08:39] [PASSED] inactive-1st_or_active-inactive
[11:08:39] [PASSED] inactive-2nd_or_active-inactive
[11:08:39] [PASSED] inactive-last_or_active-inactive
[11:08:39] [PASSED] inactive-no_or_active-inactive
[11:08:39] ============== [PASSED] xe_rtp_process_tests ===============
[11:08:39] ===================== [PASSED] xe_rtp ======================
[11:08:39] ==================== xe_wa (1 subtest) =====================
[11:08:39] ======================== xe_wa_gt  =========================
[11:08:39] [PASSED] TIGERLAKE B0
[11:08:39] [PASSED] DG1 A0
[11:08:39] [PASSED] DG1 B0
[11:08:39] [PASSED] ALDERLAKE_S A0
[11:08:39] [PASSED] ALDERLAKE_S B0
[11:08:39] [PASSED] ALDERLAKE_S C0
[11:08:39] [PASSED] ALDERLAKE_S D0
[11:08:39] [PASSED] ALDERLAKE_P A0
[11:08:39] [PASSED] ALDERLAKE_P B0
[11:08:39] [PASSED] ALDERLAKE_P C0
[11:08:39] [PASSED] ALDERLAKE_S RPLS D0
[11:08:39] [PASSED] ALDERLAKE_P RPLU E0
[11:08:39] [PASSED] DG2 G10 C0
[11:08:39] [PASSED] DG2 G11 B1
[11:08:39] [PASSED] DG2 G12 A1
[11:08:39] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:08:39] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:08:39] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[11:08:39] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[11:08:39] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[11:08:39] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[11:08:39] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[11:08:39] ==================== [PASSED] xe_wa_gt =====================
[11:08:39] ====================== [PASSED] xe_wa ======================
[11:08:39] ============================================================
[11:08:39] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[11:08:39] Elapsed time: 36.104s total, 4.235s configuring, 31.199s building, 0.614s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[11:08:39] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:08:41] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:09:06] Starting KUnit Kernel (1/1)...
[11:09:06] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:09:06] ============ drm_test_pick_cmdline (2 subtests) ============
[11:09:06] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[11:09:06] =============== drm_test_pick_cmdline_named  ===============
[11:09:06] [PASSED] NTSC
[11:09:06] [PASSED] NTSC-J
[11:09:06] [PASSED] PAL
[11:09:06] [PASSED] PAL-M
[11:09:06] =========== [PASSED] drm_test_pick_cmdline_named ===========
[11:09:06] ============== [PASSED] drm_test_pick_cmdline ==============
[11:09:06] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[11:09:06] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[11:09:06] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[11:09:06] =========== drm_validate_clone_mode (2 subtests) ===========
[11:09:06] ============== drm_test_check_in_clone_mode  ===============
[11:09:06] [PASSED] in_clone_mode
[11:09:06] [PASSED] not_in_clone_mode
[11:09:06] ========== [PASSED] drm_test_check_in_clone_mode ===========
[11:09:06] =============== drm_test_check_valid_clones  ===============
[11:09:06] [PASSED] not_in_clone_mode
[11:09:06] [PASSED] valid_clone
[11:09:06] [PASSED] invalid_clone
[11:09:06] =========== [PASSED] drm_test_check_valid_clones ===========
[11:09:06] ============= [PASSED] drm_validate_clone_mode =============
[11:09:06] ============= drm_validate_modeset (1 subtest) =============
[11:09:06] [PASSED] drm_test_check_connector_changed_modeset
[11:09:06] ============== [PASSED] drm_validate_modeset ===============
[11:09:06] ====== drm_test_bridge_get_current_state (2 subtests) ======
[11:09:06] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[11:09:06] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[11:09:06] ======== [PASSED] drm_test_bridge_get_current_state ========
[11:09:06] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[11:09:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[11:09:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[11:09:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[11:09:06] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[11:09:06] ============== drm_bridge_alloc (2 subtests) ===============
[11:09:06] [PASSED] drm_test_drm_bridge_alloc_basic
[11:09:06] [PASSED] drm_test_drm_bridge_alloc_get_put
[11:09:06] ================ [PASSED] drm_bridge_alloc =================
[11:09:06] ============= drm_cmdline_parser (40 subtests) =============
[11:09:06] [PASSED] drm_test_cmdline_force_d_only
[11:09:06] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:09:06] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:09:06] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:09:06] [PASSED] drm_test_cmdline_force_e_only
[11:09:06] [PASSED] drm_test_cmdline_res
[11:09:06] [PASSED] drm_test_cmdline_res_vesa
[11:09:06] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:09:06] [PASSED] drm_test_cmdline_res_rblank
[11:09:06] [PASSED] drm_test_cmdline_res_bpp
[11:09:06] [PASSED] drm_test_cmdline_res_refresh
[11:09:06] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:09:06] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:09:06] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:09:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:09:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:09:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:09:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:09:06] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:09:06] [PASSED] drm_test_cmdline_res_margins_force_on
[11:09:06] [PASSED] drm_test_cmdline_res_vesa_margins
[11:09:06] [PASSED] drm_test_cmdline_name
[11:09:06] [PASSED] drm_test_cmdline_name_bpp
[11:09:06] [PASSED] drm_test_cmdline_name_option
[11:09:06] [PASSED] drm_test_cmdline_name_bpp_option
[11:09:06] [PASSED] drm_test_cmdline_rotate_0
[11:09:06] [PASSED] drm_test_cmdline_rotate_90
[11:09:06] [PASSED] drm_test_cmdline_rotate_180
[11:09:06] [PASSED] drm_test_cmdline_rotate_270
[11:09:06] [PASSED] drm_test_cmdline_hmirror
[11:09:06] [PASSED] drm_test_cmdline_vmirror
[11:09:06] [PASSED] drm_test_cmdline_margin_options
[11:09:06] [PASSED] drm_test_cmdline_multiple_options
[11:09:06] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:09:06] [PASSED] drm_test_cmdline_extra_and_option
[11:09:06] [PASSED] drm_test_cmdline_freestanding_options
[11:09:06] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:09:06] [PASSED] drm_test_cmdline_panel_orientation
[11:09:06] ================ drm_test_cmdline_invalid  =================
[11:09:06] [PASSED] margin_only
[11:09:06] [PASSED] interlace_only
[11:09:06] [PASSED] res_missing_x
[11:09:06] [PASSED] res_missing_y
[11:09:06] [PASSED] res_bad_y
[11:09:06] [PASSED] res_missing_y_bpp
[11:09:06] [PASSED] res_bad_bpp
[11:09:06] [PASSED] res_bad_refresh
[11:09:06] [PASSED] res_bpp_refresh_force_on_off
[11:09:06] [PASSED] res_invalid_mode
[11:09:06] [PASSED] res_bpp_wrong_place_mode
[11:09:06] [PASSED] name_bpp_refresh
[11:09:06] [PASSED] name_refresh
[11:09:06] [PASSED] name_refresh_wrong_mode
[11:09:06] [PASSED] name_refresh_invalid_mode
[11:09:06] [PASSED] rotate_multiple
[11:09:06] [PASSED] rotate_invalid_val
[11:09:06] [PASSED] rotate_truncated
[11:09:06] [PASSED] invalid_option
[11:09:06] [PASSED] invalid_tv_option
[11:09:06] [PASSED] truncated_tv_option
[11:09:06] ============ [PASSED] drm_test_cmdline_invalid =============
[11:09:06] =============== drm_test_cmdline_tv_options  ===============
[11:09:06] [PASSED] NTSC
[11:09:06] [PASSED] NTSC_443
[11:09:06] [PASSED] NTSC_J
[11:09:06] [PASSED] PAL
[11:09:06] [PASSED] PAL_M
[11:09:06] [PASSED] PAL_N
[11:09:06] [PASSED] SECAM
[11:09:06] [PASSED] MONO_525
[11:09:06] [PASSED] MONO_625
[11:09:06] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:09:06] =============== [PASSED] drm_cmdline_parser ================
[11:09:06] ========== drmm_connector_hdmi_init (20 subtests) ==========
[11:09:06] [PASSED] drm_test_connector_hdmi_init_valid
[11:09:06] [PASSED] drm_test_connector_hdmi_init_bpc_8
[11:09:06] [PASSED] drm_test_connector_hdmi_init_bpc_10
[11:09:06] [PASSED] drm_test_connector_hdmi_init_bpc_12
[11:09:06] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[11:09:06] [PASSED] drm_test_connector_hdmi_init_bpc_null
[11:09:06] [PASSED] drm_test_connector_hdmi_init_formats_empty
[11:09:06] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[11:09:06] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[11:09:06] [PASSED] supported_formats=0x9 yuv420_allowed=1
[11:09:06] [PASSED] supported_formats=0x9 yuv420_allowed=0
[11:09:06] [PASSED] supported_formats=0x5 yuv420_allowed=1
[11:09:06] [PASSED] supported_formats=0x5 yuv420_allowed=0
[11:09:06] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:09:06] [PASSED] drm_test_connector_hdmi_init_null_ddc
[11:09:06] [PASSED] drm_test_connector_hdmi_init_null_product
[11:09:06] [PASSED] drm_test_connector_hdmi_init_null_vendor
[11:09:06] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[11:09:06] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[11:09:06] [PASSED] drm_test_connector_hdmi_init_product_valid
[11:09:06] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[11:09:06] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[11:09:06] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[11:09:06] ========= drm_test_connector_hdmi_init_type_valid  =========
[11:09:06] [PASSED] HDMI-A
[11:09:06] [PASSED] HDMI-B
[11:09:06] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[11:09:06] ======== drm_test_connector_hdmi_init_type_invalid  ========
[11:09:06] [PASSED] Unknown
[11:09:06] [PASSED] VGA
[11:09:06] [PASSED] DVI-I
[11:09:06] [PASSED] DVI-D
[11:09:06] [PASSED] DVI-A
[11:09:06] [PASSED] Composite
[11:09:06] [PASSED] SVIDEO
[11:09:06] [PASSED] LVDS
[11:09:06] [PASSED] Component
[11:09:06] [PASSED] DIN
[11:09:06] [PASSED] DP
[11:09:06] [PASSED] TV
[11:09:06] [PASSED] eDP
[11:09:06] [PASSED] Virtual
[11:09:06] [PASSED] DSI
[11:09:06] [PASSED] DPI
[11:09:06] [PASSED] Writeback
[11:09:06] [PASSED] SPI
[11:09:06] [PASSED] USB
[11:09:06] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[11:09:06] ============ [PASSED] drmm_connector_hdmi_init =============
[11:09:06] ============= drmm_connector_init (3 subtests) =============
[11:09:06] [PASSED] drm_test_drmm_connector_init
[11:09:06] [PASSED] drm_test_drmm_connector_init_null_ddc
[11:09:06] ========= drm_test_drmm_connector_init_type_valid  =========
[11:09:06] [PASSED] Unknown
[11:09:06] [PASSED] VGA
[11:09:06] [PASSED] DVI-I
[11:09:06] [PASSED] DVI-D
[11:09:06] [PASSED] DVI-A
[11:09:06] [PASSED] Composite
[11:09:06] [PASSED] SVIDEO
[11:09:06] [PASSED] LVDS
[11:09:06] [PASSED] Component
[11:09:06] [PASSED] DIN
[11:09:06] [PASSED] DP
[11:09:06] [PASSED] HDMI-A
[11:09:06] [PASSED] HDMI-B
[11:09:06] [PASSED] TV
[11:09:06] [PASSED] eDP
[11:09:06] [PASSED] Virtual
[11:09:06] [PASSED] DSI
[11:09:06] [PASSED] DPI
[11:09:06] [PASSED] Writeback
[11:09:06] [PASSED] SPI
[11:09:06] [PASSED] USB
[11:09:06] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[11:09:06] =============== [PASSED] drmm_connector_init ===============
[11:09:06] ========= drm_connector_dynamic_init (6 subtests) ==========
[11:09:06] [PASSED] drm_test_drm_connector_dynamic_init
[11:09:06] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[11:09:06] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[11:09:06] [PASSED] drm_test_drm_connector_dynamic_init_properties
[11:09:06] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[11:09:06] [PASSED] Unknown
[11:09:06] [PASSED] VGA
[11:09:06] [PASSED] DVI-I
[11:09:06] [PASSED] DVI-D
[11:09:06] [PASSED] DVI-A
[11:09:06] [PASSED] Composite
[11:09:06] [PASSED] SVIDEO
[11:09:06] [PASSED] LVDS
[11:09:06] [PASSED] Component
[11:09:06] [PASSED] DIN
[11:09:06] [PASSED] DP
[11:09:06] [PASSED] HDMI-A
[11:09:06] [PASSED] HDMI-B
[11:09:06] [PASSED] TV
[11:09:06] [PASSED] eDP
[11:09:06] [PASSED] Virtual
[11:09:06] [PASSED] DSI
[11:09:06] [PASSED] DPI
[11:09:06] [PASSED] Writeback
[11:09:06] [PASSED] SPI
[11:09:06] [PASSED] USB
[11:09:06] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[11:09:06] ======== drm_test_drm_connector_dynamic_init_name  =========
[11:09:06] [PASSED] Unknown
[11:09:06] [PASSED] VGA
[11:09:06] [PASSED] DVI-I
[11:09:06] [PASSED] DVI-D
[11:09:06] [PASSED] DVI-A
[11:09:06] [PASSED] Composite
[11:09:06] [PASSED] SVIDEO
[11:09:06] [PASSED] LVDS
[11:09:06] [PASSED] Component
[11:09:06] [PASSED] DIN
[11:09:06] [PASSED] DP
[11:09:06] [PASSED] HDMI-A
[11:09:06] [PASSED] HDMI-B
[11:09:06] [PASSED] TV
[11:09:06] [PASSED] eDP
[11:09:06] [PASSED] Virtual
[11:09:06] [PASSED] DSI
[11:09:06] [PASSED] DPI
[11:09:06] [PASSED] Writeback
[11:09:06] [PASSED] SPI
[11:09:06] [PASSED] USB
[11:09:06] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[11:09:06] =========== [PASSED] drm_connector_dynamic_init ============
[11:09:06] ==== drm_connector_dynamic_register_early (4 subtests) =====
[11:09:06] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[11:09:06] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[11:09:06] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[11:09:06] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[11:09:06] ====== [PASSED] drm_connector_dynamic_register_early =======
[11:09:06] ======= drm_connector_dynamic_register (7 subtests) ========
[11:09:06] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[11:09:06] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[11:09:06] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[11:09:06] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[11:09:06] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[11:09:06] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[11:09:06] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[11:09:06] ========= [PASSED] drm_connector_dynamic_register ==========
[11:09:06] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[11:09:06] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[11:09:06] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[11:09:06] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[11:09:06] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:09:06] ========== drm_test_get_tv_mode_from_name_valid  ===========
[11:09:06] [PASSED] NTSC
[11:09:06] [PASSED] NTSC-443
[11:09:06] [PASSED] NTSC-J
[11:09:06] [PASSED] PAL
[11:09:06] [PASSED] PAL-M
[11:09:06] [PASSED] PAL-N
[11:09:06] [PASSED] SECAM
[11:09:06] [PASSED] Mono
[11:09:06] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:09:06] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:09:06] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:09:06] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[11:09:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[11:09:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[11:09:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[11:09:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[11:09:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[11:09:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[11:09:06] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[11:09:06] [PASSED] VIC 96
[11:09:06] [PASSED] VIC 97
[11:09:06] [PASSED] VIC 101
[11:09:06] [PASSED] VIC 102
[11:09:06] [PASSED] VIC 106
[11:09:06] [PASSED] VIC 107
[11:09:06] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[11:09:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[11:09:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[11:09:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[11:09:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[11:09:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[11:09:06] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[11:09:06] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[11:09:06] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[11:09:06] [PASSED] Automatic
[11:09:06] [PASSED] Full
[11:09:06] [PASSED] Limited 16:235
[11:09:06] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[11:09:06] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[11:09:06] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[11:09:06] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[11:09:06] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[11:09:06] [PASSED] RGB
[11:09:06] [PASSED] YUV 4:2:0
[11:09:06] [PASSED] YUV 4:2:2
[11:09:06] [PASSED] YUV 4:4:4
[11:09:06] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[11:09:06] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[11:09:06] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[11:09:06] ============= drm_damage_helper (21 subtests) ==============
[11:09:06] [PASSED] drm_test_damage_iter_no_damage
[11:09:06] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:09:06] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:09:06] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:09:06] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:09:06] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:09:06] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:09:06] [PASSED] drm_test_damage_iter_simple_damage
[11:09:06] [PASSED] drm_test_damage_iter_single_damage
[11:09:06] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:09:06] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:09:06] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:09:06] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:09:06] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:09:06] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:09:06] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:09:06] [PASSED] drm_test_damage_iter_damage
[11:09:06] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:09:06] [PASSED] drm_test_damage_iter_damage_one_outside
[11:09:06] [PASSED] drm_test_damage_iter_damage_src_moved
[11:09:06] [PASSED] drm_test_damage_iter_damage_not_visible
[11:09:06] ================ [PASSED] drm_damage_helper ================
[11:09:06] ============== drm_dp_mst_helper (3 subtests) ==============
[11:09:06] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[11:09:06] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:09:06] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:09:06] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:09:06] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:09:06] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:09:06] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:09:06] ============== drm_test_dp_mst_calc_pbn_div  ===============
[11:09:06] [PASSED] Link rate 2000000 lane count 4
[11:09:06] [PASSED] Link rate 2000000 lane count 2
[11:09:06] [PASSED] Link rate 2000000 lane count 1
[11:09:06] [PASSED] Link rate 1350000 lane count 4
[11:09:06] [PASSED] Link rate 1350000 lane count 2
[11:09:06] [PASSED] Link rate 1350000 lane count 1
[11:09:06] [PASSED] Link rate 1000000 lane count 4
[11:09:06] [PASSED] Link rate 1000000 lane count 2
[11:09:06] [PASSED] Link rate 1000000 lane count 1
[11:09:06] [PASSED] Link rate 810000 lane count 4
[11:09:06] [PASSED] Link rate 810000 lane count 2
[11:09:06] [PASSED] Link rate 810000 lane count 1
[11:09:06] [PASSED] Link rate 540000 lane count 4
[11:09:06] [PASSED] Link rate 540000 lane count 2
[11:09:06] [PASSED] Link rate 540000 lane count 1
[11:09:06] [PASSED] Link rate 270000 lane count 4
[11:09:06] [PASSED] Link rate 270000 lane count 2
[11:09:06] [PASSED] Link rate 270000 lane count 1
[11:09:06] [PASSED] Link rate 162000 lane count 4
[11:09:06] [PASSED] Link rate 162000 lane count 2
[11:09:06] [PASSED] Link rate 162000 lane count 1
[11:09:06] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[11:09:06] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[11:09:06] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:09:06] [PASSED] DP_POWER_UP_PHY with port number
[11:09:06] [PASSED] DP_POWER_DOWN_PHY with port number
[11:09:06] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:09:06] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:09:06] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:09:06] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:09:06] [PASSED] DP_QUERY_PAYLOAD with port number
[11:09:06] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:09:06] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:09:06] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:09:06] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:09:06] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:09:06] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:09:06] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:09:06] [PASSED] DP_REMOTE_I2C_READ with port number
[11:09:06] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:09:06] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:09:06] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:09:06] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:09:06] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:09:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:09:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:09:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:09:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:09:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:09:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:09:06] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:09:06] ================ [PASSED] drm_dp_mst_helper ================
[11:09:06] ================== drm_exec (7 subtests) ===================
[11:09:06] [PASSED] sanitycheck
[11:09:06] [PASSED] test_lock
[11:09:06] [PASSED] test_lock_unlock
[11:09:06] [PASSED] test_duplicates
[11:09:06] [PASSED] test_prepare
[11:09:06] [PASSED] test_prepare_array
[11:09:06] [PASSED] test_multiple_loops
[11:09:06] ==================== [PASSED] drm_exec =====================
[11:09:06] =========== drm_format_helper_test (17 subtests) ===========
[11:09:06] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[11:09:06] [PASSED] single_pixel_source_buffer
[11:09:06] [PASSED] single_pixel_clip_rectangle
[11:09:06] [PASSED] well_known_colors
[11:09:06] [PASSED] destination_pitch
[11:09:06] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:09:06] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[11:09:06] [PASSED] single_pixel_source_buffer
[11:09:06] [PASSED] single_pixel_clip_rectangle
[11:09:06] [PASSED] well_known_colors
[11:09:06] [PASSED] destination_pitch
[11:09:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:09:06] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[11:09:06] [PASSED] single_pixel_source_buffer
[11:09:06] [PASSED] single_pixel_clip_rectangle
[11:09:06] [PASSED] well_known_colors
[11:09:06] [PASSED] destination_pitch
[11:09:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:09:06] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[11:09:06] [PASSED] single_pixel_source_buffer
[11:09:06] [PASSED] single_pixel_clip_rectangle
[11:09:06] [PASSED] well_known_colors
[11:09:06] [PASSED] destination_pitch
[11:09:06] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:09:06] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[11:09:06] [PASSED] single_pixel_source_buffer
[11:09:06] [PASSED] single_pixel_clip_rectangle
[11:09:06] [PASSED] well_known_colors
[11:09:06] [PASSED] destination_pitch
[11:09:06] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:09:06] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[11:09:06] [PASSED] single_pixel_source_buffer
[11:09:06] [PASSED] single_pixel_clip_rectangle
[11:09:06] [PASSED] well_known_colors
[11:09:06] [PASSED] destination_pitch
[11:09:06] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:09:06] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[11:09:06] [PASSED] single_pixel_source_buffer
[11:09:06] [PASSED] single_pixel_clip_rectangle
[11:09:06] [PASSED] well_known_colors
[11:09:06] [PASSED] destination_pitch
[11:09:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:09:06] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[11:09:06] [PASSED] single_pixel_source_buffer
[11:09:06] [PASSED] single_pixel_clip_rectangle
[11:09:06] [PASSED] well_known_colors
[11:09:06] [PASSED] destination_pitch
[11:09:06] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[11:09:06] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[11:09:06] [PASSED] single_pixel_source_buffer
[11:09:06] [PASSED] single_pixel_clip_rectangle
[11:09:06] [PASSED] well_known_colors
[11:09:06] [PASSED] destination_pitch
[11:09:06] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:09:06] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[11:09:06] [PASSED] single_pixel_source_buffer
[11:09:06] [PASSED] single_pixel_clip_rectangle
[11:09:06] [PASSED] well_known_colors
[11:09:06] [PASSED] destination_pitch
[11:09:06] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:09:06] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[11:09:06] [PASSED] single_pixel_source_buffer
[11:09:06] [PASSED] single_pixel_clip_rectangle
[11:09:06] [PASSED] well_known_colors
[11:09:06] [PASSED] destination_pitch
[11:09:06] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:09:06] ============== drm_test_fb_xrgb8888_to_mono  ===============
[11:09:06] [PASSED] single_pixel_source_buffer
[11:09:06] [PASSED] single_pixel_clip_rectangle
[11:09:06] [PASSED] well_known_colors
[11:09:06] [PASSED] destination_pitch
[11:09:06] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:09:06] ==================== drm_test_fb_swab  =====================
[11:09:06] [PASSED] single_pixel_source_buffer
[11:09:06] [PASSED] single_pixel_clip_rectangle
[11:09:06] [PASSED] well_known_colors
[11:09:06] [PASSED] destination_pitch
[11:09:06] ================ [PASSED] drm_test_fb_swab =================
[11:09:06] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[11:09:06] [PASSED] single_pixel_source_buffer
[11:09:06] [PASSED] single_pixel_clip_rectangle
[11:09:06] [PASSED] well_known_colors
[11:09:06] [PASSED] destination_pitch
[11:09:06] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[11:09:06] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[11:09:06] [PASSED] single_pixel_source_buffer
[11:09:06] [PASSED] single_pixel_clip_rectangle
[11:09:06] [PASSED] well_known_colors
[11:09:06] [PASSED] destination_pitch
[11:09:06] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[11:09:06] ================= drm_test_fb_clip_offset  =================
[11:09:06] [PASSED] pass through
[11:09:06] [PASSED] horizontal offset
[11:09:06] [PASSED] vertical offset
[11:09:06] [PASSED] horizontal and vertical offset
[11:09:06] [PASSED] horizontal offset (custom pitch)
[11:09:06] [PASSED] vertical offset (custom pitch)
[11:09:06] [PASSED] horizontal and vertical offset (custom pitch)
[11:09:06] ============= [PASSED] drm_test_fb_clip_offset =============
[11:09:06] =================== drm_test_fb_memcpy  ====================
[11:09:06] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[11:09:06] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[11:09:06] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[11:09:06] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[11:09:06] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[11:09:06] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[11:09:06] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[11:09:06] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[11:09:06] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[11:09:06] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[11:09:06] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[11:09:06] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[11:09:06] =============== [PASSED] drm_test_fb_memcpy ================
[11:09:06] ============= [PASSED] drm_format_helper_test ==============
[11:09:06] ================= drm_format (18 subtests) =================
[11:09:06] [PASSED] drm_test_format_block_width_invalid
[11:09:06] [PASSED] drm_test_format_block_width_one_plane
[11:09:06] [PASSED] drm_test_format_block_width_two_plane
[11:09:06] [PASSED] drm_test_format_block_width_three_plane
[11:09:06] [PASSED] drm_test_format_block_width_tiled
[11:09:06] [PASSED] drm_test_format_block_height_invalid
[11:09:06] [PASSED] drm_test_format_block_height_one_plane
[11:09:06] [PASSED] drm_test_format_block_height_two_plane
[11:09:06] [PASSED] drm_test_format_block_height_three_plane
[11:09:06] [PASSED] drm_test_format_block_height_tiled
[11:09:06] [PASSED] drm_test_format_min_pitch_invalid
[11:09:06] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:09:06] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:09:06] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:09:06] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:09:06] [PASSED] drm_test_format_min_pitch_two_plane
[11:09:06] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:09:06] [PASSED] drm_test_format_min_pitch_tiled
[11:09:06] =================== [PASSED] drm_format ====================
[11:09:06] ============== drm_framebuffer (10 subtests) ===============
[11:09:06] ========== drm_test_framebuffer_check_src_coords  ==========
[11:09:06] [PASSED] Success: source fits into fb
[11:09:06] [PASSED] Fail: overflowing fb with x-axis coordinate
[11:09:06] [PASSED] Fail: overflowing fb with y-axis coordinate
[11:09:06] [PASSED] Fail: overflowing fb with source width
[11:09:06] [PASSED] Fail: overflowing fb with source height
[11:09:06] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[11:09:06] [PASSED] drm_test_framebuffer_cleanup
[11:09:06] =============== drm_test_framebuffer_create  ===============
[11:09:06] [PASSED] ABGR8888 normal sizes
[11:09:06] [PASSED] ABGR8888 max sizes
[11:09:06] [PASSED] ABGR8888 pitch greater than min required
[11:09:06] [PASSED] ABGR8888 pitch less than min required
[11:09:06] [PASSED] ABGR8888 Invalid width
[11:09:06] [PASSED] ABGR8888 Invalid buffer handle
[11:09:06] [PASSED] No pixel format
[11:09:06] [PASSED] ABGR8888 Width 0
[11:09:06] [PASSED] ABGR8888 Height 0
[11:09:06] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:09:06] [PASSED] ABGR8888 Large buffer offset
[11:09:06] [PASSED] ABGR8888 Buffer offset for inexistent plane
[11:09:06] [PASSED] ABGR8888 Invalid flag
[11:09:06] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:09:06] [PASSED] ABGR8888 Valid buffer modifier
[11:09:06] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:09:06] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:09:06] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:09:06] [PASSED] NV12 Normal sizes
[11:09:06] [PASSED] NV12 Max sizes
[11:09:06] [PASSED] NV12 Invalid pitch
[11:09:06] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:09:06] [PASSED] NV12 different  modifier per-plane
[11:09:06] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:09:06] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:09:06] [PASSED] NV12 Modifier for inexistent plane
[11:09:06] [PASSED] NV12 Handle for inexistent plane
[11:09:06] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:09:06] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:09:06] [PASSED] YVU420 Normal sizes
[11:09:06] [PASSED] YVU420 Max sizes
[11:09:06] [PASSED] YVU420 Invalid pitch
[11:09:06] [PASSED] YVU420 Different pitches
[11:09:06] [PASSED] YVU420 Different buffer offsets/pitches
[11:09:06] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:09:06] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:09:06] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:09:06] [PASSED] YVU420 Valid modifier
[11:09:06] [PASSED] YVU420 Different modifiers per plane
[11:09:06] [PASSED] YVU420 Modifier for inexistent plane
[11:09:06] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[11:09:06] [PASSED] X0L2 Normal sizes
[11:09:06] [PASSED] X0L2 Max sizes
[11:09:06] [PASSED] X0L2 Invalid pitch
[11:09:06] [PASSED] X0L2 Pitch greater than minimum required
[11:09:06] [PASSED] X0L2 Handle for inexistent plane
[11:09:06] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:09:06] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:09:06] [PASSED] X0L2 Valid modifier
[11:09:06] [PASSED] X0L2 Modifier for inexistent plane
[11:09:06] =========== [PASSED] drm_test_framebuffer_create ===========
[11:09:06] [PASSED] drm_test_framebuffer_free
[11:09:06] [PASSED] drm_test_framebuffer_init
[11:09:06] [PASSED] drm_test_framebuffer_init_bad_format
[11:09:06] [PASSED] drm_test_framebuffer_init_dev_mismatch
[11:09:06] [PASSED] drm_test_framebuffer_lookup
[11:09:06] [PASSED] drm_test_framebuffer_lookup_inexistent
[11:09:06] [PASSED] drm_test_framebuffer_modifiers_not_supported
[11:09:06] ================= [PASSED] drm_framebuffer =================
[11:09:06] ================ drm_gem_shmem (8 subtests) ================
[11:09:06] [PASSED] drm_gem_shmem_test_obj_create
[11:09:06] [PASSED] drm_gem_shmem_test_obj_create_private
[11:09:06] [PASSED] drm_gem_shmem_test_pin_pages
[11:09:06] [PASSED] drm_gem_shmem_test_vmap
[11:09:06] [PASSED] drm_gem_shmem_test_get_sg_table
[11:09:06] [PASSED] drm_gem_shmem_test_get_pages_sgt
[11:09:06] [PASSED] drm_gem_shmem_test_madvise
[11:09:06] [PASSED] drm_gem_shmem_test_purge
[11:09:06] ================== [PASSED] drm_gem_shmem ==================
[11:09:06] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[11:09:06] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[11:09:06] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[11:09:06] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[11:09:06] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[11:09:06] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[11:09:06] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[11:09:06] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[11:09:06] [PASSED] Automatic
[11:09:06] [PASSED] Full
[11:09:06] [PASSED] Limited 16:235
[11:09:06] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[11:09:06] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[11:09:06] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[11:09:06] [PASSED] drm_test_check_disable_connector
[11:09:06] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[11:09:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[11:09:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[11:09:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[11:09:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[11:09:06] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[11:09:06] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[11:09:06] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[11:09:06] [PASSED] drm_test_check_output_bpc_dvi
[11:09:06] [PASSED] drm_test_check_output_bpc_format_vic_1
[11:09:06] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[11:09:06] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[11:09:06] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[11:09:06] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[11:09:06] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[11:09:06] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[11:09:06] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[11:09:06] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[11:09:06] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[11:09:06] [PASSED] drm_test_check_broadcast_rgb_value
[11:09:06] [PASSED] drm_test_check_bpc_8_value
[11:09:06] [PASSED] drm_test_check_bpc_10_value
[11:09:06] [PASSED] drm_test_check_bpc_12_value
[11:09:06] [PASSED] drm_test_check_format_value
[11:09:06] [PASSED] drm_test_check_tmds_char_value
[11:09:06] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[11:09:06] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[11:09:06] [PASSED] drm_test_check_mode_valid
[11:09:06] [PASSED] drm_test_check_mode_valid_reject
[11:09:06] [PASSED] drm_test_check_mode_valid_reject_rate
[11:09:06] [PASSED] drm_test_check_mode_valid_reject_max_clock
[11:09:06] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[11:09:06] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[11:09:06] [PASSED] drm_test_check_infoframes
[11:09:06] [PASSED] drm_test_check_reject_avi_infoframe
[11:09:06] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[11:09:06] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[11:09:06] [PASSED] drm_test_check_reject_audio_infoframe
[11:09:06] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[11:09:06] ================= drm_managed (2 subtests) =================
[11:09:06] [PASSED] drm_test_managed_release_action
[11:09:06] [PASSED] drm_test_managed_run_action
[11:09:06] =================== [PASSED] drm_managed ===================
[11:09:06] =================== drm_mm (6 subtests) ====================
[11:09:06] [PASSED] drm_test_mm_init
[11:09:06] [PASSED] drm_test_mm_debug
[11:09:06] [PASSED] drm_test_mm_align32
[11:09:06] [PASSED] drm_test_mm_align64
[11:09:06] [PASSED] drm_test_mm_lowest
[11:09:06] [PASSED] drm_test_mm_highest
[11:09:06] ===================== [PASSED] drm_mm ======================
[11:09:06] ============= drm_modes_analog_tv (5 subtests) =============
[11:09:06] [PASSED] drm_test_modes_analog_tv_mono_576i
[11:09:06] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:09:06] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:09:06] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:09:06] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:09:06] =============== [PASSED] drm_modes_analog_tv ===============
[11:09:06] ============== drm_plane_helper (2 subtests) ===============
[11:09:06] =============== drm_test_check_plane_state  ================
[11:09:06] [PASSED] clipping_simple
[11:09:06] [PASSED] clipping_rotate_reflect
[11:09:06] [PASSED] positioning_simple
[11:09:06] [PASSED] upscaling
[11:09:06] [PASSED] downscaling
[11:09:06] [PASSED] rounding1
[11:09:06] [PASSED] rounding2
[11:09:06] [PASSED] rounding3
[11:09:06] [PASSED] rounding4
[11:09:06] =========== [PASSED] drm_test_check_plane_state ============
[11:09:06] =========== drm_test_check_invalid_plane_state  ============
[11:09:06] [PASSED] positioning_invalid
[11:09:06] [PASSED] upscaling_invalid
[11:09:06] [PASSED] downscaling_invalid
[11:09:06] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:09:06] ================ [PASSED] drm_plane_helper =================
[11:09:06] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:09:06] ====== drm_test_connector_helper_tv_get_modes_check  =======
[11:09:06] [PASSED] None
[11:09:06] [PASSED] PAL
[11:09:06] [PASSED] NTSC
[11:09:06] [PASSED] Both, NTSC Default
[11:09:06] [PASSED] Both, PAL Default
[11:09:06] [PASSED] Both, NTSC Default, with PAL on command-line
[11:09:06] [PASSED] Both, PAL Default, with NTSC on command-line
[11:09:06] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:09:06] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:09:06] ================== drm_rect (9 subtests) ===================
[11:09:06] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:09:06] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:09:06] [PASSED] drm_test_rect_clip_scaled_clipped
[11:09:06] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:09:06] ================= drm_test_rect_intersect  =================
[11:09:06] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:09:06] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:09:06] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:09:06] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:09:06] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:09:06] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:09:06] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:09:06] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:09:06] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:09:06] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:09:06] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:09:06] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:09:06] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:09:06] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:09:06] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[11:09:06] ============= [PASSED] drm_test_rect_intersect =============
[11:09:06] ================ drm_test_rect_calc_hscale  ================
[11:09:06] [PASSED] normal use
[11:09:06] [PASSED] out of max range
[11:09:06] [PASSED] out of min range
[11:09:06] [PASSED] zero dst
[11:09:06] [PASSED] negative src
[11:09:06] [PASSED] negative dst
[11:09:06] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:09:06] ================ drm_test_rect_calc_vscale  ================
[11:09:06] [PASSED] normal use
[11:09:06] [PASSED] out of max range
[11:09:06] [PASSED] out of min range
[11:09:06] [PASSED] zero dst
[11:09:06] [PASSED] negative src
[11:09:06] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[11:09:06] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:09:06] ================== drm_test_rect_rotate  ===================
[11:09:06] [PASSED] reflect-x
[11:09:06] [PASSED] reflect-y
[11:09:06] [PASSED] rotate-0
[11:09:06] [PASSED] rotate-90
[11:09:06] [PASSED] rotate-180
[11:09:06] [PASSED] rotate-270
[11:09:06] ============== [PASSED] drm_test_rect_rotate ===============
[11:09:06] ================ drm_test_rect_rotate_inv  =================
[11:09:06] [PASSED] reflect-x
[11:09:06] [PASSED] reflect-y
[11:09:06] [PASSED] rotate-0
[11:09:06] [PASSED] rotate-90
[11:09:06] [PASSED] rotate-180
[11:09:06] [PASSED] rotate-270
[11:09:06] ============ [PASSED] drm_test_rect_rotate_inv =============
[11:09:06] ==================== [PASSED] drm_rect =====================
[11:09:06] ============ drm_sysfb_modeset_test (1 subtest) ============
[11:09:06] ============ drm_test_sysfb_build_fourcc_list  =============
[11:09:06] [PASSED] no native formats
[11:09:06] [PASSED] XRGB8888 as native format
[11:09:06] [PASSED] remove duplicates
[11:09:06] [PASSED] convert alpha formats
[11:09:06] [PASSED] random formats
[11:09:06] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[11:09:06] ============= [PASSED] drm_sysfb_modeset_test ==============
[11:09:06] ================== drm_fixp (2 subtests) ===================
[11:09:06] [PASSED] drm_test_int2fixp
[11:09:06] [PASSED] drm_test_sm2fixp
[11:09:06] ==================== [PASSED] drm_fixp =====================
[11:09:06] ============================================================
[11:09:06] Testing complete. Ran 621 tests: passed: 621
[11:09:06] Elapsed time: 26.455s total, 1.678s configuring, 24.595s building, 0.180s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
stty: 'standard input': Inappropriate ioctl for device
[11:09:06] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:09:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:09:17] Starting KUnit Kernel (1/1)...
[11:09:17] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:09:17] ================= ttm_device (5 subtests) ==================
[11:09:17] [PASSED] ttm_device_init_basic
[11:09:17] [PASSED] ttm_device_init_multiple
[11:09:17] [PASSED] ttm_device_fini_basic
[11:09:17] [PASSED] ttm_device_init_no_vma_man
[11:09:17] ================== ttm_device_init_pools  ==================
[11:09:17] [PASSED] No DMA allocations, no DMA32 required
[11:09:17] # ttm_device_init_pools: ASSERTION FAILED at drivers/gpu/drm/ttm/tests/ttm_device_test.c:178
[11:09:17] Expected !list_lru_count(&pt.pages) to be false, but is true
[11:09:17] [FAILED] DMA allocations, DMA32 required
[11:09:17] [PASSED] No DMA allocations, DMA32 required
[11:09:17]     # ttm_device_init_pools: ASSERTION FAILED at drivers/gpu/drm/ttm/tests/ttm_device_test.c:178
[11:09:17]     Expected !list_lru_count(&pt.pages) to be false, but is true
[11:09:17] ------------[ cut here ]------------
[11:09:17] WARNING: lib/refcount.c:28 at devres_release_all+0xaa/0x100, CPU#0: kunit_try_catch/46
[11:09:17] refcount_t: underflow; use-after-free.
[11:09:17] CPU: 0 UID: 0 PID: 46 Comm: kunit_try_catch Tainted: G        W        N  7.0.0-rc7-g0d93d3585aa5 #3 VOLUNTARY
[11:09:17] Tainted: [W]=WARN, [N]=TEST
[11:09:17] Stack:
[11:09:17]  6044ed8b 00000000 00000000 00000001
[11:09:17]  ffffff00 6044ed8b 6032367a 00000009
[11:09:17]  0000001c 60043e88 6002381c b60cbd40
[11:09:17] Call Trace:
[11:09:17]  [<6032367a>] ? devres_release_all+0xaa/0x100
[11:09:17]  [<60043e88>] ? dump_stack_lvl+0x5e/0x7a
[11:09:17]  [<6002381c>] ? _printk+0x0/0x65
[11:09:17]  [<6001f09f>] ? __warn.cold+0x79/0x11f
[11:09:17]  [<6001f1d9>] ? warn_slowpath_fmt+0x94/0xa1
[11:09:17]  [<601ef1a0>] ? kernfs_free_rcu+0x0/0x70
[11:09:17]  [<60052e36>] ? um_set_signals+0x36/0x60
[11:09:17]  [<600c5a42>] ? call_rcu+0x52/0x90
[11:09:17]  [<6001f145>] ? warn_slowpath_fmt+0x0/0xa1
[11:09:17]  [<60147f50>] ? kfree+0x0/0x250
[11:09:17]  [<6032367a>] ? devres_release_all+0xaa/0x100
[11:09:17]  [<60396bb0>] ? mutex_unlock+0x0/0x30
[11:09:17]  [<6031c3c0>] ? bus_notify+0x0/0x60
[11:09:17]  [<60396bb0>] ? mutex_unlock+0x0/0x30
[11:09:17]  [<60398620>] ? mutex_lock+0x0/0x40
[11:09:17]  [<6031ca24>] ? device_unbind_cleanup+0x14/0xb0
[11:09:17]  [<6031e1f6>] ? device_release_driver_internal+0x256/0x2b0
[11:09:17]  [<60372210>] ? kobject_put+0x0/0x150
[11:09:17]  [<601f3d40>] ? sysfs_remove_file_ns+0x0/0x20
[11:09:17]  [<6031c00f>] ? bus_remove_device+0x10f/0x1a0
[11:09:17]  [<601f3d40>] ? sysfs_remove_file_ns+0x0/0x20
[11:09:17]  [<601f17b8>] ? kernfs_remove_by_name_ns+0x98/0x130
[11:09:17]  [<60315a8c>] ? device_del+0x1bc/0x600
[11:09:17]  [<60052e00>] ? um_set_signals+0x0/0x60
[11:09:17]  [<6025b2a0>] ? device_unregister_wrapper+0x0/0x10
[11:09:17]  [<60052e00>] ? um_set_signals+0x0/0x60
[11:09:17]  [<60315ee4>] ? device_unregister+0x14/0x40
[11:09:17]  [<60257e66>] ? kunit_release_action+0xf6/0x170
[11:09:17]  [<60257d70>] ? kunit_release_action+0x0/0x170
[11:09:17]  [<6025b2e2>] ? kunit_device_unregister+0x32/0x80
[11:09:17]  [<60259890>] ? kunit_generic_run_threadfn_adapter+0x0/0x30
[11:09:17]  [<6025748e>] ? kunit_try_run_case_cleanup+0x2e/0x40
[11:09:17]  [<602598a6>] ? kunit_generic_run_threadfn_adapter+0x16/0x30
[11:09:17]  [<60081e36>] ? kthread+0xe6/0x150
[11:09:17]  [<60046435>] ? new_thread_handler+0x45/0x60
[11:09:17] ---[ end trace 0000000000000000 ]---
[11:09:17] [FAILED] DMA allocations, no DMA32 required
[11:09:17] # ttm_device_init_pools: pass:2 fail:2 skip:0 total:4
[11:09:17] ============== [FAILED] ttm_device_init_pools ==============
[11:09:17]     # module: ttm_device_test
[11:09:17] # ttm_device: pass:4 fail:1 skip:0 total:5
[11:09:17] # Totals: pass:6 fail:2 skip:0 total:8
[11:09:17] =================== [FAILED] ttm_device ====================
[11:09:17] ================== ttm_pool (8 subtests) ===================
[11:09:17] ================== ttm_pool_alloc_basic  ===================
[11:09:17] [PASSED] One page
[11:09:17] [PASSED] More than one page
[11:09:17] [PASSED] Above the allocation limit
[11:09:17] [PASSED] One page, with coherent DMA mappings enabled
[11:09:17] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:09:17] ============== [PASSED] ttm_pool_alloc_basic ===============
[11:09:17] ============== ttm_pool_alloc_basic_dma_addr  ==============
[11:09:17] [PASSED] One page
[11:09:17] [PASSED] More than one page
[11:09:17] [PASSED] Above the allocation limit
[11:09:17] [PASSED] One page, with coherent DMA mappings enabled
[11:09:17] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:09:17] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[11:09:17] [PASSED] ttm_pool_alloc_order_caching_match
[11:09:17] [PASSED] ttm_pool_alloc_caching_mismatch
[11:09:17] [PASSED] ttm_pool_alloc_order_mismatch
[11:09:17] [PASSED] ttm_pool_free_dma_alloc
[11:09:17] [ERROR] Test: ttm_pool: missing expected subtest!
[11:09:17] 
[11:09:17] Pid: 75, comm: kunit_try_catch Tainted: G        W        N  7.0.0-rc7-g0d93d3585aa5
[11:09:17] RIP: 0033:list_lru_count_node+0xe/0x20
[11:09:17] RSP: 00000000b60cbed8  EFLAGS: 00010246
[11:09:17] RAX: 0000000000000000 RBX: 00000000b6003c90 RCX: 0000000076a4c7d8
[11:09:17] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000076886880
[11:09:17] RBP: 0000000076886800 R08: 00000000b50bdc28 R09: 0000000076850c80
[11:09:17] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000076850c80
[11:09:17] R13: 0000000060440770 R14: 000000006010eb50 R15: 0000000076886880
[11:09:17] Kernel panic - not syncing: Segfault with no mm
[11:09:17] [CRASHED] 
[11:09:17] [ERROR] Test: ttm_pool: missing expected subtest!
[11:09:17] [CRASHED] 
[11:09:17] [ERROR] Test: ttm_pool: missing subtest result line!
[11:09:17] # module: ttm_pool_test
[11:09:17] ==================== [CRASHED] ttm_pool ====================
[11:09:17] [ERROR] Test: main: missing expected subtest!
[11:09:17] [CRASHED] 
[11:09:17] [ERROR] Test: main: missing expected subtest!
[11:09:17] [CRASHED] 
[11:09:17] [ERROR] Test: main: missing expected subtest!
[11:09:17] [CRASHED] 
[11:09:17] [ERROR] Test: main: missing expected subtest!
[11:09:17] [CRASHED] 
[11:09:17] ============================================================
[11:09:17] Testing complete. Ran 28 tests: passed: 20, failed: 2, crashed: 6, errors: 7
The kernel seems to have crashed; you can decode the stack traces with:
$ scripts/decode_stacktrace.sh .kunit/vmlinux .kunit < .kunit/test.log | tee .kunit/decoded.log | /kernel/tools/testing/kunit/kunit.py parse
[11:09:17] Elapsed time: 11.359s total, 1.735s configuring, 9.357s building, 0.267s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checkpatch: warning for USE drm mm instead of drm SA for CCS read/write (rev5)

[Patchwork]

== Series Details ==

Series: USE drm mm instead of drm SA for CCS read/write (rev5)
URL   : https://patchwork.freedesktop.org/series/163588/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 0137ca7595c36ea2b185d26c179b91324fb74508
Author: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Date:   Wed Apr 8 11:01:48 2026 +0000

    drm/xe/vf: Use drm mm instead of drm sa for CCS read/write
    
    The suballocator algorithm tracks a hole cursor at the last allocation
    and tries to allocate after it. This is optimized for fence-ordered
    progress, where older allocations are expected to become reusable first.
    
    In fence-enabled mode, that ordering assumption holds. In fence-disabled
    mode, allocations may be freed in arbitrary order, so limiting allocation
    to the current hole window can miss valid free space and fail allocations
    despite sufficient total space.
    
    Use DRM memory manager instead of sub-allocator to get rid of this issue
    as CCS read/write operations do not use fences.
    
    Fixes: 864690cf4dd6 ("drm/xe/vf: Attach and detach CCS copy commands with BO")
    Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
    Cc: Matthew Brost <matthew.brost@intel.com>
    Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
    Cc: Maarten Lankhorst <dev@lankhorst.se>
    Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
+ /mt/dim checkpatch 3a8d015ab84eae3d9247736f48648f870ae2a6c5 drm-intel
17d92ca4c68e drm/xe: Add memory pool with shadow support
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#31: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 466 lines checked
0137ca7595c3 drm/xe/vf: Use drm mm instead of drm sa for CCS read/write

✓ CI.KUnit: success for USE drm mm instead of drm SA for CCS read/write (rev5)

[Patchwork]

== Series Details ==

Series: USE drm mm instead of drm SA for CCS read/write (rev5)
URL   : https://patchwork.freedesktop.org/series/163588/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[05:55:08] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:55:13] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:55:47] Starting KUnit Kernel (1/1)...
[05:55:47] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:55:47] ================== guc_buf (11 subtests) ===================
[05:55:47] [PASSED] test_smallest
[05:55:47] [PASSED] test_largest
[05:55:47] [PASSED] test_granular
[05:55:47] [PASSED] test_unique
[05:55:47] [PASSED] test_overlap
[05:55:47] [PASSED] test_reusable
[05:55:47] [PASSED] test_too_big
[05:55:47] [PASSED] test_flush
[05:55:47] [PASSED] test_lookup
[05:55:47] [PASSED] test_data
[05:55:47] [PASSED] test_class
[05:55:47] ===================== [PASSED] guc_buf =====================
[05:55:47] =================== guc_dbm (7 subtests) ===================
[05:55:47] [PASSED] test_empty
[05:55:47] [PASSED] test_default
[05:55:47] ======================== test_size  ========================
[05:55:47] [PASSED] 4
[05:55:47] [PASSED] 8
[05:55:47] [PASSED] 32
[05:55:47] [PASSED] 256
[05:55:47] ==================== [PASSED] test_size ====================
[05:55:47] ======================= test_reuse  ========================
[05:55:47] [PASSED] 4
[05:55:47] [PASSED] 8
[05:55:47] [PASSED] 32
[05:55:47] [PASSED] 256
[05:55:47] =================== [PASSED] test_reuse ====================
[05:55:47] =================== test_range_overlap  ====================
[05:55:47] [PASSED] 4
[05:55:47] [PASSED] 8
[05:55:47] [PASSED] 32
[05:55:47] [PASSED] 256
[05:55:47] =============== [PASSED] test_range_overlap ================
[05:55:47] =================== test_range_compact  ====================
[05:55:47] [PASSED] 4
[05:55:47] [PASSED] 8
[05:55:47] [PASSED] 32
[05:55:47] [PASSED] 256
[05:55:47] =============== [PASSED] test_range_compact ================
[05:55:47] ==================== test_range_spare  =====================
[05:55:47] [PASSED] 4
[05:55:47] [PASSED] 8
[05:55:47] [PASSED] 32
[05:55:47] [PASSED] 256
[05:55:47] ================ [PASSED] test_range_spare =================
[05:55:47] ===================== [PASSED] guc_dbm =====================
[05:55:47] =================== guc_idm (6 subtests) ===================
[05:55:47] [PASSED] bad_init
[05:55:47] [PASSED] no_init
[05:55:47] [PASSED] init_fini
[05:55:47] [PASSED] check_used
[05:55:47] [PASSED] check_quota
[05:55:47] [PASSED] check_all
[05:55:47] ===================== [PASSED] guc_idm =====================
[05:55:47] ================== no_relay (3 subtests) ===================
[05:55:47] [PASSED] xe_drops_guc2pf_if_not_ready
[05:55:47] [PASSED] xe_drops_guc2vf_if_not_ready
[05:55:47] [PASSED] xe_rejects_send_if_not_ready
[05:55:47] ==================== [PASSED] no_relay =====================
[05:55:47] ================== pf_relay (14 subtests) ==================
[05:55:47] [PASSED] pf_rejects_guc2pf_too_short
[05:55:47] [PASSED] pf_rejects_guc2pf_too_long
[05:55:47] [PASSED] pf_rejects_guc2pf_no_payload
[05:55:47] [PASSED] pf_fails_no_payload
[05:55:47] [PASSED] pf_fails_bad_origin
[05:55:47] [PASSED] pf_fails_bad_type
[05:55:47] [PASSED] pf_txn_reports_error
[05:55:47] [PASSED] pf_txn_sends_pf2guc
[05:55:47] [PASSED] pf_sends_pf2guc
[05:55:47] [SKIPPED] pf_loopback_nop
[05:55:47] [SKIPPED] pf_loopback_echo
[05:55:47] [SKIPPED] pf_loopback_fail
[05:55:47] [SKIPPED] pf_loopback_busy
[05:55:47] [SKIPPED] pf_loopback_retry
[05:55:47] ==================== [PASSED] pf_relay =====================
[05:55:47] ================== vf_relay (3 subtests) ===================
[05:55:47] [PASSED] vf_rejects_guc2vf_too_short
[05:55:47] [PASSED] vf_rejects_guc2vf_too_long
[05:55:47] [PASSED] vf_rejects_guc2vf_no_payload
[05:55:47] ==================== [PASSED] vf_relay =====================
[05:55:47] ================ pf_gt_config (9 subtests) =================
[05:55:47] [PASSED] fair_contexts_1vf
[05:55:47] [PASSED] fair_doorbells_1vf
[05:55:47] [PASSED] fair_ggtt_1vf
[05:55:47] ====================== fair_vram_1vf  ======================
[05:55:47] [PASSED] 3.50 GiB
[05:55:47] [PASSED] 11.5 GiB
[05:55:47] [PASSED] 15.5 GiB
[05:55:47] [PASSED] 31.5 GiB
[05:55:47] [PASSED] 63.5 GiB
[05:55:47] [PASSED] 1.91 GiB
[05:55:47] ================== [PASSED] fair_vram_1vf ==================
[05:55:47] ================ fair_vram_1vf_admin_only  =================
[05:55:47] [PASSED] 3.50 GiB
[05:55:47] [PASSED] 11.5 GiB
[05:55:47] [PASSED] 15.5 GiB
[05:55:47] [PASSED] 31.5 GiB
[05:55:47] [PASSED] 63.5 GiB
[05:55:47] [PASSED] 1.91 GiB
[05:55:47] ============ [PASSED] fair_vram_1vf_admin_only =============
[05:55:47] ====================== fair_contexts  ======================
[05:55:47] [PASSED] 1 VF
[05:55:47] [PASSED] 2 VFs
[05:55:47] [PASSED] 3 VFs
[05:55:47] [PASSED] 4 VFs
[05:55:47] [PASSED] 5 VFs
[05:55:47] [PASSED] 6 VFs
[05:55:47] [PASSED] 7 VFs
[05:55:47] [PASSED] 8 VFs
[05:55:47] [PASSED] 9 VFs
[05:55:47] [PASSED] 10 VFs
[05:55:47] [PASSED] 11 VFs
[05:55:47] [PASSED] 12 VFs
[05:55:47] [PASSED] 13 VFs
[05:55:47] [PASSED] 14 VFs
[05:55:47] [PASSED] 15 VFs
[05:55:47] [PASSED] 16 VFs
[05:55:47] [PASSED] 17 VFs
[05:55:47] [PASSED] 18 VFs
[05:55:47] [PASSED] 19 VFs
[05:55:47] [PASSED] 20 VFs
[05:55:47] [PASSED] 21 VFs
[05:55:47] [PASSED] 22 VFs
[05:55:47] [PASSED] 23 VFs
[05:55:47] [PASSED] 24 VFs
[05:55:47] [PASSED] 25 VFs
[05:55:47] [PASSED] 26 VFs
[05:55:47] [PASSED] 27 VFs
[05:55:47] [PASSED] 28 VFs
[05:55:47] [PASSED] 29 VFs
[05:55:47] [PASSED] 30 VFs
[05:55:47] [PASSED] 31 VFs
[05:55:47] [PASSED] 32 VFs
[05:55:47] [PASSED] 33 VFs
[05:55:47] [PASSED] 34 VFs
[05:55:47] [PASSED] 35 VFs
[05:55:47] [PASSED] 36 VFs
[05:55:47] [PASSED] 37 VFs
[05:55:47] [PASSED] 38 VFs
[05:55:47] [PASSED] 39 VFs
[05:55:47] [PASSED] 40 VFs
[05:55:47] [PASSED] 41 VFs
[05:55:47] [PASSED] 42 VFs
[05:55:47] [PASSED] 43 VFs
[05:55:47] [PASSED] 44 VFs
[05:55:47] [PASSED] 45 VFs
[05:55:47] [PASSED] 46 VFs
[05:55:47] [PASSED] 47 VFs
[05:55:47] [PASSED] 48 VFs
[05:55:47] [PASSED] 49 VFs
[05:55:47] [PASSED] 50 VFs
[05:55:47] [PASSED] 51 VFs
[05:55:47] [PASSED] 52 VFs
[05:55:47] [PASSED] 53 VFs
[05:55:47] [PASSED] 54 VFs
[05:55:47] [PASSED] 55 VFs
[05:55:47] [PASSED] 56 VFs
[05:55:47] [PASSED] 57 VFs
[05:55:47] [PASSED] 58 VFs
[05:55:47] [PASSED] 59 VFs
[05:55:47] [PASSED] 60 VFs
[05:55:47] [PASSED] 61 VFs
[05:55:47] [PASSED] 62 VFs
[05:55:47] [PASSED] 63 VFs
[05:55:47] ================== [PASSED] fair_contexts ==================
[05:55:47] ===================== fair_doorbells  ======================
[05:55:47] [PASSED] 1 VF
[05:55:47] [PASSED] 2 VFs
[05:55:47] [PASSED] 3 VFs
[05:55:47] [PASSED] 4 VFs
[05:55:47] [PASSED] 5 VFs
[05:55:47] [PASSED] 6 VFs
[05:55:47] [PASSED] 7 VFs
[05:55:47] [PASSED] 8 VFs
[05:55:47] [PASSED] 9 VFs
[05:55:47] [PASSED] 10 VFs
[05:55:47] [PASSED] 11 VFs
[05:55:47] [PASSED] 12 VFs
[05:55:47] [PASSED] 13 VFs
[05:55:47] [PASSED] 14 VFs
[05:55:47] [PASSED] 15 VFs
[05:55:47] [PASSED] 16 VFs
[05:55:47] [PASSED] 17 VFs
[05:55:47] [PASSED] 18 VFs
[05:55:47] [PASSED] 19 VFs
[05:55:47] [PASSED] 20 VFs
[05:55:47] [PASSED] 21 VFs
[05:55:47] [PASSED] 22 VFs
[05:55:47] [PASSED] 23 VFs
[05:55:47] [PASSED] 24 VFs
[05:55:47] [PASSED] 25 VFs
[05:55:47] [PASSED] 26 VFs
[05:55:47] [PASSED] 27 VFs
[05:55:47] [PASSED] 28 VFs
[05:55:47] [PASSED] 29 VFs
[05:55:47] [PASSED] 30 VFs
[05:55:47] [PASSED] 31 VFs
[05:55:47] [PASSED] 32 VFs
[05:55:47] [PASSED] 33 VFs
[05:55:47] [PASSED] 34 VFs
[05:55:47] [PASSED] 35 VFs
[05:55:47] [PASSED] 36 VFs
[05:55:47] [PASSED] 37 VFs
[05:55:47] [PASSED] 38 VFs
[05:55:47] [PASSED] 39 VFs
[05:55:47] [PASSED] 40 VFs
[05:55:47] [PASSED] 41 VFs
[05:55:47] [PASSED] 42 VFs
[05:55:47] [PASSED] 43 VFs
[05:55:47] [PASSED] 44 VFs
[05:55:47] [PASSED] 45 VFs
[05:55:47] [PASSED] 46 VFs
[05:55:47] [PASSED] 47 VFs
[05:55:47] [PASSED] 48 VFs
[05:55:47] [PASSED] 49 VFs
[05:55:47] [PASSED] 50 VFs
[05:55:47] [PASSED] 51 VFs
[05:55:47] [PASSED] 52 VFs
[05:55:47] [PASSED] 53 VFs
[05:55:47] [PASSED] 54 VFs
[05:55:47] [PASSED] 55 VFs
[05:55:47] [PASSED] 56 VFs
[05:55:47] [PASSED] 57 VFs
[05:55:47] [PASSED] 58 VFs
[05:55:47] [PASSED] 59 VFs
[05:55:47] [PASSED] 60 VFs
[05:55:47] [PASSED] 61 VFs
[05:55:47] [PASSED] 62 VFs
[05:55:47] [PASSED] 63 VFs
[05:55:47] ================= [PASSED] fair_doorbells ==================
[05:55:47] ======================== fair_ggtt  ========================
[05:55:47] [PASSED] 1 VF
[05:55:47] [PASSED] 2 VFs
[05:55:47] [PASSED] 3 VFs
[05:55:47] [PASSED] 4 VFs
[05:55:47] [PASSED] 5 VFs
[05:55:47] [PASSED] 6 VFs
[05:55:47] [PASSED] 7 VFs
[05:55:47] [PASSED] 8 VFs
[05:55:47] [PASSED] 9 VFs
[05:55:47] [PASSED] 10 VFs
[05:55:47] [PASSED] 11 VFs
[05:55:47] [PASSED] 12 VFs
[05:55:47] [PASSED] 13 VFs
[05:55:47] [PASSED] 14 VFs
[05:55:47] [PASSED] 15 VFs
[05:55:47] [PASSED] 16 VFs
[05:55:47] [PASSED] 17 VFs
[05:55:47] [PASSED] 18 VFs
[05:55:47] [PASSED] 19 VFs
[05:55:47] [PASSED] 20 VFs
[05:55:47] [PASSED] 21 VFs
[05:55:47] [PASSED] 22 VFs
[05:55:47] [PASSED] 23 VFs
[05:55:47] [PASSED] 24 VFs
[05:55:47] [PASSED] 25 VFs
[05:55:47] [PASSED] 26 VFs
[05:55:47] [PASSED] 27 VFs
[05:55:47] [PASSED] 28 VFs
[05:55:47] [PASSED] 29 VFs
[05:55:47] [PASSED] 30 VFs
[05:55:47] [PASSED] 31 VFs
[05:55:47] [PASSED] 32 VFs
[05:55:47] [PASSED] 33 VFs
[05:55:47] [PASSED] 34 VFs
[05:55:47] [PASSED] 35 VFs
[05:55:47] [PASSED] 36 VFs
[05:55:47] [PASSED] 37 VFs
[05:55:47] [PASSED] 38 VFs
[05:55:47] [PASSED] 39 VFs
[05:55:47] [PASSED] 40 VFs
[05:55:47] [PASSED] 41 VFs
[05:55:47] [PASSED] 42 VFs
[05:55:47] [PASSED] 43 VFs
[05:55:47] [PASSED] 44 VFs
[05:55:47] [PASSED] 45 VFs
[05:55:47] [PASSED] 46 VFs
[05:55:47] [PASSED] 47 VFs
[05:55:47] [PASSED] 48 VFs
[05:55:47] [PASSED] 49 VFs
[05:55:47] [PASSED] 50 VFs
[05:55:47] [PASSED] 51 VFs
[05:55:47] [PASSED] 52 VFs
[05:55:47] [PASSED] 53 VFs
[05:55:47] [PASSED] 54 VFs
[05:55:47] [PASSED] 55 VFs
[05:55:47] [PASSED] 56 VFs
[05:55:47] [PASSED] 57 VFs
[05:55:47] [PASSED] 58 VFs
[05:55:47] [PASSED] 59 VFs
[05:55:47] [PASSED] 60 VFs
[05:55:47] [PASSED] 61 VFs
[05:55:47] [PASSED] 62 VFs
[05:55:47] [PASSED] 63 VFs
[05:55:47] ==================== [PASSED] fair_ggtt ====================
[05:55:47] ======================== fair_vram  ========================
[05:55:47] [PASSED] 1 VF
[05:55:47] [PASSED] 2 VFs
[05:55:47] [PASSED] 3 VFs
[05:55:47] [PASSED] 4 VFs
[05:55:47] [PASSED] 5 VFs
[05:55:47] [PASSED] 6 VFs
[05:55:47] [PASSED] 7 VFs
[05:55:47] [PASSED] 8 VFs
[05:55:47] [PASSED] 9 VFs
[05:55:47] [PASSED] 10 VFs
[05:55:47] [PASSED] 11 VFs
[05:55:47] [PASSED] 12 VFs
[05:55:47] [PASSED] 13 VFs
[05:55:47] [PASSED] 14 VFs
[05:55:48] [PASSED] 15 VFs
[05:55:48] [PASSED] 16 VFs
[05:55:48] [PASSED] 17 VFs
[05:55:48] [PASSED] 18 VFs
[05:55:48] [PASSED] 19 VFs
[05:55:48] [PASSED] 20 VFs
[05:55:48] [PASSED] 21 VFs
[05:55:48] [PASSED] 22 VFs
[05:55:48] [PASSED] 23 VFs
[05:55:48] [PASSED] 24 VFs
[05:55:48] [PASSED] 25 VFs
[05:55:48] [PASSED] 26 VFs
[05:55:48] [PASSED] 27 VFs
[05:55:48] [PASSED] 28 VFs
[05:55:48] [PASSED] 29 VFs
[05:55:48] [PASSED] 30 VFs
[05:55:48] [PASSED] 31 VFs
[05:55:48] [PASSED] 32 VFs
[05:55:48] [PASSED] 33 VFs
[05:55:48] [PASSED] 34 VFs
[05:55:48] [PASSED] 35 VFs
[05:55:48] [PASSED] 36 VFs
[05:55:48] [PASSED] 37 VFs
[05:55:48] [PASSED] 38 VFs
[05:55:48] [PASSED] 39 VFs
[05:55:48] [PASSED] 40 VFs
[05:55:48] [PASSED] 41 VFs
[05:55:48] [PASSED] 42 VFs
[05:55:48] [PASSED] 43 VFs
[05:55:48] [PASSED] 44 VFs
[05:55:48] [PASSED] 45 VFs
[05:55:48] [PASSED] 46 VFs
[05:55:48] [PASSED] 47 VFs
[05:55:48] [PASSED] 48 VFs
[05:55:48] [PASSED] 49 VFs
[05:55:48] [PASSED] 50 VFs
[05:55:48] [PASSED] 51 VFs
[05:55:48] [PASSED] 52 VFs
[05:55:48] [PASSED] 53 VFs
[05:55:48] [PASSED] 54 VFs
[05:55:48] [PASSED] 55 VFs
[05:55:48] [PASSED] 56 VFs
[05:55:48] [PASSED] 57 VFs
[05:55:48] [PASSED] 58 VFs
[05:55:48] [PASSED] 59 VFs
[05:55:48] [PASSED] 60 VFs
[05:55:48] [PASSED] 61 VFs
[05:55:48] [PASSED] 62 VFs
[05:55:48] [PASSED] 63 VFs
[05:55:48] ==================== [PASSED] fair_vram ====================
[05:55:48] ================== [PASSED] pf_gt_config ===================
[05:55:48] ===================== lmtt (1 subtest) =====================
[05:55:48] ======================== test_ops  =========================
[05:55:48] [PASSED] 2-level
[05:55:48] [PASSED] multi-level
[05:55:48] ==================== [PASSED] test_ops =====================
[05:55:48] ====================== [PASSED] lmtt =======================
[05:55:48] ================= pf_service (11 subtests) =================
[05:55:48] [PASSED] pf_negotiate_any
[05:55:48] [PASSED] pf_negotiate_base_match
[05:55:48] [PASSED] pf_negotiate_base_newer
[05:55:48] [PASSED] pf_negotiate_base_next
[05:55:48] [SKIPPED] pf_negotiate_base_older
[05:55:48] [PASSED] pf_negotiate_base_prev
[05:55:48] [PASSED] pf_negotiate_latest_match
[05:55:48] [PASSED] pf_negotiate_latest_newer
[05:55:48] [PASSED] pf_negotiate_latest_next
[05:55:48] [SKIPPED] pf_negotiate_latest_older
[05:55:48] [SKIPPED] pf_negotiate_latest_prev
[05:55:48] =================== [PASSED] pf_service ====================
[05:55:48] ================= xe_guc_g2g (2 subtests) ==================
[05:55:48] ============== xe_live_guc_g2g_kunit_default  ==============
[05:55:48] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[05:55:48] ============== xe_live_guc_g2g_kunit_allmem  ===============
[05:55:48] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[05:55:48] =================== [SKIPPED] xe_guc_g2g ===================
[05:55:48] =================== xe_mocs (2 subtests) ===================
[05:55:48] ================ xe_live_mocs_kernel_kunit  ================
[05:55:48] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[05:55:48] ================ xe_live_mocs_reset_kunit  =================
[05:55:48] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[05:55:48] ==================== [SKIPPED] xe_mocs =====================
[05:55:48] ================= xe_migrate (2 subtests) ==================
[05:55:48] ================= xe_migrate_sanity_kunit  =================
[05:55:48] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[05:55:48] ================== xe_validate_ccs_kunit  ==================
[05:55:48] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[05:55:48] =================== [SKIPPED] xe_migrate ===================
[05:55:48] ================== xe_dma_buf (1 subtest) ==================
[05:55:48] ==================== xe_dma_buf_kunit  =====================
[05:55:48] ================ [SKIPPED] xe_dma_buf_kunit ================
[05:55:48] =================== [SKIPPED] xe_dma_buf ===================
[05:55:48] ================= xe_bo_shrink (1 subtest) =================
[05:55:48] =================== xe_bo_shrink_kunit  ====================
[05:55:48] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[05:55:48] ================== [SKIPPED] xe_bo_shrink ==================
[05:55:48] ==================== xe_bo (2 subtests) ====================
[05:55:48] ================== xe_ccs_migrate_kunit  ===================
[05:55:48] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[05:55:48] ==================== xe_bo_evict_kunit  ====================
[05:55:48] =============== [SKIPPED] xe_bo_evict_kunit ================
[05:55:48] ===================== [SKIPPED] xe_bo ======================
[05:55:48] ==================== args (13 subtests) ====================
[05:55:48] [PASSED] count_args_test
[05:55:48] [PASSED] call_args_example
[05:55:48] [PASSED] call_args_test
[05:55:48] [PASSED] drop_first_arg_example
[05:55:48] [PASSED] drop_first_arg_test
[05:55:48] [PASSED] first_arg_example
[05:55:48] [PASSED] first_arg_test
[05:55:48] [PASSED] last_arg_example
[05:55:48] [PASSED] last_arg_test
[05:55:48] [PASSED] pick_arg_example
[05:55:48] [PASSED] if_args_example
[05:55:48] [PASSED] if_args_test
[05:55:48] [PASSED] sep_comma_example
[05:55:48] ====================== [PASSED] args =======================
[05:55:48] =================== xe_pci (3 subtests) ====================
[05:55:48] ==================== check_graphics_ip  ====================
[05:55:48] [PASSED] 12.00 Xe_LP
[05:55:48] [PASSED] 12.10 Xe_LP+
[05:55:48] [PASSED] 12.55 Xe_HPG
[05:55:48] [PASSED] 12.60 Xe_HPC
[05:55:48] [PASSED] 12.70 Xe_LPG
[05:55:48] [PASSED] 12.71 Xe_LPG
[05:55:48] [PASSED] 12.74 Xe_LPG+
[05:55:48] [PASSED] 20.01 Xe2_HPG
[05:55:48] [PASSED] 20.02 Xe2_HPG
[05:55:48] [PASSED] 20.04 Xe2_LPG
[05:55:48] [PASSED] 30.00 Xe3_LPG
[05:55:48] [PASSED] 30.01 Xe3_LPG
[05:55:48] [PASSED] 30.03 Xe3_LPG
[05:55:48] [PASSED] 30.04 Xe3_LPG
[05:55:48] [PASSED] 30.05 Xe3_LPG
[05:55:48] [PASSED] 35.10 Xe3p_LPG
[05:55:48] [PASSED] 35.11 Xe3p_XPC
[05:55:48] ================ [PASSED] check_graphics_ip ================
[05:55:48] ===================== check_media_ip  ======================
[05:55:48] [PASSED] 12.00 Xe_M
[05:55:48] [PASSED] 12.55 Xe_HPM
[05:55:48] [PASSED] 13.00 Xe_LPM+
[05:55:48] [PASSED] 13.01 Xe2_HPM
[05:55:48] [PASSED] 20.00 Xe2_LPM
[05:55:48] [PASSED] 30.00 Xe3_LPM
[05:55:48] [PASSED] 30.02 Xe3_LPM
[05:55:48] [PASSED] 35.00 Xe3p_LPM
[05:55:48] [PASSED] 35.03 Xe3p_HPM
[05:55:48] ================= [PASSED] check_media_ip ==================
[05:55:48] =================== check_platform_desc  ===================
[05:55:48] [PASSED] 0x9A60 (TIGERLAKE)
[05:55:48] [PASSED] 0x9A68 (TIGERLAKE)
[05:55:48] [PASSED] 0x9A70 (TIGERLAKE)
[05:55:48] [PASSED] 0x9A40 (TIGERLAKE)
[05:55:48] [PASSED] 0x9A49 (TIGERLAKE)
[05:55:48] [PASSED] 0x9A59 (TIGERLAKE)
[05:55:48] [PASSED] 0x9A78 (TIGERLAKE)
[05:55:48] [PASSED] 0x9AC0 (TIGERLAKE)
[05:55:48] [PASSED] 0x9AC9 (TIGERLAKE)
[05:55:48] [PASSED] 0x9AD9 (TIGERLAKE)
[05:55:48] [PASSED] 0x9AF8 (TIGERLAKE)
[05:55:48] [PASSED] 0x4C80 (ROCKETLAKE)
[05:55:48] [PASSED] 0x4C8A (ROCKETLAKE)
[05:55:48] [PASSED] 0x4C8B (ROCKETLAKE)
[05:55:48] [PASSED] 0x4C8C (ROCKETLAKE)
[05:55:48] [PASSED] 0x4C90 (ROCKETLAKE)
[05:55:48] [PASSED] 0x4C9A (ROCKETLAKE)
[05:55:48] [PASSED] 0x4680 (ALDERLAKE_S)
[05:55:48] [PASSED] 0x4682 (ALDERLAKE_S)
[05:55:48] [PASSED] 0x4688 (ALDERLAKE_S)
[05:55:48] [PASSED] 0x468A (ALDERLAKE_S)
[05:55:48] [PASSED] 0x468B (ALDERLAKE_S)
[05:55:48] [PASSED] 0x4690 (ALDERLAKE_S)
[05:55:48] [PASSED] 0x4692 (ALDERLAKE_S)
[05:55:48] [PASSED] 0x4693 (ALDERLAKE_S)
[05:55:48] [PASSED] 0x46A0 (ALDERLAKE_P)
[05:55:48] [PASSED] 0x46A1 (ALDERLAKE_P)
[05:55:48] [PASSED] 0x46A2 (ALDERLAKE_P)
[05:55:48] [PASSED] 0x46A3 (ALDERLAKE_P)
[05:55:48] [PASSED] 0x46A6 (ALDERLAKE_P)
[05:55:48] [PASSED] 0x46A8 (ALDERLAKE_P)
[05:55:48] [PASSED] 0x46AA (ALDERLAKE_P)
[05:55:48] [PASSED] 0x462A (ALDERLAKE_P)
[05:55:48] [PASSED] 0x4626 (ALDERLAKE_P)
[05:55:48] [PASSED] 0x4628 (ALDERLAKE_P)
[05:55:48] [PASSED] 0x46B0 (ALDERLAKE_P)
[05:55:48] [PASSED] 0x46B1 (ALDERLAKE_P)
[05:55:48] [PASSED] 0x46B2 (ALDERLAKE_P)
[05:55:48] [PASSED] 0x46B3 (ALDERLAKE_P)
[05:55:48] [PASSED] 0x46C0 (ALDERLAKE_P)
[05:55:48] [PASSED] 0x46C1 (ALDERLAKE_P)
[05:55:48] [PASSED] 0x46C2 (ALDERLAKE_P)
[05:55:48] [PASSED] 0x46C3 (ALDERLAKE_P)
[05:55:48] [PASSED] 0x46D0 (ALDERLAKE_N)
[05:55:48] [PASSED] 0x46D1 (ALDERLAKE_N)
[05:55:48] [PASSED] 0x46D2 (ALDERLAKE_N)
[05:55:48] [PASSED] 0x46D3 (ALDERLAKE_N)
[05:55:48] [PASSED] 0x46D4 (ALDERLAKE_N)
[05:55:48] [PASSED] 0xA721 (ALDERLAKE_P)
[05:55:48] [PASSED] 0xA7A1 (ALDERLAKE_P)
[05:55:48] [PASSED] 0xA7A9 (ALDERLAKE_P)
[05:55:48] [PASSED] 0xA7AC (ALDERLAKE_P)
[05:55:48] [PASSED] 0xA7AD (ALDERLAKE_P)
[05:55:48] [PASSED] 0xA720 (ALDERLAKE_P)
[05:55:48] [PASSED] 0xA7A0 (ALDERLAKE_P)
[05:55:48] [PASSED] 0xA7A8 (ALDERLAKE_P)
[05:55:48] [PASSED] 0xA7AA (ALDERLAKE_P)
[05:55:48] [PASSED] 0xA7AB (ALDERLAKE_P)
[05:55:48] [PASSED] 0xA780 (ALDERLAKE_S)
[05:55:48] [PASSED] 0xA781 (ALDERLAKE_S)
[05:55:48] [PASSED] 0xA782 (ALDERLAKE_S)
[05:55:48] [PASSED] 0xA783 (ALDERLAKE_S)
[05:55:48] [PASSED] 0xA788 (ALDERLAKE_S)
[05:55:48] [PASSED] 0xA789 (ALDERLAKE_S)
[05:55:48] [PASSED] 0xA78A (ALDERLAKE_S)
[05:55:48] [PASSED] 0xA78B (ALDERLAKE_S)
[05:55:48] [PASSED] 0x4905 (DG1)
[05:55:48] [PASSED] 0x4906 (DG1)
[05:55:48] [PASSED] 0x4907 (DG1)
[05:55:48] [PASSED] 0x4908 (DG1)
[05:55:48] [PASSED] 0x4909 (DG1)
[05:55:48] [PASSED] 0x56C0 (DG2)
[05:55:48] [PASSED] 0x56C2 (DG2)
[05:55:48] [PASSED] 0x56C1 (DG2)
[05:55:48] [PASSED] 0x7D51 (METEORLAKE)
[05:55:48] [PASSED] 0x7DD1 (METEORLAKE)
[05:55:48] [PASSED] 0x7D41 (METEORLAKE)
[05:55:48] [PASSED] 0x7D67 (METEORLAKE)
[05:55:48] [PASSED] 0xB640 (METEORLAKE)
[05:55:48] [PASSED] 0x56A0 (DG2)
[05:55:48] [PASSED] 0x56A1 (DG2)
[05:55:48] [PASSED] 0x56A2 (DG2)
[05:55:48] [PASSED] 0x56BE (DG2)
[05:55:48] [PASSED] 0x56BF (DG2)
[05:55:48] [PASSED] 0x5690 (DG2)
[05:55:48] [PASSED] 0x5691 (DG2)
[05:55:48] [PASSED] 0x5692 (DG2)
[05:55:48] [PASSED] 0x56A5 (DG2)
[05:55:48] [PASSED] 0x56A6 (DG2)
[05:55:48] [PASSED] 0x56B0 (DG2)
[05:55:48] [PASSED] 0x56B1 (DG2)
[05:55:48] [PASSED] 0x56BA (DG2)
[05:55:48] [PASSED] 0x56BB (DG2)
[05:55:48] [PASSED] 0x56BC (DG2)
[05:55:48] [PASSED] 0x56BD (DG2)
[05:55:48] [PASSED] 0x5693 (DG2)
[05:55:48] [PASSED] 0x5694 (DG2)
[05:55:48] [PASSED] 0x5695 (DG2)
[05:55:48] [PASSED] 0x56A3 (DG2)
[05:55:48] [PASSED] 0x56A4 (DG2)
[05:55:48] [PASSED] 0x56B2 (DG2)
[05:55:48] [PASSED] 0x56B3 (DG2)
[05:55:48] [PASSED] 0x5696 (DG2)
[05:55:48] [PASSED] 0x5697 (DG2)
[05:55:48] [PASSED] 0xB69 (PVC)
[05:55:48] [PASSED] 0xB6E (PVC)
[05:55:48] [PASSED] 0xBD4 (PVC)
[05:55:48] [PASSED] 0xBD5 (PVC)
[05:55:48] [PASSED] 0xBD6 (PVC)
[05:55:48] [PASSED] 0xBD7 (PVC)
[05:55:48] [PASSED] 0xBD8 (PVC)
[05:55:48] [PASSED] 0xBD9 (PVC)
[05:55:48] [PASSED] 0xBDA (PVC)
[05:55:48] [PASSED] 0xBDB (PVC)
[05:55:48] [PASSED] 0xBE0 (PVC)
[05:55:48] [PASSED] 0xBE1 (PVC)
[05:55:48] [PASSED] 0xBE5 (PVC)
[05:55:48] [PASSED] 0x7D40 (METEORLAKE)
[05:55:48] [PASSED] 0x7D45 (METEORLAKE)
[05:55:48] [PASSED] 0x7D55 (METEORLAKE)
[05:55:48] [PASSED] 0x7D60 (METEORLAKE)
[05:55:48] [PASSED] 0x7DD5 (METEORLAKE)
[05:55:48] [PASSED] 0x6420 (LUNARLAKE)
[05:55:48] [PASSED] 0x64A0 (LUNARLAKE)
[05:55:48] [PASSED] 0x64B0 (LUNARLAKE)
[05:55:48] [PASSED] 0xE202 (BATTLEMAGE)
[05:55:48] [PASSED] 0xE209 (BATTLEMAGE)
[05:55:48] [PASSED] 0xE20B (BATTLEMAGE)
[05:55:48] [PASSED] 0xE20C (BATTLEMAGE)
[05:55:48] [PASSED] 0xE20D (BATTLEMAGE)
[05:55:48] [PASSED] 0xE210 (BATTLEMAGE)
[05:55:48] [PASSED] 0xE211 (BATTLEMAGE)
[05:55:48] [PASSED] 0xE212 (BATTLEMAGE)
[05:55:48] [PASSED] 0xE216 (BATTLEMAGE)
[05:55:48] [PASSED] 0xE220 (BATTLEMAGE)
[05:55:48] [PASSED] 0xE221 (BATTLEMAGE)
[05:55:48] [PASSED] 0xE222 (BATTLEMAGE)
[05:55:48] [PASSED] 0xE223 (BATTLEMAGE)
[05:55:48] [PASSED] 0xB080 (PANTHERLAKE)
[05:55:48] [PASSED] 0xB081 (PANTHERLAKE)
[05:55:48] [PASSED] 0xB082 (PANTHERLAKE)
[05:55:48] [PASSED] 0xB083 (PANTHERLAKE)
[05:55:48] [PASSED] 0xB084 (PANTHERLAKE)
[05:55:48] [PASSED] 0xB085 (PANTHERLAKE)
[05:55:48] [PASSED] 0xB086 (PANTHERLAKE)
[05:55:48] [PASSED] 0xB087 (PANTHERLAKE)
[05:55:48] [PASSED] 0xB08F (PANTHERLAKE)
[05:55:48] [PASSED] 0xB090 (PANTHERLAKE)
[05:55:48] [PASSED] 0xB0A0 (PANTHERLAKE)
[05:55:48] [PASSED] 0xB0B0 (PANTHERLAKE)
[05:55:48] [PASSED] 0xFD80 (PANTHERLAKE)
[05:55:48] [PASSED] 0xFD81 (PANTHERLAKE)
[05:55:48] [PASSED] 0xD740 (NOVALAKE_S)
[05:55:48] [PASSED] 0xD741 (NOVALAKE_S)
[05:55:48] [PASSED] 0xD742 (NOVALAKE_S)
[05:55:48] [PASSED] 0xD743 (NOVALAKE_S)
[05:55:48] [PASSED] 0xD744 (NOVALAKE_S)
[05:55:48] [PASSED] 0xD745 (NOVALAKE_S)
[05:55:48] [PASSED] 0x674C (CRESCENTISLAND)
[05:55:48] [PASSED] 0xD750 (NOVALAKE_P)
[05:55:48] [PASSED] 0xD751 (NOVALAKE_P)
[05:55:48] [PASSED] 0xD752 (NOVALAKE_P)
[05:55:48] [PASSED] 0xD753 (NOVALAKE_P)
[05:55:48] [PASSED] 0xD754 (NOVALAKE_P)
[05:55:48] [PASSED] 0xD755 (NOVALAKE_P)
[05:55:48] [PASSED] 0xD756 (NOVALAKE_P)
[05:55:48] [PASSED] 0xD757 (NOVALAKE_P)
[05:55:48] [PASSED] 0xD75F (NOVALAKE_P)
[05:55:48] =============== [PASSED] check_platform_desc ===============
[05:55:48] ===================== [PASSED] xe_pci ======================
[05:55:48] =================== xe_rtp (2 subtests) ====================
[05:55:48] =============== xe_rtp_process_to_sr_tests  ================
[05:55:48] [PASSED] coalesce-same-reg
[05:55:48] [PASSED] no-match-no-add
[05:55:48] [PASSED] match-or
[05:55:48] [PASSED] match-or-xfail
[05:55:48] [PASSED] no-match-no-add-multiple-rules
[05:55:48] [PASSED] two-regs-two-entries
[05:55:48] [PASSED] clr-one-set-other
[05:55:48] [PASSED] set-field
[05:55:48] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[05:55:48] [PASSED] conflict-not-disjoint
[05:55:48] [PASSED] conflict-reg-type
[05:55:48] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[05:55:48] ================== xe_rtp_process_tests  ===================
[05:55:48] [PASSED] active1
[05:55:48] [PASSED] active2
[05:55:48] [PASSED] active-inactive
[05:55:48] [PASSED] inactive-active
[05:55:48] [PASSED] inactive-1st_or_active-inactive
[05:55:48] [PASSED] inactive-2nd_or_active-inactive
[05:55:48] [PASSED] inactive-last_or_active-inactive
[05:55:48] [PASSED] inactive-no_or_active-inactive
[05:55:48] ============== [PASSED] xe_rtp_process_tests ===============
[05:55:48] ===================== [PASSED] xe_rtp ======================
[05:55:48] ==================== xe_wa (1 subtest) =====================
[05:55:48] ======================== xe_wa_gt  =========================
[05:55:48] [PASSED] TIGERLAKE B0
[05:55:48] [PASSED] DG1 A0
[05:55:48] [PASSED] DG1 B0
[05:55:48] [PASSED] ALDERLAKE_S A0
[05:55:48] [PASSED] ALDERLAKE_S B0
[05:55:48] [PASSED] ALDERLAKE_S C0
[05:55:48] [PASSED] ALDERLAKE_S D0
[05:55:48] [PASSED] ALDERLAKE_P A0
[05:55:48] [PASSED] ALDERLAKE_P B0
[05:55:48] [PASSED] ALDERLAKE_P C0
[05:55:48] [PASSED] ALDERLAKE_S RPLS D0
[05:55:48] [PASSED] ALDERLAKE_P RPLU E0
[05:55:48] [PASSED] DG2 G10 C0
[05:55:48] [PASSED] DG2 G11 B1
[05:55:48] [PASSED] DG2 G12 A1
[05:55:48] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:55:48] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:55:48] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[05:55:48] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[05:55:48] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[05:55:48] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[05:55:48] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[05:55:48] ==================== [PASSED] xe_wa_gt =====================
[05:55:48] ====================== [PASSED] xe_wa ======================
[05:55:48] ============================================================
[05:55:48] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[05:55:48] Elapsed time: 39.144s total, 4.785s configuring, 33.643s building, 0.694s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[05:55:48] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:55:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:56:14] Starting KUnit Kernel (1/1)...
[05:56:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:56:14] ============ drm_test_pick_cmdline (2 subtests) ============
[05:56:14] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[05:56:14] =============== drm_test_pick_cmdline_named  ===============
[05:56:14] [PASSED] NTSC
[05:56:14] [PASSED] NTSC-J
[05:56:14] [PASSED] PAL
[05:56:14] [PASSED] PAL-M
[05:56:14] =========== [PASSED] drm_test_pick_cmdline_named ===========
[05:56:14] ============== [PASSED] drm_test_pick_cmdline ==============
[05:56:14] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[05:56:14] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[05:56:14] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[05:56:14] =========== drm_validate_clone_mode (2 subtests) ===========
[05:56:14] ============== drm_test_check_in_clone_mode  ===============
[05:56:14] [PASSED] in_clone_mode
[05:56:14] [PASSED] not_in_clone_mode
[05:56:14] ========== [PASSED] drm_test_check_in_clone_mode ===========
[05:56:14] =============== drm_test_check_valid_clones  ===============
[05:56:14] [PASSED] not_in_clone_mode
[05:56:14] [PASSED] valid_clone
[05:56:14] [PASSED] invalid_clone
[05:56:14] =========== [PASSED] drm_test_check_valid_clones ===========
[05:56:14] ============= [PASSED] drm_validate_clone_mode =============
[05:56:14] ============= drm_validate_modeset (1 subtest) =============
[05:56:14] [PASSED] drm_test_check_connector_changed_modeset
[05:56:14] ============== [PASSED] drm_validate_modeset ===============
[05:56:14] ====== drm_test_bridge_get_current_state (2 subtests) ======
[05:56:14] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[05:56:14] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[05:56:14] ======== [PASSED] drm_test_bridge_get_current_state ========
[05:56:14] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[05:56:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[05:56:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[05:56:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[05:56:14] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[05:56:14] ============== drm_bridge_alloc (2 subtests) ===============
[05:56:14] [PASSED] drm_test_drm_bridge_alloc_basic
[05:56:14] [PASSED] drm_test_drm_bridge_alloc_get_put
[05:56:14] ================ [PASSED] drm_bridge_alloc =================
[05:56:14] ============= drm_cmdline_parser (40 subtests) =============
[05:56:14] [PASSED] drm_test_cmdline_force_d_only
[05:56:14] [PASSED] drm_test_cmdline_force_D_only_dvi
[05:56:14] [PASSED] drm_test_cmdline_force_D_only_hdmi
[05:56:14] [PASSED] drm_test_cmdline_force_D_only_not_digital
[05:56:14] [PASSED] drm_test_cmdline_force_e_only
[05:56:14] [PASSED] drm_test_cmdline_res
[05:56:14] [PASSED] drm_test_cmdline_res_vesa
[05:56:14] [PASSED] drm_test_cmdline_res_vesa_rblank
[05:56:14] [PASSED] drm_test_cmdline_res_rblank
[05:56:14] [PASSED] drm_test_cmdline_res_bpp
[05:56:14] [PASSED] drm_test_cmdline_res_refresh
[05:56:14] [PASSED] drm_test_cmdline_res_bpp_refresh
[05:56:14] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[05:56:14] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[05:56:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[05:56:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[05:56:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[05:56:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[05:56:14] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[05:56:14] [PASSED] drm_test_cmdline_res_margins_force_on
[05:56:14] [PASSED] drm_test_cmdline_res_vesa_margins
[05:56:14] [PASSED] drm_test_cmdline_name
[05:56:14] [PASSED] drm_test_cmdline_name_bpp
[05:56:14] [PASSED] drm_test_cmdline_name_option
[05:56:14] [PASSED] drm_test_cmdline_name_bpp_option
[05:56:14] [PASSED] drm_test_cmdline_rotate_0
[05:56:14] [PASSED] drm_test_cmdline_rotate_90
[05:56:14] [PASSED] drm_test_cmdline_rotate_180
[05:56:14] [PASSED] drm_test_cmdline_rotate_270
[05:56:14] [PASSED] drm_test_cmdline_hmirror
[05:56:14] [PASSED] drm_test_cmdline_vmirror
[05:56:14] [PASSED] drm_test_cmdline_margin_options
[05:56:14] [PASSED] drm_test_cmdline_multiple_options
[05:56:14] [PASSED] drm_test_cmdline_bpp_extra_and_option
[05:56:14] [PASSED] drm_test_cmdline_extra_and_option
[05:56:14] [PASSED] drm_test_cmdline_freestanding_options
[05:56:14] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[05:56:14] [PASSED] drm_test_cmdline_panel_orientation
[05:56:14] ================ drm_test_cmdline_invalid  =================
[05:56:14] [PASSED] margin_only
[05:56:14] [PASSED] interlace_only
[05:56:14] [PASSED] res_missing_x
[05:56:14] [PASSED] res_missing_y
[05:56:14] [PASSED] res_bad_y
[05:56:14] [PASSED] res_missing_y_bpp
[05:56:14] [PASSED] res_bad_bpp
[05:56:14] [PASSED] res_bad_refresh
[05:56:14] [PASSED] res_bpp_refresh_force_on_off
[05:56:14] [PASSED] res_invalid_mode
[05:56:14] [PASSED] res_bpp_wrong_place_mode
[05:56:14] [PASSED] name_bpp_refresh
[05:56:14] [PASSED] name_refresh
[05:56:14] [PASSED] name_refresh_wrong_mode
[05:56:14] [PASSED] name_refresh_invalid_mode
[05:56:14] [PASSED] rotate_multiple
[05:56:14] [PASSED] rotate_invalid_val
[05:56:14] [PASSED] rotate_truncated
[05:56:14] [PASSED] invalid_option
[05:56:14] [PASSED] invalid_tv_option
[05:56:14] [PASSED] truncated_tv_option
[05:56:14] ============ [PASSED] drm_test_cmdline_invalid =============
[05:56:14] =============== drm_test_cmdline_tv_options  ===============
[05:56:14] [PASSED] NTSC
[05:56:14] [PASSED] NTSC_443
[05:56:14] [PASSED] NTSC_J
[05:56:14] [PASSED] PAL
[05:56:14] [PASSED] PAL_M
[05:56:14] [PASSED] PAL_N
[05:56:14] [PASSED] SECAM
[05:56:14] [PASSED] MONO_525
[05:56:14] [PASSED] MONO_625
[05:56:14] =========== [PASSED] drm_test_cmdline_tv_options ===========
[05:56:14] =============== [PASSED] drm_cmdline_parser ================
[05:56:14] ========== drmm_connector_hdmi_init (20 subtests) ==========
[05:56:14] [PASSED] drm_test_connector_hdmi_init_valid
[05:56:14] [PASSED] drm_test_connector_hdmi_init_bpc_8
[05:56:14] [PASSED] drm_test_connector_hdmi_init_bpc_10
[05:56:14] [PASSED] drm_test_connector_hdmi_init_bpc_12
[05:56:14] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[05:56:14] [PASSED] drm_test_connector_hdmi_init_bpc_null
[05:56:14] [PASSED] drm_test_connector_hdmi_init_formats_empty
[05:56:14] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[05:56:14] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[05:56:14] [PASSED] supported_formats=0x9 yuv420_allowed=1
[05:56:14] [PASSED] supported_formats=0x9 yuv420_allowed=0
[05:56:14] [PASSED] supported_formats=0x5 yuv420_allowed=1
[05:56:14] [PASSED] supported_formats=0x5 yuv420_allowed=0
[05:56:14] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[05:56:14] [PASSED] drm_test_connector_hdmi_init_null_ddc
[05:56:14] [PASSED] drm_test_connector_hdmi_init_null_product
[05:56:14] [PASSED] drm_test_connector_hdmi_init_null_vendor
[05:56:14] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[05:56:14] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[05:56:14] [PASSED] drm_test_connector_hdmi_init_product_valid
[05:56:14] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[05:56:14] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[05:56:14] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[05:56:14] ========= drm_test_connector_hdmi_init_type_valid  =========
[05:56:14] [PASSED] HDMI-A
[05:56:14] [PASSED] HDMI-B
[05:56:14] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[05:56:14] ======== drm_test_connector_hdmi_init_type_invalid  ========
[05:56:14] [PASSED] Unknown
[05:56:14] [PASSED] VGA
[05:56:14] [PASSED] DVI-I
[05:56:14] [PASSED] DVI-D
[05:56:14] [PASSED] DVI-A
[05:56:14] [PASSED] Composite
[05:56:14] [PASSED] SVIDEO
[05:56:14] [PASSED] LVDS
[05:56:14] [PASSED] Component
[05:56:14] [PASSED] DIN
[05:56:14] [PASSED] DP
[05:56:14] [PASSED] TV
[05:56:14] [PASSED] eDP
[05:56:14] [PASSED] Virtual
[05:56:14] [PASSED] DSI
[05:56:14] [PASSED] DPI
[05:56:14] [PASSED] Writeback
[05:56:14] [PASSED] SPI
[05:56:14] [PASSED] USB
[05:56:14] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[05:56:14] ============ [PASSED] drmm_connector_hdmi_init =============
[05:56:14] ============= drmm_connector_init (3 subtests) =============
[05:56:14] [PASSED] drm_test_drmm_connector_init
[05:56:14] [PASSED] drm_test_drmm_connector_init_null_ddc
[05:56:14] ========= drm_test_drmm_connector_init_type_valid  =========
[05:56:14] [PASSED] Unknown
[05:56:14] [PASSED] VGA
[05:56:14] [PASSED] DVI-I
[05:56:14] [PASSED] DVI-D
[05:56:14] [PASSED] DVI-A
[05:56:14] [PASSED] Composite
[05:56:14] [PASSED] SVIDEO
[05:56:14] [PASSED] LVDS
[05:56:14] [PASSED] Component
[05:56:14] [PASSED] DIN
[05:56:14] [PASSED] DP
[05:56:14] [PASSED] HDMI-A
[05:56:14] [PASSED] HDMI-B
[05:56:14] [PASSED] TV
[05:56:14] [PASSED] eDP
[05:56:14] [PASSED] Virtual
[05:56:14] [PASSED] DSI
[05:56:14] [PASSED] DPI
[05:56:14] [PASSED] Writeback
[05:56:14] [PASSED] SPI
[05:56:14] [PASSED] USB
[05:56:14] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[05:56:14] =============== [PASSED] drmm_connector_init ===============
[05:56:14] ========= drm_connector_dynamic_init (6 subtests) ==========
[05:56:14] [PASSED] drm_test_drm_connector_dynamic_init
[05:56:14] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[05:56:14] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[05:56:14] [PASSED] drm_test_drm_connector_dynamic_init_properties
[05:56:14] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[05:56:14] [PASSED] Unknown
[05:56:14] [PASSED] VGA
[05:56:14] [PASSED] DVI-I
[05:56:14] [PASSED] DVI-D
[05:56:14] [PASSED] DVI-A
[05:56:14] [PASSED] Composite
[05:56:14] [PASSED] SVIDEO
[05:56:14] [PASSED] LVDS
[05:56:14] [PASSED] Component
[05:56:14] [PASSED] DIN
[05:56:14] [PASSED] DP
[05:56:14] [PASSED] HDMI-A
[05:56:14] [PASSED] HDMI-B
[05:56:14] [PASSED] TV
[05:56:14] [PASSED] eDP
[05:56:14] [PASSED] Virtual
[05:56:14] [PASSED] DSI
[05:56:14] [PASSED] DPI
[05:56:14] [PASSED] Writeback
[05:56:14] [PASSED] SPI
[05:56:14] [PASSED] USB
[05:56:14] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[05:56:14] ======== drm_test_drm_connector_dynamic_init_name  =========
[05:56:14] [PASSED] Unknown
[05:56:14] [PASSED] VGA
[05:56:14] [PASSED] DVI-I
[05:56:14] [PASSED] DVI-D
[05:56:14] [PASSED] DVI-A
[05:56:14] [PASSED] Composite
[05:56:14] [PASSED] SVIDEO
[05:56:14] [PASSED] LVDS
[05:56:14] [PASSED] Component
[05:56:14] [PASSED] DIN
[05:56:14] [PASSED] DP
[05:56:14] [PASSED] HDMI-A
[05:56:14] [PASSED] HDMI-B
[05:56:14] [PASSED] TV
[05:56:14] [PASSED] eDP
[05:56:14] [PASSED] Virtual
[05:56:14] [PASSED] DSI
[05:56:14] [PASSED] DPI
[05:56:14] [PASSED] Writeback
[05:56:14] [PASSED] SPI
[05:56:14] [PASSED] USB
[05:56:14] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[05:56:14] =========== [PASSED] drm_connector_dynamic_init ============
[05:56:14] ==== drm_connector_dynamic_register_early (4 subtests) =====
[05:56:14] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[05:56:14] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[05:56:14] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[05:56:14] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[05:56:14] ====== [PASSED] drm_connector_dynamic_register_early =======
[05:56:14] ======= drm_connector_dynamic_register (7 subtests) ========
[05:56:14] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[05:56:14] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[05:56:14] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[05:56:14] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[05:56:14] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[05:56:14] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[05:56:14] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[05:56:14] ========= [PASSED] drm_connector_dynamic_register ==========
[05:56:14] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[05:56:14] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[05:56:14] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[05:56:14] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[05:56:14] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[05:56:14] ========== drm_test_get_tv_mode_from_name_valid  ===========
[05:56:14] [PASSED] NTSC
[05:56:14] [PASSED] NTSC-443
[05:56:14] [PASSED] NTSC-J
[05:56:14] [PASSED] PAL
[05:56:14] [PASSED] PAL-M
[05:56:14] [PASSED] PAL-N
[05:56:14] [PASSED] SECAM
[05:56:14] [PASSED] Mono
[05:56:14] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[05:56:14] [PASSED] drm_test_get_tv_mode_from_name_truncated
[05:56:14] ============ [PASSED] drm_get_tv_mode_from_name ============
[05:56:14] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[05:56:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[05:56:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[05:56:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[05:56:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[05:56:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[05:56:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[05:56:14] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[05:56:14] [PASSED] VIC 96
[05:56:14] [PASSED] VIC 97
[05:56:14] [PASSED] VIC 101
[05:56:14] [PASSED] VIC 102
[05:56:14] [PASSED] VIC 106
[05:56:14] [PASSED] VIC 107
[05:56:14] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[05:56:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[05:56:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[05:56:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[05:56:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[05:56:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[05:56:14] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[05:56:14] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[05:56:14] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[05:56:14] [PASSED] Automatic
[05:56:14] [PASSED] Full
[05:56:14] [PASSED] Limited 16:235
[05:56:14] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[05:56:14] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[05:56:14] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[05:56:14] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[05:56:14] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[05:56:14] [PASSED] RGB
[05:56:14] [PASSED] YUV 4:2:0
[05:56:14] [PASSED] YUV 4:2:2
[05:56:14] [PASSED] YUV 4:4:4
[05:56:14] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[05:56:14] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[05:56:14] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[05:56:14] ============= drm_damage_helper (21 subtests) ==============
[05:56:14] [PASSED] drm_test_damage_iter_no_damage
[05:56:14] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[05:56:14] [PASSED] drm_test_damage_iter_no_damage_src_moved
[05:56:14] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[05:56:14] [PASSED] drm_test_damage_iter_no_damage_not_visible
[05:56:14] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[05:56:14] [PASSED] drm_test_damage_iter_no_damage_no_fb
[05:56:14] [PASSED] drm_test_damage_iter_simple_damage
[05:56:14] [PASSED] drm_test_damage_iter_single_damage
[05:56:14] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[05:56:14] [PASSED] drm_test_damage_iter_single_damage_outside_src
[05:56:14] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[05:56:14] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[05:56:14] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[05:56:14] [PASSED] drm_test_damage_iter_single_damage_src_moved
[05:56:14] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[05:56:14] [PASSED] drm_test_damage_iter_damage
[05:56:14] [PASSED] drm_test_damage_iter_damage_one_intersect
[05:56:14] [PASSED] drm_test_damage_iter_damage_one_outside
[05:56:14] [PASSED] drm_test_damage_iter_damage_src_moved
[05:56:14] [PASSED] drm_test_damage_iter_damage_not_visible
[05:56:14] ================ [PASSED] drm_damage_helper ================
[05:56:14] ============== drm_dp_mst_helper (3 subtests) ==============
[05:56:14] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[05:56:14] [PASSED] Clock 154000 BPP 30 DSC disabled
[05:56:14] [PASSED] Clock 234000 BPP 30 DSC disabled
[05:56:14] [PASSED] Clock 297000 BPP 24 DSC disabled
[05:56:14] [PASSED] Clock 332880 BPP 24 DSC enabled
[05:56:14] [PASSED] Clock 324540 BPP 24 DSC enabled
[05:56:14] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[05:56:14] ============== drm_test_dp_mst_calc_pbn_div  ===============
[05:56:14] [PASSED] Link rate 2000000 lane count 4
[05:56:14] [PASSED] Link rate 2000000 lane count 2
[05:56:14] [PASSED] Link rate 2000000 lane count 1
[05:56:14] [PASSED] Link rate 1350000 lane count 4
[05:56:14] [PASSED] Link rate 1350000 lane count 2
[05:56:14] [PASSED] Link rate 1350000 lane count 1
[05:56:14] [PASSED] Link rate 1000000 lane count 4
[05:56:14] [PASSED] Link rate 1000000 lane count 2
[05:56:14] [PASSED] Link rate 1000000 lane count 1
[05:56:14] [PASSED] Link rate 810000 lane count 4
[05:56:14] [PASSED] Link rate 810000 lane count 2
[05:56:14] [PASSED] Link rate 810000 lane count 1
[05:56:14] [PASSED] Link rate 540000 lane count 4
[05:56:14] [PASSED] Link rate 540000 lane count 2
[05:56:14] [PASSED] Link rate 540000 lane count 1
[05:56:14] [PASSED] Link rate 270000 lane count 4
[05:56:14] [PASSED] Link rate 270000 lane count 2
[05:56:14] [PASSED] Link rate 270000 lane count 1
[05:56:14] [PASSED] Link rate 162000 lane count 4
[05:56:14] [PASSED] Link rate 162000 lane count 2
[05:56:14] [PASSED] Link rate 162000 lane count 1
[05:56:14] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[05:56:14] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[05:56:14] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[05:56:14] [PASSED] DP_POWER_UP_PHY with port number
[05:56:14] [PASSED] DP_POWER_DOWN_PHY with port number
[05:56:14] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[05:56:14] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[05:56:14] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[05:56:14] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[05:56:14] [PASSED] DP_QUERY_PAYLOAD with port number
[05:56:14] [PASSED] DP_QUERY_PAYLOAD with VCPI
[05:56:14] [PASSED] DP_REMOTE_DPCD_READ with port number
[05:56:14] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[05:56:14] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[05:56:14] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[05:56:14] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[05:56:14] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[05:56:14] [PASSED] DP_REMOTE_I2C_READ with port number
[05:56:14] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[05:56:14] [PASSED] DP_REMOTE_I2C_READ with transactions array
[05:56:14] [PASSED] DP_REMOTE_I2C_WRITE with port number
[05:56:14] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[05:56:14] [PASSED] DP_REMOTE_I2C_WRITE with data array
[05:56:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[05:56:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[05:56:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[05:56:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[05:56:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[05:56:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[05:56:14] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[05:56:14] ================ [PASSED] drm_dp_mst_helper ================
[05:56:14] ================== drm_exec (7 subtests) ===================
[05:56:14] [PASSED] sanitycheck
[05:56:14] [PASSED] test_lock
[05:56:14] [PASSED] test_lock_unlock
[05:56:14] [PASSED] test_duplicates
[05:56:14] [PASSED] test_prepare
[05:56:14] [PASSED] test_prepare_array
[05:56:14] [PASSED] test_multiple_loops
[05:56:14] ==================== [PASSED] drm_exec =====================
[05:56:14] =========== drm_format_helper_test (17 subtests) ===========
[05:56:14] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[05:56:14] [PASSED] single_pixel_source_buffer
[05:56:14] [PASSED] single_pixel_clip_rectangle
[05:56:14] [PASSED] well_known_colors
[05:56:14] [PASSED] destination_pitch
[05:56:14] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[05:56:14] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[05:56:14] [PASSED] single_pixel_source_buffer
[05:56:14] [PASSED] single_pixel_clip_rectangle
[05:56:14] [PASSED] well_known_colors
[05:56:14] [PASSED] destination_pitch
[05:56:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[05:56:14] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[05:56:14] [PASSED] single_pixel_source_buffer
[05:56:14] [PASSED] single_pixel_clip_rectangle
[05:56:14] [PASSED] well_known_colors
[05:56:14] [PASSED] destination_pitch
[05:56:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[05:56:14] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[05:56:14] [PASSED] single_pixel_source_buffer
[05:56:14] [PASSED] single_pixel_clip_rectangle
[05:56:14] [PASSED] well_known_colors
[05:56:14] [PASSED] destination_pitch
[05:56:14] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[05:56:14] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[05:56:14] [PASSED] single_pixel_source_buffer
[05:56:14] [PASSED] single_pixel_clip_rectangle
[05:56:14] [PASSED] well_known_colors
[05:56:14] [PASSED] destination_pitch
[05:56:14] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[05:56:14] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[05:56:14] [PASSED] single_pixel_source_buffer
[05:56:14] [PASSED] single_pixel_clip_rectangle
[05:56:14] [PASSED] well_known_colors
[05:56:14] [PASSED] destination_pitch
[05:56:14] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[05:56:14] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[05:56:14] [PASSED] single_pixel_source_buffer
[05:56:14] [PASSED] single_pixel_clip_rectangle
[05:56:14] [PASSED] well_known_colors
[05:56:14] [PASSED] destination_pitch
[05:56:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[05:56:14] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[05:56:14] [PASSED] single_pixel_source_buffer
[05:56:14] [PASSED] single_pixel_clip_rectangle
[05:56:14] [PASSED] well_known_colors
[05:56:14] [PASSED] destination_pitch
[05:56:14] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[05:56:14] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[05:56:14] [PASSED] single_pixel_source_buffer
[05:56:14] [PASSED] single_pixel_clip_rectangle
[05:56:14] [PASSED] well_known_colors
[05:56:14] [PASSED] destination_pitch
[05:56:14] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[05:56:14] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[05:56:14] [PASSED] single_pixel_source_buffer
[05:56:14] [PASSED] single_pixel_clip_rectangle
[05:56:14] [PASSED] well_known_colors
[05:56:14] [PASSED] destination_pitch
[05:56:14] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[05:56:14] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[05:56:14] [PASSED] single_pixel_source_buffer
[05:56:14] [PASSED] single_pixel_clip_rectangle
[05:56:14] [PASSED] well_known_colors
[05:56:14] [PASSED] destination_pitch
[05:56:14] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[05:56:14] ============== drm_test_fb_xrgb8888_to_mono  ===============
[05:56:14] [PASSED] single_pixel_source_buffer
[05:56:14] [PASSED] single_pixel_clip_rectangle
[05:56:14] [PASSED] well_known_colors
[05:56:14] [PASSED] destination_pitch
[05:56:14] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[05:56:14] ==================== drm_test_fb_swab  =====================
[05:56:14] [PASSED] single_pixel_source_buffer
[05:56:14] [PASSED] single_pixel_clip_rectangle
[05:56:14] [PASSED] well_known_colors
[05:56:14] [PASSED] destination_pitch
[05:56:14] ================ [PASSED] drm_test_fb_swab =================
[05:56:14] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[05:56:14] [PASSED] single_pixel_source_buffer
[05:56:14] [PASSED] single_pixel_clip_rectangle
[05:56:14] [PASSED] well_known_colors
[05:56:14] [PASSED] destination_pitch
[05:56:14] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[05:56:14] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[05:56:14] [PASSED] single_pixel_source_buffer
[05:56:14] [PASSED] single_pixel_clip_rectangle
[05:56:14] [PASSED] well_known_colors
[05:56:14] [PASSED] destination_pitch
[05:56:14] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[05:56:14] ================= drm_test_fb_clip_offset  =================
[05:56:14] [PASSED] pass through
[05:56:14] [PASSED] horizontal offset
[05:56:14] [PASSED] vertical offset
[05:56:14] [PASSED] horizontal and vertical offset
[05:56:14] [PASSED] horizontal offset (custom pitch)
[05:56:14] [PASSED] vertical offset (custom pitch)
[05:56:14] [PASSED] horizontal and vertical offset (custom pitch)
[05:56:14] ============= [PASSED] drm_test_fb_clip_offset =============
[05:56:14] =================== drm_test_fb_memcpy  ====================
[05:56:14] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[05:56:14] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[05:56:14] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[05:56:14] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[05:56:14] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[05:56:14] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[05:56:14] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[05:56:14] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[05:56:14] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[05:56:14] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[05:56:14] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[05:56:14] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[05:56:14] =============== [PASSED] drm_test_fb_memcpy ================
[05:56:14] ============= [PASSED] drm_format_helper_test ==============
[05:56:14] ================= drm_format (18 subtests) =================
[05:56:14] [PASSED] drm_test_format_block_width_invalid
[05:56:14] [PASSED] drm_test_format_block_width_one_plane
[05:56:14] [PASSED] drm_test_format_block_width_two_plane
[05:56:14] [PASSED] drm_test_format_block_width_three_plane
[05:56:14] [PASSED] drm_test_format_block_width_tiled
[05:56:14] [PASSED] drm_test_format_block_height_invalid
[05:56:14] [PASSED] drm_test_format_block_height_one_plane
[05:56:14] [PASSED] drm_test_format_block_height_two_plane
[05:56:14] [PASSED] drm_test_format_block_height_three_plane
[05:56:14] [PASSED] drm_test_format_block_height_tiled
[05:56:14] [PASSED] drm_test_format_min_pitch_invalid
[05:56:14] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[05:56:14] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[05:56:14] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[05:56:14] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[05:56:14] [PASSED] drm_test_format_min_pitch_two_plane
[05:56:14] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[05:56:14] [PASSED] drm_test_format_min_pitch_tiled
[05:56:14] =================== [PASSED] drm_format ====================
[05:56:14] ============== drm_framebuffer (10 subtests) ===============
[05:56:14] ========== drm_test_framebuffer_check_src_coords  ==========
[05:56:14] [PASSED] Success: source fits into fb
[05:56:14] [PASSED] Fail: overflowing fb with x-axis coordinate
[05:56:14] [PASSED] Fail: overflowing fb with y-axis coordinate
[05:56:14] [PASSED] Fail: overflowing fb with source width
[05:56:14] [PASSED] Fail: overflowing fb with source height
[05:56:14] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[05:56:14] [PASSED] drm_test_framebuffer_cleanup
[05:56:14] =============== drm_test_framebuffer_create  ===============
[05:56:14] [PASSED] ABGR8888 normal sizes
[05:56:14] [PASSED] ABGR8888 max sizes
[05:56:14] [PASSED] ABGR8888 pitch greater than min required
[05:56:14] [PASSED] ABGR8888 pitch less than min required
[05:56:14] [PASSED] ABGR8888 Invalid width
[05:56:14] [PASSED] ABGR8888 Invalid buffer handle
[05:56:14] [PASSED] No pixel format
[05:56:14] [PASSED] ABGR8888 Width 0
[05:56:14] [PASSED] ABGR8888 Height 0
[05:56:14] [PASSED] ABGR8888 Out of bound height * pitch combination
[05:56:14] [PASSED] ABGR8888 Large buffer offset
[05:56:14] [PASSED] ABGR8888 Buffer offset for inexistent plane
[05:56:14] [PASSED] ABGR8888 Invalid flag
[05:56:14] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[05:56:14] [PASSED] ABGR8888 Valid buffer modifier
[05:56:14] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[05:56:14] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[05:56:14] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[05:56:14] [PASSED] NV12 Normal sizes
[05:56:14] [PASSED] NV12 Max sizes
[05:56:14] [PASSED] NV12 Invalid pitch
[05:56:14] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[05:56:14] [PASSED] NV12 different  modifier per-plane
[05:56:14] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[05:56:14] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[05:56:14] [PASSED] NV12 Modifier for inexistent plane
[05:56:14] [PASSED] NV12 Handle for inexistent plane
[05:56:14] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[05:56:14] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[05:56:14] [PASSED] YVU420 Normal sizes
[05:56:14] [PASSED] YVU420 Max sizes
[05:56:14] [PASSED] YVU420 Invalid pitch
[05:56:14] [PASSED] YVU420 Different pitches
[05:56:14] [PASSED] YVU420 Different buffer offsets/pitches
[05:56:14] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[05:56:14] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[05:56:14] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[05:56:14] [PASSED] YVU420 Valid modifier
[05:56:14] [PASSED] YVU420 Different modifiers per plane
[05:56:14] [PASSED] YVU420 Modifier for inexistent plane
[05:56:14] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[05:56:14] [PASSED] X0L2 Normal sizes
[05:56:14] [PASSED] X0L2 Max sizes
[05:56:14] [PASSED] X0L2 Invalid pitch
[05:56:14] [PASSED] X0L2 Pitch greater than minimum required
[05:56:14] [PASSED] X0L2 Handle for inexistent plane
[05:56:14] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[05:56:14] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[05:56:14] [PASSED] X0L2 Valid modifier
[05:56:14] [PASSED] X0L2 Modifier for inexistent plane
[05:56:14] =========== [PASSED] drm_test_framebuffer_create ===========
[05:56:14] [PASSED] drm_test_framebuffer_free
[05:56:14] [PASSED] drm_test_framebuffer_init
[05:56:14] [PASSED] drm_test_framebuffer_init_bad_format
[05:56:14] [PASSED] drm_test_framebuffer_init_dev_mismatch
[05:56:14] [PASSED] drm_test_framebuffer_lookup
[05:56:14] [PASSED] drm_test_framebuffer_lookup_inexistent
[05:56:14] [PASSED] drm_test_framebuffer_modifiers_not_supported
[05:56:14] ================= [PASSED] drm_framebuffer =================
[05:56:14] ================ drm_gem_shmem (8 subtests) ================
[05:56:14] [PASSED] drm_gem_shmem_test_obj_create
[05:56:14] [PASSED] drm_gem_shmem_test_obj_create_private
[05:56:14] [PASSED] drm_gem_shmem_test_pin_pages
[05:56:14] [PASSED] drm_gem_shmem_test_vmap
[05:56:14] [PASSED] drm_gem_shmem_test_get_sg_table
[05:56:14] [PASSED] drm_gem_shmem_test_get_pages_sgt
[05:56:14] [PASSED] drm_gem_shmem_test_madvise
[05:56:14] [PASSED] drm_gem_shmem_test_purge
[05:56:14] ================== [PASSED] drm_gem_shmem ==================
[05:56:14] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[05:56:14] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[05:56:14] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[05:56:14] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[05:56:14] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[05:56:14] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[05:56:14] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[05:56:14] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[05:56:14] [PASSED] Automatic
[05:56:14] [PASSED] Full
[05:56:14] [PASSED] Limited 16:235
[05:56:14] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[05:56:14] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[05:56:14] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[05:56:14] [PASSED] drm_test_check_disable_connector
[05:56:14] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[05:56:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[05:56:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[05:56:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[05:56:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[05:56:14] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[05:56:14] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[05:56:14] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[05:56:14] [PASSED] drm_test_check_output_bpc_dvi
[05:56:14] [PASSED] drm_test_check_output_bpc_format_vic_1
[05:56:14] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[05:56:14] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[05:56:14] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[05:56:14] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[05:56:14] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[05:56:14] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[05:56:14] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[05:56:14] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[05:56:14] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[05:56:14] [PASSED] drm_test_check_broadcast_rgb_value
[05:56:14] [PASSED] drm_test_check_bpc_8_value
[05:56:14] [PASSED] drm_test_check_bpc_10_value
[05:56:14] [PASSED] drm_test_check_bpc_12_value
[05:56:14] [PASSED] drm_test_check_format_value
[05:56:14] [PASSED] drm_test_check_tmds_char_value
[05:56:14] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[05:56:14] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[05:56:14] [PASSED] drm_test_check_mode_valid
[05:56:14] [PASSED] drm_test_check_mode_valid_reject
[05:56:14] [PASSED] drm_test_check_mode_valid_reject_rate
[05:56:14] [PASSED] drm_test_check_mode_valid_reject_max_clock
[05:56:14] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[05:56:14] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[05:56:14] [PASSED] drm_test_check_infoframes
[05:56:14] [PASSED] drm_test_check_reject_avi_infoframe
[05:56:14] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[05:56:14] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[05:56:14] [PASSED] drm_test_check_reject_audio_infoframe
[05:56:14] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[05:56:14] ================= drm_managed (2 subtests) =================
[05:56:14] [PASSED] drm_test_managed_release_action
[05:56:14] [PASSED] drm_test_managed_run_action
[05:56:14] =================== [PASSED] drm_managed ===================
[05:56:14] =================== drm_mm (6 subtests) ====================
[05:56:14] [PASSED] drm_test_mm_init
[05:56:14] [PASSED] drm_test_mm_debug
[05:56:14] [PASSED] drm_test_mm_align32
[05:56:14] [PASSED] drm_test_mm_align64
[05:56:14] [PASSED] drm_test_mm_lowest
[05:56:14] [PASSED] drm_test_mm_highest
[05:56:14] ===================== [PASSED] drm_mm ======================
[05:56:14] ============= drm_modes_analog_tv (5 subtests) =============
[05:56:14] [PASSED] drm_test_modes_analog_tv_mono_576i
[05:56:14] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[05:56:14] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[05:56:14] [PASSED] drm_test_modes_analog_tv_pal_576i
[05:56:14] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[05:56:14] =============== [PASSED] drm_modes_analog_tv ===============
[05:56:14] ============== drm_plane_helper (2 subtests) ===============
[05:56:14] =============== drm_test_check_plane_state  ================
[05:56:14] [PASSED] clipping_simple
[05:56:14] [PASSED] clipping_rotate_reflect
[05:56:14] [PASSED] positioning_simple
[05:56:14] [PASSED] upscaling
[05:56:14] [PASSED] downscaling
[05:56:14] [PASSED] rounding1
[05:56:14] [PASSED] rounding2
[05:56:14] [PASSED] rounding3
[05:56:14] [PASSED] rounding4
[05:56:14] =========== [PASSED] drm_test_check_plane_state ============
[05:56:14] =========== drm_test_check_invalid_plane_state  ============
[05:56:14] [PASSED] positioning_invalid
[05:56:14] [PASSED] upscaling_invalid
[05:56:14] [PASSED] downscaling_invalid
[05:56:14] ======= [PASSED] drm_test_check_invalid_plane_state ========
[05:56:14] ================ [PASSED] drm_plane_helper =================
[05:56:14] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[05:56:14] ====== drm_test_connector_helper_tv_get_modes_check  =======
[05:56:14] [PASSED] None
[05:56:14] [PASSED] PAL
[05:56:14] [PASSED] NTSC
[05:56:14] [PASSED] Both, NTSC Default
[05:56:14] [PASSED] Both, PAL Default
[05:56:14] [PASSED] Both, NTSC Default, with PAL on command-line
[05:56:14] [PASSED] Both, PAL Default, with NTSC on command-line
[05:56:14] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[05:56:14] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[05:56:14] ================== drm_rect (9 subtests) ===================
[05:56:14] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[05:56:14] [PASSED] drm_test_rect_clip_scaled_not_clipped
[05:56:14] [PASSED] drm_test_rect_clip_scaled_clipped
[05:56:14] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[05:56:14] ================= drm_test_rect_intersect  =================
[05:56:14] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[05:56:14] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[05:56:14] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[05:56:14] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[05:56:14] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[05:56:14] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[05:56:14] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[05:56:14] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[05:56:14] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[05:56:14] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[05:56:14] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[05:56:14] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[05:56:14] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[05:56:14] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[05:56:14] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[05:56:14] ============= [PASSED] drm_test_rect_intersect =============
[05:56:14] ================ drm_test_rect_calc_hscale  ================
[05:56:14] [PASSED] normal use
[05:56:14] [PASSED] out of max range
[05:56:14] [PASSED] out of min range
[05:56:14] [PASSED] zero dst
[05:56:14] [PASSED] negative src
[05:56:14] [PASSED] negative dst
[05:56:14] ============ [PASSED] drm_test_rect_calc_hscale ============
[05:56:14] ================ drm_test_rect_calc_vscale  ================
[05:56:14] [PASSED] normal use
[05:56:14] [PASSED] out of max range
[05:56:14] [PASSED] out of min range
[05:56:14] [PASSED] zero dst
[05:56:14] [PASSED] negative src
[05:56:14] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[05:56:14] ============ [PASSED] drm_test_rect_calc_vscale ============
[05:56:14] ================== drm_test_rect_rotate  ===================
[05:56:14] [PASSED] reflect-x
[05:56:14] [PASSED] reflect-y
[05:56:14] [PASSED] rotate-0
[05:56:14] [PASSED] rotate-90
[05:56:14] [PASSED] rotate-180
[05:56:14] [PASSED] rotate-270
[05:56:14] ============== [PASSED] drm_test_rect_rotate ===============
[05:56:14] ================ drm_test_rect_rotate_inv  =================
[05:56:14] [PASSED] reflect-x
[05:56:14] [PASSED] reflect-y
[05:56:14] [PASSED] rotate-0
[05:56:14] [PASSED] rotate-90
[05:56:14] [PASSED] rotate-180
[05:56:14] [PASSED] rotate-270
[05:56:14] ============ [PASSED] drm_test_rect_rotate_inv =============
[05:56:14] ==================== [PASSED] drm_rect =====================
[05:56:14] ============ drm_sysfb_modeset_test (1 subtest) ============
[05:56:14] ============ drm_test_sysfb_build_fourcc_list  =============
[05:56:14] [PASSED] no native formats
[05:56:14] [PASSED] XRGB8888 as native format
[05:56:14] [PASSED] remove duplicates
[05:56:14] [PASSED] convert alpha formats
[05:56:14] [PASSED] random formats
[05:56:14] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[05:56:14] ============= [PASSED] drm_sysfb_modeset_test ==============
[05:56:14] ================== drm_fixp (2 subtests) ===================
[05:56:14] [PASSED] drm_test_int2fixp
[05:56:14] [PASSED] drm_test_sm2fixp
[05:56:14] ==================== [PASSED] drm_fixp =====================
[05:56:14] ============================================================
[05:56:14] Testing complete. Ran 621 tests: passed: 621
[05:56:14] Elapsed time: 26.307s total, 1.748s configuring, 24.393s building, 0.125s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[05:56:14] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:56:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:56:25] Starting KUnit Kernel (1/1)...
[05:56:25] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:56:25] ================= ttm_device (5 subtests) ==================
[05:56:25] [PASSED] ttm_device_init_basic
[05:56:25] [PASSED] ttm_device_init_multiple
[05:56:25] [PASSED] ttm_device_fini_basic
[05:56:25] [PASSED] ttm_device_init_no_vma_man
[05:56:25] ================== ttm_device_init_pools  ==================
[05:56:25] [PASSED] No DMA allocations, no DMA32 required
[05:56:25] [PASSED] DMA allocations, DMA32 required
[05:56:25] [PASSED] No DMA allocations, DMA32 required
[05:56:25] [PASSED] DMA allocations, no DMA32 required
[05:56:25] ============== [PASSED] ttm_device_init_pools ==============
[05:56:25] =================== [PASSED] ttm_device ====================
[05:56:25] ================== ttm_pool (8 subtests) ===================
[05:56:25] ================== ttm_pool_alloc_basic  ===================
[05:56:25] [PASSED] One page
[05:56:25] [PASSED] More than one page
[05:56:25] [PASSED] Above the allocation limit
[05:56:25] [PASSED] One page, with coherent DMA mappings enabled
[05:56:25] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:56:25] ============== [PASSED] ttm_pool_alloc_basic ===============
[05:56:25] ============== ttm_pool_alloc_basic_dma_addr  ==============
[05:56:25] [PASSED] One page
[05:56:25] [PASSED] More than one page
[05:56:25] [PASSED] Above the allocation limit
[05:56:25] [PASSED] One page, with coherent DMA mappings enabled
[05:56:25] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:56:25] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[05:56:25] [PASSED] ttm_pool_alloc_order_caching_match
[05:56:25] [PASSED] ttm_pool_alloc_caching_mismatch
[05:56:25] [PASSED] ttm_pool_alloc_order_mismatch
[05:56:25] [PASSED] ttm_pool_free_dma_alloc
[05:56:25] [PASSED] ttm_pool_free_no_dma_alloc
[05:56:25] [PASSED] ttm_pool_fini_basic
[05:56:25] ==================== [PASSED] ttm_pool =====================
[05:56:25] ================ ttm_resource (8 subtests) =================
[05:56:25] ================= ttm_resource_init_basic  =================
[05:56:25] [PASSED] Init resource in TTM_PL_SYSTEM
[05:56:25] [PASSED] Init resource in TTM_PL_VRAM
[05:56:25] [PASSED] Init resource in a private placement
[05:56:25] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[05:56:25] ============= [PASSED] ttm_resource_init_basic =============
[05:56:25] [PASSED] ttm_resource_init_pinned
[05:56:25] [PASSED] ttm_resource_fini_basic
[05:56:25] [PASSED] ttm_resource_manager_init_basic
[05:56:25] [PASSED] ttm_resource_manager_usage_basic
[05:56:25] [PASSED] ttm_resource_manager_set_used_basic
[05:56:25] [PASSED] ttm_sys_man_alloc_basic
[05:56:25] [PASSED] ttm_sys_man_free_basic
[05:56:25] ================== [PASSED] ttm_resource ===================
[05:56:25] =================== ttm_tt (15 subtests) ===================
[05:56:25] ==================== ttm_tt_init_basic  ====================
[05:56:25] [PASSED] Page-aligned size
[05:56:25] [PASSED] Extra pages requested
[05:56:25] ================ [PASSED] ttm_tt_init_basic ================
[05:56:25] [PASSED] ttm_tt_init_misaligned
[05:56:25] [PASSED] ttm_tt_fini_basic
[05:56:25] [PASSED] ttm_tt_fini_sg
[05:56:25] [PASSED] ttm_tt_fini_shmem
[05:56:25] [PASSED] ttm_tt_create_basic
[05:56:25] [PASSED] ttm_tt_create_invalid_bo_type
[05:56:25] [PASSED] ttm_tt_create_ttm_exists
[05:56:25] [PASSED] ttm_tt_create_failed
[05:56:25] [PASSED] ttm_tt_destroy_basic
[05:56:25] [PASSED] ttm_tt_populate_null_ttm
[05:56:25] [PASSED] ttm_tt_populate_populated_ttm
[05:56:25] [PASSED] ttm_tt_unpopulate_basic
[05:56:25] [PASSED] ttm_tt_unpopulate_empty_ttm
[05:56:25] [PASSED] ttm_tt_swapin_basic
[05:56:25] ===================== [PASSED] ttm_tt ======================
[05:56:25] =================== ttm_bo (14 subtests) ===================
[05:56:25] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[05:56:25] [PASSED] Cannot be interrupted and sleeps
[05:56:25] [PASSED] Cannot be interrupted, locks straight away
[05:56:25] [PASSED] Can be interrupted, sleeps
[05:56:25] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[05:56:25] [PASSED] ttm_bo_reserve_locked_no_sleep
[05:56:25] [PASSED] ttm_bo_reserve_no_wait_ticket
[05:56:25] [PASSED] ttm_bo_reserve_double_resv
[05:56:25] [PASSED] ttm_bo_reserve_interrupted
[05:56:25] [PASSED] ttm_bo_reserve_deadlock
[05:56:25] [PASSED] ttm_bo_unreserve_basic
[05:56:25] [PASSED] ttm_bo_unreserve_pinned
[05:56:25] [PASSED] ttm_bo_unreserve_bulk
[05:56:25] [PASSED] ttm_bo_fini_basic
[05:56:25] [PASSED] ttm_bo_fini_shared_resv
[05:56:25] [PASSED] ttm_bo_pin_basic
[05:56:25] [PASSED] ttm_bo_pin_unpin_resource
[05:56:25] [PASSED] ttm_bo_multiple_pin_one_unpin
[05:56:25] ===================== [PASSED] ttm_bo ======================
[05:56:25] ============== ttm_bo_validate (22 subtests) ===============
[05:56:25] ============== ttm_bo_init_reserved_sys_man  ===============
[05:56:25] [PASSED] Buffer object for userspace
[05:56:25] [PASSED] Kernel buffer object
[05:56:25] [PASSED] Shared buffer object
[05:56:25] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[05:56:25] ============== ttm_bo_init_reserved_mock_man  ==============
[05:56:25] [PASSED] Buffer object for userspace
[05:56:25] [PASSED] Kernel buffer object
[05:56:25] [PASSED] Shared buffer object
[05:56:25] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[05:56:25] [PASSED] ttm_bo_init_reserved_resv
[05:56:25] ================== ttm_bo_validate_basic  ==================
[05:56:25] [PASSED] Buffer object for userspace
[05:56:25] [PASSED] Kernel buffer object
[05:56:25] [PASSED] Shared buffer object
[05:56:25] ============== [PASSED] ttm_bo_validate_basic ==============
[05:56:25] [PASSED] ttm_bo_validate_invalid_placement
[05:56:25] ============= ttm_bo_validate_same_placement  ==============
[05:56:25] [PASSED] System manager
[05:56:25] [PASSED] VRAM manager
[05:56:25] ========= [PASSED] ttm_bo_validate_same_placement ==========
[05:56:25] [PASSED] ttm_bo_validate_failed_alloc
[05:56:25] [PASSED] ttm_bo_validate_pinned
[05:56:25] [PASSED] ttm_bo_validate_busy_placement
[05:56:25] ================ ttm_bo_validate_multihop  =================
[05:56:25] [PASSED] Buffer object for userspace
[05:56:25] [PASSED] Kernel buffer object
[05:56:25] [PASSED] Shared buffer object
[05:56:25] ============ [PASSED] ttm_bo_validate_multihop =============
[05:56:25] ========== ttm_bo_validate_no_placement_signaled  ==========
[05:56:25] [PASSED] Buffer object in system domain, no page vector
[05:56:25] [PASSED] Buffer object in system domain with an existing page vector
[05:56:25] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[05:56:25] ======== ttm_bo_validate_no_placement_not_signaled  ========
[05:56:25] [PASSED] Buffer object for userspace
[05:56:25] [PASSED] Kernel buffer object
[05:56:25] [PASSED] Shared buffer object
[05:56:25] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[05:56:25] [PASSED] ttm_bo_validate_move_fence_signaled
[05:56:25] ========= ttm_bo_validate_move_fence_not_signaled  =========
[05:56:25] [PASSED] Waits for GPU
[05:56:25] [PASSED] Tries to lock straight away
[05:56:25] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[05:56:25] [PASSED] ttm_bo_validate_swapout
[05:56:25] [PASSED] ttm_bo_validate_happy_evict
[05:56:25] [PASSED] ttm_bo_validate_all_pinned_evict
[05:56:25] [PASSED] ttm_bo_validate_allowed_only_evict
[05:56:25] [PASSED] ttm_bo_validate_deleted_evict
[05:56:25] [PASSED] ttm_bo_validate_busy_domain_evict
[05:56:25] [PASSED] ttm_bo_validate_evict_gutting
[05:56:25] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[05:56:25] ================= [PASSED] ttm_bo_validate =================
[05:56:25] ============================================================
[05:56:25] Testing complete. Ran 102 tests: passed: 102
[05:56:25] Elapsed time: 11.280s total, 1.633s configuring, 9.431s building, 0.185s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for USE drm mm instead of drm SA for CCS read/write (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1418 bytes --]

== Series Details ==

Series: USE drm mm instead of drm SA for CCS read/write (rev5)
URL   : https://patchwork.freedesktop.org/series/163588/
State : success

== Summary ==

CI Bug Log - changes from xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1_BAT -> xe-pw-163588v5_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-163588v5_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@reltime:
    - bat-dg2-oem2:       [PASS][1] -> [FAIL][2] ([Intel XE#6520])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1/bat-dg2-oem2/igt@xe_waitfence@reltime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/bat-dg2-oem2/igt@xe_waitfence@reltime.html

  
  [Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520


Build changes
-------------

  * Linux: xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1 -> xe-pw-163588v5

  IGT_8852: 8852
  xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1: b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1
  xe-pw-163588v5: 163588v5

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/index.html

[-- Attachment #2: Type: text/html, Size: 1983 bytes --]

✗ Xe.CI.FULL: failure for USE drm mm instead of drm SA for CCS read/write (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 18650 bytes --]

== Series Details ==

Series: USE drm mm instead of drm SA for CCS read/write (rev5)
URL   : https://patchwork.freedesktop.org/series/163588/
State : failure

== Summary ==

CI Bug Log - changes from xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1_FULL -> xe-pw-163588v5_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-163588v5_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-163588v5_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-163588v5_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-bmg:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1/shard-bmg-4/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-10/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@xe_exec_balancer@many-virtual-basic:
    - shard-bmg:          [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1/shard-bmg-6/igt@xe_exec_balancer@many-virtual-basic.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-6/igt@xe_exec_balancer@many-virtual-basic.html

  
Known issues
------------

  Here are the changes found in xe-pw-163588v5_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2327]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#7059] / [Intel XE#7085])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#1124]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html

  * igt@kms_bw@connected-linear-tiling-1-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#7621])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_bw@connected-linear-tiling-1-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-2-displays-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#367] / [Intel XE#7354])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2887]) +3 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#3432])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_chamelium_edid@dp-edid-resolution-list:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2252]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_chamelium_edid@dp-edid-resolution-list.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          NOTRUN -> [FAIL][13] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_content_protection@atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2286] / [Intel XE#6035])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#4422] / [Intel XE#7442])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [PASS][16] -> [FAIL][17] ([Intel XE#301]) +1 other test fail
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2311]) +6 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#4141]) +2 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2313]) +7 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#6901])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_plane@pixel-format-y-tiled-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#7283]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_plane@pixel-format-y-tiled-modifier.html

  * igt@kms_plane_cursor@primary:
    - shard-bmg:          [PASS][24] -> [ABORT][25] ([Intel XE#5545] / [Intel XE#6652] / [Intel XE#7200]) +1 other test abort
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1/shard-bmg-5/igt@kms_plane_cursor@primary.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-2/igt@kms_plane_cursor@primary.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-lnl:          [PASS][26] -> [FAIL][27] ([Intel XE#7340])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1/shard-lnl-1/igt@kms_pm_dc@dc5-psr.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-lnl-6/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#1439] / [Intel XE#7402] / [Intel XE#836])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#1489]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr@fbc-psr-sprite-render:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_psr@fbc-psr-sprite-render.html

  * igt@kms_sharpness_filter@filter-strength:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#6503])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_sharpness_filter@filter-strength.html

  * igt@kms_vrr@flip-basic:
    - shard-lnl:          [PASS][32] -> [FAIL][33] ([Intel XE#4227] / [Intel XE#7397]) +1 other test fail
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1/shard-lnl-3/igt@kms_vrr@flip-basic.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-lnl-2/igt@kms_vrr@flip-basic.html

  * igt@xe_eudebug_online@single-step-one:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#7636]) +2 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@xe_eudebug_online@single-step-one.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [PASS][35] -> [INCOMPLETE][36] ([Intel XE#6321])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1/shard-bmg-5/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-10/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_evict@evict-small-multi-queue-cm:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#7140])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@xe_evict@evict-small-multi-queue-cm.html

  * igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2322] / [Intel XE#7372])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-rebind-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#7136]) +2 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@xe_exec_fault_mode@twice-multi-queue-userptr-rebind-prefetch.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#6874]) +5 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@xe_exec_multi_queue@few-execs-preempt-mode-userptr-invalidate.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma:
    - shard-lnl:          [PASS][41] -> [FAIL][42] ([Intel XE#5625])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1/shard-lnl-7/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-lnl-1/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html

  * igt@xe_exec_threads@threads-multi-queue-fd-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#7138]) +2 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@xe_exec_threads@threads-multi-queue-fd-userptr-rebind.html

  * igt@xe_multigpu_svm@mgpu-xgpu-access-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#6964])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@xe_multigpu_svm@mgpu-xgpu-access-prefetch.html

  * igt@xe_pm@d3cold-mmap-system:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#2284] / [Intel XE#7370])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@xe_pm@d3cold-mmap-system.html

  * igt@xe_query@multigpu-query-cs-cycles:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#944])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@xe_query@multigpu-query-cs-cycles.html

  
#### Possible fixes ####

  * igt@kms_async_flips@alternate-sync-async-flip-atomic:
    - shard-bmg:          [FAIL][47] ([Intel XE#3718] / [Intel XE#6078]) -> [PASS][48] +1 other test pass
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1/shard-bmg-10/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-2/igt@kms_async_flips@alternate-sync-async-flip-atomic.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-bmg:          [ABORT][49] ([Intel XE#5545] / [Intel XE#6652] / [Intel XE#7200]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1/shard-bmg-2/igt@kms_setmode@clone-exclusive-crtc.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-8/igt@kms_setmode@clone-exclusive-crtc.html

  
#### Warnings ####

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][51] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][52] ([Intel XE#2426] / [Intel XE#5848])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
  [Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
  [Intel XE#7200]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7200
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7340
  [Intel XE#7354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7354
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
  [Intel XE#7402]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7402
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7442
  [Intel XE#7621]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7621
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1 -> xe-pw-163588v5

  IGT_8852: 8852
  xe-4878-b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1: b6a5ad2db4f7519d2c4f4c872cf5d664e6a7fff1
  xe-pw-163588v5: 163588v5

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v5/index.html

[-- Attachment #2: Type: text/html, Size: 20228 bytes --]

Re: [PATCH v4 1/2] drm/xe: Add memory pool with shadow support

[Matthew Brost]

On Wed, Apr 08, 2026 at 11:01:47AM +0000, Satyanarayana K V P wrote:
> Add a memory pool to allocate sub-ranges from a BO-backed pool
> using drm_mm.
> 
> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>

Reviewed-by: Matthew Brost <matthew.brost@intel.com>

> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Maarten Lankhorst <dev@lankhorst.se>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> 
> ---
> V3 -> V4:
> - Cleaned documentation.
> - Squashed chnages from xe_bb.c to xe_mem_pool.c
> - Made xe_mem_pool_shadow_init() local.
> - Renamed the xe_mem_pool_manager to xe_mem_pool.
> - Fixed some other review comments.
> - Cached iomem status in mem_pool, as the pool->cpu_addr need to be freed
> in xe_mem_pool_fini() which is part of drm cleanup, but the BO is part of
> devm cleanup.
> 
> V2 -> V3:
> - Renamed xe_mm_suballoc to xe_mem_pool_manager.
> - Splitted xe_mm_suballoc_manager_init() into xe_mem_pool_init() and
> xe_mem_pool_shadow_init() (Michal)
> - Made xe_mm_sa_manager structure private. (Matt)
> - Introduced init flags to initialize allocated pools.
> 
> V1 -> V2:
> - Renamed xe_drm_mm to xe_mm_suballoc (Thomas)
> - Removed memset during manager init and insert (Matt)
> ---
>  drivers/gpu/drm/xe/Makefile            |   1 +
>  drivers/gpu/drm/xe/xe_mem_pool.c       | 403 +++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_mem_pool.h       |  35 +++
>  drivers/gpu/drm/xe/xe_mem_pool_types.h |  21 ++
>  4 files changed, 460 insertions(+)
>  create mode 100644 drivers/gpu/drm/xe/xe_mem_pool.c
>  create mode 100644 drivers/gpu/drm/xe/xe_mem_pool.h
>  create mode 100644 drivers/gpu/drm/xe/xe_mem_pool_types.h
> 
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 110fef511fe2..e42e582aca5c 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -88,6 +88,7 @@ xe-y += xe_bb.o \
>  	xe_irq.o \
>  	xe_late_bind_fw.o \
>  	xe_lrc.o \
> +	xe_mem_pool.o \
>  	xe_migrate.o \
>  	xe_mmio.o \
>  	xe_mmio_gem.o \
> diff --git a/drivers/gpu/drm/xe/xe_mem_pool.c b/drivers/gpu/drm/xe/xe_mem_pool.c
> new file mode 100644
> index 000000000000..d5e24d6aa88d
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_mem_pool.c
> @@ -0,0 +1,403 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include <linux/kernel.h>
> +
> +#include <drm/drm_managed.h>
> +
> +#include "instructions/xe_mi_commands.h"
> +#include "xe_bo.h"
> +#include "xe_device_types.h"
> +#include "xe_map.h"
> +#include "xe_mem_pool.h"
> +#include "xe_mem_pool_types.h"
> +#include "xe_tile_printk.h"
> +
> +/**
> + * struct xe_mem_pool - DRM MM pool for sub-allocating memory from a BO on an
> + * XE tile.
> + *
> + * The XE memory pool is a DRM MM manager that provides sub-allocation of memory
> + * from a backing buffer object (BO) on a specific XE tile. It is designed to
> + * manage memory for GPU workloads, allowing for efficient allocation and
> + * deallocation of memory regions within the BO.
> + *
> + * The memory pool maintains a primary BO that is pinned in the GGTT and mapped
> + * into the CPU address space for direct access. Optionally, it can also maintain
> + * a shadow BO that can be used for atomic updates to the primary BO's contents.
> + *
> + * The API provided by the memory pool allows clients to allocate and free memory
> + * regions, retrieve GPU and CPU addresses, and synchronize data between the
> + * primary and shadow BOs as needed.
> + */
> +struct xe_mem_pool {
> +	/** @base: Range allocator over [0, @size) in bytes */
> +	struct drm_mm base;
> +	/** @bo: Active pool BO (GGTT-pinned, CPU-mapped). */
> +	struct xe_bo *bo;
> +	/** @shadow: Shadow BO for atomic command updates. */
> +	struct xe_bo *shadow;
> +	/** @swap_guard: Timeline guard updating @bo and @shadow */
> +	struct mutex swap_guard;
> +	/** @cpu_addr: CPU virtual address of the active BO. */
> +	void *cpu_addr;
> +	/** @is_iomem: Indicates if the BO mapping is I/O memory. */
> +	bool is_iomem;
> +};
> +
> +static struct xe_mem_pool *node_to_pool(struct xe_mem_pool_node *node)
> +{
> +	return container_of(node->sa_node.mm, struct xe_mem_pool, base);
> +}
> +
> +static struct xe_tile *pool_to_tile(struct xe_mem_pool *pool)
> +{
> +	return pool->bo->tile;
> +}
> +
> +static void fini_pool_action(struct drm_device *drm, void *arg)
> +{
> +	struct xe_mem_pool *pool = arg;
> +
> +	if (pool->is_iomem)
> +		kvfree(pool->cpu_addr);
> +
> +	drm_mm_takedown(&pool->base);
> +}
> +
> +static int pool_shadow_init(struct xe_mem_pool *pool)
> +{
> +	struct xe_tile *tile = pool->bo->tile;
> +	struct xe_device *xe = tile_to_xe(tile);
> +	struct xe_bo *shadow;
> +	int ret;
> +
> +	xe_assert(xe, !pool->shadow);
> +
> +	ret = drmm_mutex_init(&xe->drm, &pool->swap_guard);
> +	if (ret)
> +		return ret;
> +
> +	if (IS_ENABLED(CONFIG_PROVE_LOCKING)) {
> +		fs_reclaim_acquire(GFP_KERNEL);
> +		might_lock(&pool->swap_guard);
> +		fs_reclaim_release(GFP_KERNEL);
> +	}
> +	shadow = xe_managed_bo_create_pin_map(xe, tile,
> +					      xe_bo_size(pool->bo),
> +					      XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> +					      XE_BO_FLAG_GGTT |
> +					      XE_BO_FLAG_GGTT_INVALIDATE |
> +					      XE_BO_FLAG_PINNED_NORESTORE);
> +	if (IS_ERR(shadow))
> +		return PTR_ERR(shadow);
> +
> +	pool->shadow = shadow;
> +
> +	return 0;
> +}
> +
> +/**
> + * xe_mem_pool_init() - Initialize memory pool.
> + * @tile: the &xe_tile where allocate.
> + * @size: number of bytes to allocate.
> + * @guard: the size of the guard region at the end of the BO that is not
> + * sub-allocated, in bytes.
> + * @flags: flags to use to create shadow pool.
> + *
> + * Initializes a memory pool for sub-allocating memory from a backing BO on the
> + * specified XE tile. The backing BO is pinned in the GGTT and mapped into
> + * the CPU address space for direct access. Optionally, a shadow BO can also be
> + * initialized for atomic updates to the primary BO's contents.
> + *
> + * Returns: a pointer to the &xe_mem_pool, or an error pointer on failure.
> + */
> +struct xe_mem_pool *xe_mem_pool_init(struct xe_tile *tile, u32 size,
> +				     u32 guard, int flags)
> +{
> +	struct xe_device *xe = tile_to_xe(tile);
> +	struct xe_mem_pool *pool;
> +	struct xe_bo *bo;
> +	u32 managed_size;
> +	int ret;
> +
> +	xe_tile_assert(tile, size > guard);
> +	managed_size = size - guard;
> +
> +	pool = drmm_kzalloc(&xe->drm, sizeof(*pool), GFP_KERNEL);
> +	if (!pool)
> +		return ERR_PTR(-ENOMEM);
> +
> +	bo = xe_managed_bo_create_pin_map(xe, tile, size,
> +					  XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> +					  XE_BO_FLAG_GGTT |
> +					  XE_BO_FLAG_GGTT_INVALIDATE |
> +					  XE_BO_FLAG_PINNED_NORESTORE);
> +	if (IS_ERR(bo)) {
> +		xe_tile_err(tile, "Failed to prepare %uKiB BO for mem pool (%pe)\n",
> +			    size / SZ_1K, bo);
> +		return ERR_CAST(bo);
> +	}
> +	pool->bo = bo;
> +	pool->is_iomem = bo->vmap.is_iomem;
> +
> +	if (pool->is_iomem) {
> +		pool->cpu_addr = kvzalloc(size, GFP_KERNEL);
> +		if (!pool->cpu_addr)
> +			return ERR_PTR(-ENOMEM);
> +	} else {
> +		pool->cpu_addr = bo->vmap.vaddr;
> +	}
> +
> +	if (flags & XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY) {
> +		ret = pool_shadow_init(pool);
> +
> +		if (ret)
> +			goto out_err;
> +	}
> +
> +	drm_mm_init(&pool->base, 0, managed_size);
> +	ret = drmm_add_action_or_reset(&xe->drm, fini_pool_action, pool);
> +	if (ret)
> +		return ERR_PTR(ret);
> +
> +	return pool;
> +
> +out_err:
> +	if (flags & XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY)
> +		xe_tile_err(tile,
> +			    "Failed to initialize shadow BO for mem pool (%d)\n", ret);
> +	if (bo->vmap.is_iomem)
> +		kvfree(pool->cpu_addr);
> +	return ERR_PTR(ret);
> +}
> +
> +/**
> + * xe_mem_pool_sync() - Copy the entire contents of the main pool to shadow pool.
> + * @pool: the memory pool containing the primary and shadow BOs.
> + *
> + * Copies the entire contents of the primary pool to the shadow pool. This must
> + * be done after xe_mem_pool_init() with the XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY
> + * flag to ensure that the shadow pool has the same initial contents as the primary
> + * pool. After this initial synchronization, clients can choose to synchronize the
> + * shadow pool with the primary pool on a node  basis using
> + * xe_mem_pool_sync_shadow_locked() as needed.
> + *
> + * Return: None.
> + */
> +void xe_mem_pool_sync(struct xe_mem_pool *pool)
> +{
> +	struct xe_tile *tile = pool_to_tile(pool);
> +	struct xe_device *xe = tile_to_xe(tile);
> +
> +	xe_tile_assert(tile, pool->shadow);
> +
> +	xe_map_memcpy_to(xe, &pool->shadow->vmap, 0,
> +			 pool->cpu_addr, xe_bo_size(pool->bo));
> +}
> +
> +/**
> + * xe_mem_pool_swap_shadow_locked() - Swap the primary BO with the shadow BO.
> + * @pool: the memory pool containing the primary and shadow BOs.
> + *
> + * Swaps the primary buffer object with the shadow buffer object in the mem
> + * pool. This allows for atomic updates to the contents of the primary BO
> + * by first writing to the shadow BO and then swapping it with the primary BO.
> + * Swap_guard must be held to ensure synchronization with any concurrent swap
> + * operations.
> + *
> + * Return: None.
> + */
> +void xe_mem_pool_swap_shadow_locked(struct xe_mem_pool *pool)
> +{
> +	struct xe_tile *tile = pool_to_tile(pool);
> +
> +	xe_tile_assert(tile, pool->shadow);
> +	lockdep_assert_held(&pool->swap_guard);
> +
> +	swap(pool->bo, pool->shadow);
> +	if (!pool->bo->vmap.is_iomem)
> +		pool->cpu_addr = pool->bo->vmap.vaddr;
> +}
> +
> +/**
> + * xe_mem_pool_sync_shadow_locked() - Copy node from primary pool to shadow pool.
> + * @node: the node allocated in the memory pool.
> + *
> + * Copies the specified batch buffer from the primary pool to the shadow pool.
> + * Swap_guard must be held to ensure synchronization with any concurrent swap
> + * operations.
> + *
> + * Return: None.
> + */
> +void xe_mem_pool_sync_shadow_locked(struct xe_mem_pool_node *node)
> +{
> +	struct xe_mem_pool *pool = node_to_pool(node);
> +	struct xe_tile *tile = pool_to_tile(pool);
> +	struct xe_device *xe = tile_to_xe(tile);
> +	struct drm_mm_node *sa_node = &node->sa_node;
> +
> +	xe_tile_assert(tile, pool->shadow);
> +	lockdep_assert_held(&pool->swap_guard);
> +
> +	xe_map_memcpy_to(xe, &pool->shadow->vmap,
> +			 sa_node->start,
> +			 pool->cpu_addr + sa_node->start,
> +			 sa_node->size);
> +}
> +
> +/**
> + * xe_mem_pool_gpu_addr() - Retrieve GPU address of memory pool.
> + * @pool: the memory pool
> + *
> + * Returns: GGTT address of the memory pool.
> + */
> +u64 xe_mem_pool_gpu_addr(struct xe_mem_pool *pool)
> +{
> +	return xe_bo_ggtt_addr(pool->bo);
> +}
> +
> +/**
> + * xe_mem_pool_cpu_addr() - Retrieve CPU address of manager pool.
> + * @pool: the memory pool
> + *
> + * Returns: CPU virtual address of memory pool.
> + */
> +void *xe_mem_pool_cpu_addr(struct xe_mem_pool *pool)
> +{
> +	return pool->cpu_addr;
> +}
> +
> +/**
> + * xe_mem_pool_bo_swap_guard() - Retrieve the mutex used to guard swap
> + * operations on a memory pool.
> + * @pool: the memory pool
> + *
> + * Returns: Swap guard mutex or NULL if shadow pool is not created.
> + */
> +struct mutex *xe_mem_pool_bo_swap_guard(struct xe_mem_pool *pool)
> +{
> +	if (!pool->shadow)
> +		return NULL;
> +
> +	return &pool->swap_guard;
> +}
> +
> +/**
> + * xe_mem_pool_bo_flush_write() - Copy the data from the sub-allocation
> + * to the GPU memory.
> + * @node: the node allocated in the memory pool to flush.
> + */
> +void xe_mem_pool_bo_flush_write(struct xe_mem_pool_node *node)
> +{
> +	struct xe_mem_pool *pool = node_to_pool(node);
> +	struct xe_tile *tile = pool_to_tile(pool);
> +	struct xe_device *xe = tile_to_xe(tile);
> +	struct drm_mm_node *sa_node = &node->sa_node;
> +
> +	if (!pool->bo->vmap.is_iomem)
> +		return;
> +
> +	xe_map_memcpy_to(xe, &pool->bo->vmap, sa_node->start,
> +			 pool->cpu_addr + sa_node->start,
> +			 sa_node->size);
> +}
> +
> +/**
> + * xe_mem_pool_bo_sync_read() - Copy the data from GPU memory to the
> + * sub-allocation.
> + * @node: the node allocated in the memory pool to read back.
> + */
> +void xe_mem_pool_bo_sync_read(struct xe_mem_pool_node *node)
> +{
> +	struct xe_mem_pool *pool = node_to_pool(node);
> +	struct xe_tile *tile = pool_to_tile(pool);
> +	struct xe_device *xe = tile_to_xe(tile);
> +	struct drm_mm_node *sa_node = &node->sa_node;
> +
> +	if (!pool->bo->vmap.is_iomem)
> +		return;
> +
> +	xe_map_memcpy_from(xe, pool->cpu_addr + sa_node->start,
> +			   &pool->bo->vmap, sa_node->start, sa_node->size);
> +}
> +
> +/**
> + * xe_mem_pool_alloc_node() - Allocate a new node for use with xe_mem_pool.
> + *
> + * Returns: node structure or an ERR_PTR(-ENOMEM).
> + */
> +struct xe_mem_pool_node *xe_mem_pool_alloc_node(void)
> +{
> +	struct xe_mem_pool_node *node = kzalloc_obj(*node);
> +
> +	if (!node)
> +		return ERR_PTR(-ENOMEM);
> +
> +	return node;
> +}
> +
> +/**
> + * xe_mem_pool_insert_node() - Insert a node into the memory pool.
> + * @pool: the memory pool to insert into
> + * @node: the node to insert
> + * @size: the size of the node to be allocated in bytes.
> + *
> + * Inserts a node into the specified memory pool using drm_mm for
> + * allocation.
> + *
> + * Returns: 0 on success or a negative error code on failure.
> + */
> +int xe_mem_pool_insert_node(struct xe_mem_pool *pool,
> +			    struct xe_mem_pool_node *node, u32 size)
> +{
> +	if (!pool)
> +		return -EINVAL;
> +
> +	return drm_mm_insert_node(&pool->base, &node->sa_node, size);
> +}
> +
> +/**
> + * xe_mem_pool_free_node() - Free a node allocated from the memory pool.
> + * @node: the node to free
> + *
> + * Returns: None.
> + */
> +void xe_mem_pool_free_node(struct xe_mem_pool_node *node)
> +{
> +	if (!node)
> +		return;
> +
> +	drm_mm_remove_node(&node->sa_node);
> +	kfree(node);
> +}
> +
> +/**
> + * xe_mem_pool_node_cpu_addr() - Retrieve CPU address of the node.
> + * @node: the node allocated in the memory pool
> + *
> + * Returns: CPU virtual address of the node.
> + */
> +void *xe_mem_pool_node_cpu_addr(struct xe_mem_pool_node *node)
> +{
> +	struct xe_mem_pool *pool = node_to_pool(node);
> +
> +	return xe_mem_pool_cpu_addr(pool) + node->sa_node.start;
> +}
> +
> +/**
> + * xe_mem_pool_dump() - Dump the state of the DRM MM manager for debugging.
> + * @pool: the memory pool info be dumped.
> + * @p: The DRM printer to use for output.
> + *
> + * Only the drm managed region is dumped, not the state of the BOs or any other
> + * pool information.
> + *
> + * Returns: None.
> + */
> +void xe_mem_pool_dump(struct xe_mem_pool *pool, struct drm_printer *p)
> +{
> +	drm_mm_print(&pool->base, p);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_mem_pool.h b/drivers/gpu/drm/xe/xe_mem_pool.h
> new file mode 100644
> index 000000000000..89cd2555fe91
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_mem_pool.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +#ifndef _XE_MEM_POOL_H_
> +#define _XE_MEM_POOL_H_
> +
> +#include <linux/sizes.h>
> +#include <linux/types.h>
> +
> +#include <drm/drm_mm.h>
> +#include "xe_mem_pool_types.h"
> +
> +struct drm_printer;
> +struct xe_mem_pool;
> +struct xe_tile;
> +
> +struct xe_mem_pool *xe_mem_pool_init(struct xe_tile *tile, u32 size,
> +				     u32 guard, int flags);
> +void xe_mem_pool_sync(struct xe_mem_pool *pool);
> +void xe_mem_pool_swap_shadow_locked(struct xe_mem_pool *pool);
> +void xe_mem_pool_sync_shadow_locked(struct xe_mem_pool_node *node);
> +u64 xe_mem_pool_gpu_addr(struct xe_mem_pool *pool);
> +void *xe_mem_pool_cpu_addr(struct xe_mem_pool *pool);
> +struct mutex *xe_mem_pool_bo_swap_guard(struct xe_mem_pool *pool);
> +void xe_mem_pool_bo_flush_write(struct xe_mem_pool_node *node);
> +void xe_mem_pool_bo_sync_read(struct xe_mem_pool_node *node);
> +struct xe_mem_pool_node *xe_mem_pool_alloc_node(void);
> +int xe_mem_pool_insert_node(struct xe_mem_pool *pool,
> +			    struct xe_mem_pool_node *node, u32 size);
> +void xe_mem_pool_free_node(struct xe_mem_pool_node *node);
> +void *xe_mem_pool_node_cpu_addr(struct xe_mem_pool_node *node);
> +void xe_mem_pool_dump(struct xe_mem_pool *pool, struct drm_printer *p);
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_mem_pool_types.h b/drivers/gpu/drm/xe/xe_mem_pool_types.h
> new file mode 100644
> index 000000000000..d5e926c93351
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_mem_pool_types.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_MEM_POOL_TYPES_H_
> +#define _XE_MEM_POOL_TYPES_H_
> +
> +#include <drm/drm_mm.h>
> +
> +#define XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY			BIT(0)
> +
> +/**
> + * struct xe_mem_pool_node - Sub-range allocations from mem pool.
> + */
> +struct xe_mem_pool_node {
> +	/** @sa_node: drm_mm_node for this allocation. */
> +	struct drm_mm_node sa_node;
> +};
> +
> +#endif
> -- 
> 2.43.0
> 

Re: [PATCH v4 2/2] drm/xe/vf: Use drm mm instead of drm sa for CCS read/write

[Matthew Brost]

On Wed, Apr 08, 2026 at 11:01:48AM +0000, Satyanarayana K V P wrote:
> The suballocator algorithm tracks a hole cursor at the last allocation
> and tries to allocate after it. This is optimized for fence-ordered
> progress, where older allocations are expected to become reusable first.
> 
> In fence-enabled mode, that ordering assumption holds. In fence-disabled
> mode, allocations may be freed in arbitrary order, so limiting allocation
> to the current hole window can miss valid free space and fail allocations
> despite sufficient total space.
> 
> Use DRM memory manager instead of sub-allocator to get rid of this issue
> as CCS read/write operations do not use fences.
> 
> Fixes: 864690cf4dd6 ("drm/xe/vf: Attach and detach CCS copy commands with BO")
> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>

Reviewed-by: Matthew Brost <matthew.brost@intel.com>

> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Maarten Lankhorst <dev@lankhorst.se>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> 
> ---
> V3 -> V4:
> - Updated changes as per xe_mem_pool.
> - Updated Fixes: field (Thomas)
> 
> V2 -> V3:
> - Used xe_mem_pool_init() and xe_mem_pool_shadow_init() to allocate BB
> pools.
> 
> V1 -> V2:
> - Renamed xe_drm_mm to xe_mm_suballoc (Thomas)
> ---
>  drivers/gpu/drm/xe/xe_bo_types.h           |  3 +-
>  drivers/gpu/drm/xe/xe_migrate.c            | 56 ++++++++++++----------
>  drivers/gpu/drm/xe/xe_sriov_vf_ccs.c       | 54 +++++++++++----------
>  drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h |  5 +-
>  4 files changed, 63 insertions(+), 55 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h
> index ff8317bfc1ae..9d19940b8fc0 100644
> --- a/drivers/gpu/drm/xe/xe_bo_types.h
> +++ b/drivers/gpu/drm/xe/xe_bo_types.h
> @@ -18,6 +18,7 @@
>  #include "xe_ggtt_types.h"
>  
>  struct xe_device;
> +struct xe_mem_pool_node;
>  struct xe_vm;
>  
>  #define XE_BO_MAX_PLACEMENTS	3
> @@ -88,7 +89,7 @@ struct xe_bo {
>  	bool ccs_cleared;
>  
>  	/** @bb_ccs: BB instructions of CCS read/write. Valid only for VF */
> -	struct xe_bb *bb_ccs[XE_SRIOV_VF_CCS_CTX_COUNT];
> +	struct xe_mem_pool_node *bb_ccs[XE_SRIOV_VF_CCS_CTX_COUNT];
>  
>  	/**
>  	 * @cpu_caching: CPU caching mode. Currently only used for userspace
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index fc918b4fba54..5fdc89ed5256 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -29,6 +29,7 @@
>  #include "xe_hw_engine.h"
>  #include "xe_lrc.h"
>  #include "xe_map.h"
> +#include "xe_mem_pool.h"
>  #include "xe_mocs.h"
>  #include "xe_printk.h"
>  #include "xe_pt.h"
> @@ -1166,11 +1167,12 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
>  	u32 batch_size, batch_size_allocated;
>  	struct xe_device *xe = gt_to_xe(gt);
>  	struct xe_res_cursor src_it, ccs_it;
> +	struct xe_mem_pool *bb_pool;
>  	struct xe_sriov_vf_ccs_ctx *ctx;
> -	struct xe_sa_manager *bb_pool;
>  	u64 size = xe_bo_size(src_bo);
> -	struct xe_bb *bb = NULL;
> +	struct xe_mem_pool_node *bb;
>  	u64 src_L0, src_L0_ofs;
> +	struct xe_bb xe_bb_tmp;
>  	u32 src_L0_pt;
>  	int err;
>  
> @@ -1208,18 +1210,18 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
>  		size -= src_L0;
>  	}
>  
> -	bb = xe_bb_alloc(gt);
> +	bb = xe_mem_pool_alloc_node();
>  	if (IS_ERR(bb))
>  		return PTR_ERR(bb);
>  
>  	bb_pool = ctx->mem.ccs_bb_pool;
> -	scoped_guard(mutex, xe_sa_bo_swap_guard(bb_pool)) {
> -		xe_sa_bo_swap_shadow(bb_pool);
> +	scoped_guard(mutex, xe_mem_pool_bo_swap_guard(bb_pool)) {
> +		xe_mem_pool_swap_shadow_locked(bb_pool);
>  
> -		err = xe_bb_init(bb, bb_pool, batch_size);
> +		err = xe_mem_pool_insert_node(bb_pool, bb, batch_size * sizeof(u32));
>  		if (err) {
>  			xe_gt_err(gt, "BB allocation failed.\n");
> -			xe_bb_free(bb, NULL);
> +			kfree(bb);
>  			return err;
>  		}
>  
> @@ -1227,6 +1229,7 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
>  		size = xe_bo_size(src_bo);
>  		batch_size = 0;
>  
> +		xe_bb_tmp = (struct xe_bb){ .cs = xe_mem_pool_node_cpu_addr(bb), .len = 0 };
>  		/*
>  		 * Emit PTE and copy commands here.
>  		 * The CCS copy command can only support limited size. If the size to be
> @@ -1255,24 +1258,27 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
>  			xe_assert(xe, IS_ALIGNED(ccs_it.start, PAGE_SIZE));
>  			batch_size += EMIT_COPY_CCS_DW;
>  
> -			emit_pte(m, bb, src_L0_pt, false, true, &src_it, src_L0, src);
> +			emit_pte(m, &xe_bb_tmp, src_L0_pt, false, true, &src_it, src_L0, src);
>  
> -			emit_pte(m, bb, ccs_pt, false, false, &ccs_it, ccs_size, src);
> +			emit_pte(m, &xe_bb_tmp, ccs_pt, false, false, &ccs_it, ccs_size, src);
>  
> -			bb->len = emit_flush_invalidate(bb->cs, bb->len, flush_flags);
> -			flush_flags = xe_migrate_ccs_copy(m, bb, src_L0_ofs, src_is_pltt,
> +			xe_bb_tmp.len = emit_flush_invalidate(xe_bb_tmp.cs, xe_bb_tmp.len,
> +							      flush_flags);
> +			flush_flags = xe_migrate_ccs_copy(m, &xe_bb_tmp, src_L0_ofs, src_is_pltt,
>  							  src_L0_ofs, dst_is_pltt,
>  							  src_L0, ccs_ofs, true);
> -			bb->len = emit_flush_invalidate(bb->cs, bb->len, flush_flags);
> +			xe_bb_tmp.len = emit_flush_invalidate(xe_bb_tmp.cs, xe_bb_tmp.len,
> +							      flush_flags);
>  
>  			size -= src_L0;
>  		}
>  
> -		xe_assert(xe, (batch_size_allocated == bb->len));
> +		xe_assert(xe, (batch_size_allocated == xe_bb_tmp.len));
> +		xe_assert(xe, bb->sa_node.size == xe_bb_tmp.len * sizeof(u32));
>  		src_bo->bb_ccs[read_write] = bb;
>  
>  		xe_sriov_vf_ccs_rw_update_bb_addr(ctx);
> -		xe_sa_bo_sync_shadow(bb->bo);
> +		xe_mem_pool_sync_shadow_locked(bb);
>  	}
>  
>  	return 0;
> @@ -1297,10 +1303,10 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
>  void xe_migrate_ccs_rw_copy_clear(struct xe_bo *src_bo,
>  				  enum xe_sriov_vf_ccs_rw_ctxs read_write)
>  {
> -	struct xe_bb *bb = src_bo->bb_ccs[read_write];
> +	struct xe_mem_pool_node *bb = src_bo->bb_ccs[read_write];
>  	struct xe_device *xe = xe_bo_device(src_bo);
> +	struct xe_mem_pool *bb_pool;
>  	struct xe_sriov_vf_ccs_ctx *ctx;
> -	struct xe_sa_manager *bb_pool;
>  	u32 *cs;
>  
>  	xe_assert(xe, IS_SRIOV_VF(xe));
> @@ -1308,17 +1314,17 @@ void xe_migrate_ccs_rw_copy_clear(struct xe_bo *src_bo,
>  	ctx = &xe->sriov.vf.ccs.contexts[read_write];
>  	bb_pool = ctx->mem.ccs_bb_pool;
>  
> -	guard(mutex) (xe_sa_bo_swap_guard(bb_pool));
> -	xe_sa_bo_swap_shadow(bb_pool);
> -
> -	cs = xe_sa_bo_cpu_addr(bb->bo);
> -	memset(cs, MI_NOOP, bb->len * sizeof(u32));
> -	xe_sriov_vf_ccs_rw_update_bb_addr(ctx);
> +	scoped_guard(mutex, xe_mem_pool_bo_swap_guard(bb_pool)) {
> +		xe_mem_pool_swap_shadow_locked(bb_pool);
>  
> -	xe_sa_bo_sync_shadow(bb->bo);
> +		cs = xe_mem_pool_node_cpu_addr(bb);
> +		memset(cs, MI_NOOP, bb->sa_node.size);
> +		xe_sriov_vf_ccs_rw_update_bb_addr(ctx);
>  
> -	xe_bb_free(bb, NULL);
> -	src_bo->bb_ccs[read_write] = NULL;
> +		xe_mem_pool_sync_shadow_locked(bb);
> +		xe_mem_pool_free_node(bb);
> +		src_bo->bb_ccs[read_write] = NULL;
> +	}
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> index db023fb66a27..09b99fb2608b 100644
> --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> @@ -14,9 +14,9 @@
>  #include "xe_guc.h"
>  #include "xe_guc_submit.h"
>  #include "xe_lrc.h"
> +#include "xe_mem_pool.h"
>  #include "xe_migrate.h"
>  #include "xe_pm.h"
> -#include "xe_sa.h"
>  #include "xe_sriov_printk.h"
>  #include "xe_sriov_vf.h"
>  #include "xe_sriov_vf_ccs.h"
> @@ -141,43 +141,47 @@ static u64 get_ccs_bb_pool_size(struct xe_device *xe)
>  
>  static int alloc_bb_pool(struct xe_tile *tile, struct xe_sriov_vf_ccs_ctx *ctx)
>  {
> +	struct xe_mem_pool *pool;
>  	struct xe_device *xe = tile_to_xe(tile);
> -	struct xe_sa_manager *sa_manager;
> +	u32 *pool_cpu_addr, *last_dw_addr;
>  	u64 bb_pool_size;
> -	int offset, err;
> +	int err;
>  
>  	bb_pool_size = get_ccs_bb_pool_size(xe);
>  	xe_sriov_info(xe, "Allocating %s CCS BB pool size = %lldMB\n",
>  		      ctx->ctx_id ? "Restore" : "Save", bb_pool_size / SZ_1M);
>  
> -	sa_manager = __xe_sa_bo_manager_init(tile, bb_pool_size, SZ_4K, SZ_16,
> -					     XE_SA_BO_MANAGER_FLAG_SHADOW);
> -
> -	if (IS_ERR(sa_manager)) {
> -		xe_sriov_err(xe, "Suballocator init failed with error: %pe\n",
> -			     sa_manager);
> -		err = PTR_ERR(sa_manager);
> +	pool = xe_mem_pool_init(tile, bb_pool_size, sizeof(u32),
> +				XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY);
> +	if (IS_ERR(pool)) {
> +		xe_sriov_err(xe, "xe_mem_pool_init failed with error: %pe\n",
> +			     pool);
> +		err = PTR_ERR(pool);
>  		return err;
>  	}
>  
> -	offset = 0;
> -	xe_map_memset(xe, &sa_manager->bo->vmap, offset, MI_NOOP,
> -		      bb_pool_size);
> -	xe_map_memset(xe, &sa_manager->shadow->vmap, offset, MI_NOOP,
> -		      bb_pool_size);
> +	pool_cpu_addr = xe_mem_pool_cpu_addr(pool);
> +	memset(pool_cpu_addr, 0, bb_pool_size);
>  
> -	offset = bb_pool_size - sizeof(u32);
> -	xe_map_wr(xe, &sa_manager->bo->vmap, offset, u32, MI_BATCH_BUFFER_END);
> -	xe_map_wr(xe, &sa_manager->shadow->vmap, offset, u32, MI_BATCH_BUFFER_END);
> +	last_dw_addr = pool_cpu_addr + (bb_pool_size / sizeof(u32)) - 1;
> +	*last_dw_addr = MI_BATCH_BUFFER_END;
>  
> -	ctx->mem.ccs_bb_pool = sa_manager;
> +	/**
> +	 * Sync the main copy and shadow copy so that the shadow copy is
> +	 * replica of main copy. We sync only BBs after init part. So, we
> +	 * need to make sure the main pool and shadow copy are in sync after
> +	 * this point. This is needed as GuC may read the BB commands from
> +	 * shadow copy.
> +	 */
> +	xe_mem_pool_sync(pool);
>  
> +	ctx->mem.ccs_bb_pool = pool;
>  	return 0;
>  }
>  
>  static void ccs_rw_update_ring(struct xe_sriov_vf_ccs_ctx *ctx)
>  {
> -	u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool);
> +	u64 addr = xe_mem_pool_gpu_addr(ctx->mem.ccs_bb_pool);
>  	struct xe_lrc *lrc = xe_exec_queue_lrc(ctx->mig_q);
>  	u32 dw[10], i = 0;
>  
> @@ -388,7 +392,7 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe)
>  #define XE_SRIOV_VF_CCS_RW_BB_ADDR_OFFSET	(2 * sizeof(u32))
>  void xe_sriov_vf_ccs_rw_update_bb_addr(struct xe_sriov_vf_ccs_ctx *ctx)
>  {
> -	u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool);
> +	u64 addr = xe_mem_pool_gpu_addr(ctx->mem.ccs_bb_pool);
>  	struct xe_lrc *lrc = xe_exec_queue_lrc(ctx->mig_q);
>  	struct xe_device *xe = gt_to_xe(ctx->mig_q->gt);
>  
> @@ -412,8 +416,8 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo)
>  	struct xe_device *xe = xe_bo_device(bo);
>  	enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
>  	struct xe_sriov_vf_ccs_ctx *ctx;
> +	struct xe_mem_pool_node *bb;
>  	struct xe_tile *tile;
> -	struct xe_bb *bb;
>  	int err = 0;
>  
>  	xe_assert(xe, IS_VF_CCS_READY(xe));
> @@ -445,7 +449,7 @@ int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo)
>  {
>  	struct xe_device *xe = xe_bo_device(bo);
>  	enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
> -	struct xe_bb *bb;
> +	struct xe_mem_pool_node *bb;
>  
>  	xe_assert(xe, IS_VF_CCS_READY(xe));
>  
> @@ -471,8 +475,8 @@ int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo)
>   */
>  void xe_sriov_vf_ccs_print(struct xe_device *xe, struct drm_printer *p)
>  {
> -	struct xe_sa_manager *bb_pool;
>  	enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
> +	struct xe_mem_pool *bb_pool;
>  
>  	if (!IS_VF_CCS_READY(xe))
>  		return;
> @@ -485,7 +489,7 @@ void xe_sriov_vf_ccs_print(struct xe_device *xe, struct drm_printer *p)
>  
>  		drm_printf(p, "ccs %s bb suballoc info\n", ctx_id ? "write" : "read");
>  		drm_printf(p, "-------------------------\n");
> -		drm_suballoc_dump_debug_info(&bb_pool->base, p, xe_sa_manager_gpu_addr(bb_pool));
> +		xe_mem_pool_dump(bb_pool, p);
>  		drm_puts(p, "\n");
>  	}
>  }
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
> index 22c499943d2a..6fc8f97ef3f4 100644
> --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
> @@ -17,9 +17,6 @@ enum xe_sriov_vf_ccs_rw_ctxs {
>  	XE_SRIOV_VF_CCS_CTX_COUNT
>  };
>  
> -struct xe_migrate;
> -struct xe_sa_manager;
> -
>  /**
>   * struct xe_sriov_vf_ccs_ctx - VF CCS migration context data.
>   */
> @@ -33,7 +30,7 @@ struct xe_sriov_vf_ccs_ctx {
>  	/** @mem: memory data */
>  	struct {
>  		/** @mem.ccs_bb_pool: Pool from which batch buffers are allocated. */
> -		struct xe_sa_manager *ccs_bb_pool;
> +		struct xe_mem_pool *ccs_bb_pool;
>  	} mem;
>  };
>  
> -- 
> 2.43.0
>