From: "Michał Winiarski" <michal.winiarski@intel.com>
To: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: <intel-xe@lists.freedesktop.org>,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Matthew Brost <matthew.brost@intel.com>,
Ilia Levi <ilia.levi@intel.com>
Subject: Re: [PATCH 1/2] drm/xe/memirq: Update interrupt handler logic
Date: Wed, 13 May 2026 15:26:41 +0200 [thread overview]
Message-ID: <agR7rvCSTcAaRAou@nostramo> (raw)
In-Reply-To: <20260511172838.2299-2-michal.wajdeczko@intel.com>
On Mon, May 11, 2026 at 07:28:37PM +0200, Michal Wajdeczko wrote:
> To workaround some corner case hardware limitations, new programming
> note for the memory based interrupt handler suggests to assume that
> some status bytes, like GT_MI_USER_INTERRUPT and GUC_INTR_GUC2HOST,
> are always set. Update our interrupt handler to follow the new rules.
>
> Bspec: 53672
> Fixes: a6581ebe7685 ("drm/xe/vf: Introduce Memory Based Interrupts Handler")
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Thanks,
-Michał
next prev parent reply other threads:[~2026-05-13 13:26 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-11 17:28 [PATCH 0/2] drm/xe/memirq: Update interrupt handler logic Michal Wajdeczko
2026-05-11 17:28 ` [PATCH 1/2] " Michal Wajdeczko
2026-05-13 13:26 ` Michał Winiarski [this message]
2026-05-11 17:28 ` [PATCH 2/2] drm/xe/memirq: Enable GT_MI_USER_INTERRUPT only Michal Wajdeczko
2026-05-13 13:27 ` Michał Winiarski
2026-05-12 3:25 ` ✓ CI.KUnit: success for drm/xe/memirq: Update interrupt handler logic Patchwork
2026-05-12 4:35 ` ✓ Xe.CI.BAT: " Patchwork
2026-05-12 10:07 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-05-12 18:43 ` Michal Wajdeczko
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