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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: James Xiong <james.xiong@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
	gustavo.sousa@intel.com, jani.nikula@linux.intel.com,
	imre.deak@intel.com
Subject: Re: [PATCH v4] drm/i915/dmc: fix assert_dmc_loaded WARN during async firmware load
Date: Fri, 29 May 2026 18:40:40 +0300	[thread overview]
Message-ID: <ahmzeOA79VxnmWD3@intel.com> (raw)
In-Reply-To: <20260511173101.723421-1-james.xiong@intel.com>

On Mon, May 11, 2026 at 10:31:01AM -0700, James Xiong wrote:
> During driver probe, DMC firmware is loaded asynchronously via a
> workqueue. There is a race between parse_dmc_fw() setting the payload
> pointer (making has_dmc_id_fw() return true) and intel_dmc_load_program()
> writing the firmware to hardware registers. If the probe thread calls
> intel_dmc_enable_pipe() -> assert_dmc_loaded() in this window via
> intel_modeset_setup_hw_state(), it sees parsed payload but stale HW
> registers, triggering a ~20% intermittent WARNING on ADL-N warm boot.
> 
> v2: Fix by calling intel_dmc_wait_fw_load() in
>     intel_modeset_setup_hw_state() before iterating the CRTCs (Gustavo
>     Sousa).
> 
> v3: Move intel_dmc_wait_fw_load() into intel_dmc_enable_pipe() itself
>     so the function is self-contained (Jani Nikula, Gustavo Sousa).
> 
> Fixes: 3af2ff0840be ("drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled")
> Signed-off-by: James Xiong <james.xiong@intel.com>
> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dmc.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 0df4f42ba3e3..4151eae92744 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -786,7 +786,12 @@ void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state)
>  	enum pipe pipe = crtc->pipe;
>  	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
>  
> -	if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
> +	if (!is_valid_dmc_id(dmc_id))
> +		return;
> +
> +	intel_dmc_wait_fw_load(display);

I was going to say that intel_flipq_init() already did that, but
looks like that's called later not before.

I think what we probably want is an unconditional
intel_dmc_wait_fw_load() somewhere before this so that the whole
thing isn't so random.

> +
> +	if (!has_dmc_id_fw(display, dmc_id))
>  		return;
>  
>  	if (!can_enable_pipedmc(crtc_state)) {
> -- 
> 2.34.1

-- 
Ville Syrjälä
Intel

  parent reply	other threads:[~2026-05-29 15:40 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-11 17:31 [PATCH v4] drm/i915/dmc: fix assert_dmc_loaded WARN during async firmware load James Xiong
2026-05-12  5:59 ` ✓ CI.KUnit: success for drm/i915/dmc: fix assert_dmc_loaded WARN during async firmware load (rev3) Patchwork
2026-05-12  7:11 ` ✓ Xe.CI.BAT: " Patchwork
2026-05-12 14:27 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-05-29 15:40 ` Ville Syrjälä [this message]
2026-06-01 16:06   ` [PATCH v4] drm/i915/dmc: fix assert_dmc_loaded WARN during async firmware load Jani Nikula

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