From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C210FCD6E56 for ; Wed, 3 Jun 2026 12:13:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8118510FCF2; Wed, 3 Jun 2026 12:13:12 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="I639u830"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3E56210FCF2; Wed, 3 Jun 2026 12:13:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780488791; x=1812024791; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=sETcxPSDW82x8ce8cPxleZqxZYrqetBSOKYD5RYJfXc=; b=I639u830UDWivh6go+5OrWv9lYCmx8lsQ8LzkAQr2qi6qJf78zW+0MLy sswIG1QNBJ6o896LFBuplGG9KKJP51yQwf0FrrjlJxBDuEB17HIIAFXw2 tj3VCxSwyQreV3MwQoki1t44qIjx2MzZtWf1rRSdUQIPZMWg4m+zhZeKN h5bNaf9tiOhulv0jLMLXxCFf3YiQvGmccz8cd+ogu6TQjcECtG54ytWwM 1zcMK+NjSQ89Fh22GzM7yhwlUsy6OG1QNOB2lxFLUFB4PUwqRQcPlSMlq 9F8yAebVCNv7fylrLpFcEAEqk4HDsEBa/k/UcXlJ58Ck1o7MHKshInEFh g==; X-CSE-ConnectionGUID: chLLqr/WRHupH//8mKzIZA== X-CSE-MsgGUID: LkoAsNnfToWI2Y/j/axpbg== X-IronPort-AV: E=McAfee;i="6800,10657,11805"; a="85182626" X-IronPort-AV: E=Sophos;i="6.24,185,1774335600"; d="scan'208";a="85182626" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 05:13:10 -0700 X-CSE-ConnectionGUID: t3wnsNcfTV6o8wtimtQ7vQ== X-CSE-MsgGUID: MQDD0adJTW6gC3Tf0C3jkA== X-ExtLoop1: 1 Received: from fpallare-mobl4.ger.corp.intel.com (HELO localhost) ([10.245.244.220]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 05:13:09 -0700 Date: Wed, 3 Jun 2026 15:13:05 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Ankit Nautiyal Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, navaremanasi@google.com Subject: Re: [PATCH 1/6] drm/i915/display: Handle VSYNC timing in LRR path Message-ID: References: <20260522132511.321540-1-ankit.k.nautiyal@intel.com> <20260522132511.321540-2-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260522132511.321540-2-ankit.k.nautiyal@intel.com> X-Patchwork-Hint: comment Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Fri, May 22, 2026 at 06:55:06PM +0530, Ankit Nautiyal wrote: > LRR already updates crtc_vtotal/crtc_vblank_end seamlessly. > Extend the same handling to crtc_vsync_start/crtc_vsync_end so > VSYNC timing changes are programmed and accepted via the LRR path instead > of forcing a full modeset. > > Signed-off-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 757a78c75bbf..75c998960864 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2797,6 +2797,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc > intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), > VBLANK_START(crtc_vblank_start - 1) | > VBLANK_END(crtc_vblank_end - 1)); I'm thinking we probably want some kind of comment here. Perhaps something like this: /* * DP doesn't have vertical sync, so TRANS_VSYNC only affects * the position of the vsync interrupt (and does so even when * using the VRR timing generator!). Thus updating TRANS_VSYNC * here seems fine even if it isn't double buffered. */ With that Reviewed-by: Ville Syrjälä > + intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), > + VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | > + VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); > /* > * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal > * bits are not required. Since the support for these bits is going to > @@ -5166,9 +5169,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ > if (!fastset || !allow_vblank_delay_fastset(current_config)) \ > PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ > - PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ > - PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ > if (!fastset || !pipe_config->update_lrr) { \ > + PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ > + PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ > PIPE_CONF_CHECK_I(name.crtc_vtotal); \ > PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ > } \ > @@ -5782,6 +5785,8 @@ static bool lrr_params_changed(const struct intel_crtc_state *old_crtc_state, > > return old_adjusted_mode->crtc_vblank_start != new_adjusted_mode->crtc_vblank_start || > old_adjusted_mode->crtc_vblank_end != new_adjusted_mode->crtc_vblank_end || > + old_adjusted_mode->crtc_vsync_start != new_adjusted_mode->crtc_vsync_start || > + old_adjusted_mode->crtc_vsync_end != new_adjusted_mode->crtc_vsync_end || > old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal || > old_crtc_state->set_context_latency != new_crtc_state->set_context_latency; > } > -- > 2.45.2 -- Ville Syrjälä Intel