Re: [PATCH 2/2] drm/xe/xe_ras: Add support for PCIe error component handling

[Raag Jadav <raag.jadav@intel.com>]

On Tue, Aug 25, 2026 at 07:41:12PM +0530, Riana Tauro wrote:
> PCIe Subsystem GPMA errors and other uncorrectable non-fatal usp errors
> are collected and classified by system controller under component PCIe.
> For PCIe SS GPMA errors, request a Secondary Bus Reset.

Again, can you please elaborate? I'm struggling to keep up :(

> All other PCIe errors are treated as recovered with no further action.
> 
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_ras.c       | 18 ++++++++++++++++++
>  drivers/gpu/drm/xe/xe_ras_types.h |  1 +
>  2 files changed, 19 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 586dc28a638a..39e5fdb9770d 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -394,6 +394,21 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
>  	return XE_RAS_RECOVERY_ACTION_RECOVERED;
>  }
>  
> +static u8 handle_pcie_errors(struct xe_device *xe, struct xe_ras_error_array *arr)
> +{
> +	struct xe_ras_ieh_error *info = (void *)arr->details;
> +
> +	if (info->global_error_status & XE_RAS_PCIE_IEH_GPMA) {
> +		xe_log_comp_fatal(xe, PCIE, &arr->counter, sizeof(arr->counter),
> +				  "GPMA error detected\n");
> +		return XE_RAS_RECOVERY_ACTION_RESET;
> +	}
> +
> +	xe_log_comp_recoverable(xe, PCIE, &arr->counter, sizeof(arr->counter),
> +				"Other errors detected\n");

Ditto for 'unknown'.

Raag

> +	return XE_RAS_RECOVERY_ACTION_RECOVERED;
> +}
> +
>  static u8 handle_fabric_errors(struct xe_device *xe, struct xe_ras_error_array *arr)
>  {
>  	struct xe_ras_error_product *product = &arr->counter.product;
> @@ -572,6 +587,9 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
>  			case XE_RAS_COMP_DEVICE_MEMORY:
>  				action = handle_device_memory_errors(xe, arr);
>  				break;
> +			case XE_RAS_COMP_PCIE:
> +				action = handle_pcie_errors(xe, arr);
> +				break;
>  			case XE_RAS_COMP_FABRIC:
>  				action = handle_fabric_errors(xe, arr);
>  				break;
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> index 73517fd0d415..0a9747df8a69 100644
> --- a/drivers/gpu/drm/xe/xe_ras_types.h
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -12,6 +12,7 @@
>  #define XE_RAS_NUM_ERROR_ARR			3
>  /* Error bits in IEH global error status register */
>  #define XE_RAS_SOC_IEH_PUNIT			BIT(1)
> +#define XE_RAS_PCIE_IEH_GPMA			BIT(5)
>  /* Bits 16-31 represent individual SAF MHB unit */
>  #define XE_RAS_FAB_IEH_SAF_MHB			GENMASK(31, 16)
>  /* Fabric Data payload parity errors */
> -- 
> 2.47.1
>