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But from Xe3p LT PHY was introduced > which powers down the PHY. Which means we need to make sure > "Disable DC5/6" of AUX Programming sequence is honored. > Disable Dc5/6 when programming AUX. > > Bspec: 68851, 68967 > Co-developed-by: Ramanaidu Naladala > Signed-off-by: Suraj Kandpal > --- > v1 -> v2: > -Fix commit message (Arun) > -Fix the if typo (Arun, Sashiko) > > drivers/gpu/drm/i915/display/intel_dp_aux.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c > index 3cb07b0a901c..879b203f9258 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c > @@ -260,6 +260,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, > u32 aux_clock_divider; > enum intel_display_power_domain aux_domain; > struct ref_tracker *aux_wakeref; > + struct ref_tracker *dc_off_wakeref = NULL; > struct ref_tracker *pps_wakeref = NULL; > int i, ret, recv_bytes; > int try, clock = 0; > @@ -286,6 +287,9 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, > > aux_wakeref = intel_display_power_get(display, aux_domain); > > + if (HAS_LT_PHY(display)) > + dc_off_wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF); Please don't do this. There is already a way to enable all dependent power wells for a power domain, in this case for the above AUX domain, which would do the correct thing whenever the AUX domain is enabled; as opposed to the above special casing of the AUX transfer. For NVL+ setting that dependency would be something like: I915_DECL_PW_DOMAINS(nvl_pwdoms_dc_off, POWER_DOMAIN_DC_OFF, XE3LPD_PW_2_POWER_DOMAINS, XE3LPD_PW_C_POWER_DOMAINS, XE3LPD_PW_D_POWER_DOMAINS, POWER_DOMAIN_AUDIO_MMIO, POWER_DOMAIN_AUDIO_PLAYBACK, POWER_DOMAIN_AUX_A, \ POWER_DOMAIN_AUX_B, \ POWER_DOMAIN_AUX_USBC1, \ POWER_DOMAIN_AUX_USBC2, \ POWER_DOMAIN_AUX_USBC3, \ POWER_DOMAIN_AUX_USBC4, \ POWER_DOMAIN_AUX_TBT1, \ POWER_DOMAIN_AUX_TBT2, \ POWER_DOMAIN_AUX_TBT3, \ POWER_DOMAIN_AUX_TBT4, \ POWER_DOMAIN_INIT); static const struct i915_power_well_desc nvl_power_wells_dcoff[] = { { .instances = &I915_PW_INSTANCES( I915_PW("DC_off", &nvl_pwdoms_dc_off, .id = SKL_DISP_DC_OFF), ), .ops = &gen9_dc_off_power_well_ops, }, }; static const struct i915_power_well_desc_list nvl_power_wells[] = { I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), I915_PW_DESCRIPTORS(icl_power_wells_pw_1), I915_PW_DESCRIPTORS(nvl_power_wells_dcoff), I915_PW_DESCRIPTORS(xe3lpd_power_wells_main), I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica), I915_PW_DESCRIPTORS(xelpdp_power_wells_aux), }; and using nvl_power_wells[] on NVL and platforms with the above DC_OFF dependency. > + > /* > * The PPS state needs to be locked for: > * - eDP on all platforms, since AUX transfers on eDP need VDD power > @@ -459,6 +463,9 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, > if (pps_wakeref) > intel_pps_unlock(intel_dp, pps_wakeref); > > + if (dc_off_wakeref) > + intel_display_power_put(display, POWER_DOMAIN_DC_OFF, dc_off_wakeref); > + > intel_display_power_put_async(display, aux_domain, aux_wakeref); > out_unlock: > intel_digital_port_unlock(encoder); > -- > 2.34.1 >