Re: [PATCH v2 2/2] drm/xe/hwmon: Use shared pcode default timeout for power limit write

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Mon, Sep 07, 2026 at 02:05:20PM +0530, Karthik Poosa wrote:
> Drop the local PL_WRITE_MBX_TIMEOUT_MS macro and use the common
> PCODE_DEFAULT_TIMEOUT_MS for the power limit write mailbox command.
> This removes a duplicate timeout definition and keeps hwmon in sync with
> the pcode default (now 10ms).
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_hwmon.c | 7 +------
>  1 file changed, 1 insertion(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 5284cab6703d..5edeac961ec3 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -101,11 +101,6 @@ enum sensor_attr_power {
>  
>  #define PWR_ATTR_TO_STR(attr)	(((attr) == hwmon_power_max) ? "PL1" : "PL2")
>  
> -/*
> - * Timeout for power limit write mailbox command.
> - */
> -#define PL_WRITE_MBX_TIMEOUT_MS	(1)
> -
>  /* Index of memory controller in READ_THERMAL_DATA output */
>  #define TEMP_INDEX_MCTRL	2
>  
> @@ -252,7 +247,7 @@ static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr
>  							     (channel == CHANNEL_CARD) ?
>  							     WRITE_PSYSGPU_POWER_LIMIT :
>  							     WRITE_PACKAGE_POWER_LIMIT, 0),
> -							     val0, val1, PL_WRITE_MBX_TIMEOUT_MS);
> +							     val0, val1, PCODE_DEFAULT_TIMEOUT_MS);
>  	if (ret)
>  		drm_dbg(&hwmon->xe->drm, "write failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
>  			channel, val0, val1, ret);
> -- 
> 2.25.1
>