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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: <intel-xe@lists.freedesktop.org>,
	Badal Nilawar <badal.nilawar@intel.com>
Subject: Re: [PATCH v2 2/2] drm/xe: Poll GT for C6 before D3
Date: Thu, 10 Sep 2026 18:23:54 -0400	[thread overview]
Message-ID: <aqMt-pHhq4T5hLhO@intel.com> (raw)
In-Reply-To: <20260910212823.2358362-2-vinay.belgaumkar@intel.com>

On Thu, Sep 10, 2026 at 02:28:23PM -0700, Vinay Belgaumkar wrote:
> Check if GTs are in C6 before transitioning to D3. PM subsystem can
> retry if this is not the case. This ensures some component is not
> accessing the GT when D3 state is forced. This check can be added
> to the runtime idle check since it helps to check for pending
> forcewakes as well before we poll for GT C6.
> 
> v2: Force resume when we cancel suspend due to C6 check (Sashiko)
> 
> Cc: Badal Nilawar <badal.nilawar@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_gt_idle.c | 37 +++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_gt_idle.h |  1 +
>  drivers/gpu/drm/xe/xe_pci.c     |  9 ++++++++
>  drivers/gpu/drm/xe/xe_pm.c      |  4 ++++
>  4 files changed, 51 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt_idle.c b/drivers/gpu/drm/xe/xe_gt_idle.c
> index c208d7563e36..e077f9a13473 100644
> --- a/drivers/gpu/drm/xe/xe_gt_idle.c
> +++ b/drivers/gpu/drm/xe/xe_gt_idle.c
> @@ -8,10 +8,12 @@
>  #include <drm/drm_managed.h>
>  
>  #include <generated/xe_wa_oob.h>
> +#include <linux/iopoll.h>
>  #include "xe_force_wake.h"
>  #include "xe_device.h"
>  #include "xe_gt.h"
>  #include "xe_gt_idle.h"
> +#include "xe_gt_printk.h"
>  #include "xe_gt_sysfs.h"
>  #include "xe_guc_pc.h"
>  #include "regs/xe_gt_regs.h"
> @@ -451,3 +453,38 @@ int xe_gt_idle_disable_c6(struct xe_gt *gt)
>  
>  	return 0;
>  }
> +
> +static int wait_for_gt_c6_state(struct xe_gt *gt,
> +				u16 timeout_ms)
> +{
> +	struct xe_guc_pc *pc = &gt->uc.guc.pc;
> +	enum xe_gt_idle_state state;
> +
> +	return poll_timeout_us(state = gt->gtidle.idle_status(pc),
> +			       state == GT_IDLE_C6,
> +			       20,
> +			       timeout_ms * USEC_PER_MSEC,
> +			       false);
> +}
> +
> +/**
> + * xe_gt_idle_wait_for_c6 - Poll for GT C6
> + * @gt: GT object
> + * @timeout_ms: wait time in ms
> + *
> + * This function polls for GT C6 state
> + *
> + * Return: 0 on success, -EAGAIN otherwise
> + */
> +int xe_gt_idle_wait_for_c6(struct xe_gt *gt, u16 timeout_ms)
> +{
> +	if (IS_SRIOV_VF(gt_to_xe(gt)))
> +		return 0;
> +
> +	if (wait_for_gt_c6_state(gt, timeout_ms)) {
> +		xe_gt_dbg(gt, "GT is not in C6\n");
> +		return -EAGAIN;
> +	}
> +
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_gt_idle.h b/drivers/gpu/drm/xe/xe_gt_idle.h
> index 9c34a155e102..74d6bd167fab 100644
> --- a/drivers/gpu/drm/xe/xe_gt_idle.h
> +++ b/drivers/gpu/drm/xe/xe_gt_idle.h
> @@ -18,5 +18,6 @@ void xe_gt_idle_enable_pg(struct xe_gt *gt);
>  void xe_gt_idle_disable_pg(struct xe_gt *gt);
>  int xe_gt_idle_pg_print(struct xe_gt *gt, struct drm_printer *p);
>  u64 xe_gt_idle_residency_msec(struct xe_gt_idle *gtidle);
> +int xe_gt_idle_wait_for_c6(struct xe_gt *gt, u16 timeout_ms);
>  
>  #endif /* _XE_GT_IDLE_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index a79d928ad75a..ca7898cce2aa 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -1343,6 +1343,15 @@ static int xe_pci_suspend(struct device *dev)
>  	 */
>  	d3cold_toggle(pdev, D3COLD_ENABLE);
>  
> +	err = xe_pm_check_runtime_idle(xe);

I don't like the _idle inside the _suspend...
This can get messed really quickly.

Le'ts only do the wait in here, but keep the _idle only
checking for the fw bits...

> +	if (err) {
> +		err = xe_pm_runtime_resume(xe);
> +		if (err) {
> +			drm_err(&xe->drm, "Resume failed after suspend was canceled");
> +			return err;
> +		}
> +	}
> +
>  	pci_save_state(pdev);
>  	pci_disable_device(pdev);
>  	pci_set_power_state(pdev, PCI_D3cold);
> diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c
> index e8d4cdbaef88..04529a242998 100644
> --- a/drivers/gpu/drm/xe/xe_pm.c
> +++ b/drivers/gpu/drm/xe/xe_pm.c
> @@ -1046,6 +1046,10 @@ int xe_pm_check_runtime_idle(struct xe_device *xe)
>  		if (xe_force_wake_any_bit_set(gt_to_fw(gt), XE_FW_DOMAIN_ID_GT))
>  			return -EBUSY;
>  
> +	for_each_gt(gt, xe, id)
> +		if (xe_gt_idle_wait_for_c6(gt, 200))
> +			return -EAGAIN;
> +
>  	return 0;
>  }
>  
> -- 
> 2.38.1
> 

  parent reply	other threads:[~2026-09-10 22:24 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-10 21:28 [PATCH v2 1/2] drm/xe: Inspect all forcewake bits for runtime idleness Vinay Belgaumkar
2026-09-10 21:28 ` [PATCH v2 2/2] drm/xe: Poll GT for C6 before D3 Vinay Belgaumkar
2026-09-10 21:41   ` sashiko-bot
2026-09-10 22:23   ` Rodrigo Vivi [this message]
2026-09-10 21:41 ` ✓ CI.KUnit: success for series starting with [v2,1/2] drm/xe: Inspect all forcewake bits for runtime idleness Patchwork
2026-09-10 21:45 ` [PATCH v2 1/2] " sashiko-bot
2026-09-10 21:53   ` Belgaumkar, Vinay
2026-09-10 22:17 ` Rodrigo Vivi
2026-09-10 23:00   ` Belgaumkar, Vinay
2026-09-11 21:58     ` Rodrigo Vivi
2026-09-11 23:02       ` Belgaumkar, Vinay
2026-09-14 13:03         ` Rodrigo Vivi
2026-09-10 22:35 ` ✓ Xe.CI.BAT: success for series starting with [v2,1/2] " Patchwork
2026-09-11  7:03 ` ✗ Xe.CI.FULL: failure " Patchwork

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