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Ruhl wrote: > > > The Crescent Island (CRI) GPU supports PMT via Xe driver > > registration. > > > > The CRI PMT MMIO mapping is shared for each PMT feature and it is > > necessary to set an index register value to access the correct memory > > space. > > > > The PMT driver has a callback infrastructure to access data areas with > > driver specific access. It is does not support the PMT control access. > > > > CRI discovery/control spaces are part of the access window so a driver > > callback is necessary to allow for the correct window to be exposed. > > > > Add control path callback support to the PMT driver. > > > > Add CRI PMT discovery information. > > > > Update the Xe driver to support the CRI PMT access. > > > > The crashlog access needs to be done with power enabled (telem is only > > available when the device is powered). > > > > Determine which access is requested, and do the appropriate power > > request. > > > > CRI FW is loaded at device power. Support the late-binding API to > > wait for FW readiness. (pending sysctl patch set implements the API). > > > > v2: > > Address AI feedback: > > - add missing entry->cb check > > - address SRIOV VF concerns > > - use xe_pm_runtime_put instead of _get in error path > > > > Address review comments: > > - redo power/lock sequencing > > - support device hotplug events > > > > v3: > > - cleanup power manangement flow > > - fixed an out of order power management locking issue > > - add a GUID caching mechanism, for GUID read > > - removed unused parameter (mmio) > > > > v4: > > - address various review comments > > - refactor crashlog to allow for return values > > - for callback usage, decouple PMT remap of data areas > > - use IS_SRIOV_VF() rather than expose soc-remapper internals > > - separate locking fixes intos distinct steps > > - refactor define update patches to seperate BMG and CRI updates > > - separate internal GUID into separate steps > > > > v5: > > - removed callback helpers > > - do not return error message with sysfs > > - fix missed return code check in trigger_store > > - return error value not false > > - use DEFINE_RES_MEM > > - document when base is unused > > - return error on invalid GUID request > > > > v6: > > - fix enabled/disabled inversion > > - fix missing DOC reference > > - change memcpy_to/fromio to readl/writel for register read > > - guid cache comment and update on valid guid > > > > v7: > > - reordered to have BMG updates followed by CRI support > > - separate base_offset usage for clarity > > - added EAGAIN usage to block uninitialized use of the API > > > > v8: > > - fix punit crashlog offset (should be 0xE60 not 0xE78) > > - remove EAGAIN support and re-order probe steps to initialize > > VSEC before other features use it > > > > v9: > > - added appropriate reviewed-bys > > - use dev_err instead of pr_err > > - enforce defined base usage when callbacks are in plcace > > - move SRIOV check to get_platform_info > > - assert SRIOV for API check > > - use scoped_guard() where possible > > - update to use correct sysctrl helper > > > > v10: > > - fix incorrect return type (broken in refactor, int -> bool) > > - fix incorrectly documented error return values > > - doc text cleanup > > > > v11: > > - add reviewed-by > > - fix minor checkpatch issue > > - use xe_assert() for a consistent API check > > > > Michael J. Ruhl (18): > > platform/x86/intel/pmt: complete pcidev to device update > > platform/x86/intel/pmt: refactor rmw with a return value > > platform/x86/intel/pmt: refactor rc with a return value > > platform/x86/intel/pmt: Add register access callbacks > > platform/x86/intel/pmt: Do not remap when using callbacks > > These platform drivers side patches looked ready so I've taken these > into a separate branch in pdx86 repo (+ one standalone pmt fix that looked > relevant to this case). > > I can do an IB PR out of that branch as needed if xe side wants to take > the rest sometime in this cycle. Well, I'd say that patch 17 is the only blocking on the rest of the series. If that gets reworked today/tomorrow then I would prefer to take all the patches through drm-xe-next with your ack. Otherwise, please go with your pull request and then when we backmerge the next -rc1/-rc2 we push the rest of the series to drm-xe-next. Thanks, Rodrigo. > > > drm/xe/vsec: Do not register BMG PMT for VF > > drm/xe/vsec: Correct locking order > > drm/xe/vsec: Use correct pm state get > > drm/xe/vsec: Add DOC text for VSEC > > drm/xe/vsec: Support possible hotplug exit > > drm/xe/vsec: Refactor BattleMage PMT defines > > drm/xe/vsec: Update VSEC probe order > > drm/xe/vsec: Add base_offset to allow for more flexibilty > > drm/xe/vsec: Support Crescent Island PMT > > drm/xe/vsec: Crescent Island PMT decode > > drm/xe/vsec: Crescent Island PMT callbacks > > drm/xe/vsec: Support late bind fw information > > drm/xe/vsec: Add PMT GUID internal access > > drm/xe/vsec: Update PMT internal access > > drm/xe/vsec: Refactor platform check > > > > Documentation/gpu/xe/index.rst | 1 + > > Documentation/gpu/xe/xe_vsec.rst | 14 + > > drivers/gpu/drm/xe/regs/xe_pmt.h | 12 +- > > drivers/gpu/drm/xe/xe_debugfs.c | 45 +- > > drivers/gpu/drm/xe/xe_device.c | 6 +- > > drivers/gpu/drm/xe/xe_device_types.h | 9 + > > drivers/gpu/drm/xe/xe_hwmon.c | 10 +- > > drivers/gpu/drm/xe/xe_pcode.c | 10 +- > > drivers/gpu/drm/xe/xe_vsec.c | 552 +++++++++++++++++++-- > > drivers/gpu/drm/xe/xe_vsec.h | 3 +- > > drivers/platform/x86/intel/pmt/class.c | 26 +- > > drivers/platform/x86/intel/pmt/class.h | 5 +- > > drivers/platform/x86/intel/pmt/crashlog.c | 235 ++++++--- > > drivers/platform/x86/intel/pmt/discovery.c | 2 +- > > drivers/platform/x86/intel/pmt/telemetry.c | 3 + > > include/linux/intel_vsec.h | 14 +- > > 16 files changed, 781 insertions(+), 166 deletions(-) > > create mode 100644 Documentation/gpu/xe/xe_vsec.rst > > > > > > -- > i. >