From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Mika Kahola <mika.kahola@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
Victor Carreras <vicajilau@gmail.com>
Subject: Re: [PATCH] drm/i915/dp: Don't recheck the eDP link state after a passing link training
Date: Tue, 10 Nov 2026 13:40:51 +0200 [thread overview]
Message-ID: <avMCw5rPER8uY_wu@intel.com> (raw)
In-Reply-To: <20261110101713.3684346-1-mika.kahola@intel.com>
On Tue, Nov 10, 2026 at 10:17:13AM +0000, Mika Kahola wrote:
> On eDP, a link retrain power cycles the panel. If the panel reports a
> transient link error after power-on, the link state recheck after a
> passing link training ends up in a retrain loop. Skip this recheck on
> eDP.
>
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/17737
> Tested-by: Victor Carreras <vicajilau@gmail.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> .../drm/i915/display/intel_dp_link_training.c | 19 +++++++++++++++----
> 1 file changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index ac1aff6edf05..35bf29f7b996 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1800,12 +1800,23 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp,
>
> intel_hpd_unblock(encoder);
>
> - if (!display->hotplug.ignore_long_hpd &&
> - link_recovery_autoretrain_allowed(link_training)) {
> - int delay_ms = link_recovery_autoretrain_pending(link_training) ? 0 : 2000;
> + if (display->hotplug.ignore_long_hpd ||
> + !link_recovery_autoretrain_allowed(link_training))
> + return;
>
> - intel_encoder_link_check_queue_work(encoder, delay_ms);
> + if (link_recovery_autoretrain_pending(link_training)) {
> + intel_encoder_link_check_queue_work(encoder, 0);
> + return;
> }
> +
> + /*
> + * An eDP retrain power cycles the panel, which can retrigger
> + * a transient link error after power-on, leading to a retrain loop.
> + */
Is it a transient error? Ie. does the interlane align bit ping-ponging
randomly or does it always (as in every link rate and lane count
that is possible) stay completely off after link training?
We know that on those crappy CH7511 bridges the bit only works during
link training, and then just permanently turns off when link training
ends. IIRC on those the bit disappears exactly when we switch the
training pattern off.
> + if (intel_dp_is_edp(intel_dp))
> + return;
> +
> + intel_encoder_link_check_queue_work(encoder, 2000);
> }
>
> static bool
> --
> 2.43.0
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2026-11-10 11:41 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 10:17 [PATCH] drm/i915/dp: Don't recheck the eDP link state after a passing link training Mika Kahola
2026-11-10 10:26 ` ✓ CI.KUnit: success for " Patchwork
2026-11-10 11:17 ` ✓ Xe.CI.BAT: " Patchwork
2026-11-10 11:40 ` Ville Syrjälä [this message]
2026-11-10 15:38 ` [PATCH] " Kahola, Mika
2026-11-10 13:20 ` ✓ Xe.CI.FULL: success for " Patchwork
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