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d="scan'208";a="253436878" Received: from jkrzyszt-mobl2.ger.corp.intel.com (HELO localhost) ([10.245.246.152]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2026 07:01:44 -0700 From: Jani Nikula To: Ville Syrjala , intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: Re: [PATCH 9/9] drm/i915/wm: Include .min_ddb_alloc_uv in the wm dumps In-Reply-To: <20260319114034.7093-10-ville.syrjala@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland References: <20260319114034.7093-1-ville.syrjala@linux.intel.com> <20260319114034.7093-10-ville.syrjala@linux.intel.com> Date: Thu, 19 Mar 2026 16:01:39 +0200 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Thu, 19 Mar 2026, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > We include the Y/RGB .min_ddb_alloc in the wm state change dumps. > Do the same for .min_ddb_alloc_uv, on the platforms where it is > used. > > Also adjust the whitespace in the other debug prints to keep > the values for each wm level lined up across all the lines. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/display/skl_watermark.c | 30 +++++++++++++++++--- > 1 file changed, 26 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/d= rm/i915/display/skl_watermark.c > index 345767349988..4725927acfd4 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark.c > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c > @@ -2624,7 +2624,7 @@ skl_print_plane_wm_changes(struct intel_plane *plan= e, > struct intel_display *display =3D to_intel_display(plane); >=20=20 > drm_dbg_kms(display->drm, > - "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%= cwm7,%ctwm,%cswm,%cstwm" > + "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm= 6,%cwm7,%ctwm,%cswm,%cstwm" > " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%= cstwm\n", > plane->base.base.id, plane->base.name, > enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable), > @@ -2643,7 +2643,7 @@ skl_print_plane_wm_changes(struct intel_plane *plan= e, > enast(new_wm->sagv.trans_wm.enable)); >=20=20 > drm_dbg_kms(display->drm, > - "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%= c%3d,%c%3d,%c%3d,%c%4d" > + "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3= d,%c%3d,%c%3d,%c%3d,%c%4d" > " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d= ,%c%4d\n", > plane->base.base.id, plane->base.name, > enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines, > @@ -2670,7 +2670,7 @@ skl_print_plane_wm_changes(struct intel_plane *plan= e, > enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.l= ines); >=20=20 > drm_dbg_kms(display->drm, > - "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d" > + "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,= %5d" > " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n", > plane->base.base.id, plane->base.name, > old_wm->wm[0].blocks, old_wm->wm[1].blocks, > @@ -2689,7 +2689,7 @@ skl_print_plane_wm_changes(struct intel_plane *plan= e, > new_wm->sagv.trans_wm.blocks); >=20=20 > drm_dbg_kms(display->drm, > - "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d" > + "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,= %5d" I wonder if the space changes would've been cleared with something like: "[PLANE:%d:%s] min_ddb: %4d... but *shrug*. Reviewed-by: Jani Nikula > " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n", > plane->base.base.id, plane->base.name, > old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc, > @@ -2706,6 +2706,28 @@ skl_print_plane_wm_changes(struct intel_plane *pla= ne, > new_wm->trans_wm.min_ddb_alloc, > new_wm->sagv.wm0.min_ddb_alloc, > new_wm->sagv.trans_wm.min_ddb_alloc); > + > + if (DISPLAY_VER(display) >=3D 11) > + return; > + > + drm_dbg_kms(display->drm, > + "[PLANE:%d:%s] min_ddb_uv %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,= %5d" > + " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n", > + plane->base.base.id, plane->base.name, > + old_wm->wm[0].min_ddb_alloc_uv, old_wm->wm[1].min_ddb_alloc_uv, > + old_wm->wm[2].min_ddb_alloc_uv, old_wm->wm[3].min_ddb_alloc_uv, > + old_wm->wm[4].min_ddb_alloc_uv, old_wm->wm[5].min_ddb_alloc_uv, > + old_wm->wm[6].min_ddb_alloc_uv, old_wm->wm[7].min_ddb_alloc_uv, > + old_wm->trans_wm.min_ddb_alloc_uv, > + old_wm->sagv.wm0.min_ddb_alloc_uv, > + old_wm->sagv.trans_wm.min_ddb_alloc_uv, > + new_wm->wm[0].min_ddb_alloc_uv, new_wm->wm[1].min_ddb_alloc_uv, > + new_wm->wm[2].min_ddb_alloc_uv, new_wm->wm[3].min_ddb_alloc_uv, > + new_wm->wm[4].min_ddb_alloc_uv, new_wm->wm[5].min_ddb_alloc_uv, > + new_wm->wm[6].min_ddb_alloc_uv, new_wm->wm[7].min_ddb_alloc_uv, > + new_wm->trans_wm.min_ddb_alloc_uv, > + new_wm->sagv.wm0.min_ddb_alloc_uv, > + new_wm->sagv.trans_wm.min_ddb_alloc_uv); > } >=20=20 > static void --=20 Jani Nikula, Intel